Commit | Line | Data |
---|---|---|
b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
c767a54b JP |
2 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
3 | ||
61c4628b SS |
4 | #include <linux/errno.h> |
5 | #include <linux/kernel.h> | |
6 | #include <linux/mm.h> | |
7 | #include <linux/smp.h> | |
389d1fb1 | 8 | #include <linux/prctl.h> |
61c4628b SS |
9 | #include <linux/slab.h> |
10 | #include <linux/sched.h> | |
4c822698 | 11 | #include <linux/sched/idle.h> |
b17b0153 | 12 | #include <linux/sched/debug.h> |
29930025 | 13 | #include <linux/sched/task.h> |
68db0cf1 | 14 | #include <linux/sched/task_stack.h> |
186f4360 PG |
15 | #include <linux/init.h> |
16 | #include <linux/export.h> | |
7f424a8b | 17 | #include <linux/pm.h> |
162a688e | 18 | #include <linux/tick.h> |
9d62dcdf | 19 | #include <linux/random.h> |
7c68af6e | 20 | #include <linux/user-return-notifier.h> |
814e2c84 AI |
21 | #include <linux/dmi.h> |
22 | #include <linux/utsname.h> | |
90e24014 | 23 | #include <linux/stackprotector.h> |
90e24014 | 24 | #include <linux/cpuidle.h> |
89f579ce YW |
25 | #include <linux/acpi.h> |
26 | #include <linux/elf-randomize.h> | |
aaa3896b | 27 | #include <linux/static_call.h> |
61613521 | 28 | #include <trace/events/power.h> |
24f1e32c | 29 | #include <linux/hw_breakpoint.h> |
93789b32 | 30 | #include <asm/cpu.h> |
d3ec5cae | 31 | #include <asm/apic.h> |
7c0f6ba6 | 32 | #include <linux/uaccess.h> |
b253149b | 33 | #include <asm/mwait.h> |
db8268df | 34 | #include <asm/fpu/api.h> |
63e81807 | 35 | #include <asm/fpu/sched.h> |
500afbf6 | 36 | #include <asm/fpu/xstate.h> |
66cb5917 | 37 | #include <asm/debugreg.h> |
90e24014 | 38 | #include <asm/nmi.h> |
375074cc | 39 | #include <asm/tlbflush.h> |
8838eb6c | 40 | #include <asm/mce.h> |
9fda6a06 | 41 | #include <asm/vm86.h> |
7b32aead | 42 | #include <asm/switch_to.h> |
b7ffc44d | 43 | #include <asm/desc.h> |
e9ea1e7f | 44 | #include <asm/prctl.h> |
885f82bf | 45 | #include <asm/spec-ctrl.h> |
577d5cd7 | 46 | #include <asm/io_bitmap.h> |
89f579ce | 47 | #include <asm/proto.h> |
6f9885a3 | 48 | #include <asm/frame.h> |
5d1ceb39 | 49 | #include <asm/unwind.h> |
bfe6ed0c | 50 | #include <asm/tdx.h> |
74c228d2 | 51 | #include <asm/mmu_context.h> |
90e24014 | 52 | |
ff16701a TG |
53 | #include "process.h" |
54 | ||
45046892 TG |
55 | /* |
56 | * per-CPU TSS segments. Threads are completely 'soft' on Linux, | |
57 | * no more per-task TSS's. The TSS size is kept cacheline-aligned | |
58 | * so they are allowed to end up in the .data..cacheline_aligned | |
59 | * section. Since TSS's are completely CPU-local, we want them | |
60 | * on exact cacheline boundaries, to eliminate cacheline ping-pong. | |
61 | */ | |
2fd9c41a | 62 | __visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = { |
d0a0de21 | 63 | .x86_tss = { |
20bb8344 AL |
64 | /* |
65 | * .sp0 is only used when entering ring 0 from a lower | |
66 | * privilege level. Since the init task never runs anything | |
67 | * but ring 0 code, there is no need for a valid value here. | |
68 | * Poison it. | |
69 | */ | |
70 | .sp0 = (1UL << (BITS_PER_LONG-1)) + 1, | |
9aaefe7b | 71 | |
1591584e | 72 | #ifdef CONFIG_X86_32 |
9aaefe7b | 73 | .sp1 = TOP_OF_INIT_STACK, |
9aaefe7b | 74 | |
d0a0de21 AL |
75 | .ss0 = __KERNEL_DS, |
76 | .ss1 = __KERNEL_CS, | |
d0a0de21 | 77 | #endif |
ecc7e37d | 78 | .io_bitmap_base = IO_BITMAP_OFFSET_INVALID, |
d0a0de21 | 79 | }, |
d0a0de21 | 80 | }; |
c482feef | 81 | EXPORT_PER_CPU_SYMBOL(cpu_tss_rw); |
45046892 | 82 | |
b7ceaec1 AL |
83 | DEFINE_PER_CPU(bool, __tss_limit_invalid); |
84 | EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid); | |
b7ffc44d | 85 | |
55ccf3fe SS |
86 | /* |
87 | * this gets called so that we can store lazy state into memory and copy the | |
88 | * current task into the new thread. | |
89 | */ | |
61c4628b SS |
90 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
91 | { | |
5aaeb5c0 | 92 | memcpy(dst, src, arch_task_struct_size); |
2459ee86 AL |
93 | #ifdef CONFIG_VM86 |
94 | dst->thread.vm86 = NULL; | |
95 | #endif | |
f0cbc8b3 TG |
96 | /* Drop the copied pointer to current's fpstate */ |
97 | dst->thread.fpu.fpstate = NULL; | |
500afbf6 | 98 | |
2d16a187 | 99 | return 0; |
61c4628b | 100 | } |
7f424a8b | 101 | |
500afbf6 CB |
102 | #ifdef CONFIG_X86_64 |
103 | void arch_release_task_struct(struct task_struct *tsk) | |
104 | { | |
105 | if (fpu_state_size_dynamic()) | |
106 | fpstate_free(&tsk->thread.fpu); | |
61c4628b | 107 | } |
500afbf6 | 108 | #endif |
7f424a8b | 109 | |
389d1fb1 | 110 | /* |
4bfe6cce | 111 | * Free thread data structures etc.. |
389d1fb1 | 112 | */ |
e6464694 | 113 | void exit_thread(struct task_struct *tsk) |
389d1fb1 | 114 | { |
e6464694 | 115 | struct thread_struct *t = &tsk->thread; |
ca6787ba | 116 | struct fpu *fpu = &t->fpu; |
ea5f1cd7 TG |
117 | |
118 | if (test_thread_flag(TIF_IO_BITMAP)) | |
4bfe6cce | 119 | io_bitmap_exit(tsk); |
1dcc8d7b | 120 | |
9fda6a06 BG |
121 | free_vm86(t); |
122 | ||
50338615 | 123 | fpu__drop(fpu); |
389d1fb1 JF |
124 | } |
125 | ||
2fff071d TG |
126 | static int set_new_tls(struct task_struct *p, unsigned long tls) |
127 | { | |
128 | struct user_desc __user *utls = (struct user_desc __user *)tls; | |
129 | ||
130 | if (in_ia32_syscall()) | |
131 | return do_set_thread_area(p, -1, utls, 0); | |
132 | else | |
133 | return do_set_thread_area_64(p, ARCH_SET_FS, tls); | |
134 | } | |
135 | ||
c5febea0 | 136 | int copy_thread(struct task_struct *p, const struct kernel_clone_args *args) |
2fff071d | 137 | { |
c5febea0 EB |
138 | unsigned long clone_flags = args->flags; |
139 | unsigned long sp = args->stack; | |
c5febea0 | 140 | unsigned long tls = args->tls; |
2fff071d TG |
141 | struct inactive_task_frame *frame; |
142 | struct fork_frame *fork_frame; | |
143 | struct pt_regs *childregs; | |
4804e382 | 144 | int ret = 0; |
2fff071d TG |
145 | |
146 | childregs = task_pt_regs(p); | |
147 | fork_frame = container_of(childregs, struct fork_frame, regs); | |
148 | frame = &fork_frame->frame; | |
149 | ||
6f9885a3 | 150 | frame->bp = encode_frame_pointer(childregs); |
2fff071d TG |
151 | frame->ret_addr = (unsigned long) ret_from_fork; |
152 | p->thread.sp = (unsigned long) fork_frame; | |
577d5cd7 | 153 | p->thread.io_bitmap = NULL; |
b968e84b | 154 | p->thread.iopl_warn = 0; |
2fff071d TG |
155 | memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps)); |
156 | ||
157 | #ifdef CONFIG_X86_64 | |
005f141e CB |
158 | current_save_fsgs(); |
159 | p->thread.fsindex = current->thread.fsindex; | |
160 | p->thread.fsbase = current->thread.fsbase; | |
161 | p->thread.gsindex = current->thread.gsindex; | |
162 | p->thread.gsbase = current->thread.gsbase; | |
163 | ||
2fff071d TG |
164 | savesegment(es, p->thread.es); |
165 | savesegment(ds, p->thread.ds); | |
166 | #else | |
167 | p->thread.sp0 = (unsigned long) (childregs + 1); | |
3a24a608 | 168 | savesegment(gs, p->thread.gs); |
2fff071d TG |
169 | /* |
170 | * Clear all status flags including IF and set fixed bit. 64bit | |
171 | * does not have this initialization as the frame does not contain | |
172 | * flags. The flags consistency (especially vs. AC) is there | |
173 | * ensured via objtool, which lacks 32bit support. | |
174 | */ | |
175 | frame->flags = X86_EFLAGS_FIXED; | |
176 | #endif | |
177 | ||
5bd2e97c | 178 | fpu_clone(p, clone_flags, args->fn); |
2d16a187 | 179 | |
2fff071d | 180 | /* Kernel thread ? */ |
50b7b6f2 | 181 | if (unlikely(p->flags & PF_KTHREAD)) { |
9782a712 | 182 | p->thread.pkru = pkru_get_init_value(); |
2fff071d | 183 | memset(childregs, 0, sizeof(struct pt_regs)); |
5bd2e97c | 184 | kthread_frame_init(frame, args->fn, args->fn_arg); |
2fff071d TG |
185 | return 0; |
186 | } | |
187 | ||
9782a712 DH |
188 | /* |
189 | * Clone current's PKRU value from hardware. tsk->thread.pkru | |
190 | * is only valid when scheduled out. | |
191 | */ | |
192 | p->thread.pkru = read_pkru(); | |
193 | ||
2fff071d TG |
194 | frame->bx = 0; |
195 | *childregs = *current_pt_regs(); | |
196 | childregs->ax = 0; | |
197 | if (sp) | |
198 | childregs->sp = sp; | |
199 | ||
5bd2e97c | 200 | if (unlikely(args->fn)) { |
50b7b6f2 | 201 | /* |
5bd2e97c EB |
202 | * A user space thread, but it doesn't return to |
203 | * ret_after_fork(). | |
50b7b6f2 SM |
204 | * |
205 | * In order to indicate that to tools like gdb, | |
206 | * we reset the stack and instruction pointers. | |
207 | * | |
208 | * It does the same kernel frame setup to return to a kernel | |
209 | * function that a kernel thread does. | |
210 | */ | |
211 | childregs->sp = 0; | |
212 | childregs->ip = 0; | |
5bd2e97c | 213 | kthread_frame_init(frame, args->fn, args->fn_arg); |
50b7b6f2 SM |
214 | return 0; |
215 | } | |
216 | ||
2fff071d | 217 | /* Set a new TLS for the child thread? */ |
4804e382 | 218 | if (clone_flags & CLONE_SETTLS) |
2fff071d | 219 | ret = set_new_tls(p, tls); |
4804e382 TG |
220 | |
221 | if (!ret && unlikely(test_tsk_thread_flag(current, TIF_IO_BITMAP))) | |
222 | io_bitmap_share(p); | |
223 | ||
2fff071d TG |
224 | return ret; |
225 | } | |
226 | ||
33344368 AL |
227 | static void pkru_flush_thread(void) |
228 | { | |
229 | /* | |
230 | * If PKRU is enabled the default PKRU value has to be loaded into | |
231 | * the hardware right here (similar to context switch). | |
232 | */ | |
233 | pkru_write_default(); | |
234 | } | |
235 | ||
389d1fb1 JF |
236 | void flush_thread(void) |
237 | { | |
238 | struct task_struct *tsk = current; | |
239 | ||
24f1e32c | 240 | flush_ptrace_hw_breakpoint(tsk); |
389d1fb1 | 241 | memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); |
110d7f75 | 242 | |
e7ecad17 | 243 | fpu_flush_thread(); |
33344368 | 244 | pkru_flush_thread(); |
389d1fb1 JF |
245 | } |
246 | ||
389d1fb1 JF |
247 | void disable_TSC(void) |
248 | { | |
249 | preempt_disable(); | |
250 | if (!test_and_set_thread_flag(TIF_NOTSC)) | |
251 | /* | |
252 | * Must flip the CPU state synchronously with | |
253 | * TIF_NOTSC in the current running context. | |
254 | */ | |
5a920155 | 255 | cr4_set_bits(X86_CR4_TSD); |
389d1fb1 JF |
256 | preempt_enable(); |
257 | } | |
258 | ||
389d1fb1 JF |
259 | static void enable_TSC(void) |
260 | { | |
261 | preempt_disable(); | |
262 | if (test_and_clear_thread_flag(TIF_NOTSC)) | |
263 | /* | |
264 | * Must flip the CPU state synchronously with | |
265 | * TIF_NOTSC in the current running context. | |
266 | */ | |
5a920155 | 267 | cr4_clear_bits(X86_CR4_TSD); |
389d1fb1 JF |
268 | preempt_enable(); |
269 | } | |
270 | ||
271 | int get_tsc_mode(unsigned long adr) | |
272 | { | |
273 | unsigned int val; | |
274 | ||
275 | if (test_thread_flag(TIF_NOTSC)) | |
276 | val = PR_TSC_SIGSEGV; | |
277 | else | |
278 | val = PR_TSC_ENABLE; | |
279 | ||
280 | return put_user(val, (unsigned int __user *)adr); | |
281 | } | |
282 | ||
283 | int set_tsc_mode(unsigned int val) | |
284 | { | |
285 | if (val == PR_TSC_SIGSEGV) | |
286 | disable_TSC(); | |
287 | else if (val == PR_TSC_ENABLE) | |
288 | enable_TSC(); | |
289 | else | |
290 | return -EINVAL; | |
291 | ||
292 | return 0; | |
293 | } | |
294 | ||
e9ea1e7f KH |
295 | DEFINE_PER_CPU(u64, msr_misc_features_shadow); |
296 | ||
297 | static void set_cpuid_faulting(bool on) | |
298 | { | |
299 | u64 msrval; | |
300 | ||
301 | msrval = this_cpu_read(msr_misc_features_shadow); | |
302 | msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT; | |
303 | msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT); | |
304 | this_cpu_write(msr_misc_features_shadow, msrval); | |
305 | wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval); | |
306 | } | |
307 | ||
308 | static void disable_cpuid(void) | |
309 | { | |
310 | preempt_disable(); | |
311 | if (!test_and_set_thread_flag(TIF_NOCPUID)) { | |
312 | /* | |
313 | * Must flip the CPU state synchronously with | |
314 | * TIF_NOCPUID in the current running context. | |
315 | */ | |
316 | set_cpuid_faulting(true); | |
317 | } | |
318 | preempt_enable(); | |
319 | } | |
320 | ||
321 | static void enable_cpuid(void) | |
322 | { | |
323 | preempt_disable(); | |
324 | if (test_and_clear_thread_flag(TIF_NOCPUID)) { | |
325 | /* | |
326 | * Must flip the CPU state synchronously with | |
327 | * TIF_NOCPUID in the current running context. | |
328 | */ | |
329 | set_cpuid_faulting(false); | |
330 | } | |
331 | preempt_enable(); | |
332 | } | |
333 | ||
334 | static int get_cpuid_mode(void) | |
335 | { | |
336 | return !test_thread_flag(TIF_NOCPUID); | |
337 | } | |
338 | ||
f5c0b4f3 | 339 | static int set_cpuid_mode(unsigned long cpuid_enabled) |
e9ea1e7f | 340 | { |
67e87d43 | 341 | if (!boot_cpu_has(X86_FEATURE_CPUID_FAULT)) |
e9ea1e7f KH |
342 | return -ENODEV; |
343 | ||
344 | if (cpuid_enabled) | |
345 | enable_cpuid(); | |
346 | else | |
347 | disable_cpuid(); | |
348 | ||
349 | return 0; | |
350 | } | |
351 | ||
352 | /* | |
353 | * Called immediately after a successful exec. | |
354 | */ | |
355 | void arch_setup_new_exec(void) | |
356 | { | |
357 | /* If cpuid was previously disabled for this task, re-enable it. */ | |
358 | if (test_thread_flag(TIF_NOCPUID)) | |
359 | enable_cpuid(); | |
71368af9 WL |
360 | |
361 | /* | |
362 | * Don't inherit TIF_SSBD across exec boundary when | |
363 | * PR_SPEC_DISABLE_NOEXEC is used. | |
364 | */ | |
365 | if (test_thread_flag(TIF_SSBD) && | |
366 | task_spec_ssb_noexec(current)) { | |
367 | clear_thread_flag(TIF_SSBD); | |
368 | task_clear_spec_ssb_disable(current); | |
369 | task_clear_spec_ssb_noexec(current); | |
dca99fb6 | 370 | speculation_ctrl_update(read_thread_flags()); |
71368af9 | 371 | } |
74c228d2 KS |
372 | |
373 | mm_reset_untag_mask(current->mm); | |
e9ea1e7f KH |
374 | } |
375 | ||
111e7b15 | 376 | #ifdef CONFIG_X86_IOPL_IOPERM |
22fe5b04 TG |
377 | static inline void switch_to_bitmap(unsigned long tifp) |
378 | { | |
379 | /* | |
380 | * Invalidate I/O bitmap if the previous task used it. This prevents | |
381 | * any possible leakage of an active I/O bitmap. | |
382 | * | |
383 | * If the next task has an I/O bitmap it will handle it on exit to | |
384 | * user mode. | |
385 | */ | |
386 | if (tifp & _TIF_IO_BITMAP) | |
cadfad87 | 387 | tss_invalidate_io_bitmap(); |
22fe5b04 TG |
388 | } |
389 | ||
390 | static void tss_copy_io_bitmap(struct tss_struct *tss, struct io_bitmap *iobm) | |
060aa16f TG |
391 | { |
392 | /* | |
393 | * Copy at least the byte range of the incoming tasks bitmap which | |
394 | * covers the permitted I/O ports. | |
395 | * | |
396 | * If the previous task which used an I/O bitmap had more bits | |
397 | * permitted, then the copy needs to cover those as well so they | |
398 | * get turned off. | |
399 | */ | |
400 | memcpy(tss->io_bitmap.bitmap, iobm->bitmap, | |
401 | max(tss->io_bitmap.prev_max, iobm->max)); | |
402 | ||
403 | /* | |
404 | * Store the new max and the sequence number of this bitmap | |
405 | * and a pointer to the bitmap itself. | |
406 | */ | |
407 | tss->io_bitmap.prev_max = iobm->max; | |
408 | tss->io_bitmap.prev_sequence = iobm->sequence; | |
409 | } | |
410 | ||
22fe5b04 | 411 | /** |
dbb5ab6d | 412 | * native_tss_update_io_bitmap - Update I/O bitmap before exiting to user mode |
22fe5b04 | 413 | */ |
99bcd4a6 | 414 | void native_tss_update_io_bitmap(void) |
af8b3cd3 | 415 | { |
ff16701a | 416 | struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); |
7b0b8cfd | 417 | struct thread_struct *t = ¤t->thread; |
c8137ace | 418 | u16 *base = &tss->x86_tss.io_bitmap_base; |
ff16701a | 419 | |
7b0b8cfd | 420 | if (!test_thread_flag(TIF_IO_BITMAP)) { |
cadfad87 | 421 | native_tss_invalidate_io_bitmap(); |
7b0b8cfd BP |
422 | return; |
423 | } | |
424 | ||
425 | if (IS_ENABLED(CONFIG_X86_IOPL_IOPERM) && t->iopl_emul == 3) { | |
426 | *base = IO_BITMAP_OFFSET_VALID_ALL; | |
427 | } else { | |
428 | struct io_bitmap *iobm = t->io_bitmap; | |
429 | ||
af8b3cd3 | 430 | /* |
7b0b8cfd BP |
431 | * Only copy bitmap data when the sequence number differs. The |
432 | * update time is accounted to the incoming task. | |
af8b3cd3 | 433 | */ |
7b0b8cfd BP |
434 | if (tss->io_bitmap.prev_sequence != iobm->sequence) |
435 | tss_copy_io_bitmap(tss, iobm); | |
436 | ||
437 | /* Enable the bitmap */ | |
438 | *base = IO_BITMAP_OFFSET_VALID_MAP; | |
af8b3cd3 | 439 | } |
7b0b8cfd BP |
440 | |
441 | /* | |
442 | * Make sure that the TSS limit is covering the IO bitmap. It might have | |
443 | * been cut down by a VMEXIT to 0x67 which would cause a subsequent I/O | |
444 | * access from user space to trigger a #GP because tbe bitmap is outside | |
445 | * the TSS limit. | |
446 | */ | |
447 | refresh_tss_limit(); | |
af8b3cd3 | 448 | } |
111e7b15 TG |
449 | #else /* CONFIG_X86_IOPL_IOPERM */ |
450 | static inline void switch_to_bitmap(unsigned long tifp) { } | |
451 | #endif | |
af8b3cd3 | 452 | |
1f50ddb4 TG |
453 | #ifdef CONFIG_SMP |
454 | ||
455 | struct ssb_state { | |
456 | struct ssb_state *shared_state; | |
457 | raw_spinlock_t lock; | |
458 | unsigned int disable_state; | |
459 | unsigned long local_state; | |
460 | }; | |
461 | ||
462 | #define LSTATE_SSB 0 | |
463 | ||
464 | static DEFINE_PER_CPU(struct ssb_state, ssb_state); | |
465 | ||
466 | void speculative_store_bypass_ht_init(void) | |
885f82bf | 467 | { |
1f50ddb4 TG |
468 | struct ssb_state *st = this_cpu_ptr(&ssb_state); |
469 | unsigned int this_cpu = smp_processor_id(); | |
470 | unsigned int cpu; | |
471 | ||
472 | st->local_state = 0; | |
473 | ||
474 | /* | |
475 | * Shared state setup happens once on the first bringup | |
476 | * of the CPU. It's not destroyed on CPU hotunplug. | |
477 | */ | |
478 | if (st->shared_state) | |
479 | return; | |
480 | ||
481 | raw_spin_lock_init(&st->lock); | |
482 | ||
483 | /* | |
484 | * Go over HT siblings and check whether one of them has set up the | |
485 | * shared state pointer already. | |
486 | */ | |
487 | for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) { | |
488 | if (cpu == this_cpu) | |
489 | continue; | |
490 | ||
491 | if (!per_cpu(ssb_state, cpu).shared_state) | |
492 | continue; | |
493 | ||
494 | /* Link it to the state of the sibling: */ | |
495 | st->shared_state = per_cpu(ssb_state, cpu).shared_state; | |
496 | return; | |
497 | } | |
498 | ||
499 | /* | |
500 | * First HT sibling to come up on the core. Link shared state of | |
501 | * the first HT sibling to itself. The siblings on the same core | |
502 | * which come up later will see the shared state pointer and link | |
d9f6e12f | 503 | * themselves to the state of this CPU. |
1f50ddb4 TG |
504 | */ |
505 | st->shared_state = st; | |
506 | } | |
885f82bf | 507 | |
1f50ddb4 TG |
508 | /* |
509 | * Logic is: First HT sibling enables SSBD for both siblings in the core | |
510 | * and last sibling to disable it, disables it for the whole core. This how | |
511 | * MSR_SPEC_CTRL works in "hardware": | |
512 | * | |
513 | * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL | |
514 | */ | |
515 | static __always_inline void amd_set_core_ssb_state(unsigned long tifn) | |
516 | { | |
517 | struct ssb_state *st = this_cpu_ptr(&ssb_state); | |
518 | u64 msr = x86_amd_ls_cfg_base; | |
519 | ||
520 | if (!static_cpu_has(X86_FEATURE_ZEN)) { | |
521 | msr |= ssbd_tif_to_amd_ls_cfg(tifn); | |
885f82bf | 522 | wrmsrl(MSR_AMD64_LS_CFG, msr); |
1f50ddb4 TG |
523 | return; |
524 | } | |
525 | ||
526 | if (tifn & _TIF_SSBD) { | |
527 | /* | |
528 | * Since this can race with prctl(), block reentry on the | |
529 | * same CPU. | |
530 | */ | |
531 | if (__test_and_set_bit(LSTATE_SSB, &st->local_state)) | |
532 | return; | |
533 | ||
534 | msr |= x86_amd_ls_cfg_ssbd_mask; | |
535 | ||
536 | raw_spin_lock(&st->shared_state->lock); | |
537 | /* First sibling enables SSBD: */ | |
538 | if (!st->shared_state->disable_state) | |
539 | wrmsrl(MSR_AMD64_LS_CFG, msr); | |
540 | st->shared_state->disable_state++; | |
541 | raw_spin_unlock(&st->shared_state->lock); | |
885f82bf | 542 | } else { |
1f50ddb4 TG |
543 | if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state)) |
544 | return; | |
545 | ||
546 | raw_spin_lock(&st->shared_state->lock); | |
547 | st->shared_state->disable_state--; | |
548 | if (!st->shared_state->disable_state) | |
549 | wrmsrl(MSR_AMD64_LS_CFG, msr); | |
550 | raw_spin_unlock(&st->shared_state->lock); | |
885f82bf TG |
551 | } |
552 | } | |
1f50ddb4 TG |
553 | #else |
554 | static __always_inline void amd_set_core_ssb_state(unsigned long tifn) | |
555 | { | |
556 | u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn); | |
557 | ||
558 | wrmsrl(MSR_AMD64_LS_CFG, msr); | |
559 | } | |
560 | #endif | |
561 | ||
11fb0683 TL |
562 | static __always_inline void amd_set_ssb_virt_state(unsigned long tifn) |
563 | { | |
564 | /* | |
565 | * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL, | |
566 | * so ssbd_tif_to_spec_ctrl() just works. | |
567 | */ | |
568 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn)); | |
569 | } | |
570 | ||
01daf568 TC |
571 | /* |
572 | * Update the MSRs managing speculation control, during context switch. | |
573 | * | |
574 | * tifp: Previous task's thread flags | |
575 | * tifn: Next task's thread flags | |
576 | */ | |
577 | static __always_inline void __speculation_ctrl_update(unsigned long tifp, | |
578 | unsigned long tifn) | |
1f50ddb4 | 579 | { |
5bfbe3ad | 580 | unsigned long tif_diff = tifp ^ tifn; |
01daf568 TC |
581 | u64 msr = x86_spec_ctrl_base; |
582 | bool updmsr = false; | |
583 | ||
2f5fb193 TG |
584 | lockdep_assert_irqs_disabled(); |
585 | ||
dbbe2ad0 AS |
586 | /* Handle change of TIF_SSBD depending on the mitigation method. */ |
587 | if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) { | |
588 | if (tif_diff & _TIF_SSBD) | |
01daf568 | 589 | amd_set_ssb_virt_state(tifn); |
dbbe2ad0 AS |
590 | } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) { |
591 | if (tif_diff & _TIF_SSBD) | |
01daf568 | 592 | amd_set_core_ssb_state(tifn); |
dbbe2ad0 AS |
593 | } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || |
594 | static_cpu_has(X86_FEATURE_AMD_SSBD)) { | |
595 | updmsr |= !!(tif_diff & _TIF_SSBD); | |
596 | msr |= ssbd_tif_to_spec_ctrl(tifn); | |
01daf568 | 597 | } |
1f50ddb4 | 598 | |
dbbe2ad0 | 599 | /* Only evaluate TIF_SPEC_IB if conditional STIBP is enabled. */ |
5bfbe3ad TC |
600 | if (IS_ENABLED(CONFIG_SMP) && |
601 | static_branch_unlikely(&switch_to_cond_stibp)) { | |
602 | updmsr |= !!(tif_diff & _TIF_SPEC_IB); | |
603 | msr |= stibp_tif_to_spec_ctrl(tifn); | |
604 | } | |
605 | ||
01daf568 | 606 | if (updmsr) |
66065157 | 607 | update_spec_ctrl_cond(msr); |
1f50ddb4 TG |
608 | } |
609 | ||
6d991ba5 | 610 | static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk) |
1f50ddb4 | 611 | { |
6d991ba5 TG |
612 | if (test_and_clear_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE)) { |
613 | if (task_spec_ssb_disable(tsk)) | |
614 | set_tsk_thread_flag(tsk, TIF_SSBD); | |
615 | else | |
616 | clear_tsk_thread_flag(tsk, TIF_SSBD); | |
9137bb27 TG |
617 | |
618 | if (task_spec_ib_disable(tsk)) | |
619 | set_tsk_thread_flag(tsk, TIF_SPEC_IB); | |
620 | else | |
621 | clear_tsk_thread_flag(tsk, TIF_SPEC_IB); | |
6d991ba5 TG |
622 | } |
623 | /* Return the updated threadinfo flags*/ | |
dca99fb6 | 624 | return read_task_thread_flags(tsk); |
1f50ddb4 | 625 | } |
885f82bf | 626 | |
26c4d75b | 627 | void speculation_ctrl_update(unsigned long tif) |
885f82bf | 628 | { |
2f5fb193 TG |
629 | unsigned long flags; |
630 | ||
01daf568 | 631 | /* Forced update. Make sure all relevant TIF flags are different */ |
2f5fb193 | 632 | local_irq_save(flags); |
01daf568 | 633 | __speculation_ctrl_update(~tif, tif); |
2f5fb193 | 634 | local_irq_restore(flags); |
885f82bf TG |
635 | } |
636 | ||
6d991ba5 TG |
637 | /* Called from seccomp/prctl update */ |
638 | void speculation_ctrl_update_current(void) | |
639 | { | |
640 | preempt_disable(); | |
641 | speculation_ctrl_update(speculation_ctrl_update_tif(current)); | |
642 | preempt_enable(); | |
643 | } | |
644 | ||
d8f0b353 TG |
645 | static inline void cr4_toggle_bits_irqsoff(unsigned long mask) |
646 | { | |
647 | unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4); | |
648 | ||
649 | newval = cr4 ^ mask; | |
650 | if (newval != cr4) { | |
651 | this_cpu_write(cpu_tlbstate.cr4, newval); | |
652 | __write_cr4(newval); | |
653 | } | |
654 | } | |
655 | ||
ff16701a | 656 | void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p) |
389d1fb1 | 657 | { |
af8b3cd3 | 658 | unsigned long tifp, tifn; |
389d1fb1 | 659 | |
dca99fb6 MR |
660 | tifn = read_task_thread_flags(next_p); |
661 | tifp = read_task_thread_flags(prev_p); | |
22fe5b04 TG |
662 | |
663 | switch_to_bitmap(tifp); | |
af8b3cd3 KH |
664 | |
665 | propagate_user_return_notify(prev_p, next_p); | |
666 | ||
b9894a2f KH |
667 | if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) && |
668 | arch_has_block_step()) { | |
669 | unsigned long debugctl, msk; | |
ea8e61b7 | 670 | |
b9894a2f | 671 | rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); |
ea8e61b7 | 672 | debugctl &= ~DEBUGCTLMSR_BTF; |
b9894a2f KH |
673 | msk = tifn & _TIF_BLOCKSTEP; |
674 | debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT; | |
675 | wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); | |
ea8e61b7 | 676 | } |
389d1fb1 | 677 | |
5a920155 | 678 | if ((tifp ^ tifn) & _TIF_NOTSC) |
9d0b6232 | 679 | cr4_toggle_bits_irqsoff(X86_CR4_TSD); |
e9ea1e7f KH |
680 | |
681 | if ((tifp ^ tifn) & _TIF_NOCPUID) | |
682 | set_cpuid_faulting(!!(tifn & _TIF_NOCPUID)); | |
885f82bf | 683 | |
6d991ba5 TG |
684 | if (likely(!((tifp | tifn) & _TIF_SPEC_FORCE_UPDATE))) { |
685 | __speculation_ctrl_update(tifp, tifn); | |
686 | } else { | |
687 | speculation_ctrl_update_tif(prev_p); | |
688 | tifn = speculation_ctrl_update_tif(next_p); | |
689 | ||
690 | /* Enforce MSR update to ensure consistent state */ | |
691 | __speculation_ctrl_update(~tifn, tifn); | |
692 | } | |
389d1fb1 JF |
693 | } |
694 | ||
00dba564 TG |
695 | /* |
696 | * Idle related variables and functions | |
697 | */ | |
d1896049 | 698 | unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; |
00dba564 TG |
699 | EXPORT_SYMBOL(boot_option_idle_override); |
700 | ||
aaa3896b PZ |
701 | /* |
702 | * We use this if we don't have any better idle routine.. | |
703 | */ | |
704 | void __cpuidle default_idle(void) | |
705 | { | |
706 | raw_safe_halt(); | |
89b30987 | 707 | raw_local_irq_disable(); |
aaa3896b PZ |
708 | } |
709 | #if defined(CONFIG_APM_MODULE) || defined(CONFIG_HALTPOLL_CPUIDLE_MODULE) | |
710 | EXPORT_SYMBOL(default_idle); | |
711 | #endif | |
712 | ||
713 | DEFINE_STATIC_CALL_NULL(x86_idle, default_idle); | |
714 | ||
715 | static bool x86_idle_set(void) | |
716 | { | |
717 | return !!static_call_query(x86_idle); | |
718 | } | |
00dba564 | 719 | |
90e24014 RW |
720 | #ifndef CONFIG_SMP |
721 | static inline void play_dead(void) | |
722 | { | |
723 | BUG(); | |
724 | } | |
725 | #endif | |
726 | ||
7d1a9417 TG |
727 | void arch_cpu_idle_enter(void) |
728 | { | |
6a369583 | 729 | tsc_verify_tsc_adjust(false); |
7d1a9417 | 730 | local_touch_nmi(); |
7d1a9417 | 731 | } |
90e24014 | 732 | |
7d1a9417 TG |
733 | void arch_cpu_idle_dead(void) |
734 | { | |
735 | play_dead(); | |
736 | } | |
90e24014 | 737 | |
7d1a9417 TG |
738 | /* |
739 | * Called from the generic idle code. | |
740 | */ | |
aaa3896b | 741 | void __cpuidle arch_cpu_idle(void) |
00dba564 | 742 | { |
aaa3896b | 743 | static_call(x86_idle)(); |
00dba564 | 744 | } |
716ff71a | 745 | EXPORT_SYMBOL_GPL(arch_cpu_idle); |
00dba564 | 746 | |
6a377ddc LB |
747 | #ifdef CONFIG_XEN |
748 | bool xen_set_default_idle(void) | |
e5fd47bf | 749 | { |
aaa3896b | 750 | bool ret = x86_idle_set(); |
e5fd47bf | 751 | |
aaa3896b | 752 | static_call_update(x86_idle, default_idle); |
e5fd47bf KRW |
753 | |
754 | return ret; | |
755 | } | |
6a377ddc | 756 | #endif |
bba4ed01 | 757 | |
f9cdf7ca | 758 | void __noreturn stop_this_cpu(void *dummy) |
d3ec5cae IV |
759 | { |
760 | local_irq_disable(); | |
761 | /* | |
762 | * Remove this CPU: | |
763 | */ | |
4f062896 | 764 | set_cpu_online(smp_processor_id(), false); |
d3ec5cae | 765 | disable_local_APIC(); |
8838eb6c | 766 | mcheck_cpu_clear(this_cpu_ptr(&cpu_info)); |
d3ec5cae | 767 | |
f23d74f6 TL |
768 | /* |
769 | * Use wbinvd on processors that support SME. This provides support | |
770 | * for performing a successful kexec when going from SME inactive | |
771 | * to SME active (or vice-versa). The cache must be cleared so that | |
772 | * if there are entries with the same physical address, both with and | |
773 | * without the encryption bit, they don't race each other when flushed | |
774 | * and potentially end up with the wrong entry being committed to | |
775 | * memory. | |
08f253ec ML |
776 | * |
777 | * Test the CPUID bit directly because the machine might've cleared | |
778 | * X86_FEATURE_SME due to cmdline options. | |
f23d74f6 | 779 | */ |
08f253ec | 780 | if (cpuid_eax(0x8000001f) & BIT(0)) |
f23d74f6 | 781 | native_wbinvd(); |
bba4ed01 TL |
782 | for (;;) { |
783 | /* | |
f23d74f6 TL |
784 | * Use native_halt() so that memory contents don't change |
785 | * (stack usage and variables) after possibly issuing the | |
786 | * native_wbinvd() above. | |
bba4ed01 | 787 | */ |
f23d74f6 | 788 | native_halt(); |
bba4ed01 | 789 | } |
7f424a8b PZ |
790 | } |
791 | ||
aa276e1c | 792 | /* |
07c94a38 BP |
793 | * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power |
794 | * states (local apic timer and TSC stop). | |
58c644ba PZ |
795 | * |
796 | * XXX this function is completely buggered vs RCU and tracing. | |
aa276e1c | 797 | */ |
02c68a02 | 798 | static void amd_e400_idle(void) |
aa276e1c | 799 | { |
07c94a38 BP |
800 | /* |
801 | * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E | |
802 | * gets set after static_cpu_has() places have been converted via | |
803 | * alternatives. | |
804 | */ | |
805 | if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { | |
806 | default_idle(); | |
807 | return; | |
aa276e1c TG |
808 | } |
809 | ||
07c94a38 | 810 | tick_broadcast_enter(); |
aa276e1c | 811 | |
07c94a38 | 812 | default_idle(); |
0beefa20 | 813 | |
07c94a38 | 814 | tick_broadcast_exit(); |
aa276e1c TG |
815 | } |
816 | ||
b253149b | 817 | /* |
aebef63c WK |
818 | * Prefer MWAIT over HALT if MWAIT is supported, MWAIT_CPUID leaf |
819 | * exists and whenever MONITOR/MWAIT extensions are present there is at | |
820 | * least one C1 substate. | |
b253149b | 821 | * |
aebef63c WK |
822 | * Do not prefer MWAIT if MONITOR instruction has a bug or idle=nomwait |
823 | * is passed to kernel commandline parameter. | |
b253149b LB |
824 | */ |
825 | static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c) | |
826 | { | |
aebef63c WK |
827 | u32 eax, ebx, ecx, edx; |
828 | ||
8bcedb4c WK |
829 | /* User has disallowed the use of MWAIT. Fallback to HALT */ |
830 | if (boot_option_idle_override == IDLE_NOMWAIT) | |
b253149b LB |
831 | return 0; |
832 | ||
aebef63c WK |
833 | /* MWAIT is not supported on this platform. Fallback to HALT */ |
834 | if (!cpu_has(c, X86_FEATURE_MWAIT)) | |
b253149b LB |
835 | return 0; |
836 | ||
aebef63c WK |
837 | /* Monitor has a bug. Fallback to HALT */ |
838 | if (boot_cpu_has_bug(X86_BUG_MONITOR)) | |
b253149b LB |
839 | return 0; |
840 | ||
aebef63c WK |
841 | cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx); |
842 | ||
843 | /* | |
844 | * If MWAIT extensions are not available, it is safe to use MWAIT | |
845 | * with EAX=0, ECX=0. | |
846 | */ | |
847 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) | |
848 | return 1; | |
849 | ||
850 | /* | |
851 | * If MWAIT extensions are available, there should be at least one | |
852 | * MWAIT C1 substate present. | |
853 | */ | |
854 | return (edx & MWAIT_C1_SUBSTATE_MASK); | |
b253149b LB |
855 | } |
856 | ||
857 | /* | |
0fb0328d HR |
858 | * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT |
859 | * with interrupts enabled and no flags, which is backwards compatible with the | |
860 | * original MWAIT implementation. | |
b253149b | 861 | */ |
6727ad9e | 862 | static __cpuidle void mwait_idle(void) |
b253149b | 863 | { |
f8e617f4 MG |
864 | if (!current_set_polling_and_test()) { |
865 | if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) { | |
ca59809f | 866 | mb(); /* quirk */ |
b253149b | 867 | clflush((void *)¤t_thread_info()->flags); |
ca59809f | 868 | mb(); /* quirk */ |
f8e617f4 | 869 | } |
b253149b LB |
870 | |
871 | __monitor((void *)¤t_thread_info()->flags, 0, 0); | |
89b30987 | 872 | if (!need_resched()) { |
b253149b | 873 | __sti_mwait(0, 0); |
89b30987 PZ |
874 | raw_local_irq_disable(); |
875 | } | |
f8e617f4 MG |
876 | } |
877 | __current_clr_polling(); | |
b253149b LB |
878 | } |
879 | ||
148f9bb8 | 880 | void select_idle_routine(const struct cpuinfo_x86 *c) |
7f424a8b | 881 | { |
3e5095d1 | 882 | #ifdef CONFIG_SMP |
7d1a9417 | 883 | if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1) |
c767a54b | 884 | pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n"); |
7f424a8b | 885 | #endif |
aaa3896b | 886 | if (x86_idle_set() || boot_option_idle_override == IDLE_POLL) |
6ddd2a27 TG |
887 | return; |
888 | ||
3344ed30 | 889 | if (boot_cpu_has_bug(X86_BUG_AMD_E400)) { |
c767a54b | 890 | pr_info("using AMD E400 aware idle routine\n"); |
aaa3896b | 891 | static_call_update(x86_idle, amd_e400_idle); |
b253149b LB |
892 | } else if (prefer_mwait_c1_over_halt(c)) { |
893 | pr_info("using mwait in idle threads\n"); | |
aaa3896b | 894 | static_call_update(x86_idle, mwait_idle); |
bfe6ed0c KS |
895 | } else if (cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) { |
896 | pr_info("using TDX aware idle routine\n"); | |
aaa3896b | 897 | static_call_update(x86_idle, tdx_safe_halt); |
6ddd2a27 | 898 | } else |
aaa3896b | 899 | static_call_update(x86_idle, default_idle); |
7f424a8b PZ |
900 | } |
901 | ||
07c94a38 | 902 | void amd_e400_c1e_apic_setup(void) |
30e1e6d1 | 903 | { |
07c94a38 BP |
904 | if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { |
905 | pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id()); | |
906 | local_irq_disable(); | |
907 | tick_broadcast_force(); | |
908 | local_irq_enable(); | |
909 | } | |
30e1e6d1 RR |
910 | } |
911 | ||
e7ff3a47 TG |
912 | void __init arch_post_acpi_subsys_init(void) |
913 | { | |
914 | u32 lo, hi; | |
915 | ||
916 | if (!boot_cpu_has_bug(X86_BUG_AMD_E400)) | |
917 | return; | |
918 | ||
919 | /* | |
920 | * AMD E400 detection needs to happen after ACPI has been enabled. If | |
921 | * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in | |
922 | * MSR_K8_INT_PENDING_MSG. | |
923 | */ | |
924 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); | |
925 | if (!(lo & K8_INTP_C1E_ACTIVE_MASK)) | |
926 | return; | |
927 | ||
928 | boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E); | |
929 | ||
930 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) | |
931 | mark_tsc_unstable("TSC halt in AMD C1E"); | |
932 | pr_info("System has AMD C1E enabled\n"); | |
933 | } | |
934 | ||
7f424a8b PZ |
935 | static int __init idle_setup(char *str) |
936 | { | |
ab6bc3e3 CG |
937 | if (!str) |
938 | return -EINVAL; | |
939 | ||
7f424a8b | 940 | if (!strcmp(str, "poll")) { |
c767a54b | 941 | pr_info("using polling idle threads\n"); |
d1896049 | 942 | boot_option_idle_override = IDLE_POLL; |
7d1a9417 | 943 | cpu_idle_poll_ctrl(true); |
d1896049 | 944 | } else if (!strcmp(str, "halt")) { |
c1e3b377 ZY |
945 | /* |
946 | * When the boot option of idle=halt is added, halt is | |
947 | * forced to be used for CPU idle. In such case CPU C2/C3 | |
948 | * won't be used again. | |
949 | * To continue to load the CPU idle driver, don't touch | |
950 | * the boot_option_idle_override. | |
951 | */ | |
aaa3896b | 952 | static_call_update(x86_idle, default_idle); |
d1896049 | 953 | boot_option_idle_override = IDLE_HALT; |
da5e09a1 ZY |
954 | } else if (!strcmp(str, "nomwait")) { |
955 | /* | |
956 | * If the boot option of "idle=nomwait" is added, | |
8bcedb4c WK |
957 | * it means that mwait will be disabled for CPU C1/C2/C3 |
958 | * states. | |
da5e09a1 | 959 | */ |
d1896049 | 960 | boot_option_idle_override = IDLE_NOMWAIT; |
c1e3b377 | 961 | } else |
7f424a8b PZ |
962 | return -1; |
963 | ||
7f424a8b PZ |
964 | return 0; |
965 | } | |
966 | early_param("idle", idle_setup); | |
967 | ||
9d62dcdf AW |
968 | unsigned long arch_align_stack(unsigned long sp) |
969 | { | |
970 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
8032bf12 | 971 | sp -= get_random_u32_below(8192); |
9d62dcdf AW |
972 | return sp & ~0xf; |
973 | } | |
974 | ||
975 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
976 | { | |
9c6f0902 | 977 | return randomize_page(mm->brk, 0x02000000); |
9d62dcdf AW |
978 | } |
979 | ||
7ba78053 TG |
980 | /* |
981 | * Called from fs/proc with a reference on @p to find the function | |
982 | * which called into schedule(). This needs to be done carefully | |
983 | * because the task might wake up and we might look at a stack | |
984 | * changing under us. | |
985 | */ | |
42a20f86 | 986 | unsigned long __get_wchan(struct task_struct *p) |
7ba78053 | 987 | { |
5d1ceb39 PZ |
988 | struct unwind_state state; |
989 | unsigned long addr = 0; | |
7ba78053 | 990 | |
0dc636b3 PZ |
991 | if (!try_get_task_stack(p)) |
992 | return 0; | |
993 | ||
5d1ceb39 PZ |
994 | for (unwind_start(&state, p, NULL, NULL); !unwind_done(&state); |
995 | unwind_next_frame(&state)) { | |
996 | addr = unwind_get_return_address(&state); | |
997 | if (!addr) | |
998 | break; | |
999 | if (in_sched_functions(addr)) | |
1000 | continue; | |
1001 | break; | |
1002 | } | |
1003 | ||
0dc636b3 PZ |
1004 | put_task_stack(p); |
1005 | ||
5d1ceb39 | 1006 | return addr; |
7ba78053 | 1007 | } |
b0b9b014 | 1008 | |
f5c0b4f3 | 1009 | long do_arch_prctl_common(int option, unsigned long arg2) |
b0b9b014 | 1010 | { |
e9ea1e7f KH |
1011 | switch (option) { |
1012 | case ARCH_GET_CPUID: | |
1013 | return get_cpuid_mode(); | |
1014 | case ARCH_SET_CPUID: | |
f5c0b4f3 | 1015 | return set_cpuid_mode(arg2); |
db8268df CB |
1016 | case ARCH_GET_XCOMP_SUPP: |
1017 | case ARCH_GET_XCOMP_PERM: | |
1018 | case ARCH_REQ_XCOMP_PERM: | |
980fe2fd TG |
1019 | case ARCH_GET_XCOMP_GUEST_PERM: |
1020 | case ARCH_REQ_XCOMP_GUEST_PERM: | |
f5c0b4f3 | 1021 | return fpu_xstate_prctl(option, arg2); |
e9ea1e7f KH |
1022 | } |
1023 | ||
b0b9b014 KH |
1024 | return -EINVAL; |
1025 | } |