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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
c767a54b JP |
2 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
3 | ||
61c4628b SS |
4 | #include <linux/errno.h> |
5 | #include <linux/kernel.h> | |
6 | #include <linux/mm.h> | |
7 | #include <linux/smp.h> | |
389d1fb1 | 8 | #include <linux/prctl.h> |
61c4628b SS |
9 | #include <linux/slab.h> |
10 | #include <linux/sched.h> | |
4c822698 | 11 | #include <linux/sched/idle.h> |
b17b0153 | 12 | #include <linux/sched/debug.h> |
29930025 | 13 | #include <linux/sched/task.h> |
68db0cf1 | 14 | #include <linux/sched/task_stack.h> |
186f4360 PG |
15 | #include <linux/init.h> |
16 | #include <linux/export.h> | |
7f424a8b | 17 | #include <linux/pm.h> |
162a688e | 18 | #include <linux/tick.h> |
9d62dcdf | 19 | #include <linux/random.h> |
7c68af6e | 20 | #include <linux/user-return-notifier.h> |
814e2c84 AI |
21 | #include <linux/dmi.h> |
22 | #include <linux/utsname.h> | |
90e24014 | 23 | #include <linux/stackprotector.h> |
90e24014 | 24 | #include <linux/cpuidle.h> |
61613521 | 25 | #include <trace/events/power.h> |
24f1e32c | 26 | #include <linux/hw_breakpoint.h> |
93789b32 | 27 | #include <asm/cpu.h> |
d3ec5cae | 28 | #include <asm/apic.h> |
2c1b284e | 29 | #include <asm/syscalls.h> |
7c0f6ba6 | 30 | #include <linux/uaccess.h> |
b253149b | 31 | #include <asm/mwait.h> |
78f7f1e5 | 32 | #include <asm/fpu/internal.h> |
66cb5917 | 33 | #include <asm/debugreg.h> |
90e24014 | 34 | #include <asm/nmi.h> |
375074cc | 35 | #include <asm/tlbflush.h> |
8838eb6c | 36 | #include <asm/mce.h> |
9fda6a06 | 37 | #include <asm/vm86.h> |
7b32aead | 38 | #include <asm/switch_to.h> |
b7ffc44d | 39 | #include <asm/desc.h> |
e9ea1e7f | 40 | #include <asm/prctl.h> |
885f82bf | 41 | #include <asm/spec-ctrl.h> |
90e24014 | 42 | |
ff16701a TG |
43 | #include "process.h" |
44 | ||
45046892 TG |
45 | /* |
46 | * per-CPU TSS segments. Threads are completely 'soft' on Linux, | |
47 | * no more per-task TSS's. The TSS size is kept cacheline-aligned | |
48 | * so they are allowed to end up in the .data..cacheline_aligned | |
49 | * section. Since TSS's are completely CPU-local, we want them | |
50 | * on exact cacheline boundaries, to eliminate cacheline ping-pong. | |
51 | */ | |
2fd9c41a | 52 | __visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = { |
d0a0de21 | 53 | .x86_tss = { |
20bb8344 AL |
54 | /* |
55 | * .sp0 is only used when entering ring 0 from a lower | |
56 | * privilege level. Since the init task never runs anything | |
57 | * but ring 0 code, there is no need for a valid value here. | |
58 | * Poison it. | |
59 | */ | |
60 | .sp0 = (1UL << (BITS_PER_LONG-1)) + 1, | |
9aaefe7b | 61 | |
9aaefe7b AL |
62 | /* |
63 | * .sp1 is cpu_current_top_of_stack. The init task never | |
64 | * runs user code, but cpu_current_top_of_stack should still | |
65 | * be well defined before the first context switch. | |
66 | */ | |
67 | .sp1 = TOP_OF_INIT_STACK, | |
9aaefe7b | 68 | |
d0a0de21 AL |
69 | #ifdef CONFIG_X86_32 |
70 | .ss0 = __KERNEL_DS, | |
71 | .ss1 = __KERNEL_CS, | |
72 | .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, | |
73 | #endif | |
74 | }, | |
75 | #ifdef CONFIG_X86_32 | |
76 | /* | |
77 | * Note that the .io_bitmap member must be extra-big. This is because | |
78 | * the CPU will access an additional byte beyond the end of the IO | |
79 | * permission bitmap. The extra byte must be all 1 bits, and must | |
80 | * be within the limit. | |
81 | */ | |
82 | .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, | |
83 | #endif | |
84 | }; | |
c482feef | 85 | EXPORT_PER_CPU_SYMBOL(cpu_tss_rw); |
45046892 | 86 | |
b7ceaec1 AL |
87 | DEFINE_PER_CPU(bool, __tss_limit_invalid); |
88 | EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid); | |
b7ffc44d | 89 | |
55ccf3fe SS |
90 | /* |
91 | * this gets called so that we can store lazy state into memory and copy the | |
92 | * current task into the new thread. | |
93 | */ | |
61c4628b SS |
94 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
95 | { | |
5aaeb5c0 | 96 | memcpy(dst, src, arch_task_struct_size); |
2459ee86 AL |
97 | #ifdef CONFIG_VM86 |
98 | dst->thread.vm86 = NULL; | |
99 | #endif | |
f1853505 | 100 | |
c69e098b | 101 | return fpu__copy(&dst->thread.fpu, &src->thread.fpu); |
61c4628b | 102 | } |
7f424a8b | 103 | |
389d1fb1 JF |
104 | /* |
105 | * Free current thread data structures etc.. | |
106 | */ | |
e6464694 | 107 | void exit_thread(struct task_struct *tsk) |
389d1fb1 | 108 | { |
e6464694 | 109 | struct thread_struct *t = &tsk->thread; |
250981e6 | 110 | unsigned long *bp = t->io_bitmap_ptr; |
ca6787ba | 111 | struct fpu *fpu = &t->fpu; |
389d1fb1 | 112 | |
250981e6 | 113 | if (bp) { |
c482feef | 114 | struct tss_struct *tss = &per_cpu(cpu_tss_rw, get_cpu()); |
389d1fb1 | 115 | |
389d1fb1 JF |
116 | t->io_bitmap_ptr = NULL; |
117 | clear_thread_flag(TIF_IO_BITMAP); | |
118 | /* | |
119 | * Careful, clear this in the TSS too: | |
120 | */ | |
121 | memset(tss->io_bitmap, 0xff, t->io_bitmap_max); | |
122 | t->io_bitmap_max = 0; | |
123 | put_cpu(); | |
250981e6 | 124 | kfree(bp); |
389d1fb1 | 125 | } |
1dcc8d7b | 126 | |
9fda6a06 BG |
127 | free_vm86(t); |
128 | ||
50338615 | 129 | fpu__drop(fpu); |
389d1fb1 JF |
130 | } |
131 | ||
132 | void flush_thread(void) | |
133 | { | |
134 | struct task_struct *tsk = current; | |
135 | ||
24f1e32c | 136 | flush_ptrace_hw_breakpoint(tsk); |
389d1fb1 | 137 | memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); |
110d7f75 | 138 | |
04c8e01d | 139 | fpu__clear(&tsk->thread.fpu); |
389d1fb1 JF |
140 | } |
141 | ||
389d1fb1 JF |
142 | void disable_TSC(void) |
143 | { | |
144 | preempt_disable(); | |
145 | if (!test_and_set_thread_flag(TIF_NOTSC)) | |
146 | /* | |
147 | * Must flip the CPU state synchronously with | |
148 | * TIF_NOTSC in the current running context. | |
149 | */ | |
5a920155 | 150 | cr4_set_bits(X86_CR4_TSD); |
389d1fb1 JF |
151 | preempt_enable(); |
152 | } | |
153 | ||
389d1fb1 JF |
154 | static void enable_TSC(void) |
155 | { | |
156 | preempt_disable(); | |
157 | if (test_and_clear_thread_flag(TIF_NOTSC)) | |
158 | /* | |
159 | * Must flip the CPU state synchronously with | |
160 | * TIF_NOTSC in the current running context. | |
161 | */ | |
5a920155 | 162 | cr4_clear_bits(X86_CR4_TSD); |
389d1fb1 JF |
163 | preempt_enable(); |
164 | } | |
165 | ||
166 | int get_tsc_mode(unsigned long adr) | |
167 | { | |
168 | unsigned int val; | |
169 | ||
170 | if (test_thread_flag(TIF_NOTSC)) | |
171 | val = PR_TSC_SIGSEGV; | |
172 | else | |
173 | val = PR_TSC_ENABLE; | |
174 | ||
175 | return put_user(val, (unsigned int __user *)adr); | |
176 | } | |
177 | ||
178 | int set_tsc_mode(unsigned int val) | |
179 | { | |
180 | if (val == PR_TSC_SIGSEGV) | |
181 | disable_TSC(); | |
182 | else if (val == PR_TSC_ENABLE) | |
183 | enable_TSC(); | |
184 | else | |
185 | return -EINVAL; | |
186 | ||
187 | return 0; | |
188 | } | |
189 | ||
e9ea1e7f KH |
190 | DEFINE_PER_CPU(u64, msr_misc_features_shadow); |
191 | ||
192 | static void set_cpuid_faulting(bool on) | |
193 | { | |
194 | u64 msrval; | |
195 | ||
196 | msrval = this_cpu_read(msr_misc_features_shadow); | |
197 | msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT; | |
198 | msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT); | |
199 | this_cpu_write(msr_misc_features_shadow, msrval); | |
200 | wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval); | |
201 | } | |
202 | ||
203 | static void disable_cpuid(void) | |
204 | { | |
205 | preempt_disable(); | |
206 | if (!test_and_set_thread_flag(TIF_NOCPUID)) { | |
207 | /* | |
208 | * Must flip the CPU state synchronously with | |
209 | * TIF_NOCPUID in the current running context. | |
210 | */ | |
211 | set_cpuid_faulting(true); | |
212 | } | |
213 | preempt_enable(); | |
214 | } | |
215 | ||
216 | static void enable_cpuid(void) | |
217 | { | |
218 | preempt_disable(); | |
219 | if (test_and_clear_thread_flag(TIF_NOCPUID)) { | |
220 | /* | |
221 | * Must flip the CPU state synchronously with | |
222 | * TIF_NOCPUID in the current running context. | |
223 | */ | |
224 | set_cpuid_faulting(false); | |
225 | } | |
226 | preempt_enable(); | |
227 | } | |
228 | ||
229 | static int get_cpuid_mode(void) | |
230 | { | |
231 | return !test_thread_flag(TIF_NOCPUID); | |
232 | } | |
233 | ||
234 | static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled) | |
235 | { | |
236 | if (!static_cpu_has(X86_FEATURE_CPUID_FAULT)) | |
237 | return -ENODEV; | |
238 | ||
239 | if (cpuid_enabled) | |
240 | enable_cpuid(); | |
241 | else | |
242 | disable_cpuid(); | |
243 | ||
244 | return 0; | |
245 | } | |
246 | ||
247 | /* | |
248 | * Called immediately after a successful exec. | |
249 | */ | |
250 | void arch_setup_new_exec(void) | |
251 | { | |
252 | /* If cpuid was previously disabled for this task, re-enable it. */ | |
253 | if (test_thread_flag(TIF_NOCPUID)) | |
254 | enable_cpuid(); | |
255 | } | |
256 | ||
ff16701a | 257 | static inline void switch_to_bitmap(struct thread_struct *prev, |
af8b3cd3 KH |
258 | struct thread_struct *next, |
259 | unsigned long tifp, unsigned long tifn) | |
260 | { | |
ff16701a TG |
261 | struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); |
262 | ||
af8b3cd3 KH |
263 | if (tifn & _TIF_IO_BITMAP) { |
264 | /* | |
265 | * Copy the relevant range of the IO bitmap. | |
266 | * Normally this is 128 bytes or less: | |
267 | */ | |
268 | memcpy(tss->io_bitmap, next->io_bitmap_ptr, | |
269 | max(prev->io_bitmap_max, next->io_bitmap_max)); | |
270 | /* | |
271 | * Make sure that the TSS limit is correct for the CPU | |
272 | * to notice the IO bitmap. | |
273 | */ | |
274 | refresh_tss_limit(); | |
275 | } else if (tifp & _TIF_IO_BITMAP) { | |
276 | /* | |
277 | * Clear any possible leftover bits: | |
278 | */ | |
279 | memset(tss->io_bitmap, 0xff, prev->io_bitmap_max); | |
280 | } | |
281 | } | |
282 | ||
1f50ddb4 TG |
283 | #ifdef CONFIG_SMP |
284 | ||
285 | struct ssb_state { | |
286 | struct ssb_state *shared_state; | |
287 | raw_spinlock_t lock; | |
288 | unsigned int disable_state; | |
289 | unsigned long local_state; | |
290 | }; | |
291 | ||
292 | #define LSTATE_SSB 0 | |
293 | ||
294 | static DEFINE_PER_CPU(struct ssb_state, ssb_state); | |
295 | ||
296 | void speculative_store_bypass_ht_init(void) | |
885f82bf | 297 | { |
1f50ddb4 TG |
298 | struct ssb_state *st = this_cpu_ptr(&ssb_state); |
299 | unsigned int this_cpu = smp_processor_id(); | |
300 | unsigned int cpu; | |
301 | ||
302 | st->local_state = 0; | |
303 | ||
304 | /* | |
305 | * Shared state setup happens once on the first bringup | |
306 | * of the CPU. It's not destroyed on CPU hotunplug. | |
307 | */ | |
308 | if (st->shared_state) | |
309 | return; | |
310 | ||
311 | raw_spin_lock_init(&st->lock); | |
312 | ||
313 | /* | |
314 | * Go over HT siblings and check whether one of them has set up the | |
315 | * shared state pointer already. | |
316 | */ | |
317 | for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) { | |
318 | if (cpu == this_cpu) | |
319 | continue; | |
320 | ||
321 | if (!per_cpu(ssb_state, cpu).shared_state) | |
322 | continue; | |
323 | ||
324 | /* Link it to the state of the sibling: */ | |
325 | st->shared_state = per_cpu(ssb_state, cpu).shared_state; | |
326 | return; | |
327 | } | |
328 | ||
329 | /* | |
330 | * First HT sibling to come up on the core. Link shared state of | |
331 | * the first HT sibling to itself. The siblings on the same core | |
332 | * which come up later will see the shared state pointer and link | |
333 | * themself to the state of this CPU. | |
334 | */ | |
335 | st->shared_state = st; | |
336 | } | |
885f82bf | 337 | |
1f50ddb4 TG |
338 | /* |
339 | * Logic is: First HT sibling enables SSBD for both siblings in the core | |
340 | * and last sibling to disable it, disables it for the whole core. This how | |
341 | * MSR_SPEC_CTRL works in "hardware": | |
342 | * | |
343 | * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL | |
344 | */ | |
345 | static __always_inline void amd_set_core_ssb_state(unsigned long tifn) | |
346 | { | |
347 | struct ssb_state *st = this_cpu_ptr(&ssb_state); | |
348 | u64 msr = x86_amd_ls_cfg_base; | |
349 | ||
350 | if (!static_cpu_has(X86_FEATURE_ZEN)) { | |
351 | msr |= ssbd_tif_to_amd_ls_cfg(tifn); | |
885f82bf | 352 | wrmsrl(MSR_AMD64_LS_CFG, msr); |
1f50ddb4 TG |
353 | return; |
354 | } | |
355 | ||
356 | if (tifn & _TIF_SSBD) { | |
357 | /* | |
358 | * Since this can race with prctl(), block reentry on the | |
359 | * same CPU. | |
360 | */ | |
361 | if (__test_and_set_bit(LSTATE_SSB, &st->local_state)) | |
362 | return; | |
363 | ||
364 | msr |= x86_amd_ls_cfg_ssbd_mask; | |
365 | ||
366 | raw_spin_lock(&st->shared_state->lock); | |
367 | /* First sibling enables SSBD: */ | |
368 | if (!st->shared_state->disable_state) | |
369 | wrmsrl(MSR_AMD64_LS_CFG, msr); | |
370 | st->shared_state->disable_state++; | |
371 | raw_spin_unlock(&st->shared_state->lock); | |
885f82bf | 372 | } else { |
1f50ddb4 TG |
373 | if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state)) |
374 | return; | |
375 | ||
376 | raw_spin_lock(&st->shared_state->lock); | |
377 | st->shared_state->disable_state--; | |
378 | if (!st->shared_state->disable_state) | |
379 | wrmsrl(MSR_AMD64_LS_CFG, msr); | |
380 | raw_spin_unlock(&st->shared_state->lock); | |
885f82bf TG |
381 | } |
382 | } | |
1f50ddb4 TG |
383 | #else |
384 | static __always_inline void amd_set_core_ssb_state(unsigned long tifn) | |
385 | { | |
386 | u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn); | |
387 | ||
388 | wrmsrl(MSR_AMD64_LS_CFG, msr); | |
389 | } | |
390 | #endif | |
391 | ||
11fb0683 TL |
392 | static __always_inline void amd_set_ssb_virt_state(unsigned long tifn) |
393 | { | |
394 | /* | |
395 | * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL, | |
396 | * so ssbd_tif_to_spec_ctrl() just works. | |
397 | */ | |
398 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn)); | |
399 | } | |
400 | ||
01daf568 TC |
401 | /* |
402 | * Update the MSRs managing speculation control, during context switch. | |
403 | * | |
404 | * tifp: Previous task's thread flags | |
405 | * tifn: Next task's thread flags | |
406 | */ | |
407 | static __always_inline void __speculation_ctrl_update(unsigned long tifp, | |
408 | unsigned long tifn) | |
1f50ddb4 | 409 | { |
5bfbe3ad | 410 | unsigned long tif_diff = tifp ^ tifn; |
01daf568 TC |
411 | u64 msr = x86_spec_ctrl_base; |
412 | bool updmsr = false; | |
413 | ||
5bfbe3ad TC |
414 | /* |
415 | * If TIF_SSBD is different, select the proper mitigation | |
416 | * method. Note that if SSBD mitigation is disabled or permanentely | |
417 | * enabled this branch can't be taken because nothing can set | |
418 | * TIF_SSBD. | |
419 | */ | |
420 | if (tif_diff & _TIF_SSBD) { | |
01daf568 TC |
421 | if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) { |
422 | amd_set_ssb_virt_state(tifn); | |
423 | } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) { | |
424 | amd_set_core_ssb_state(tifn); | |
425 | } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || | |
426 | static_cpu_has(X86_FEATURE_AMD_SSBD)) { | |
427 | msr |= ssbd_tif_to_spec_ctrl(tifn); | |
428 | updmsr = true; | |
429 | } | |
430 | } | |
1f50ddb4 | 431 | |
5bfbe3ad TC |
432 | /* |
433 | * Only evaluate TIF_SPEC_IB if conditional STIBP is enabled, | |
434 | * otherwise avoid the MSR write. | |
435 | */ | |
436 | if (IS_ENABLED(CONFIG_SMP) && | |
437 | static_branch_unlikely(&switch_to_cond_stibp)) { | |
438 | updmsr |= !!(tif_diff & _TIF_SPEC_IB); | |
439 | msr |= stibp_tif_to_spec_ctrl(tifn); | |
440 | } | |
441 | ||
01daf568 TC |
442 | if (updmsr) |
443 | wrmsrl(MSR_IA32_SPEC_CTRL, msr); | |
1f50ddb4 | 444 | } |
885f82bf | 445 | |
6d991ba5 TG |
446 | static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk) |
447 | { | |
448 | if (test_and_clear_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE)) { | |
449 | if (task_spec_ssb_disable(tsk)) | |
450 | set_tsk_thread_flag(tsk, TIF_SSBD); | |
451 | else | |
452 | clear_tsk_thread_flag(tsk, TIF_SSBD); | |
453 | } | |
454 | /* Return the updated threadinfo flags*/ | |
455 | return task_thread_info(tsk)->flags; | |
456 | } | |
457 | ||
26c4d75b | 458 | void speculation_ctrl_update(unsigned long tif) |
885f82bf | 459 | { |
01daf568 | 460 | /* Forced update. Make sure all relevant TIF flags are different */ |
1f50ddb4 | 461 | preempt_disable(); |
01daf568 | 462 | __speculation_ctrl_update(~tif, tif); |
1f50ddb4 | 463 | preempt_enable(); |
885f82bf TG |
464 | } |
465 | ||
6d991ba5 TG |
466 | /* Called from seccomp/prctl update */ |
467 | void speculation_ctrl_update_current(void) | |
468 | { | |
469 | preempt_disable(); | |
470 | speculation_ctrl_update(speculation_ctrl_update_tif(current)); | |
471 | preempt_enable(); | |
472 | } | |
473 | ||
ff16701a | 474 | void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p) |
389d1fb1 JF |
475 | { |
476 | struct thread_struct *prev, *next; | |
af8b3cd3 | 477 | unsigned long tifp, tifn; |
389d1fb1 JF |
478 | |
479 | prev = &prev_p->thread; | |
480 | next = &next_p->thread; | |
481 | ||
af8b3cd3 KH |
482 | tifn = READ_ONCE(task_thread_info(next_p)->flags); |
483 | tifp = READ_ONCE(task_thread_info(prev_p)->flags); | |
ff16701a | 484 | switch_to_bitmap(prev, next, tifp, tifn); |
af8b3cd3 KH |
485 | |
486 | propagate_user_return_notify(prev_p, next_p); | |
487 | ||
b9894a2f KH |
488 | if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) && |
489 | arch_has_block_step()) { | |
490 | unsigned long debugctl, msk; | |
ea8e61b7 | 491 | |
b9894a2f | 492 | rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); |
ea8e61b7 | 493 | debugctl &= ~DEBUGCTLMSR_BTF; |
b9894a2f KH |
494 | msk = tifn & _TIF_BLOCKSTEP; |
495 | debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT; | |
496 | wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); | |
ea8e61b7 | 497 | } |
389d1fb1 | 498 | |
5a920155 | 499 | if ((tifp ^ tifn) & _TIF_NOTSC) |
9d0b6232 | 500 | cr4_toggle_bits_irqsoff(X86_CR4_TSD); |
e9ea1e7f KH |
501 | |
502 | if ((tifp ^ tifn) & _TIF_NOCPUID) | |
503 | set_cpuid_faulting(!!(tifn & _TIF_NOCPUID)); | |
885f82bf | 504 | |
6d991ba5 TG |
505 | if (likely(!((tifp | tifn) & _TIF_SPEC_FORCE_UPDATE))) { |
506 | __speculation_ctrl_update(tifp, tifn); | |
507 | } else { | |
508 | speculation_ctrl_update_tif(prev_p); | |
509 | tifn = speculation_ctrl_update_tif(next_p); | |
510 | ||
511 | /* Enforce MSR update to ensure consistent state */ | |
512 | __speculation_ctrl_update(~tifn, tifn); | |
513 | } | |
389d1fb1 JF |
514 | } |
515 | ||
00dba564 TG |
516 | /* |
517 | * Idle related variables and functions | |
518 | */ | |
d1896049 | 519 | unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; |
00dba564 TG |
520 | EXPORT_SYMBOL(boot_option_idle_override); |
521 | ||
a476bda3 | 522 | static void (*x86_idle)(void); |
00dba564 | 523 | |
90e24014 RW |
524 | #ifndef CONFIG_SMP |
525 | static inline void play_dead(void) | |
526 | { | |
527 | BUG(); | |
528 | } | |
529 | #endif | |
530 | ||
7d1a9417 TG |
531 | void arch_cpu_idle_enter(void) |
532 | { | |
6a369583 | 533 | tsc_verify_tsc_adjust(false); |
7d1a9417 | 534 | local_touch_nmi(); |
7d1a9417 | 535 | } |
90e24014 | 536 | |
7d1a9417 TG |
537 | void arch_cpu_idle_dead(void) |
538 | { | |
539 | play_dead(); | |
540 | } | |
90e24014 | 541 | |
7d1a9417 TG |
542 | /* |
543 | * Called from the generic idle code. | |
544 | */ | |
545 | void arch_cpu_idle(void) | |
546 | { | |
16f8b05a | 547 | x86_idle(); |
90e24014 RW |
548 | } |
549 | ||
00dba564 | 550 | /* |
7d1a9417 | 551 | * We use this if we don't have any better idle routine.. |
00dba564 | 552 | */ |
6727ad9e | 553 | void __cpuidle default_idle(void) |
00dba564 | 554 | { |
4d0e42cc | 555 | trace_cpu_idle_rcuidle(1, smp_processor_id()); |
7d1a9417 | 556 | safe_halt(); |
4d0e42cc | 557 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); |
00dba564 | 558 | } |
60b8b1de | 559 | #ifdef CONFIG_APM_MODULE |
00dba564 TG |
560 | EXPORT_SYMBOL(default_idle); |
561 | #endif | |
562 | ||
6a377ddc LB |
563 | #ifdef CONFIG_XEN |
564 | bool xen_set_default_idle(void) | |
e5fd47bf | 565 | { |
a476bda3 | 566 | bool ret = !!x86_idle; |
e5fd47bf | 567 | |
a476bda3 | 568 | x86_idle = default_idle; |
e5fd47bf KRW |
569 | |
570 | return ret; | |
571 | } | |
6a377ddc | 572 | #endif |
bba4ed01 | 573 | |
d3ec5cae IV |
574 | void stop_this_cpu(void *dummy) |
575 | { | |
576 | local_irq_disable(); | |
577 | /* | |
578 | * Remove this CPU: | |
579 | */ | |
4f062896 | 580 | set_cpu_online(smp_processor_id(), false); |
d3ec5cae | 581 | disable_local_APIC(); |
8838eb6c | 582 | mcheck_cpu_clear(this_cpu_ptr(&cpu_info)); |
d3ec5cae | 583 | |
f23d74f6 TL |
584 | /* |
585 | * Use wbinvd on processors that support SME. This provides support | |
586 | * for performing a successful kexec when going from SME inactive | |
587 | * to SME active (or vice-versa). The cache must be cleared so that | |
588 | * if there are entries with the same physical address, both with and | |
589 | * without the encryption bit, they don't race each other when flushed | |
590 | * and potentially end up with the wrong entry being committed to | |
591 | * memory. | |
592 | */ | |
593 | if (boot_cpu_has(X86_FEATURE_SME)) | |
594 | native_wbinvd(); | |
bba4ed01 TL |
595 | for (;;) { |
596 | /* | |
f23d74f6 TL |
597 | * Use native_halt() so that memory contents don't change |
598 | * (stack usage and variables) after possibly issuing the | |
599 | * native_wbinvd() above. | |
bba4ed01 | 600 | */ |
f23d74f6 | 601 | native_halt(); |
bba4ed01 | 602 | } |
7f424a8b PZ |
603 | } |
604 | ||
aa276e1c | 605 | /* |
07c94a38 BP |
606 | * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power |
607 | * states (local apic timer and TSC stop). | |
aa276e1c | 608 | */ |
02c68a02 | 609 | static void amd_e400_idle(void) |
aa276e1c | 610 | { |
07c94a38 BP |
611 | /* |
612 | * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E | |
613 | * gets set after static_cpu_has() places have been converted via | |
614 | * alternatives. | |
615 | */ | |
616 | if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { | |
617 | default_idle(); | |
618 | return; | |
aa276e1c TG |
619 | } |
620 | ||
07c94a38 | 621 | tick_broadcast_enter(); |
aa276e1c | 622 | |
07c94a38 | 623 | default_idle(); |
0beefa20 | 624 | |
07c94a38 BP |
625 | /* |
626 | * The switch back from broadcast mode needs to be called with | |
627 | * interrupts disabled. | |
628 | */ | |
629 | local_irq_disable(); | |
630 | tick_broadcast_exit(); | |
631 | local_irq_enable(); | |
aa276e1c TG |
632 | } |
633 | ||
b253149b LB |
634 | /* |
635 | * Intel Core2 and older machines prefer MWAIT over HALT for C1. | |
636 | * We can't rely on cpuidle installing MWAIT, because it will not load | |
637 | * on systems that support only C1 -- so the boot default must be MWAIT. | |
638 | * | |
639 | * Some AMD machines are the opposite, they depend on using HALT. | |
640 | * | |
641 | * So for default C1, which is used during boot until cpuidle loads, | |
642 | * use MWAIT-C1 on Intel HW that has it, else use HALT. | |
643 | */ | |
644 | static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c) | |
645 | { | |
646 | if (c->x86_vendor != X86_VENDOR_INTEL) | |
647 | return 0; | |
648 | ||
08e237fa | 649 | if (!cpu_has(c, X86_FEATURE_MWAIT) || static_cpu_has_bug(X86_BUG_MONITOR)) |
b253149b LB |
650 | return 0; |
651 | ||
652 | return 1; | |
653 | } | |
654 | ||
655 | /* | |
0fb0328d HR |
656 | * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT |
657 | * with interrupts enabled and no flags, which is backwards compatible with the | |
658 | * original MWAIT implementation. | |
b253149b | 659 | */ |
6727ad9e | 660 | static __cpuidle void mwait_idle(void) |
b253149b | 661 | { |
f8e617f4 | 662 | if (!current_set_polling_and_test()) { |
e43d0189 | 663 | trace_cpu_idle_rcuidle(1, smp_processor_id()); |
f8e617f4 | 664 | if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) { |
ca59809f | 665 | mb(); /* quirk */ |
b253149b | 666 | clflush((void *)¤t_thread_info()->flags); |
ca59809f | 667 | mb(); /* quirk */ |
f8e617f4 | 668 | } |
b253149b LB |
669 | |
670 | __monitor((void *)¤t_thread_info()->flags, 0, 0); | |
b253149b LB |
671 | if (!need_resched()) |
672 | __sti_mwait(0, 0); | |
673 | else | |
674 | local_irq_enable(); | |
e43d0189 | 675 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); |
f8e617f4 | 676 | } else { |
b253149b | 677 | local_irq_enable(); |
f8e617f4 MG |
678 | } |
679 | __current_clr_polling(); | |
b253149b LB |
680 | } |
681 | ||
148f9bb8 | 682 | void select_idle_routine(const struct cpuinfo_x86 *c) |
7f424a8b | 683 | { |
3e5095d1 | 684 | #ifdef CONFIG_SMP |
7d1a9417 | 685 | if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1) |
c767a54b | 686 | pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n"); |
7f424a8b | 687 | #endif |
7d1a9417 | 688 | if (x86_idle || boot_option_idle_override == IDLE_POLL) |
6ddd2a27 TG |
689 | return; |
690 | ||
3344ed30 | 691 | if (boot_cpu_has_bug(X86_BUG_AMD_E400)) { |
c767a54b | 692 | pr_info("using AMD E400 aware idle routine\n"); |
a476bda3 | 693 | x86_idle = amd_e400_idle; |
b253149b LB |
694 | } else if (prefer_mwait_c1_over_halt(c)) { |
695 | pr_info("using mwait in idle threads\n"); | |
696 | x86_idle = mwait_idle; | |
6ddd2a27 | 697 | } else |
a476bda3 | 698 | x86_idle = default_idle; |
7f424a8b PZ |
699 | } |
700 | ||
07c94a38 | 701 | void amd_e400_c1e_apic_setup(void) |
30e1e6d1 | 702 | { |
07c94a38 BP |
703 | if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { |
704 | pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id()); | |
705 | local_irq_disable(); | |
706 | tick_broadcast_force(); | |
707 | local_irq_enable(); | |
708 | } | |
30e1e6d1 RR |
709 | } |
710 | ||
e7ff3a47 TG |
711 | void __init arch_post_acpi_subsys_init(void) |
712 | { | |
713 | u32 lo, hi; | |
714 | ||
715 | if (!boot_cpu_has_bug(X86_BUG_AMD_E400)) | |
716 | return; | |
717 | ||
718 | /* | |
719 | * AMD E400 detection needs to happen after ACPI has been enabled. If | |
720 | * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in | |
721 | * MSR_K8_INT_PENDING_MSG. | |
722 | */ | |
723 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); | |
724 | if (!(lo & K8_INTP_C1E_ACTIVE_MASK)) | |
725 | return; | |
726 | ||
727 | boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E); | |
728 | ||
729 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) | |
730 | mark_tsc_unstable("TSC halt in AMD C1E"); | |
731 | pr_info("System has AMD C1E enabled\n"); | |
732 | } | |
733 | ||
7f424a8b PZ |
734 | static int __init idle_setup(char *str) |
735 | { | |
ab6bc3e3 CG |
736 | if (!str) |
737 | return -EINVAL; | |
738 | ||
7f424a8b | 739 | if (!strcmp(str, "poll")) { |
c767a54b | 740 | pr_info("using polling idle threads\n"); |
d1896049 | 741 | boot_option_idle_override = IDLE_POLL; |
7d1a9417 | 742 | cpu_idle_poll_ctrl(true); |
d1896049 | 743 | } else if (!strcmp(str, "halt")) { |
c1e3b377 ZY |
744 | /* |
745 | * When the boot option of idle=halt is added, halt is | |
746 | * forced to be used for CPU idle. In such case CPU C2/C3 | |
747 | * won't be used again. | |
748 | * To continue to load the CPU idle driver, don't touch | |
749 | * the boot_option_idle_override. | |
750 | */ | |
a476bda3 | 751 | x86_idle = default_idle; |
d1896049 | 752 | boot_option_idle_override = IDLE_HALT; |
da5e09a1 ZY |
753 | } else if (!strcmp(str, "nomwait")) { |
754 | /* | |
755 | * If the boot option of "idle=nomwait" is added, | |
756 | * it means that mwait will be disabled for CPU C2/C3 | |
757 | * states. In such case it won't touch the variable | |
758 | * of boot_option_idle_override. | |
759 | */ | |
d1896049 | 760 | boot_option_idle_override = IDLE_NOMWAIT; |
c1e3b377 | 761 | } else |
7f424a8b PZ |
762 | return -1; |
763 | ||
7f424a8b PZ |
764 | return 0; |
765 | } | |
766 | early_param("idle", idle_setup); | |
767 | ||
9d62dcdf AW |
768 | unsigned long arch_align_stack(unsigned long sp) |
769 | { | |
770 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
771 | sp -= get_random_int() % 8192; | |
772 | return sp & ~0xf; | |
773 | } | |
774 | ||
775 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
776 | { | |
9c6f0902 | 777 | return randomize_page(mm->brk, 0x02000000); |
9d62dcdf AW |
778 | } |
779 | ||
7ba78053 TG |
780 | /* |
781 | * Called from fs/proc with a reference on @p to find the function | |
782 | * which called into schedule(). This needs to be done carefully | |
783 | * because the task might wake up and we might look at a stack | |
784 | * changing under us. | |
785 | */ | |
786 | unsigned long get_wchan(struct task_struct *p) | |
787 | { | |
74327a3e | 788 | unsigned long start, bottom, top, sp, fp, ip, ret = 0; |
7ba78053 TG |
789 | int count = 0; |
790 | ||
791 | if (!p || p == current || p->state == TASK_RUNNING) | |
792 | return 0; | |
793 | ||
74327a3e AL |
794 | if (!try_get_task_stack(p)) |
795 | return 0; | |
796 | ||
7ba78053 TG |
797 | start = (unsigned long)task_stack_page(p); |
798 | if (!start) | |
74327a3e | 799 | goto out; |
7ba78053 TG |
800 | |
801 | /* | |
802 | * Layout of the stack page: | |
803 | * | |
804 | * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long) | |
805 | * PADDING | |
806 | * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING | |
807 | * stack | |
15f4eae7 | 808 | * ----------- bottom = start |
7ba78053 TG |
809 | * |
810 | * The tasks stack pointer points at the location where the | |
811 | * framepointer is stored. The data on the stack is: | |
812 | * ... IP FP ... IP FP | |
813 | * | |
814 | * We need to read FP and IP, so we need to adjust the upper | |
815 | * bound by another unsigned long. | |
816 | */ | |
817 | top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; | |
818 | top -= 2 * sizeof(unsigned long); | |
15f4eae7 | 819 | bottom = start; |
7ba78053 TG |
820 | |
821 | sp = READ_ONCE(p->thread.sp); | |
822 | if (sp < bottom || sp > top) | |
74327a3e | 823 | goto out; |
7ba78053 | 824 | |
7b32aead | 825 | fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp); |
7ba78053 TG |
826 | do { |
827 | if (fp < bottom || fp > top) | |
74327a3e | 828 | goto out; |
f7d27c35 | 829 | ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long))); |
74327a3e AL |
830 | if (!in_sched_functions(ip)) { |
831 | ret = ip; | |
832 | goto out; | |
833 | } | |
f7d27c35 | 834 | fp = READ_ONCE_NOCHECK(*(unsigned long *)fp); |
7ba78053 | 835 | } while (count++ < 16 && p->state != TASK_RUNNING); |
74327a3e AL |
836 | |
837 | out: | |
838 | put_task_stack(p); | |
839 | return ret; | |
7ba78053 | 840 | } |
b0b9b014 KH |
841 | |
842 | long do_arch_prctl_common(struct task_struct *task, int option, | |
843 | unsigned long cpuid_enabled) | |
844 | { | |
e9ea1e7f KH |
845 | switch (option) { |
846 | case ARCH_GET_CPUID: | |
847 | return get_cpuid_mode(); | |
848 | case ARCH_SET_CPUID: | |
849 | return set_cpuid_mode(task, cpuid_enabled); | |
850 | } | |
851 | ||
b0b9b014 KH |
852 | return -EINVAL; |
853 | } |