Commit | Line | Data |
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61c4628b SS |
1 | #include <linux/errno.h> |
2 | #include <linux/kernel.h> | |
3 | #include <linux/mm.h> | |
4 | #include <linux/smp.h> | |
5 | #include <linux/slab.h> | |
6 | #include <linux/sched.h> | |
7f424a8b PZ |
7 | #include <linux/module.h> |
8 | #include <linux/pm.h> | |
aa276e1c | 9 | #include <linux/clockchips.h> |
c1e3b377 ZY |
10 | #include <asm/system.h> |
11 | ||
12 | unsigned long idle_halt; | |
13 | EXPORT_SYMBOL(idle_halt); | |
da5e09a1 ZY |
14 | unsigned long idle_nomwait; |
15 | EXPORT_SYMBOL(idle_nomwait); | |
61c4628b | 16 | |
aa283f49 | 17 | struct kmem_cache *task_xstate_cachep; |
61c4628b SS |
18 | |
19 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) | |
20 | { | |
21 | *dst = *src; | |
aa283f49 SS |
22 | if (src->thread.xstate) { |
23 | dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep, | |
24 | GFP_KERNEL); | |
25 | if (!dst->thread.xstate) | |
26 | return -ENOMEM; | |
27 | WARN_ON((unsigned long)dst->thread.xstate & 15); | |
28 | memcpy(dst->thread.xstate, src->thread.xstate, xstate_size); | |
29 | } | |
61c4628b SS |
30 | return 0; |
31 | } | |
32 | ||
aa283f49 | 33 | void free_thread_xstate(struct task_struct *tsk) |
61c4628b | 34 | { |
aa283f49 SS |
35 | if (tsk->thread.xstate) { |
36 | kmem_cache_free(task_xstate_cachep, tsk->thread.xstate); | |
37 | tsk->thread.xstate = NULL; | |
38 | } | |
39 | } | |
40 | ||
aa283f49 SS |
41 | void free_thread_info(struct thread_info *ti) |
42 | { | |
43 | free_thread_xstate(ti->task); | |
1679f271 | 44 | free_pages((unsigned long)ti, get_order(THREAD_SIZE)); |
61c4628b SS |
45 | } |
46 | ||
47 | void arch_task_cache_init(void) | |
48 | { | |
49 | task_xstate_cachep = | |
50 | kmem_cache_create("task_xstate", xstate_size, | |
51 | __alignof__(union thread_xstate), | |
52 | SLAB_PANIC, NULL); | |
53 | } | |
7f424a8b | 54 | |
00dba564 TG |
55 | /* |
56 | * Idle related variables and functions | |
57 | */ | |
58 | unsigned long boot_option_idle_override = 0; | |
59 | EXPORT_SYMBOL(boot_option_idle_override); | |
60 | ||
61 | /* | |
62 | * Powermanagement idle function, if any.. | |
63 | */ | |
64 | void (*pm_idle)(void); | |
65 | EXPORT_SYMBOL(pm_idle); | |
66 | ||
67 | #ifdef CONFIG_X86_32 | |
68 | /* | |
69 | * This halt magic was a workaround for ancient floppy DMA | |
70 | * wreckage. It should be safe to remove. | |
71 | */ | |
72 | static int hlt_counter; | |
73 | void disable_hlt(void) | |
74 | { | |
75 | hlt_counter++; | |
76 | } | |
77 | EXPORT_SYMBOL(disable_hlt); | |
78 | ||
79 | void enable_hlt(void) | |
80 | { | |
81 | hlt_counter--; | |
82 | } | |
83 | EXPORT_SYMBOL(enable_hlt); | |
84 | ||
85 | static inline int hlt_use_halt(void) | |
86 | { | |
87 | return (!hlt_counter && boot_cpu_data.hlt_works_ok); | |
88 | } | |
89 | #else | |
90 | static inline int hlt_use_halt(void) | |
91 | { | |
92 | return 1; | |
93 | } | |
94 | #endif | |
95 | ||
96 | /* | |
97 | * We use this if we don't have any better | |
98 | * idle routine.. | |
99 | */ | |
100 | void default_idle(void) | |
101 | { | |
102 | if (hlt_use_halt()) { | |
103 | current_thread_info()->status &= ~TS_POLLING; | |
104 | /* | |
105 | * TS_POLLING-cleared state must be visible before we | |
106 | * test NEED_RESCHED: | |
107 | */ | |
108 | smp_mb(); | |
109 | ||
110 | if (!need_resched()) | |
111 | safe_halt(); /* enables interrupts racelessly */ | |
112 | else | |
113 | local_irq_enable(); | |
114 | current_thread_info()->status |= TS_POLLING; | |
115 | } else { | |
116 | local_irq_enable(); | |
117 | /* loop is done by the caller */ | |
118 | cpu_relax(); | |
119 | } | |
120 | } | |
121 | #ifdef CONFIG_APM_MODULE | |
122 | EXPORT_SYMBOL(default_idle); | |
123 | #endif | |
124 | ||
7f424a8b PZ |
125 | static void do_nothing(void *unused) |
126 | { | |
127 | } | |
128 | ||
129 | /* | |
130 | * cpu_idle_wait - Used to ensure that all the CPUs discard old value of | |
131 | * pm_idle and update to new pm_idle value. Required while changing pm_idle | |
132 | * handler on SMP systems. | |
133 | * | |
134 | * Caller must have changed pm_idle to the new value before the call. Old | |
135 | * pm_idle value will not be used by any CPU after the return of this function. | |
136 | */ | |
137 | void cpu_idle_wait(void) | |
138 | { | |
139 | smp_mb(); | |
140 | /* kick all the CPUs so that they exit out of pm_idle */ | |
127a237a | 141 | smp_call_function(do_nothing, NULL, 1); |
7f424a8b PZ |
142 | } |
143 | EXPORT_SYMBOL_GPL(cpu_idle_wait); | |
144 | ||
145 | /* | |
146 | * This uses new MONITOR/MWAIT instructions on P4 processors with PNI, | |
147 | * which can obviate IPI to trigger checking of need_resched. | |
148 | * We execute MONITOR against need_resched and enter optimized wait state | |
149 | * through MWAIT. Whenever someone changes need_resched, we would be woken | |
150 | * up from MWAIT (without an IPI). | |
151 | * | |
152 | * New with Core Duo processors, MWAIT can take some hints based on CPU | |
153 | * capability. | |
154 | */ | |
155 | void mwait_idle_with_hints(unsigned long ax, unsigned long cx) | |
156 | { | |
157 | if (!need_resched()) { | |
158 | __monitor((void *)¤t_thread_info()->flags, 0, 0); | |
159 | smp_mb(); | |
160 | if (!need_resched()) | |
161 | __mwait(ax, cx); | |
162 | } | |
163 | } | |
164 | ||
165 | /* Default MONITOR/MWAIT with no hints, used for default C1 state */ | |
166 | static void mwait_idle(void) | |
167 | { | |
168 | if (!need_resched()) { | |
169 | __monitor((void *)¤t_thread_info()->flags, 0, 0); | |
170 | smp_mb(); | |
171 | if (!need_resched()) | |
172 | __sti_mwait(0, 0); | |
173 | else | |
174 | local_irq_enable(); | |
175 | } else | |
176 | local_irq_enable(); | |
177 | } | |
178 | ||
7f424a8b PZ |
179 | /* |
180 | * On SMP it's slightly faster (but much more power-consuming!) | |
181 | * to poll the ->work.need_resched flag instead of waiting for the | |
182 | * cross-CPU IPI to arrive. Use this option with caution. | |
183 | */ | |
184 | static void poll_idle(void) | |
185 | { | |
186 | local_irq_enable(); | |
187 | cpu_relax(); | |
188 | } | |
189 | ||
e9623b35 TG |
190 | /* |
191 | * mwait selection logic: | |
192 | * | |
193 | * It depends on the CPU. For AMD CPUs that support MWAIT this is | |
194 | * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings | |
195 | * then depend on a clock divisor and current Pstate of the core. If | |
196 | * all cores of a processor are in halt state (C1) the processor can | |
197 | * enter the C1E (C1 enhanced) state. If mwait is used this will never | |
198 | * happen. | |
199 | * | |
200 | * idle=mwait overrides this decision and forces the usage of mwait. | |
201 | */ | |
09fd4b4e TG |
202 | |
203 | #define MWAIT_INFO 0x05 | |
204 | #define MWAIT_ECX_EXTENDED_INFO 0x01 | |
205 | #define MWAIT_EDX_C1 0xf0 | |
206 | ||
e9623b35 TG |
207 | static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c) |
208 | { | |
09fd4b4e TG |
209 | u32 eax, ebx, ecx, edx; |
210 | ||
e9623b35 TG |
211 | if (force_mwait) |
212 | return 1; | |
213 | ||
09fd4b4e TG |
214 | if (c->cpuid_level < MWAIT_INFO) |
215 | return 0; | |
216 | ||
217 | cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx); | |
218 | /* Check, whether EDX has extended info about MWAIT */ | |
219 | if (!(ecx & MWAIT_ECX_EXTENDED_INFO)) | |
220 | return 1; | |
221 | ||
222 | /* | |
223 | * edx enumeratios MONITOR/MWAIT extensions. Check, whether | |
224 | * C1 supports MWAIT | |
225 | */ | |
226 | return (edx & MWAIT_EDX_C1); | |
e9623b35 TG |
227 | } |
228 | ||
aa276e1c TG |
229 | /* |
230 | * Check for AMD CPUs, which have potentially C1E support | |
231 | */ | |
232 | static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c) | |
233 | { | |
234 | if (c->x86_vendor != X86_VENDOR_AMD) | |
235 | return 0; | |
236 | ||
237 | if (c->x86 < 0x0F) | |
238 | return 0; | |
239 | ||
240 | /* Family 0x0f models < rev F do not have C1E */ | |
241 | if (c->x86 == 0x0f && c->x86_model < 0x40) | |
242 | return 0; | |
243 | ||
244 | return 1; | |
245 | } | |
246 | ||
247 | /* | |
248 | * C1E aware idle routine. We check for C1E active in the interrupt | |
249 | * pending message MSR. If we detect C1E, then we handle it the same | |
250 | * way as C3 power states (local apic timer and TSC stop) | |
251 | */ | |
252 | static void c1e_idle(void) | |
253 | { | |
254 | static cpumask_t c1e_mask = CPU_MASK_NONE; | |
255 | static int c1e_detected; | |
256 | ||
257 | if (need_resched()) | |
258 | return; | |
259 | ||
260 | if (!c1e_detected) { | |
261 | u32 lo, hi; | |
262 | ||
263 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); | |
264 | if (lo & K8_INTP_C1E_ACTIVE_MASK) { | |
265 | c1e_detected = 1; | |
266 | mark_tsc_unstable("TSC halt in C1E"); | |
267 | printk(KERN_INFO "System has C1E enabled\n"); | |
268 | } | |
269 | } | |
270 | ||
271 | if (c1e_detected) { | |
272 | int cpu = smp_processor_id(); | |
273 | ||
274 | if (!cpu_isset(cpu, c1e_mask)) { | |
275 | cpu_set(cpu, c1e_mask); | |
0beefa20 TG |
276 | /* |
277 | * Force broadcast so ACPI can not interfere. Needs | |
278 | * to run with interrupts enabled as it uses | |
279 | * smp_function_call. | |
280 | */ | |
281 | local_irq_enable(); | |
aa276e1c TG |
282 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE, |
283 | &cpu); | |
284 | printk(KERN_INFO "Switch to broadcast mode on CPU%d\n", | |
285 | cpu); | |
0beefa20 | 286 | local_irq_disable(); |
aa276e1c TG |
287 | } |
288 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu); | |
0beefa20 | 289 | |
aa276e1c | 290 | default_idle(); |
0beefa20 TG |
291 | |
292 | /* | |
293 | * The switch back from broadcast mode needs to be | |
294 | * called with interrupts disabled. | |
295 | */ | |
296 | local_irq_disable(); | |
297 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu); | |
298 | local_irq_enable(); | |
aa276e1c TG |
299 | } else |
300 | default_idle(); | |
301 | } | |
302 | ||
7f424a8b PZ |
303 | void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c) |
304 | { | |
7f424a8b PZ |
305 | #ifdef CONFIG_X86_SMP |
306 | if (pm_idle == poll_idle && smp_num_siblings > 1) { | |
307 | printk(KERN_WARNING "WARNING: polling idle and HT enabled," | |
308 | " performance may degrade.\n"); | |
309 | } | |
310 | #endif | |
6ddd2a27 TG |
311 | if (pm_idle) |
312 | return; | |
313 | ||
e9623b35 | 314 | if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) { |
7f424a8b | 315 | /* |
7f424a8b PZ |
316 | * One CPU supports mwait => All CPUs supports mwait |
317 | */ | |
6ddd2a27 TG |
318 | printk(KERN_INFO "using mwait in idle threads.\n"); |
319 | pm_idle = mwait_idle; | |
aa276e1c TG |
320 | } else if (check_c1e_idle(c)) { |
321 | printk(KERN_INFO "using C1E aware idle routine\n"); | |
322 | pm_idle = c1e_idle; | |
6ddd2a27 TG |
323 | } else |
324 | pm_idle = default_idle; | |
7f424a8b PZ |
325 | } |
326 | ||
327 | static int __init idle_setup(char *str) | |
328 | { | |
329 | if (!strcmp(str, "poll")) { | |
330 | printk("using polling idle threads.\n"); | |
331 | pm_idle = poll_idle; | |
332 | } else if (!strcmp(str, "mwait")) | |
333 | force_mwait = 1; | |
c1e3b377 ZY |
334 | else if (!strcmp(str, "halt")) { |
335 | /* | |
336 | * When the boot option of idle=halt is added, halt is | |
337 | * forced to be used for CPU idle. In such case CPU C2/C3 | |
338 | * won't be used again. | |
339 | * To continue to load the CPU idle driver, don't touch | |
340 | * the boot_option_idle_override. | |
341 | */ | |
342 | pm_idle = default_idle; | |
343 | idle_halt = 1; | |
344 | return 0; | |
da5e09a1 ZY |
345 | } else if (!strcmp(str, "nomwait")) { |
346 | /* | |
347 | * If the boot option of "idle=nomwait" is added, | |
348 | * it means that mwait will be disabled for CPU C2/C3 | |
349 | * states. In such case it won't touch the variable | |
350 | * of boot_option_idle_override. | |
351 | */ | |
352 | idle_nomwait = 1; | |
353 | return 0; | |
c1e3b377 | 354 | } else |
7f424a8b PZ |
355 | return -1; |
356 | ||
357 | boot_option_idle_override = 1; | |
358 | return 0; | |
359 | } | |
360 | early_param("idle", idle_setup); | |
361 |