Commit | Line | Data |
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61c4628b SS |
1 | #include <linux/errno.h> |
2 | #include <linux/kernel.h> | |
3 | #include <linux/mm.h> | |
4 | #include <linux/smp.h> | |
389d1fb1 | 5 | #include <linux/prctl.h> |
61c4628b SS |
6 | #include <linux/slab.h> |
7 | #include <linux/sched.h> | |
7f424a8b PZ |
8 | #include <linux/module.h> |
9 | #include <linux/pm.h> | |
aa276e1c | 10 | #include <linux/clockchips.h> |
9d62dcdf | 11 | #include <linux/random.h> |
7c68af6e | 12 | #include <linux/user-return-notifier.h> |
814e2c84 AI |
13 | #include <linux/dmi.h> |
14 | #include <linux/utsname.h> | |
90e24014 RW |
15 | #include <linux/stackprotector.h> |
16 | #include <linux/tick.h> | |
17 | #include <linux/cpuidle.h> | |
61613521 | 18 | #include <trace/events/power.h> |
24f1e32c | 19 | #include <linux/hw_breakpoint.h> |
93789b32 | 20 | #include <asm/cpu.h> |
d3ec5cae | 21 | #include <asm/apic.h> |
2c1b284e | 22 | #include <asm/syscalls.h> |
389d1fb1 JF |
23 | #include <asm/idle.h> |
24 | #include <asm/uaccess.h> | |
25 | #include <asm/i387.h> | |
1361b83a | 26 | #include <asm/fpu-internal.h> |
66cb5917 | 27 | #include <asm/debugreg.h> |
90e24014 RW |
28 | #include <asm/nmi.h> |
29 | ||
30 | #ifdef CONFIG_X86_64 | |
31 | static DEFINE_PER_CPU(unsigned char, is_idle); | |
32 | static ATOMIC_NOTIFIER_HEAD(idle_notifier); | |
33 | ||
34 | void idle_notifier_register(struct notifier_block *n) | |
35 | { | |
36 | atomic_notifier_chain_register(&idle_notifier, n); | |
37 | } | |
38 | EXPORT_SYMBOL_GPL(idle_notifier_register); | |
39 | ||
40 | void idle_notifier_unregister(struct notifier_block *n) | |
41 | { | |
42 | atomic_notifier_chain_unregister(&idle_notifier, n); | |
43 | } | |
44 | EXPORT_SYMBOL_GPL(idle_notifier_unregister); | |
45 | #endif | |
c1e3b377 | 46 | |
aa283f49 | 47 | struct kmem_cache *task_xstate_cachep; |
5ee481da | 48 | EXPORT_SYMBOL_GPL(task_xstate_cachep); |
61c4628b | 49 | |
55ccf3fe SS |
50 | /* |
51 | * this gets called so that we can store lazy state into memory and copy the | |
52 | * current task into the new thread. | |
53 | */ | |
61c4628b SS |
54 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
55 | { | |
86603283 AK |
56 | int ret; |
57 | ||
55ccf3fe SS |
58 | unlazy_fpu(src); |
59 | ||
61c4628b | 60 | *dst = *src; |
86603283 AK |
61 | if (fpu_allocated(&src->thread.fpu)) { |
62 | memset(&dst->thread.fpu, 0, sizeof(dst->thread.fpu)); | |
63 | ret = fpu_alloc(&dst->thread.fpu); | |
64 | if (ret) | |
65 | return ret; | |
66 | fpu_copy(&dst->thread.fpu, &src->thread.fpu); | |
aa283f49 | 67 | } |
61c4628b SS |
68 | return 0; |
69 | } | |
70 | ||
aa283f49 | 71 | void free_thread_xstate(struct task_struct *tsk) |
61c4628b | 72 | { |
86603283 | 73 | fpu_free(&tsk->thread.fpu); |
aa283f49 SS |
74 | } |
75 | ||
aa283f49 SS |
76 | void free_thread_info(struct thread_info *ti) |
77 | { | |
78 | free_thread_xstate(ti->task); | |
c812d8f7 | 79 | free_pages((unsigned long)ti, THREAD_ORDER); |
61c4628b SS |
80 | } |
81 | ||
82 | void arch_task_cache_init(void) | |
83 | { | |
84 | task_xstate_cachep = | |
85 | kmem_cache_create("task_xstate", xstate_size, | |
86 | __alignof__(union thread_xstate), | |
2dff4405 | 87 | SLAB_PANIC | SLAB_NOTRACK, NULL); |
61c4628b | 88 | } |
7f424a8b | 89 | |
389d1fb1 JF |
90 | /* |
91 | * Free current thread data structures etc.. | |
92 | */ | |
93 | void exit_thread(void) | |
94 | { | |
95 | struct task_struct *me = current; | |
96 | struct thread_struct *t = &me->thread; | |
250981e6 | 97 | unsigned long *bp = t->io_bitmap_ptr; |
389d1fb1 | 98 | |
250981e6 | 99 | if (bp) { |
389d1fb1 JF |
100 | struct tss_struct *tss = &per_cpu(init_tss, get_cpu()); |
101 | ||
389d1fb1 JF |
102 | t->io_bitmap_ptr = NULL; |
103 | clear_thread_flag(TIF_IO_BITMAP); | |
104 | /* | |
105 | * Careful, clear this in the TSS too: | |
106 | */ | |
107 | memset(tss->io_bitmap, 0xff, t->io_bitmap_max); | |
108 | t->io_bitmap_max = 0; | |
109 | put_cpu(); | |
250981e6 | 110 | kfree(bp); |
389d1fb1 | 111 | } |
389d1fb1 JF |
112 | } |
113 | ||
3bef4447 BG |
114 | void show_regs(struct pt_regs *regs) |
115 | { | |
116 | show_registers(regs); | |
e8e999cf | 117 | show_trace(NULL, regs, (unsigned long *)kernel_stack_pointer(regs), 0); |
3bef4447 BG |
118 | } |
119 | ||
814e2c84 AI |
120 | void show_regs_common(void) |
121 | { | |
84e383b3 | 122 | const char *vendor, *product, *board; |
814e2c84 | 123 | |
84e383b3 NC |
124 | vendor = dmi_get_system_info(DMI_SYS_VENDOR); |
125 | if (!vendor) | |
126 | vendor = ""; | |
a1884b8e AI |
127 | product = dmi_get_system_info(DMI_PRODUCT_NAME); |
128 | if (!product) | |
129 | product = ""; | |
814e2c84 | 130 | |
84e383b3 NC |
131 | /* Board Name is optional */ |
132 | board = dmi_get_system_info(DMI_BOARD_NAME); | |
133 | ||
d015a092 | 134 | printk(KERN_CONT "\n"); |
84e383b3 | 135 | printk(KERN_DEFAULT "Pid: %d, comm: %.20s %s %s %.*s", |
814e2c84 AI |
136 | current->pid, current->comm, print_tainted(), |
137 | init_utsname()->release, | |
138 | (int)strcspn(init_utsname()->version, " "), | |
84e383b3 | 139 | init_utsname()->version); |
fd8fa4d3 JB |
140 | printk(KERN_CONT " %s %s", vendor, product); |
141 | if (board) | |
142 | printk(KERN_CONT "/%s", board); | |
84e383b3 | 143 | printk(KERN_CONT "\n"); |
814e2c84 AI |
144 | } |
145 | ||
389d1fb1 JF |
146 | void flush_thread(void) |
147 | { | |
148 | struct task_struct *tsk = current; | |
149 | ||
24f1e32c | 150 | flush_ptrace_hw_breakpoint(tsk); |
389d1fb1 JF |
151 | memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); |
152 | /* | |
153 | * Forget coprocessor state.. | |
154 | */ | |
155 | tsk->fpu_counter = 0; | |
156 | clear_fpu(tsk); | |
157 | clear_used_math(); | |
158 | } | |
159 | ||
160 | static void hard_disable_TSC(void) | |
161 | { | |
162 | write_cr4(read_cr4() | X86_CR4_TSD); | |
163 | } | |
164 | ||
165 | void disable_TSC(void) | |
166 | { | |
167 | preempt_disable(); | |
168 | if (!test_and_set_thread_flag(TIF_NOTSC)) | |
169 | /* | |
170 | * Must flip the CPU state synchronously with | |
171 | * TIF_NOTSC in the current running context. | |
172 | */ | |
173 | hard_disable_TSC(); | |
174 | preempt_enable(); | |
175 | } | |
176 | ||
177 | static void hard_enable_TSC(void) | |
178 | { | |
179 | write_cr4(read_cr4() & ~X86_CR4_TSD); | |
180 | } | |
181 | ||
182 | static void enable_TSC(void) | |
183 | { | |
184 | preempt_disable(); | |
185 | if (test_and_clear_thread_flag(TIF_NOTSC)) | |
186 | /* | |
187 | * Must flip the CPU state synchronously with | |
188 | * TIF_NOTSC in the current running context. | |
189 | */ | |
190 | hard_enable_TSC(); | |
191 | preempt_enable(); | |
192 | } | |
193 | ||
194 | int get_tsc_mode(unsigned long adr) | |
195 | { | |
196 | unsigned int val; | |
197 | ||
198 | if (test_thread_flag(TIF_NOTSC)) | |
199 | val = PR_TSC_SIGSEGV; | |
200 | else | |
201 | val = PR_TSC_ENABLE; | |
202 | ||
203 | return put_user(val, (unsigned int __user *)adr); | |
204 | } | |
205 | ||
206 | int set_tsc_mode(unsigned int val) | |
207 | { | |
208 | if (val == PR_TSC_SIGSEGV) | |
209 | disable_TSC(); | |
210 | else if (val == PR_TSC_ENABLE) | |
211 | enable_TSC(); | |
212 | else | |
213 | return -EINVAL; | |
214 | ||
215 | return 0; | |
216 | } | |
217 | ||
218 | void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, | |
219 | struct tss_struct *tss) | |
220 | { | |
221 | struct thread_struct *prev, *next; | |
222 | ||
223 | prev = &prev_p->thread; | |
224 | next = &next_p->thread; | |
225 | ||
ea8e61b7 PZ |
226 | if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^ |
227 | test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) { | |
228 | unsigned long debugctl = get_debugctlmsr(); | |
229 | ||
230 | debugctl &= ~DEBUGCTLMSR_BTF; | |
231 | if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) | |
232 | debugctl |= DEBUGCTLMSR_BTF; | |
233 | ||
234 | update_debugctlmsr(debugctl); | |
235 | } | |
389d1fb1 | 236 | |
389d1fb1 JF |
237 | if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^ |
238 | test_tsk_thread_flag(next_p, TIF_NOTSC)) { | |
239 | /* prev and next are different */ | |
240 | if (test_tsk_thread_flag(next_p, TIF_NOTSC)) | |
241 | hard_disable_TSC(); | |
242 | else | |
243 | hard_enable_TSC(); | |
244 | } | |
245 | ||
246 | if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) { | |
247 | /* | |
248 | * Copy the relevant range of the IO bitmap. | |
249 | * Normally this is 128 bytes or less: | |
250 | */ | |
251 | memcpy(tss->io_bitmap, next->io_bitmap_ptr, | |
252 | max(prev->io_bitmap_max, next->io_bitmap_max)); | |
253 | } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) { | |
254 | /* | |
255 | * Clear any possible leftover bits: | |
256 | */ | |
257 | memset(tss->io_bitmap, 0xff, prev->io_bitmap_max); | |
258 | } | |
7c68af6e | 259 | propagate_user_return_notify(prev_p, next_p); |
389d1fb1 JF |
260 | } |
261 | ||
262 | int sys_fork(struct pt_regs *regs) | |
263 | { | |
264 | return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL); | |
265 | } | |
266 | ||
267 | /* | |
268 | * This is trivial, and on the face of it looks like it | |
269 | * could equally well be done in user mode. | |
270 | * | |
271 | * Not so, for quite unobvious reasons - register pressure. | |
272 | * In user mode vfork() cannot have a stack frame, and if | |
273 | * done by calling the "clone()" system call directly, you | |
274 | * do not have enough call-clobbered registers to hold all | |
275 | * the information you need. | |
276 | */ | |
277 | int sys_vfork(struct pt_regs *regs) | |
278 | { | |
279 | return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0, | |
280 | NULL, NULL); | |
281 | } | |
282 | ||
f839bbc5 BG |
283 | long |
284 | sys_clone(unsigned long clone_flags, unsigned long newsp, | |
285 | void __user *parent_tid, void __user *child_tid, struct pt_regs *regs) | |
286 | { | |
287 | if (!newsp) | |
288 | newsp = regs->sp; | |
289 | return do_fork(clone_flags, newsp, regs, 0, parent_tid, child_tid); | |
290 | } | |
291 | ||
df59e7bf BG |
292 | /* |
293 | * This gets run with %si containing the | |
294 | * function to call, and %di containing | |
295 | * the "args". | |
296 | */ | |
297 | extern void kernel_thread_helper(void); | |
298 | ||
299 | /* | |
300 | * Create a kernel thread | |
301 | */ | |
302 | int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags) | |
303 | { | |
304 | struct pt_regs regs; | |
305 | ||
306 | memset(®s, 0, sizeof(regs)); | |
307 | ||
308 | regs.si = (unsigned long) fn; | |
309 | regs.di = (unsigned long) arg; | |
310 | ||
311 | #ifdef CONFIG_X86_32 | |
312 | regs.ds = __USER_DS; | |
313 | regs.es = __USER_DS; | |
314 | regs.fs = __KERNEL_PERCPU; | |
315 | regs.gs = __KERNEL_STACK_CANARY; | |
864a0922 CG |
316 | #else |
317 | regs.ss = __KERNEL_DS; | |
df59e7bf BG |
318 | #endif |
319 | ||
320 | regs.orig_ax = -1; | |
321 | regs.ip = (unsigned long) kernel_thread_helper; | |
322 | regs.cs = __KERNEL_CS | get_kernel_rpl(); | |
1cf8343f | 323 | regs.flags = X86_EFLAGS_IF | X86_EFLAGS_BIT1; |
df59e7bf BG |
324 | |
325 | /* Ok, create the new process.. */ | |
326 | return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, ®s, 0, NULL, NULL); | |
327 | } | |
328 | EXPORT_SYMBOL(kernel_thread); | |
389d1fb1 | 329 | |
11cf88bd BG |
330 | /* |
331 | * sys_execve() executes a new program. | |
332 | */ | |
d7627467 DH |
333 | long sys_execve(const char __user *name, |
334 | const char __user *const __user *argv, | |
335 | const char __user *const __user *envp, struct pt_regs *regs) | |
11cf88bd BG |
336 | { |
337 | long error; | |
338 | char *filename; | |
339 | ||
340 | filename = getname(name); | |
341 | error = PTR_ERR(filename); | |
342 | if (IS_ERR(filename)) | |
343 | return error; | |
344 | error = do_execve(filename, argv, envp, regs); | |
345 | ||
346 | #ifdef CONFIG_X86_32 | |
347 | if (error == 0) { | |
348 | /* Make sure we don't return using sysenter.. */ | |
349 | set_thread_flag(TIF_IRET); | |
350 | } | |
351 | #endif | |
352 | ||
353 | putname(filename); | |
354 | return error; | |
355 | } | |
389d1fb1 | 356 | |
00dba564 TG |
357 | /* |
358 | * Idle related variables and functions | |
359 | */ | |
d1896049 | 360 | unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; |
00dba564 TG |
361 | EXPORT_SYMBOL(boot_option_idle_override); |
362 | ||
363 | /* | |
364 | * Powermanagement idle function, if any.. | |
365 | */ | |
366 | void (*pm_idle)(void); | |
60b8b1de | 367 | #ifdef CONFIG_APM_MODULE |
00dba564 | 368 | EXPORT_SYMBOL(pm_idle); |
06ae40ce | 369 | #endif |
00dba564 | 370 | |
00dba564 TG |
371 | static inline int hlt_use_halt(void) |
372 | { | |
373 | return 1; | |
374 | } | |
00dba564 | 375 | |
90e24014 RW |
376 | #ifndef CONFIG_SMP |
377 | static inline void play_dead(void) | |
378 | { | |
379 | BUG(); | |
380 | } | |
381 | #endif | |
382 | ||
383 | #ifdef CONFIG_X86_64 | |
384 | void enter_idle(void) | |
385 | { | |
386 | percpu_write(is_idle, 1); | |
387 | atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL); | |
388 | } | |
389 | ||
390 | static void __exit_idle(void) | |
391 | { | |
392 | if (x86_test_and_clear_bit_percpu(0, is_idle) == 0) | |
393 | return; | |
394 | atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL); | |
395 | } | |
396 | ||
397 | /* Called from interrupts to signify idle end */ | |
398 | void exit_idle(void) | |
399 | { | |
400 | /* idle loop has pid 0 */ | |
401 | if (current->pid) | |
402 | return; | |
403 | __exit_idle(); | |
404 | } | |
405 | #endif | |
406 | ||
407 | /* | |
408 | * The idle thread. There's no useful work to be | |
409 | * done, so just try to conserve power and have a | |
410 | * low exit latency (ie sit in a loop waiting for | |
411 | * somebody to say that they'd like to reschedule) | |
412 | */ | |
413 | void cpu_idle(void) | |
414 | { | |
415 | /* | |
416 | * If we're the non-boot CPU, nothing set the stack canary up | |
417 | * for us. CPU0 already has it initialized but no harm in | |
418 | * doing it again. This is a good place for updating it, as | |
419 | * we wont ever return from this function (so the invalid | |
420 | * canaries already on the stack wont ever trigger). | |
421 | */ | |
422 | boot_init_stack_canary(); | |
423 | current_thread_info()->status |= TS_POLLING; | |
424 | ||
425 | while (1) { | |
426 | tick_nohz_idle_enter(); | |
427 | ||
428 | while (!need_resched()) { | |
429 | rmb(); | |
430 | ||
431 | if (cpu_is_offline(smp_processor_id())) | |
432 | play_dead(); | |
433 | ||
434 | /* | |
435 | * Idle routines should keep interrupts disabled | |
436 | * from here on, until they go to idle. | |
437 | * Otherwise, idle callbacks can misfire. | |
438 | */ | |
439 | local_touch_nmi(); | |
440 | local_irq_disable(); | |
441 | ||
442 | enter_idle(); | |
443 | ||
444 | /* Don't trace irqs off for idle */ | |
445 | stop_critical_timings(); | |
446 | ||
447 | /* enter_idle() needs rcu for notifiers */ | |
448 | rcu_idle_enter(); | |
449 | ||
450 | if (cpuidle_idle_call()) | |
451 | pm_idle(); | |
452 | ||
453 | rcu_idle_exit(); | |
454 | start_critical_timings(); | |
455 | ||
456 | /* In many cases the interrupt that ended idle | |
457 | has already called exit_idle. But some idle | |
458 | loops can be woken up without interrupt. */ | |
459 | __exit_idle(); | |
460 | } | |
461 | ||
462 | tick_nohz_idle_exit(); | |
463 | preempt_enable_no_resched(); | |
464 | schedule(); | |
465 | preempt_disable(); | |
466 | } | |
467 | } | |
468 | ||
00dba564 TG |
469 | /* |
470 | * We use this if we don't have any better | |
471 | * idle routine.. | |
472 | */ | |
473 | void default_idle(void) | |
474 | { | |
475 | if (hlt_use_halt()) { | |
48454650 SR |
476 | trace_power_start_rcuidle(POWER_CSTATE, 1, smp_processor_id()); |
477 | trace_cpu_idle_rcuidle(1, smp_processor_id()); | |
00dba564 TG |
478 | current_thread_info()->status &= ~TS_POLLING; |
479 | /* | |
480 | * TS_POLLING-cleared state must be visible before we | |
481 | * test NEED_RESCHED: | |
482 | */ | |
483 | smp_mb(); | |
484 | ||
485 | if (!need_resched()) | |
486 | safe_halt(); /* enables interrupts racelessly */ | |
487 | else | |
488 | local_irq_enable(); | |
489 | current_thread_info()->status |= TS_POLLING; | |
48454650 SR |
490 | trace_power_end_rcuidle(smp_processor_id()); |
491 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); | |
00dba564 TG |
492 | } else { |
493 | local_irq_enable(); | |
494 | /* loop is done by the caller */ | |
495 | cpu_relax(); | |
496 | } | |
497 | } | |
60b8b1de | 498 | #ifdef CONFIG_APM_MODULE |
00dba564 TG |
499 | EXPORT_SYMBOL(default_idle); |
500 | #endif | |
501 | ||
e5fd47bf KRW |
502 | bool set_pm_idle_to_default(void) |
503 | { | |
504 | bool ret = !!pm_idle; | |
505 | ||
506 | pm_idle = default_idle; | |
507 | ||
508 | return ret; | |
509 | } | |
d3ec5cae IV |
510 | void stop_this_cpu(void *dummy) |
511 | { | |
512 | local_irq_disable(); | |
513 | /* | |
514 | * Remove this CPU: | |
515 | */ | |
4f062896 | 516 | set_cpu_online(smp_processor_id(), false); |
d3ec5cae IV |
517 | disable_local_APIC(); |
518 | ||
519 | for (;;) { | |
520 | if (hlt_works(smp_processor_id())) | |
521 | halt(); | |
522 | } | |
523 | } | |
524 | ||
7f424a8b PZ |
525 | static void do_nothing(void *unused) |
526 | { | |
527 | } | |
528 | ||
529 | /* | |
530 | * cpu_idle_wait - Used to ensure that all the CPUs discard old value of | |
531 | * pm_idle and update to new pm_idle value. Required while changing pm_idle | |
532 | * handler on SMP systems. | |
533 | * | |
534 | * Caller must have changed pm_idle to the new value before the call. Old | |
535 | * pm_idle value will not be used by any CPU after the return of this function. | |
536 | */ | |
537 | void cpu_idle_wait(void) | |
538 | { | |
539 | smp_mb(); | |
540 | /* kick all the CPUs so that they exit out of pm_idle */ | |
127a237a | 541 | smp_call_function(do_nothing, NULL, 1); |
7f424a8b PZ |
542 | } |
543 | EXPORT_SYMBOL_GPL(cpu_idle_wait); | |
544 | ||
7f424a8b PZ |
545 | /* Default MONITOR/MWAIT with no hints, used for default C1 state */ |
546 | static void mwait_idle(void) | |
547 | { | |
548 | if (!need_resched()) { | |
48454650 SR |
549 | trace_power_start_rcuidle(POWER_CSTATE, 1, smp_processor_id()); |
550 | trace_cpu_idle_rcuidle(1, smp_processor_id()); | |
349c004e | 551 | if (this_cpu_has(X86_FEATURE_CLFLUSH_MONITOR)) |
e736ad54 PV |
552 | clflush((void *)¤t_thread_info()->flags); |
553 | ||
7f424a8b PZ |
554 | __monitor((void *)¤t_thread_info()->flags, 0, 0); |
555 | smp_mb(); | |
556 | if (!need_resched()) | |
557 | __sti_mwait(0, 0); | |
558 | else | |
559 | local_irq_enable(); | |
48454650 SR |
560 | trace_power_end_rcuidle(smp_processor_id()); |
561 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); | |
7f424a8b PZ |
562 | } else |
563 | local_irq_enable(); | |
564 | } | |
565 | ||
7f424a8b PZ |
566 | /* |
567 | * On SMP it's slightly faster (but much more power-consuming!) | |
568 | * to poll the ->work.need_resched flag instead of waiting for the | |
569 | * cross-CPU IPI to arrive. Use this option with caution. | |
570 | */ | |
571 | static void poll_idle(void) | |
572 | { | |
48454650 SR |
573 | trace_power_start_rcuidle(POWER_CSTATE, 0, smp_processor_id()); |
574 | trace_cpu_idle_rcuidle(0, smp_processor_id()); | |
7f424a8b | 575 | local_irq_enable(); |
2c7e9fd4 JK |
576 | while (!need_resched()) |
577 | cpu_relax(); | |
48454650 SR |
578 | trace_power_end_rcuidle(smp_processor_id()); |
579 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); | |
7f424a8b PZ |
580 | } |
581 | ||
e9623b35 TG |
582 | /* |
583 | * mwait selection logic: | |
584 | * | |
585 | * It depends on the CPU. For AMD CPUs that support MWAIT this is | |
586 | * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings | |
587 | * then depend on a clock divisor and current Pstate of the core. If | |
588 | * all cores of a processor are in halt state (C1) the processor can | |
589 | * enter the C1E (C1 enhanced) state. If mwait is used this will never | |
590 | * happen. | |
591 | * | |
592 | * idle=mwait overrides this decision and forces the usage of mwait. | |
593 | */ | |
09fd4b4e TG |
594 | |
595 | #define MWAIT_INFO 0x05 | |
596 | #define MWAIT_ECX_EXTENDED_INFO 0x01 | |
597 | #define MWAIT_EDX_C1 0xf0 | |
598 | ||
1c9d16e3 | 599 | int mwait_usable(const struct cpuinfo_x86 *c) |
e9623b35 | 600 | { |
09fd4b4e TG |
601 | u32 eax, ebx, ecx, edx; |
602 | ||
d1896049 | 603 | if (boot_option_idle_override == IDLE_FORCE_MWAIT) |
e9623b35 TG |
604 | return 1; |
605 | ||
09fd4b4e TG |
606 | if (c->cpuid_level < MWAIT_INFO) |
607 | return 0; | |
608 | ||
609 | cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx); | |
610 | /* Check, whether EDX has extended info about MWAIT */ | |
611 | if (!(ecx & MWAIT_ECX_EXTENDED_INFO)) | |
612 | return 1; | |
613 | ||
614 | /* | |
615 | * edx enumeratios MONITOR/MWAIT extensions. Check, whether | |
616 | * C1 supports MWAIT | |
617 | */ | |
618 | return (edx & MWAIT_EDX_C1); | |
e9623b35 TG |
619 | } |
620 | ||
02c68a02 LB |
621 | bool amd_e400_c1e_detected; |
622 | EXPORT_SYMBOL(amd_e400_c1e_detected); | |
aa276e1c | 623 | |
02c68a02 | 624 | static cpumask_var_t amd_e400_c1e_mask; |
4faac97d | 625 | |
02c68a02 | 626 | void amd_e400_remove_cpu(int cpu) |
4faac97d | 627 | { |
02c68a02 LB |
628 | if (amd_e400_c1e_mask != NULL) |
629 | cpumask_clear_cpu(cpu, amd_e400_c1e_mask); | |
4faac97d TG |
630 | } |
631 | ||
aa276e1c | 632 | /* |
02c68a02 | 633 | * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt |
aa276e1c TG |
634 | * pending message MSR. If we detect C1E, then we handle it the same |
635 | * way as C3 power states (local apic timer and TSC stop) | |
636 | */ | |
02c68a02 | 637 | static void amd_e400_idle(void) |
aa276e1c | 638 | { |
aa276e1c TG |
639 | if (need_resched()) |
640 | return; | |
641 | ||
02c68a02 | 642 | if (!amd_e400_c1e_detected) { |
aa276e1c TG |
643 | u32 lo, hi; |
644 | ||
645 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); | |
e8c534ec | 646 | |
aa276e1c | 647 | if (lo & K8_INTP_C1E_ACTIVE_MASK) { |
02c68a02 | 648 | amd_e400_c1e_detected = true; |
40fb1715 | 649 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
09bfeea1 AH |
650 | mark_tsc_unstable("TSC halt in AMD C1E"); |
651 | printk(KERN_INFO "System has AMD C1E enabled\n"); | |
aa276e1c TG |
652 | } |
653 | } | |
654 | ||
02c68a02 | 655 | if (amd_e400_c1e_detected) { |
aa276e1c TG |
656 | int cpu = smp_processor_id(); |
657 | ||
02c68a02 LB |
658 | if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) { |
659 | cpumask_set_cpu(cpu, amd_e400_c1e_mask); | |
0beefa20 | 660 | /* |
f833bab8 | 661 | * Force broadcast so ACPI can not interfere. |
0beefa20 | 662 | */ |
aa276e1c TG |
663 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE, |
664 | &cpu); | |
665 | printk(KERN_INFO "Switch to broadcast mode on CPU%d\n", | |
666 | cpu); | |
667 | } | |
668 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu); | |
0beefa20 | 669 | |
aa276e1c | 670 | default_idle(); |
0beefa20 TG |
671 | |
672 | /* | |
673 | * The switch back from broadcast mode needs to be | |
674 | * called with interrupts disabled. | |
675 | */ | |
676 | local_irq_disable(); | |
677 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu); | |
678 | local_irq_enable(); | |
aa276e1c TG |
679 | } else |
680 | default_idle(); | |
681 | } | |
682 | ||
7f424a8b PZ |
683 | void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c) |
684 | { | |
3e5095d1 | 685 | #ifdef CONFIG_SMP |
7f424a8b | 686 | if (pm_idle == poll_idle && smp_num_siblings > 1) { |
d6dd6921 | 687 | printk_once(KERN_WARNING "WARNING: polling idle and HT enabled," |
7f424a8b PZ |
688 | " performance may degrade.\n"); |
689 | } | |
690 | #endif | |
6ddd2a27 TG |
691 | if (pm_idle) |
692 | return; | |
693 | ||
e9623b35 | 694 | if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) { |
7f424a8b | 695 | /* |
7f424a8b PZ |
696 | * One CPU supports mwait => All CPUs supports mwait |
697 | */ | |
6ddd2a27 TG |
698 | printk(KERN_INFO "using mwait in idle threads.\n"); |
699 | pm_idle = mwait_idle; | |
9d8888c2 HR |
700 | } else if (cpu_has_amd_erratum(amd_erratum_400)) { |
701 | /* E400: APIC timer interrupt does not wake up CPU from C1e */ | |
02c68a02 LB |
702 | printk(KERN_INFO "using AMD E400 aware idle routine\n"); |
703 | pm_idle = amd_e400_idle; | |
6ddd2a27 TG |
704 | } else |
705 | pm_idle = default_idle; | |
7f424a8b PZ |
706 | } |
707 | ||
02c68a02 | 708 | void __init init_amd_e400_c1e_mask(void) |
30e1e6d1 | 709 | { |
02c68a02 LB |
710 | /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */ |
711 | if (pm_idle == amd_e400_idle) | |
712 | zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL); | |
30e1e6d1 RR |
713 | } |
714 | ||
7f424a8b PZ |
715 | static int __init idle_setup(char *str) |
716 | { | |
ab6bc3e3 CG |
717 | if (!str) |
718 | return -EINVAL; | |
719 | ||
7f424a8b PZ |
720 | if (!strcmp(str, "poll")) { |
721 | printk("using polling idle threads.\n"); | |
722 | pm_idle = poll_idle; | |
d1896049 TR |
723 | boot_option_idle_override = IDLE_POLL; |
724 | } else if (!strcmp(str, "mwait")) { | |
725 | boot_option_idle_override = IDLE_FORCE_MWAIT; | |
af0d6a0a | 726 | WARN_ONCE(1, "\"idle=mwait\" will be removed in 2012\n"); |
d1896049 | 727 | } else if (!strcmp(str, "halt")) { |
c1e3b377 ZY |
728 | /* |
729 | * When the boot option of idle=halt is added, halt is | |
730 | * forced to be used for CPU idle. In such case CPU C2/C3 | |
731 | * won't be used again. | |
732 | * To continue to load the CPU idle driver, don't touch | |
733 | * the boot_option_idle_override. | |
734 | */ | |
735 | pm_idle = default_idle; | |
d1896049 | 736 | boot_option_idle_override = IDLE_HALT; |
da5e09a1 ZY |
737 | } else if (!strcmp(str, "nomwait")) { |
738 | /* | |
739 | * If the boot option of "idle=nomwait" is added, | |
740 | * it means that mwait will be disabled for CPU C2/C3 | |
741 | * states. In such case it won't touch the variable | |
742 | * of boot_option_idle_override. | |
743 | */ | |
d1896049 | 744 | boot_option_idle_override = IDLE_NOMWAIT; |
c1e3b377 | 745 | } else |
7f424a8b PZ |
746 | return -1; |
747 | ||
7f424a8b PZ |
748 | return 0; |
749 | } | |
750 | early_param("idle", idle_setup); | |
751 | ||
9d62dcdf AW |
752 | unsigned long arch_align_stack(unsigned long sp) |
753 | { | |
754 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
755 | sp -= get_random_int() % 8192; | |
756 | return sp & ~0xf; | |
757 | } | |
758 | ||
759 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
760 | { | |
761 | unsigned long range_end = mm->brk + 0x02000000; | |
762 | return randomize_range(mm->brk, range_end, 0) ? : mm->brk; | |
763 | } | |
764 |