Commit | Line | Data |
---|---|---|
c767a54b JP |
1 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
2 | ||
61c4628b SS |
3 | #include <linux/errno.h> |
4 | #include <linux/kernel.h> | |
5 | #include <linux/mm.h> | |
6 | #include <linux/smp.h> | |
389d1fb1 | 7 | #include <linux/prctl.h> |
61c4628b SS |
8 | #include <linux/slab.h> |
9 | #include <linux/sched.h> | |
7f424a8b PZ |
10 | #include <linux/module.h> |
11 | #include <linux/pm.h> | |
aa276e1c | 12 | #include <linux/clockchips.h> |
9d62dcdf | 13 | #include <linux/random.h> |
7c68af6e | 14 | #include <linux/user-return-notifier.h> |
814e2c84 AI |
15 | #include <linux/dmi.h> |
16 | #include <linux/utsname.h> | |
90e24014 RW |
17 | #include <linux/stackprotector.h> |
18 | #include <linux/tick.h> | |
19 | #include <linux/cpuidle.h> | |
61613521 | 20 | #include <trace/events/power.h> |
24f1e32c | 21 | #include <linux/hw_breakpoint.h> |
93789b32 | 22 | #include <asm/cpu.h> |
d3ec5cae | 23 | #include <asm/apic.h> |
2c1b284e | 24 | #include <asm/syscalls.h> |
389d1fb1 JF |
25 | #include <asm/idle.h> |
26 | #include <asm/uaccess.h> | |
27 | #include <asm/i387.h> | |
1361b83a | 28 | #include <asm/fpu-internal.h> |
66cb5917 | 29 | #include <asm/debugreg.h> |
90e24014 | 30 | #include <asm/nmi.h> |
375074cc | 31 | #include <asm/tlbflush.h> |
90e24014 | 32 | |
45046892 TG |
33 | /* |
34 | * per-CPU TSS segments. Threads are completely 'soft' on Linux, | |
35 | * no more per-task TSS's. The TSS size is kept cacheline-aligned | |
36 | * so they are allowed to end up in the .data..cacheline_aligned | |
37 | * section. Since TSS's are completely CPU-local, we want them | |
38 | * on exact cacheline boundaries, to eliminate cacheline ping-pong. | |
39 | */ | |
d0a0de21 AL |
40 | __visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss) = { |
41 | .x86_tss = { | |
42 | .sp0 = (unsigned long)&init_stack + sizeof(init_stack), | |
43 | #ifdef CONFIG_X86_32 | |
44 | .ss0 = __KERNEL_DS, | |
45 | .ss1 = __KERNEL_CS, | |
46 | .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, | |
47 | #endif | |
48 | }, | |
49 | #ifdef CONFIG_X86_32 | |
50 | /* | |
51 | * Note that the .io_bitmap member must be extra-big. This is because | |
52 | * the CPU will access an additional byte beyond the end of the IO | |
53 | * permission bitmap. The extra byte must be all 1 bits, and must | |
54 | * be within the limit. | |
55 | */ | |
56 | .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, | |
57 | #endif | |
58 | }; | |
24933b82 | 59 | EXPORT_PER_CPU_SYMBOL_GPL(cpu_tss); |
45046892 | 60 | |
90e24014 RW |
61 | #ifdef CONFIG_X86_64 |
62 | static DEFINE_PER_CPU(unsigned char, is_idle); | |
63 | static ATOMIC_NOTIFIER_HEAD(idle_notifier); | |
64 | ||
65 | void idle_notifier_register(struct notifier_block *n) | |
66 | { | |
67 | atomic_notifier_chain_register(&idle_notifier, n); | |
68 | } | |
69 | EXPORT_SYMBOL_GPL(idle_notifier_register); | |
70 | ||
71 | void idle_notifier_unregister(struct notifier_block *n) | |
72 | { | |
73 | atomic_notifier_chain_unregister(&idle_notifier, n); | |
74 | } | |
75 | EXPORT_SYMBOL_GPL(idle_notifier_unregister); | |
76 | #endif | |
c1e3b377 | 77 | |
aa283f49 | 78 | struct kmem_cache *task_xstate_cachep; |
5ee481da | 79 | EXPORT_SYMBOL_GPL(task_xstate_cachep); |
61c4628b | 80 | |
55ccf3fe SS |
81 | /* |
82 | * this gets called so that we can store lazy state into memory and copy the | |
83 | * current task into the new thread. | |
84 | */ | |
61c4628b SS |
85 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
86 | { | |
87 | *dst = *src; | |
f1853505 | 88 | |
dc56c0f9 | 89 | dst->thread.fpu_counter = 0; |
5e23fee2 ON |
90 | dst->thread.fpu.has_fpu = 0; |
91 | dst->thread.fpu.last_cpu = ~0; | |
92 | dst->thread.fpu.state = NULL; | |
f1853505 ON |
93 | if (tsk_used_math(src)) { |
94 | int err = fpu_alloc(&dst->thread.fpu); | |
95 | if (err) | |
96 | return err; | |
304bceda | 97 | fpu_copy(dst, src); |
aa283f49 | 98 | } |
61c4628b SS |
99 | return 0; |
100 | } | |
101 | ||
aa283f49 | 102 | void free_thread_xstate(struct task_struct *tsk) |
61c4628b | 103 | { |
86603283 | 104 | fpu_free(&tsk->thread.fpu); |
aa283f49 SS |
105 | } |
106 | ||
38e7c572 | 107 | void arch_release_task_struct(struct task_struct *tsk) |
aa283f49 | 108 | { |
38e7c572 | 109 | free_thread_xstate(tsk); |
61c4628b SS |
110 | } |
111 | ||
112 | void arch_task_cache_init(void) | |
113 | { | |
114 | task_xstate_cachep = | |
115 | kmem_cache_create("task_xstate", xstate_size, | |
116 | __alignof__(union thread_xstate), | |
2dff4405 | 117 | SLAB_PANIC | SLAB_NOTRACK, NULL); |
7496d645 | 118 | setup_xstate_comp(); |
61c4628b | 119 | } |
7f424a8b | 120 | |
389d1fb1 JF |
121 | /* |
122 | * Free current thread data structures etc.. | |
123 | */ | |
124 | void exit_thread(void) | |
125 | { | |
126 | struct task_struct *me = current; | |
127 | struct thread_struct *t = &me->thread; | |
250981e6 | 128 | unsigned long *bp = t->io_bitmap_ptr; |
389d1fb1 | 129 | |
250981e6 | 130 | if (bp) { |
24933b82 | 131 | struct tss_struct *tss = &per_cpu(cpu_tss, get_cpu()); |
389d1fb1 | 132 | |
389d1fb1 JF |
133 | t->io_bitmap_ptr = NULL; |
134 | clear_thread_flag(TIF_IO_BITMAP); | |
135 | /* | |
136 | * Careful, clear this in the TSS too: | |
137 | */ | |
138 | memset(tss->io_bitmap, 0xff, t->io_bitmap_max); | |
139 | t->io_bitmap_max = 0; | |
140 | put_cpu(); | |
250981e6 | 141 | kfree(bp); |
389d1fb1 | 142 | } |
1dcc8d7b SS |
143 | |
144 | drop_fpu(me); | |
389d1fb1 JF |
145 | } |
146 | ||
147 | void flush_thread(void) | |
148 | { | |
149 | struct task_struct *tsk = current; | |
150 | ||
24f1e32c | 151 | flush_ptrace_hw_breakpoint(tsk); |
389d1fb1 | 152 | memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); |
304bceda SS |
153 | drop_init_fpu(tsk); |
154 | /* | |
155 | * Free the FPU state for non xsave platforms. They get reallocated | |
156 | * lazily at the first use. | |
157 | */ | |
5d2bd700 | 158 | if (!use_eager_fpu()) |
304bceda | 159 | free_thread_xstate(tsk); |
389d1fb1 JF |
160 | } |
161 | ||
162 | static void hard_disable_TSC(void) | |
163 | { | |
375074cc | 164 | cr4_set_bits(X86_CR4_TSD); |
389d1fb1 JF |
165 | } |
166 | ||
167 | void disable_TSC(void) | |
168 | { | |
169 | preempt_disable(); | |
170 | if (!test_and_set_thread_flag(TIF_NOTSC)) | |
171 | /* | |
172 | * Must flip the CPU state synchronously with | |
173 | * TIF_NOTSC in the current running context. | |
174 | */ | |
175 | hard_disable_TSC(); | |
176 | preempt_enable(); | |
177 | } | |
178 | ||
179 | static void hard_enable_TSC(void) | |
180 | { | |
375074cc | 181 | cr4_clear_bits(X86_CR4_TSD); |
389d1fb1 JF |
182 | } |
183 | ||
184 | static void enable_TSC(void) | |
185 | { | |
186 | preempt_disable(); | |
187 | if (test_and_clear_thread_flag(TIF_NOTSC)) | |
188 | /* | |
189 | * Must flip the CPU state synchronously with | |
190 | * TIF_NOTSC in the current running context. | |
191 | */ | |
192 | hard_enable_TSC(); | |
193 | preempt_enable(); | |
194 | } | |
195 | ||
196 | int get_tsc_mode(unsigned long adr) | |
197 | { | |
198 | unsigned int val; | |
199 | ||
200 | if (test_thread_flag(TIF_NOTSC)) | |
201 | val = PR_TSC_SIGSEGV; | |
202 | else | |
203 | val = PR_TSC_ENABLE; | |
204 | ||
205 | return put_user(val, (unsigned int __user *)adr); | |
206 | } | |
207 | ||
208 | int set_tsc_mode(unsigned int val) | |
209 | { | |
210 | if (val == PR_TSC_SIGSEGV) | |
211 | disable_TSC(); | |
212 | else if (val == PR_TSC_ENABLE) | |
213 | enable_TSC(); | |
214 | else | |
215 | return -EINVAL; | |
216 | ||
217 | return 0; | |
218 | } | |
219 | ||
220 | void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, | |
221 | struct tss_struct *tss) | |
222 | { | |
223 | struct thread_struct *prev, *next; | |
224 | ||
225 | prev = &prev_p->thread; | |
226 | next = &next_p->thread; | |
227 | ||
ea8e61b7 PZ |
228 | if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^ |
229 | test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) { | |
230 | unsigned long debugctl = get_debugctlmsr(); | |
231 | ||
232 | debugctl &= ~DEBUGCTLMSR_BTF; | |
233 | if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) | |
234 | debugctl |= DEBUGCTLMSR_BTF; | |
235 | ||
236 | update_debugctlmsr(debugctl); | |
237 | } | |
389d1fb1 | 238 | |
389d1fb1 JF |
239 | if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^ |
240 | test_tsk_thread_flag(next_p, TIF_NOTSC)) { | |
241 | /* prev and next are different */ | |
242 | if (test_tsk_thread_flag(next_p, TIF_NOTSC)) | |
243 | hard_disable_TSC(); | |
244 | else | |
245 | hard_enable_TSC(); | |
246 | } | |
247 | ||
248 | if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) { | |
249 | /* | |
250 | * Copy the relevant range of the IO bitmap. | |
251 | * Normally this is 128 bytes or less: | |
252 | */ | |
253 | memcpy(tss->io_bitmap, next->io_bitmap_ptr, | |
254 | max(prev->io_bitmap_max, next->io_bitmap_max)); | |
255 | } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) { | |
256 | /* | |
257 | * Clear any possible leftover bits: | |
258 | */ | |
259 | memset(tss->io_bitmap, 0xff, prev->io_bitmap_max); | |
260 | } | |
7c68af6e | 261 | propagate_user_return_notify(prev_p, next_p); |
389d1fb1 JF |
262 | } |
263 | ||
00dba564 TG |
264 | /* |
265 | * Idle related variables and functions | |
266 | */ | |
d1896049 | 267 | unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; |
00dba564 TG |
268 | EXPORT_SYMBOL(boot_option_idle_override); |
269 | ||
a476bda3 | 270 | static void (*x86_idle)(void); |
00dba564 | 271 | |
90e24014 RW |
272 | #ifndef CONFIG_SMP |
273 | static inline void play_dead(void) | |
274 | { | |
275 | BUG(); | |
276 | } | |
277 | #endif | |
278 | ||
279 | #ifdef CONFIG_X86_64 | |
280 | void enter_idle(void) | |
281 | { | |
c6ae41e7 | 282 | this_cpu_write(is_idle, 1); |
90e24014 RW |
283 | atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL); |
284 | } | |
285 | ||
286 | static void __exit_idle(void) | |
287 | { | |
288 | if (x86_test_and_clear_bit_percpu(0, is_idle) == 0) | |
289 | return; | |
290 | atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL); | |
291 | } | |
292 | ||
293 | /* Called from interrupts to signify idle end */ | |
294 | void exit_idle(void) | |
295 | { | |
296 | /* idle loop has pid 0 */ | |
297 | if (current->pid) | |
298 | return; | |
299 | __exit_idle(); | |
300 | } | |
301 | #endif | |
302 | ||
7d1a9417 TG |
303 | void arch_cpu_idle_enter(void) |
304 | { | |
305 | local_touch_nmi(); | |
306 | enter_idle(); | |
307 | } | |
90e24014 | 308 | |
7d1a9417 TG |
309 | void arch_cpu_idle_exit(void) |
310 | { | |
311 | __exit_idle(); | |
312 | } | |
90e24014 | 313 | |
7d1a9417 TG |
314 | void arch_cpu_idle_dead(void) |
315 | { | |
316 | play_dead(); | |
317 | } | |
90e24014 | 318 | |
7d1a9417 TG |
319 | /* |
320 | * Called from the generic idle code. | |
321 | */ | |
322 | void arch_cpu_idle(void) | |
323 | { | |
16f8b05a | 324 | x86_idle(); |
90e24014 RW |
325 | } |
326 | ||
00dba564 | 327 | /* |
7d1a9417 | 328 | * We use this if we don't have any better idle routine.. |
00dba564 TG |
329 | */ |
330 | void default_idle(void) | |
331 | { | |
4d0e42cc | 332 | trace_cpu_idle_rcuidle(1, smp_processor_id()); |
7d1a9417 | 333 | safe_halt(); |
4d0e42cc | 334 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); |
00dba564 | 335 | } |
60b8b1de | 336 | #ifdef CONFIG_APM_MODULE |
00dba564 TG |
337 | EXPORT_SYMBOL(default_idle); |
338 | #endif | |
339 | ||
6a377ddc LB |
340 | #ifdef CONFIG_XEN |
341 | bool xen_set_default_idle(void) | |
e5fd47bf | 342 | { |
a476bda3 | 343 | bool ret = !!x86_idle; |
e5fd47bf | 344 | |
a476bda3 | 345 | x86_idle = default_idle; |
e5fd47bf KRW |
346 | |
347 | return ret; | |
348 | } | |
6a377ddc | 349 | #endif |
d3ec5cae IV |
350 | void stop_this_cpu(void *dummy) |
351 | { | |
352 | local_irq_disable(); | |
353 | /* | |
354 | * Remove this CPU: | |
355 | */ | |
4f062896 | 356 | set_cpu_online(smp_processor_id(), false); |
d3ec5cae IV |
357 | disable_local_APIC(); |
358 | ||
27be4570 LB |
359 | for (;;) |
360 | halt(); | |
7f424a8b PZ |
361 | } |
362 | ||
02c68a02 LB |
363 | bool amd_e400_c1e_detected; |
364 | EXPORT_SYMBOL(amd_e400_c1e_detected); | |
aa276e1c | 365 | |
02c68a02 | 366 | static cpumask_var_t amd_e400_c1e_mask; |
4faac97d | 367 | |
02c68a02 | 368 | void amd_e400_remove_cpu(int cpu) |
4faac97d | 369 | { |
02c68a02 LB |
370 | if (amd_e400_c1e_mask != NULL) |
371 | cpumask_clear_cpu(cpu, amd_e400_c1e_mask); | |
4faac97d TG |
372 | } |
373 | ||
aa276e1c | 374 | /* |
02c68a02 | 375 | * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt |
aa276e1c TG |
376 | * pending message MSR. If we detect C1E, then we handle it the same |
377 | * way as C3 power states (local apic timer and TSC stop) | |
378 | */ | |
02c68a02 | 379 | static void amd_e400_idle(void) |
aa276e1c | 380 | { |
02c68a02 | 381 | if (!amd_e400_c1e_detected) { |
aa276e1c TG |
382 | u32 lo, hi; |
383 | ||
384 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); | |
e8c534ec | 385 | |
aa276e1c | 386 | if (lo & K8_INTP_C1E_ACTIVE_MASK) { |
02c68a02 | 387 | amd_e400_c1e_detected = true; |
40fb1715 | 388 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
09bfeea1 | 389 | mark_tsc_unstable("TSC halt in AMD C1E"); |
c767a54b | 390 | pr_info("System has AMD C1E enabled\n"); |
aa276e1c TG |
391 | } |
392 | } | |
393 | ||
02c68a02 | 394 | if (amd_e400_c1e_detected) { |
aa276e1c TG |
395 | int cpu = smp_processor_id(); |
396 | ||
02c68a02 LB |
397 | if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) { |
398 | cpumask_set_cpu(cpu, amd_e400_c1e_mask); | |
0beefa20 | 399 | /* |
f833bab8 | 400 | * Force broadcast so ACPI can not interfere. |
0beefa20 | 401 | */ |
aa276e1c TG |
402 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE, |
403 | &cpu); | |
c767a54b | 404 | pr_info("Switch to broadcast mode on CPU%d\n", cpu); |
aa276e1c TG |
405 | } |
406 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu); | |
0beefa20 | 407 | |
aa276e1c | 408 | default_idle(); |
0beefa20 TG |
409 | |
410 | /* | |
411 | * The switch back from broadcast mode needs to be | |
412 | * called with interrupts disabled. | |
413 | */ | |
ea811747 PZ |
414 | local_irq_disable(); |
415 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu); | |
416 | local_irq_enable(); | |
aa276e1c TG |
417 | } else |
418 | default_idle(); | |
419 | } | |
420 | ||
148f9bb8 | 421 | void select_idle_routine(const struct cpuinfo_x86 *c) |
7f424a8b | 422 | { |
3e5095d1 | 423 | #ifdef CONFIG_SMP |
7d1a9417 | 424 | if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1) |
c767a54b | 425 | pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n"); |
7f424a8b | 426 | #endif |
7d1a9417 | 427 | if (x86_idle || boot_option_idle_override == IDLE_POLL) |
6ddd2a27 TG |
428 | return; |
429 | ||
7d7dc116 | 430 | if (cpu_has_bug(c, X86_BUG_AMD_APIC_C1E)) { |
9d8888c2 | 431 | /* E400: APIC timer interrupt does not wake up CPU from C1e */ |
c767a54b | 432 | pr_info("using AMD E400 aware idle routine\n"); |
a476bda3 | 433 | x86_idle = amd_e400_idle; |
6ddd2a27 | 434 | } else |
a476bda3 | 435 | x86_idle = default_idle; |
7f424a8b PZ |
436 | } |
437 | ||
02c68a02 | 438 | void __init init_amd_e400_c1e_mask(void) |
30e1e6d1 | 439 | { |
02c68a02 | 440 | /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */ |
a476bda3 | 441 | if (x86_idle == amd_e400_idle) |
02c68a02 | 442 | zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL); |
30e1e6d1 RR |
443 | } |
444 | ||
7f424a8b PZ |
445 | static int __init idle_setup(char *str) |
446 | { | |
ab6bc3e3 CG |
447 | if (!str) |
448 | return -EINVAL; | |
449 | ||
7f424a8b | 450 | if (!strcmp(str, "poll")) { |
c767a54b | 451 | pr_info("using polling idle threads\n"); |
d1896049 | 452 | boot_option_idle_override = IDLE_POLL; |
7d1a9417 | 453 | cpu_idle_poll_ctrl(true); |
d1896049 | 454 | } else if (!strcmp(str, "halt")) { |
c1e3b377 ZY |
455 | /* |
456 | * When the boot option of idle=halt is added, halt is | |
457 | * forced to be used for CPU idle. In such case CPU C2/C3 | |
458 | * won't be used again. | |
459 | * To continue to load the CPU idle driver, don't touch | |
460 | * the boot_option_idle_override. | |
461 | */ | |
a476bda3 | 462 | x86_idle = default_idle; |
d1896049 | 463 | boot_option_idle_override = IDLE_HALT; |
da5e09a1 ZY |
464 | } else if (!strcmp(str, "nomwait")) { |
465 | /* | |
466 | * If the boot option of "idle=nomwait" is added, | |
467 | * it means that mwait will be disabled for CPU C2/C3 | |
468 | * states. In such case it won't touch the variable | |
469 | * of boot_option_idle_override. | |
470 | */ | |
d1896049 | 471 | boot_option_idle_override = IDLE_NOMWAIT; |
c1e3b377 | 472 | } else |
7f424a8b PZ |
473 | return -1; |
474 | ||
7f424a8b PZ |
475 | return 0; |
476 | } | |
477 | early_param("idle", idle_setup); | |
478 | ||
9d62dcdf AW |
479 | unsigned long arch_align_stack(unsigned long sp) |
480 | { | |
481 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
482 | sp -= get_random_int() % 8192; | |
483 | return sp & ~0xf; | |
484 | } | |
485 | ||
486 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
487 | { | |
488 | unsigned long range_end = mm->brk + 0x02000000; | |
489 | return randomize_range(mm->brk, range_end, 0) ? : mm->brk; | |
490 | } | |
491 |