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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
c767a54b JP |
2 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
3 | ||
61c4628b SS |
4 | #include <linux/errno.h> |
5 | #include <linux/kernel.h> | |
6 | #include <linux/mm.h> | |
7 | #include <linux/smp.h> | |
b4c108d7 | 8 | #include <linux/cpu.h> |
389d1fb1 | 9 | #include <linux/prctl.h> |
61c4628b SS |
10 | #include <linux/slab.h> |
11 | #include <linux/sched.h> | |
4c822698 | 12 | #include <linux/sched/idle.h> |
b17b0153 | 13 | #include <linux/sched/debug.h> |
29930025 | 14 | #include <linux/sched/task.h> |
68db0cf1 | 15 | #include <linux/sched/task_stack.h> |
186f4360 PG |
16 | #include <linux/init.h> |
17 | #include <linux/export.h> | |
7f424a8b | 18 | #include <linux/pm.h> |
162a688e | 19 | #include <linux/tick.h> |
9d62dcdf | 20 | #include <linux/random.h> |
7c68af6e | 21 | #include <linux/user-return-notifier.h> |
814e2c84 AI |
22 | #include <linux/dmi.h> |
23 | #include <linux/utsname.h> | |
90e24014 | 24 | #include <linux/stackprotector.h> |
90e24014 | 25 | #include <linux/cpuidle.h> |
89f579ce YW |
26 | #include <linux/acpi.h> |
27 | #include <linux/elf-randomize.h> | |
aaa3896b | 28 | #include <linux/static_call.h> |
61613521 | 29 | #include <trace/events/power.h> |
24f1e32c | 30 | #include <linux/hw_breakpoint.h> |
3aec4ecb | 31 | #include <linux/entry-common.h> |
93789b32 | 32 | #include <asm/cpu.h> |
d3ec5cae | 33 | #include <asm/apic.h> |
7c0f6ba6 | 34 | #include <linux/uaccess.h> |
b253149b | 35 | #include <asm/mwait.h> |
db8268df | 36 | #include <asm/fpu/api.h> |
63e81807 | 37 | #include <asm/fpu/sched.h> |
500afbf6 | 38 | #include <asm/fpu/xstate.h> |
66cb5917 | 39 | #include <asm/debugreg.h> |
90e24014 | 40 | #include <asm/nmi.h> |
375074cc | 41 | #include <asm/tlbflush.h> |
8838eb6c | 42 | #include <asm/mce.h> |
9fda6a06 | 43 | #include <asm/vm86.h> |
7b32aead | 44 | #include <asm/switch_to.h> |
b7ffc44d | 45 | #include <asm/desc.h> |
e9ea1e7f | 46 | #include <asm/prctl.h> |
885f82bf | 47 | #include <asm/spec-ctrl.h> |
577d5cd7 | 48 | #include <asm/io_bitmap.h> |
89f579ce | 49 | #include <asm/proto.h> |
6f9885a3 | 50 | #include <asm/frame.h> |
5d1ceb39 | 51 | #include <asm/unwind.h> |
bfe6ed0c | 52 | #include <asm/tdx.h> |
74c228d2 | 53 | #include <asm/mmu_context.h> |
90e24014 | 54 | |
ff16701a TG |
55 | #include "process.h" |
56 | ||
45046892 TG |
57 | /* |
58 | * per-CPU TSS segments. Threads are completely 'soft' on Linux, | |
59 | * no more per-task TSS's. The TSS size is kept cacheline-aligned | |
60 | * so they are allowed to end up in the .data..cacheline_aligned | |
61 | * section. Since TSS's are completely CPU-local, we want them | |
62 | * on exact cacheline boundaries, to eliminate cacheline ping-pong. | |
63 | */ | |
2fd9c41a | 64 | __visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = { |
d0a0de21 | 65 | .x86_tss = { |
20bb8344 AL |
66 | /* |
67 | * .sp0 is only used when entering ring 0 from a lower | |
68 | * privilege level. Since the init task never runs anything | |
69 | * but ring 0 code, there is no need for a valid value here. | |
70 | * Poison it. | |
71 | */ | |
72 | .sp0 = (1UL << (BITS_PER_LONG-1)) + 1, | |
9aaefe7b | 73 | |
1591584e | 74 | #ifdef CONFIG_X86_32 |
9aaefe7b | 75 | .sp1 = TOP_OF_INIT_STACK, |
9aaefe7b | 76 | |
d0a0de21 AL |
77 | .ss0 = __KERNEL_DS, |
78 | .ss1 = __KERNEL_CS, | |
d0a0de21 | 79 | #endif |
ecc7e37d | 80 | .io_bitmap_base = IO_BITMAP_OFFSET_INVALID, |
d0a0de21 | 81 | }, |
d0a0de21 | 82 | }; |
c482feef | 83 | EXPORT_PER_CPU_SYMBOL(cpu_tss_rw); |
45046892 | 84 | |
b7ceaec1 AL |
85 | DEFINE_PER_CPU(bool, __tss_limit_invalid); |
86 | EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid); | |
b7ffc44d | 87 | |
55ccf3fe SS |
88 | /* |
89 | * this gets called so that we can store lazy state into memory and copy the | |
90 | * current task into the new thread. | |
91 | */ | |
61c4628b SS |
92 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
93 | { | |
5aaeb5c0 | 94 | memcpy(dst, src, arch_task_struct_size); |
2459ee86 AL |
95 | #ifdef CONFIG_VM86 |
96 | dst->thread.vm86 = NULL; | |
97 | #endif | |
f0cbc8b3 TG |
98 | /* Drop the copied pointer to current's fpstate */ |
99 | dst->thread.fpu.fpstate = NULL; | |
500afbf6 | 100 | |
2d16a187 | 101 | return 0; |
61c4628b | 102 | } |
7f424a8b | 103 | |
500afbf6 CB |
104 | #ifdef CONFIG_X86_64 |
105 | void arch_release_task_struct(struct task_struct *tsk) | |
106 | { | |
107 | if (fpu_state_size_dynamic()) | |
108 | fpstate_free(&tsk->thread.fpu); | |
61c4628b | 109 | } |
500afbf6 | 110 | #endif |
7f424a8b | 111 | |
389d1fb1 | 112 | /* |
4bfe6cce | 113 | * Free thread data structures etc.. |
389d1fb1 | 114 | */ |
e6464694 | 115 | void exit_thread(struct task_struct *tsk) |
389d1fb1 | 116 | { |
e6464694 | 117 | struct thread_struct *t = &tsk->thread; |
ca6787ba | 118 | struct fpu *fpu = &t->fpu; |
ea5f1cd7 TG |
119 | |
120 | if (test_thread_flag(TIF_IO_BITMAP)) | |
4bfe6cce | 121 | io_bitmap_exit(tsk); |
1dcc8d7b | 122 | |
9fda6a06 BG |
123 | free_vm86(t); |
124 | ||
50338615 | 125 | fpu__drop(fpu); |
389d1fb1 JF |
126 | } |
127 | ||
2fff071d TG |
128 | static int set_new_tls(struct task_struct *p, unsigned long tls) |
129 | { | |
130 | struct user_desc __user *utls = (struct user_desc __user *)tls; | |
131 | ||
132 | if (in_ia32_syscall()) | |
133 | return do_set_thread_area(p, -1, utls, 0); | |
134 | else | |
135 | return do_set_thread_area_64(p, ARCH_SET_FS, tls); | |
136 | } | |
137 | ||
3aec4ecb BG |
138 | __visible void ret_from_fork(struct task_struct *prev, struct pt_regs *regs, |
139 | int (*fn)(void *), void *fn_arg) | |
140 | { | |
141 | schedule_tail(prev); | |
142 | ||
143 | /* Is this a kernel thread? */ | |
144 | if (unlikely(fn)) { | |
145 | fn(fn_arg); | |
146 | /* | |
147 | * A kernel thread is allowed to return here after successfully | |
148 | * calling kernel_execve(). Exit to userspace to complete the | |
149 | * execve() syscall. | |
150 | */ | |
151 | regs->ax = 0; | |
152 | } | |
153 | ||
154 | syscall_exit_to_user_mode(regs); | |
155 | } | |
156 | ||
c5febea0 | 157 | int copy_thread(struct task_struct *p, const struct kernel_clone_args *args) |
2fff071d | 158 | { |
c5febea0 EB |
159 | unsigned long clone_flags = args->flags; |
160 | unsigned long sp = args->stack; | |
c5febea0 | 161 | unsigned long tls = args->tls; |
2fff071d TG |
162 | struct inactive_task_frame *frame; |
163 | struct fork_frame *fork_frame; | |
164 | struct pt_regs *childregs; | |
4804e382 | 165 | int ret = 0; |
2fff071d TG |
166 | |
167 | childregs = task_pt_regs(p); | |
168 | fork_frame = container_of(childregs, struct fork_frame, regs); | |
169 | frame = &fork_frame->frame; | |
170 | ||
6f9885a3 | 171 | frame->bp = encode_frame_pointer(childregs); |
3aec4ecb | 172 | frame->ret_addr = (unsigned long) ret_from_fork_asm; |
2fff071d | 173 | p->thread.sp = (unsigned long) fork_frame; |
577d5cd7 | 174 | p->thread.io_bitmap = NULL; |
b968e84b | 175 | p->thread.iopl_warn = 0; |
2fff071d TG |
176 | memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps)); |
177 | ||
178 | #ifdef CONFIG_X86_64 | |
005f141e CB |
179 | current_save_fsgs(); |
180 | p->thread.fsindex = current->thread.fsindex; | |
181 | p->thread.fsbase = current->thread.fsbase; | |
182 | p->thread.gsindex = current->thread.gsindex; | |
183 | p->thread.gsbase = current->thread.gsbase; | |
184 | ||
2fff071d TG |
185 | savesegment(es, p->thread.es); |
186 | savesegment(ds, p->thread.ds); | |
2f8794bd KS |
187 | |
188 | if (p->mm && (clone_flags & (CLONE_VM | CLONE_VFORK)) == CLONE_VM) | |
189 | set_bit(MM_CONTEXT_LOCK_LAM, &p->mm->context.flags); | |
2fff071d TG |
190 | #else |
191 | p->thread.sp0 = (unsigned long) (childregs + 1); | |
3a24a608 | 192 | savesegment(gs, p->thread.gs); |
2fff071d TG |
193 | /* |
194 | * Clear all status flags including IF and set fixed bit. 64bit | |
195 | * does not have this initialization as the frame does not contain | |
196 | * flags. The flags consistency (especially vs. AC) is there | |
197 | * ensured via objtool, which lacks 32bit support. | |
198 | */ | |
199 | frame->flags = X86_EFLAGS_FIXED; | |
200 | #endif | |
201 | ||
5bd2e97c | 202 | fpu_clone(p, clone_flags, args->fn); |
2d16a187 | 203 | |
2fff071d | 204 | /* Kernel thread ? */ |
50b7b6f2 | 205 | if (unlikely(p->flags & PF_KTHREAD)) { |
9782a712 | 206 | p->thread.pkru = pkru_get_init_value(); |
2fff071d | 207 | memset(childregs, 0, sizeof(struct pt_regs)); |
5bd2e97c | 208 | kthread_frame_init(frame, args->fn, args->fn_arg); |
2fff071d TG |
209 | return 0; |
210 | } | |
211 | ||
9782a712 DH |
212 | /* |
213 | * Clone current's PKRU value from hardware. tsk->thread.pkru | |
214 | * is only valid when scheduled out. | |
215 | */ | |
216 | p->thread.pkru = read_pkru(); | |
217 | ||
2fff071d TG |
218 | frame->bx = 0; |
219 | *childregs = *current_pt_regs(); | |
220 | childregs->ax = 0; | |
221 | if (sp) | |
222 | childregs->sp = sp; | |
223 | ||
5bd2e97c | 224 | if (unlikely(args->fn)) { |
50b7b6f2 | 225 | /* |
5bd2e97c EB |
226 | * A user space thread, but it doesn't return to |
227 | * ret_after_fork(). | |
50b7b6f2 SM |
228 | * |
229 | * In order to indicate that to tools like gdb, | |
230 | * we reset the stack and instruction pointers. | |
231 | * | |
232 | * It does the same kernel frame setup to return to a kernel | |
233 | * function that a kernel thread does. | |
234 | */ | |
235 | childregs->sp = 0; | |
236 | childregs->ip = 0; | |
5bd2e97c | 237 | kthread_frame_init(frame, args->fn, args->fn_arg); |
50b7b6f2 SM |
238 | return 0; |
239 | } | |
240 | ||
2fff071d | 241 | /* Set a new TLS for the child thread? */ |
4804e382 | 242 | if (clone_flags & CLONE_SETTLS) |
2fff071d | 243 | ret = set_new_tls(p, tls); |
4804e382 TG |
244 | |
245 | if (!ret && unlikely(test_tsk_thread_flag(current, TIF_IO_BITMAP))) | |
246 | io_bitmap_share(p); | |
247 | ||
2fff071d TG |
248 | return ret; |
249 | } | |
250 | ||
33344368 AL |
251 | static void pkru_flush_thread(void) |
252 | { | |
253 | /* | |
254 | * If PKRU is enabled the default PKRU value has to be loaded into | |
255 | * the hardware right here (similar to context switch). | |
256 | */ | |
257 | pkru_write_default(); | |
258 | } | |
259 | ||
389d1fb1 JF |
260 | void flush_thread(void) |
261 | { | |
262 | struct task_struct *tsk = current; | |
263 | ||
24f1e32c | 264 | flush_ptrace_hw_breakpoint(tsk); |
389d1fb1 | 265 | memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); |
110d7f75 | 266 | |
e7ecad17 | 267 | fpu_flush_thread(); |
33344368 | 268 | pkru_flush_thread(); |
389d1fb1 JF |
269 | } |
270 | ||
389d1fb1 JF |
271 | void disable_TSC(void) |
272 | { | |
273 | preempt_disable(); | |
274 | if (!test_and_set_thread_flag(TIF_NOTSC)) | |
275 | /* | |
276 | * Must flip the CPU state synchronously with | |
277 | * TIF_NOTSC in the current running context. | |
278 | */ | |
5a920155 | 279 | cr4_set_bits(X86_CR4_TSD); |
389d1fb1 JF |
280 | preempt_enable(); |
281 | } | |
282 | ||
389d1fb1 JF |
283 | static void enable_TSC(void) |
284 | { | |
285 | preempt_disable(); | |
286 | if (test_and_clear_thread_flag(TIF_NOTSC)) | |
287 | /* | |
288 | * Must flip the CPU state synchronously with | |
289 | * TIF_NOTSC in the current running context. | |
290 | */ | |
5a920155 | 291 | cr4_clear_bits(X86_CR4_TSD); |
389d1fb1 JF |
292 | preempt_enable(); |
293 | } | |
294 | ||
295 | int get_tsc_mode(unsigned long adr) | |
296 | { | |
297 | unsigned int val; | |
298 | ||
299 | if (test_thread_flag(TIF_NOTSC)) | |
300 | val = PR_TSC_SIGSEGV; | |
301 | else | |
302 | val = PR_TSC_ENABLE; | |
303 | ||
304 | return put_user(val, (unsigned int __user *)adr); | |
305 | } | |
306 | ||
307 | int set_tsc_mode(unsigned int val) | |
308 | { | |
309 | if (val == PR_TSC_SIGSEGV) | |
310 | disable_TSC(); | |
311 | else if (val == PR_TSC_ENABLE) | |
312 | enable_TSC(); | |
313 | else | |
314 | return -EINVAL; | |
315 | ||
316 | return 0; | |
317 | } | |
318 | ||
e9ea1e7f KH |
319 | DEFINE_PER_CPU(u64, msr_misc_features_shadow); |
320 | ||
321 | static void set_cpuid_faulting(bool on) | |
322 | { | |
323 | u64 msrval; | |
324 | ||
325 | msrval = this_cpu_read(msr_misc_features_shadow); | |
326 | msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT; | |
327 | msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT); | |
328 | this_cpu_write(msr_misc_features_shadow, msrval); | |
329 | wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval); | |
330 | } | |
331 | ||
332 | static void disable_cpuid(void) | |
333 | { | |
334 | preempt_disable(); | |
335 | if (!test_and_set_thread_flag(TIF_NOCPUID)) { | |
336 | /* | |
337 | * Must flip the CPU state synchronously with | |
338 | * TIF_NOCPUID in the current running context. | |
339 | */ | |
340 | set_cpuid_faulting(true); | |
341 | } | |
342 | preempt_enable(); | |
343 | } | |
344 | ||
345 | static void enable_cpuid(void) | |
346 | { | |
347 | preempt_disable(); | |
348 | if (test_and_clear_thread_flag(TIF_NOCPUID)) { | |
349 | /* | |
350 | * Must flip the CPU state synchronously with | |
351 | * TIF_NOCPUID in the current running context. | |
352 | */ | |
353 | set_cpuid_faulting(false); | |
354 | } | |
355 | preempt_enable(); | |
356 | } | |
357 | ||
358 | static int get_cpuid_mode(void) | |
359 | { | |
360 | return !test_thread_flag(TIF_NOCPUID); | |
361 | } | |
362 | ||
f5c0b4f3 | 363 | static int set_cpuid_mode(unsigned long cpuid_enabled) |
e9ea1e7f | 364 | { |
67e87d43 | 365 | if (!boot_cpu_has(X86_FEATURE_CPUID_FAULT)) |
e9ea1e7f KH |
366 | return -ENODEV; |
367 | ||
368 | if (cpuid_enabled) | |
369 | enable_cpuid(); | |
370 | else | |
371 | disable_cpuid(); | |
372 | ||
373 | return 0; | |
374 | } | |
375 | ||
376 | /* | |
377 | * Called immediately after a successful exec. | |
378 | */ | |
379 | void arch_setup_new_exec(void) | |
380 | { | |
381 | /* If cpuid was previously disabled for this task, re-enable it. */ | |
382 | if (test_thread_flag(TIF_NOCPUID)) | |
383 | enable_cpuid(); | |
71368af9 WL |
384 | |
385 | /* | |
386 | * Don't inherit TIF_SSBD across exec boundary when | |
387 | * PR_SPEC_DISABLE_NOEXEC is used. | |
388 | */ | |
389 | if (test_thread_flag(TIF_SSBD) && | |
390 | task_spec_ssb_noexec(current)) { | |
391 | clear_thread_flag(TIF_SSBD); | |
392 | task_clear_spec_ssb_disable(current); | |
393 | task_clear_spec_ssb_noexec(current); | |
dca99fb6 | 394 | speculation_ctrl_update(read_thread_flags()); |
71368af9 | 395 | } |
74c228d2 KS |
396 | |
397 | mm_reset_untag_mask(current->mm); | |
e9ea1e7f KH |
398 | } |
399 | ||
111e7b15 | 400 | #ifdef CONFIG_X86_IOPL_IOPERM |
22fe5b04 TG |
401 | static inline void switch_to_bitmap(unsigned long tifp) |
402 | { | |
403 | /* | |
404 | * Invalidate I/O bitmap if the previous task used it. This prevents | |
405 | * any possible leakage of an active I/O bitmap. | |
406 | * | |
407 | * If the next task has an I/O bitmap it will handle it on exit to | |
408 | * user mode. | |
409 | */ | |
410 | if (tifp & _TIF_IO_BITMAP) | |
cadfad87 | 411 | tss_invalidate_io_bitmap(); |
22fe5b04 TG |
412 | } |
413 | ||
414 | static void tss_copy_io_bitmap(struct tss_struct *tss, struct io_bitmap *iobm) | |
060aa16f TG |
415 | { |
416 | /* | |
417 | * Copy at least the byte range of the incoming tasks bitmap which | |
418 | * covers the permitted I/O ports. | |
419 | * | |
420 | * If the previous task which used an I/O bitmap had more bits | |
421 | * permitted, then the copy needs to cover those as well so they | |
422 | * get turned off. | |
423 | */ | |
424 | memcpy(tss->io_bitmap.bitmap, iobm->bitmap, | |
425 | max(tss->io_bitmap.prev_max, iobm->max)); | |
426 | ||
427 | /* | |
428 | * Store the new max and the sequence number of this bitmap | |
429 | * and a pointer to the bitmap itself. | |
430 | */ | |
431 | tss->io_bitmap.prev_max = iobm->max; | |
432 | tss->io_bitmap.prev_sequence = iobm->sequence; | |
433 | } | |
434 | ||
22fe5b04 | 435 | /** |
dbb5ab6d | 436 | * native_tss_update_io_bitmap - Update I/O bitmap before exiting to user mode |
22fe5b04 | 437 | */ |
99bcd4a6 | 438 | void native_tss_update_io_bitmap(void) |
af8b3cd3 | 439 | { |
ff16701a | 440 | struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); |
7b0b8cfd | 441 | struct thread_struct *t = ¤t->thread; |
c8137ace | 442 | u16 *base = &tss->x86_tss.io_bitmap_base; |
ff16701a | 443 | |
7b0b8cfd | 444 | if (!test_thread_flag(TIF_IO_BITMAP)) { |
cadfad87 | 445 | native_tss_invalidate_io_bitmap(); |
7b0b8cfd BP |
446 | return; |
447 | } | |
448 | ||
449 | if (IS_ENABLED(CONFIG_X86_IOPL_IOPERM) && t->iopl_emul == 3) { | |
450 | *base = IO_BITMAP_OFFSET_VALID_ALL; | |
451 | } else { | |
452 | struct io_bitmap *iobm = t->io_bitmap; | |
453 | ||
af8b3cd3 | 454 | /* |
7b0b8cfd BP |
455 | * Only copy bitmap data when the sequence number differs. The |
456 | * update time is accounted to the incoming task. | |
af8b3cd3 | 457 | */ |
7b0b8cfd BP |
458 | if (tss->io_bitmap.prev_sequence != iobm->sequence) |
459 | tss_copy_io_bitmap(tss, iobm); | |
460 | ||
461 | /* Enable the bitmap */ | |
462 | *base = IO_BITMAP_OFFSET_VALID_MAP; | |
af8b3cd3 | 463 | } |
7b0b8cfd BP |
464 | |
465 | /* | |
466 | * Make sure that the TSS limit is covering the IO bitmap. It might have | |
467 | * been cut down by a VMEXIT to 0x67 which would cause a subsequent I/O | |
468 | * access from user space to trigger a #GP because tbe bitmap is outside | |
469 | * the TSS limit. | |
470 | */ | |
471 | refresh_tss_limit(); | |
af8b3cd3 | 472 | } |
111e7b15 TG |
473 | #else /* CONFIG_X86_IOPL_IOPERM */ |
474 | static inline void switch_to_bitmap(unsigned long tifp) { } | |
475 | #endif | |
af8b3cd3 | 476 | |
1f50ddb4 TG |
477 | #ifdef CONFIG_SMP |
478 | ||
479 | struct ssb_state { | |
480 | struct ssb_state *shared_state; | |
481 | raw_spinlock_t lock; | |
482 | unsigned int disable_state; | |
483 | unsigned long local_state; | |
484 | }; | |
485 | ||
486 | #define LSTATE_SSB 0 | |
487 | ||
488 | static DEFINE_PER_CPU(struct ssb_state, ssb_state); | |
489 | ||
490 | void speculative_store_bypass_ht_init(void) | |
885f82bf | 491 | { |
1f50ddb4 TG |
492 | struct ssb_state *st = this_cpu_ptr(&ssb_state); |
493 | unsigned int this_cpu = smp_processor_id(); | |
494 | unsigned int cpu; | |
495 | ||
496 | st->local_state = 0; | |
497 | ||
498 | /* | |
499 | * Shared state setup happens once on the first bringup | |
500 | * of the CPU. It's not destroyed on CPU hotunplug. | |
501 | */ | |
502 | if (st->shared_state) | |
503 | return; | |
504 | ||
505 | raw_spin_lock_init(&st->lock); | |
506 | ||
507 | /* | |
508 | * Go over HT siblings and check whether one of them has set up the | |
509 | * shared state pointer already. | |
510 | */ | |
511 | for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) { | |
512 | if (cpu == this_cpu) | |
513 | continue; | |
514 | ||
515 | if (!per_cpu(ssb_state, cpu).shared_state) | |
516 | continue; | |
517 | ||
518 | /* Link it to the state of the sibling: */ | |
519 | st->shared_state = per_cpu(ssb_state, cpu).shared_state; | |
520 | return; | |
521 | } | |
522 | ||
523 | /* | |
524 | * First HT sibling to come up on the core. Link shared state of | |
525 | * the first HT sibling to itself. The siblings on the same core | |
526 | * which come up later will see the shared state pointer and link | |
d9f6e12f | 527 | * themselves to the state of this CPU. |
1f50ddb4 TG |
528 | */ |
529 | st->shared_state = st; | |
530 | } | |
885f82bf | 531 | |
1f50ddb4 TG |
532 | /* |
533 | * Logic is: First HT sibling enables SSBD for both siblings in the core | |
534 | * and last sibling to disable it, disables it for the whole core. This how | |
535 | * MSR_SPEC_CTRL works in "hardware": | |
536 | * | |
537 | * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL | |
538 | */ | |
539 | static __always_inline void amd_set_core_ssb_state(unsigned long tifn) | |
540 | { | |
541 | struct ssb_state *st = this_cpu_ptr(&ssb_state); | |
542 | u64 msr = x86_amd_ls_cfg_base; | |
543 | ||
544 | if (!static_cpu_has(X86_FEATURE_ZEN)) { | |
545 | msr |= ssbd_tif_to_amd_ls_cfg(tifn); | |
885f82bf | 546 | wrmsrl(MSR_AMD64_LS_CFG, msr); |
1f50ddb4 TG |
547 | return; |
548 | } | |
549 | ||
550 | if (tifn & _TIF_SSBD) { | |
551 | /* | |
552 | * Since this can race with prctl(), block reentry on the | |
553 | * same CPU. | |
554 | */ | |
555 | if (__test_and_set_bit(LSTATE_SSB, &st->local_state)) | |
556 | return; | |
557 | ||
558 | msr |= x86_amd_ls_cfg_ssbd_mask; | |
559 | ||
560 | raw_spin_lock(&st->shared_state->lock); | |
561 | /* First sibling enables SSBD: */ | |
562 | if (!st->shared_state->disable_state) | |
563 | wrmsrl(MSR_AMD64_LS_CFG, msr); | |
564 | st->shared_state->disable_state++; | |
565 | raw_spin_unlock(&st->shared_state->lock); | |
885f82bf | 566 | } else { |
1f50ddb4 TG |
567 | if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state)) |
568 | return; | |
569 | ||
570 | raw_spin_lock(&st->shared_state->lock); | |
571 | st->shared_state->disable_state--; | |
572 | if (!st->shared_state->disable_state) | |
573 | wrmsrl(MSR_AMD64_LS_CFG, msr); | |
574 | raw_spin_unlock(&st->shared_state->lock); | |
885f82bf TG |
575 | } |
576 | } | |
1f50ddb4 TG |
577 | #else |
578 | static __always_inline void amd_set_core_ssb_state(unsigned long tifn) | |
579 | { | |
580 | u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn); | |
581 | ||
582 | wrmsrl(MSR_AMD64_LS_CFG, msr); | |
583 | } | |
584 | #endif | |
585 | ||
11fb0683 TL |
586 | static __always_inline void amd_set_ssb_virt_state(unsigned long tifn) |
587 | { | |
588 | /* | |
589 | * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL, | |
590 | * so ssbd_tif_to_spec_ctrl() just works. | |
591 | */ | |
592 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn)); | |
593 | } | |
594 | ||
01daf568 TC |
595 | /* |
596 | * Update the MSRs managing speculation control, during context switch. | |
597 | * | |
598 | * tifp: Previous task's thread flags | |
599 | * tifn: Next task's thread flags | |
600 | */ | |
601 | static __always_inline void __speculation_ctrl_update(unsigned long tifp, | |
602 | unsigned long tifn) | |
1f50ddb4 | 603 | { |
5bfbe3ad | 604 | unsigned long tif_diff = tifp ^ tifn; |
01daf568 TC |
605 | u64 msr = x86_spec_ctrl_base; |
606 | bool updmsr = false; | |
607 | ||
2f5fb193 TG |
608 | lockdep_assert_irqs_disabled(); |
609 | ||
dbbe2ad0 AS |
610 | /* Handle change of TIF_SSBD depending on the mitigation method. */ |
611 | if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) { | |
612 | if (tif_diff & _TIF_SSBD) | |
01daf568 | 613 | amd_set_ssb_virt_state(tifn); |
dbbe2ad0 AS |
614 | } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) { |
615 | if (tif_diff & _TIF_SSBD) | |
01daf568 | 616 | amd_set_core_ssb_state(tifn); |
dbbe2ad0 AS |
617 | } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || |
618 | static_cpu_has(X86_FEATURE_AMD_SSBD)) { | |
619 | updmsr |= !!(tif_diff & _TIF_SSBD); | |
620 | msr |= ssbd_tif_to_spec_ctrl(tifn); | |
01daf568 | 621 | } |
1f50ddb4 | 622 | |
dbbe2ad0 | 623 | /* Only evaluate TIF_SPEC_IB if conditional STIBP is enabled. */ |
5bfbe3ad TC |
624 | if (IS_ENABLED(CONFIG_SMP) && |
625 | static_branch_unlikely(&switch_to_cond_stibp)) { | |
626 | updmsr |= !!(tif_diff & _TIF_SPEC_IB); | |
627 | msr |= stibp_tif_to_spec_ctrl(tifn); | |
628 | } | |
629 | ||
01daf568 | 630 | if (updmsr) |
66065157 | 631 | update_spec_ctrl_cond(msr); |
1f50ddb4 TG |
632 | } |
633 | ||
6d991ba5 | 634 | static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk) |
1f50ddb4 | 635 | { |
6d991ba5 TG |
636 | if (test_and_clear_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE)) { |
637 | if (task_spec_ssb_disable(tsk)) | |
638 | set_tsk_thread_flag(tsk, TIF_SSBD); | |
639 | else | |
640 | clear_tsk_thread_flag(tsk, TIF_SSBD); | |
9137bb27 TG |
641 | |
642 | if (task_spec_ib_disable(tsk)) | |
643 | set_tsk_thread_flag(tsk, TIF_SPEC_IB); | |
644 | else | |
645 | clear_tsk_thread_flag(tsk, TIF_SPEC_IB); | |
6d991ba5 TG |
646 | } |
647 | /* Return the updated threadinfo flags*/ | |
dca99fb6 | 648 | return read_task_thread_flags(tsk); |
1f50ddb4 | 649 | } |
885f82bf | 650 | |
26c4d75b | 651 | void speculation_ctrl_update(unsigned long tif) |
885f82bf | 652 | { |
2f5fb193 TG |
653 | unsigned long flags; |
654 | ||
01daf568 | 655 | /* Forced update. Make sure all relevant TIF flags are different */ |
2f5fb193 | 656 | local_irq_save(flags); |
01daf568 | 657 | __speculation_ctrl_update(~tif, tif); |
2f5fb193 | 658 | local_irq_restore(flags); |
885f82bf TG |
659 | } |
660 | ||
6d991ba5 TG |
661 | /* Called from seccomp/prctl update */ |
662 | void speculation_ctrl_update_current(void) | |
663 | { | |
664 | preempt_disable(); | |
665 | speculation_ctrl_update(speculation_ctrl_update_tif(current)); | |
666 | preempt_enable(); | |
667 | } | |
668 | ||
d8f0b353 TG |
669 | static inline void cr4_toggle_bits_irqsoff(unsigned long mask) |
670 | { | |
671 | unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4); | |
672 | ||
673 | newval = cr4 ^ mask; | |
674 | if (newval != cr4) { | |
675 | this_cpu_write(cpu_tlbstate.cr4, newval); | |
676 | __write_cr4(newval); | |
677 | } | |
678 | } | |
679 | ||
ff16701a | 680 | void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p) |
389d1fb1 | 681 | { |
af8b3cd3 | 682 | unsigned long tifp, tifn; |
389d1fb1 | 683 | |
dca99fb6 MR |
684 | tifn = read_task_thread_flags(next_p); |
685 | tifp = read_task_thread_flags(prev_p); | |
22fe5b04 TG |
686 | |
687 | switch_to_bitmap(tifp); | |
af8b3cd3 KH |
688 | |
689 | propagate_user_return_notify(prev_p, next_p); | |
690 | ||
b9894a2f KH |
691 | if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) && |
692 | arch_has_block_step()) { | |
693 | unsigned long debugctl, msk; | |
ea8e61b7 | 694 | |
b9894a2f | 695 | rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); |
ea8e61b7 | 696 | debugctl &= ~DEBUGCTLMSR_BTF; |
b9894a2f KH |
697 | msk = tifn & _TIF_BLOCKSTEP; |
698 | debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT; | |
699 | wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); | |
ea8e61b7 | 700 | } |
389d1fb1 | 701 | |
5a920155 | 702 | if ((tifp ^ tifn) & _TIF_NOTSC) |
9d0b6232 | 703 | cr4_toggle_bits_irqsoff(X86_CR4_TSD); |
e9ea1e7f KH |
704 | |
705 | if ((tifp ^ tifn) & _TIF_NOCPUID) | |
706 | set_cpuid_faulting(!!(tifn & _TIF_NOCPUID)); | |
885f82bf | 707 | |
6d991ba5 TG |
708 | if (likely(!((tifp | tifn) & _TIF_SPEC_FORCE_UPDATE))) { |
709 | __speculation_ctrl_update(tifp, tifn); | |
710 | } else { | |
711 | speculation_ctrl_update_tif(prev_p); | |
712 | tifn = speculation_ctrl_update_tif(next_p); | |
713 | ||
714 | /* Enforce MSR update to ensure consistent state */ | |
715 | __speculation_ctrl_update(~tifn, tifn); | |
716 | } | |
389d1fb1 JF |
717 | } |
718 | ||
00dba564 TG |
719 | /* |
720 | * Idle related variables and functions | |
721 | */ | |
d1896049 | 722 | unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; |
00dba564 TG |
723 | EXPORT_SYMBOL(boot_option_idle_override); |
724 | ||
aaa3896b PZ |
725 | /* |
726 | * We use this if we don't have any better idle routine.. | |
727 | */ | |
728 | void __cpuidle default_idle(void) | |
729 | { | |
730 | raw_safe_halt(); | |
89b30987 | 731 | raw_local_irq_disable(); |
aaa3896b PZ |
732 | } |
733 | #if defined(CONFIG_APM_MODULE) || defined(CONFIG_HALTPOLL_CPUIDLE_MODULE) | |
734 | EXPORT_SYMBOL(default_idle); | |
735 | #endif | |
736 | ||
737 | DEFINE_STATIC_CALL_NULL(x86_idle, default_idle); | |
738 | ||
739 | static bool x86_idle_set(void) | |
740 | { | |
741 | return !!static_call_query(x86_idle); | |
742 | } | |
00dba564 | 743 | |
90e24014 | 744 | #ifndef CONFIG_SMP |
eab89405 | 745 | static inline void __noreturn play_dead(void) |
90e24014 RW |
746 | { |
747 | BUG(); | |
748 | } | |
749 | #endif | |
750 | ||
7d1a9417 TG |
751 | void arch_cpu_idle_enter(void) |
752 | { | |
6a369583 | 753 | tsc_verify_tsc_adjust(false); |
7d1a9417 | 754 | local_touch_nmi(); |
7d1a9417 | 755 | } |
90e24014 | 756 | |
071c44e4 | 757 | void __noreturn arch_cpu_idle_dead(void) |
7d1a9417 TG |
758 | { |
759 | play_dead(); | |
760 | } | |
90e24014 | 761 | |
7d1a9417 TG |
762 | /* |
763 | * Called from the generic idle code. | |
764 | */ | |
aaa3896b | 765 | void __cpuidle arch_cpu_idle(void) |
00dba564 | 766 | { |
aaa3896b | 767 | static_call(x86_idle)(); |
00dba564 | 768 | } |
716ff71a | 769 | EXPORT_SYMBOL_GPL(arch_cpu_idle); |
00dba564 | 770 | |
6a377ddc LB |
771 | #ifdef CONFIG_XEN |
772 | bool xen_set_default_idle(void) | |
e5fd47bf | 773 | { |
aaa3896b | 774 | bool ret = x86_idle_set(); |
e5fd47bf | 775 | |
aaa3896b | 776 | static_call_update(x86_idle, default_idle); |
e5fd47bf KRW |
777 | |
778 | return ret; | |
779 | } | |
6a377ddc | 780 | #endif |
bba4ed01 | 781 | |
1f5e7eb7 TG |
782 | struct cpumask cpus_stop_mask; |
783 | ||
f9cdf7ca | 784 | void __noreturn stop_this_cpu(void *dummy) |
d3ec5cae | 785 | { |
9b040453 | 786 | struct cpuinfo_x86 *c = this_cpu_ptr(&cpu_info); |
1f5e7eb7 TG |
787 | unsigned int cpu = smp_processor_id(); |
788 | ||
d3ec5cae | 789 | local_irq_disable(); |
1f5e7eb7 | 790 | |
d3ec5cae | 791 | /* |
1f5e7eb7 TG |
792 | * Remove this CPU from the online mask and disable it |
793 | * unconditionally. This might be redundant in case that the reboot | |
794 | * vector was handled late and stop_other_cpus() sent an NMI. | |
795 | * | |
796 | * According to SDM and APM NMIs can be accepted even after soft | |
797 | * disabling the local APIC. | |
d3ec5cae | 798 | */ |
1f5e7eb7 | 799 | set_cpu_online(cpu, false); |
d3ec5cae | 800 | disable_local_APIC(); |
9b040453 | 801 | mcheck_cpu_clear(c); |
d3ec5cae | 802 | |
f23d74f6 TL |
803 | /* |
804 | * Use wbinvd on processors that support SME. This provides support | |
805 | * for performing a successful kexec when going from SME inactive | |
806 | * to SME active (or vice-versa). The cache must be cleared so that | |
807 | * if there are entries with the same physical address, both with and | |
808 | * without the encryption bit, they don't race each other when flushed | |
809 | * and potentially end up with the wrong entry being committed to | |
810 | * memory. | |
08f253ec ML |
811 | * |
812 | * Test the CPUID bit directly because the machine might've cleared | |
813 | * X86_FEATURE_SME due to cmdline options. | |
f23d74f6 | 814 | */ |
9b040453 | 815 | if (c->extended_cpuid_level >= 0x8000001f && (cpuid_eax(0x8000001f) & BIT(0))) |
f23d74f6 | 816 | native_wbinvd(); |
1f5e7eb7 TG |
817 | |
818 | /* | |
819 | * This brings a cache line back and dirties it, but | |
820 | * native_stop_other_cpus() will overwrite cpus_stop_mask after it | |
821 | * observed that all CPUs reported stop. This write will invalidate | |
822 | * the related cache line on this CPU. | |
823 | */ | |
824 | cpumask_clear_cpu(cpu, &cpus_stop_mask); | |
825 | ||
bba4ed01 TL |
826 | for (;;) { |
827 | /* | |
f23d74f6 TL |
828 | * Use native_halt() so that memory contents don't change |
829 | * (stack usage and variables) after possibly issuing the | |
830 | * native_wbinvd() above. | |
bba4ed01 | 831 | */ |
f23d74f6 | 832 | native_halt(); |
bba4ed01 | 833 | } |
7f424a8b PZ |
834 | } |
835 | ||
aa276e1c | 836 | /* |
07c94a38 BP |
837 | * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power |
838 | * states (local apic timer and TSC stop). | |
58c644ba PZ |
839 | * |
840 | * XXX this function is completely buggered vs RCU and tracing. | |
aa276e1c | 841 | */ |
02c68a02 | 842 | static void amd_e400_idle(void) |
aa276e1c | 843 | { |
07c94a38 BP |
844 | /* |
845 | * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E | |
846 | * gets set after static_cpu_has() places have been converted via | |
847 | * alternatives. | |
848 | */ | |
849 | if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { | |
850 | default_idle(); | |
851 | return; | |
aa276e1c TG |
852 | } |
853 | ||
07c94a38 | 854 | tick_broadcast_enter(); |
aa276e1c | 855 | |
07c94a38 | 856 | default_idle(); |
0beefa20 | 857 | |
07c94a38 | 858 | tick_broadcast_exit(); |
aa276e1c TG |
859 | } |
860 | ||
b253149b | 861 | /* |
aebef63c WK |
862 | * Prefer MWAIT over HALT if MWAIT is supported, MWAIT_CPUID leaf |
863 | * exists and whenever MONITOR/MWAIT extensions are present there is at | |
864 | * least one C1 substate. | |
b253149b | 865 | * |
aebef63c WK |
866 | * Do not prefer MWAIT if MONITOR instruction has a bug or idle=nomwait |
867 | * is passed to kernel commandline parameter. | |
b253149b LB |
868 | */ |
869 | static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c) | |
870 | { | |
aebef63c WK |
871 | u32 eax, ebx, ecx, edx; |
872 | ||
8bcedb4c WK |
873 | /* User has disallowed the use of MWAIT. Fallback to HALT */ |
874 | if (boot_option_idle_override == IDLE_NOMWAIT) | |
b253149b LB |
875 | return 0; |
876 | ||
aebef63c WK |
877 | /* MWAIT is not supported on this platform. Fallback to HALT */ |
878 | if (!cpu_has(c, X86_FEATURE_MWAIT)) | |
b253149b LB |
879 | return 0; |
880 | ||
aebef63c WK |
881 | /* Monitor has a bug. Fallback to HALT */ |
882 | if (boot_cpu_has_bug(X86_BUG_MONITOR)) | |
b253149b LB |
883 | return 0; |
884 | ||
aebef63c WK |
885 | cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx); |
886 | ||
887 | /* | |
888 | * If MWAIT extensions are not available, it is safe to use MWAIT | |
889 | * with EAX=0, ECX=0. | |
890 | */ | |
891 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) | |
892 | return 1; | |
893 | ||
894 | /* | |
895 | * If MWAIT extensions are available, there should be at least one | |
896 | * MWAIT C1 substate present. | |
897 | */ | |
898 | return (edx & MWAIT_C1_SUBSTATE_MASK); | |
b253149b LB |
899 | } |
900 | ||
901 | /* | |
0fb0328d HR |
902 | * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT |
903 | * with interrupts enabled and no flags, which is backwards compatible with the | |
904 | * original MWAIT implementation. | |
b253149b | 905 | */ |
6727ad9e | 906 | static __cpuidle void mwait_idle(void) |
b253149b | 907 | { |
f8e617f4 MG |
908 | if (!current_set_polling_and_test()) { |
909 | if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) { | |
ca59809f | 910 | mb(); /* quirk */ |
b253149b | 911 | clflush((void *)¤t_thread_info()->flags); |
ca59809f | 912 | mb(); /* quirk */ |
f8e617f4 | 913 | } |
b253149b LB |
914 | |
915 | __monitor((void *)¤t_thread_info()->flags, 0, 0); | |
89b30987 | 916 | if (!need_resched()) { |
b253149b | 917 | __sti_mwait(0, 0); |
89b30987 PZ |
918 | raw_local_irq_disable(); |
919 | } | |
f8e617f4 MG |
920 | } |
921 | __current_clr_polling(); | |
b253149b LB |
922 | } |
923 | ||
148f9bb8 | 924 | void select_idle_routine(const struct cpuinfo_x86 *c) |
7f424a8b | 925 | { |
3e5095d1 | 926 | #ifdef CONFIG_SMP |
7d1a9417 | 927 | if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1) |
c767a54b | 928 | pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n"); |
7f424a8b | 929 | #endif |
aaa3896b | 930 | if (x86_idle_set() || boot_option_idle_override == IDLE_POLL) |
6ddd2a27 TG |
931 | return; |
932 | ||
3344ed30 | 933 | if (boot_cpu_has_bug(X86_BUG_AMD_E400)) { |
c767a54b | 934 | pr_info("using AMD E400 aware idle routine\n"); |
aaa3896b | 935 | static_call_update(x86_idle, amd_e400_idle); |
b253149b LB |
936 | } else if (prefer_mwait_c1_over_halt(c)) { |
937 | pr_info("using mwait in idle threads\n"); | |
aaa3896b | 938 | static_call_update(x86_idle, mwait_idle); |
bfe6ed0c KS |
939 | } else if (cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) { |
940 | pr_info("using TDX aware idle routine\n"); | |
aaa3896b | 941 | static_call_update(x86_idle, tdx_safe_halt); |
6ddd2a27 | 942 | } else |
aaa3896b | 943 | static_call_update(x86_idle, default_idle); |
7f424a8b PZ |
944 | } |
945 | ||
07c94a38 | 946 | void amd_e400_c1e_apic_setup(void) |
30e1e6d1 | 947 | { |
07c94a38 BP |
948 | if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { |
949 | pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id()); | |
950 | local_irq_disable(); | |
951 | tick_broadcast_force(); | |
952 | local_irq_enable(); | |
953 | } | |
30e1e6d1 RR |
954 | } |
955 | ||
e7ff3a47 TG |
956 | void __init arch_post_acpi_subsys_init(void) |
957 | { | |
958 | u32 lo, hi; | |
959 | ||
960 | if (!boot_cpu_has_bug(X86_BUG_AMD_E400)) | |
961 | return; | |
962 | ||
963 | /* | |
964 | * AMD E400 detection needs to happen after ACPI has been enabled. If | |
965 | * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in | |
966 | * MSR_K8_INT_PENDING_MSG. | |
967 | */ | |
968 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); | |
969 | if (!(lo & K8_INTP_C1E_ACTIVE_MASK)) | |
970 | return; | |
971 | ||
972 | boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E); | |
973 | ||
974 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) | |
975 | mark_tsc_unstable("TSC halt in AMD C1E"); | |
976 | pr_info("System has AMD C1E enabled\n"); | |
977 | } | |
978 | ||
7f424a8b PZ |
979 | static int __init idle_setup(char *str) |
980 | { | |
ab6bc3e3 CG |
981 | if (!str) |
982 | return -EINVAL; | |
983 | ||
7f424a8b | 984 | if (!strcmp(str, "poll")) { |
c767a54b | 985 | pr_info("using polling idle threads\n"); |
d1896049 | 986 | boot_option_idle_override = IDLE_POLL; |
7d1a9417 | 987 | cpu_idle_poll_ctrl(true); |
d1896049 | 988 | } else if (!strcmp(str, "halt")) { |
c1e3b377 ZY |
989 | /* |
990 | * When the boot option of idle=halt is added, halt is | |
991 | * forced to be used for CPU idle. In such case CPU C2/C3 | |
992 | * won't be used again. | |
993 | * To continue to load the CPU idle driver, don't touch | |
994 | * the boot_option_idle_override. | |
995 | */ | |
aaa3896b | 996 | static_call_update(x86_idle, default_idle); |
d1896049 | 997 | boot_option_idle_override = IDLE_HALT; |
da5e09a1 ZY |
998 | } else if (!strcmp(str, "nomwait")) { |
999 | /* | |
1000 | * If the boot option of "idle=nomwait" is added, | |
8bcedb4c WK |
1001 | * it means that mwait will be disabled for CPU C1/C2/C3 |
1002 | * states. | |
da5e09a1 | 1003 | */ |
d1896049 | 1004 | boot_option_idle_override = IDLE_NOMWAIT; |
c1e3b377 | 1005 | } else |
7f424a8b PZ |
1006 | return -1; |
1007 | ||
7f424a8b PZ |
1008 | return 0; |
1009 | } | |
1010 | early_param("idle", idle_setup); | |
1011 | ||
9d62dcdf AW |
1012 | unsigned long arch_align_stack(unsigned long sp) |
1013 | { | |
1014 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
8032bf12 | 1015 | sp -= get_random_u32_below(8192); |
9d62dcdf AW |
1016 | return sp & ~0xf; |
1017 | } | |
1018 | ||
1019 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
1020 | { | |
9c6f0902 | 1021 | return randomize_page(mm->brk, 0x02000000); |
9d62dcdf AW |
1022 | } |
1023 | ||
7ba78053 TG |
1024 | /* |
1025 | * Called from fs/proc with a reference on @p to find the function | |
1026 | * which called into schedule(). This needs to be done carefully | |
1027 | * because the task might wake up and we might look at a stack | |
1028 | * changing under us. | |
1029 | */ | |
42a20f86 | 1030 | unsigned long __get_wchan(struct task_struct *p) |
7ba78053 | 1031 | { |
5d1ceb39 PZ |
1032 | struct unwind_state state; |
1033 | unsigned long addr = 0; | |
7ba78053 | 1034 | |
0dc636b3 PZ |
1035 | if (!try_get_task_stack(p)) |
1036 | return 0; | |
1037 | ||
5d1ceb39 PZ |
1038 | for (unwind_start(&state, p, NULL, NULL); !unwind_done(&state); |
1039 | unwind_next_frame(&state)) { | |
1040 | addr = unwind_get_return_address(&state); | |
1041 | if (!addr) | |
1042 | break; | |
1043 | if (in_sched_functions(addr)) | |
1044 | continue; | |
1045 | break; | |
1046 | } | |
1047 | ||
0dc636b3 PZ |
1048 | put_task_stack(p); |
1049 | ||
5d1ceb39 | 1050 | return addr; |
7ba78053 | 1051 | } |
b0b9b014 | 1052 | |
f5c0b4f3 | 1053 | long do_arch_prctl_common(int option, unsigned long arg2) |
b0b9b014 | 1054 | { |
e9ea1e7f KH |
1055 | switch (option) { |
1056 | case ARCH_GET_CPUID: | |
1057 | return get_cpuid_mode(); | |
1058 | case ARCH_SET_CPUID: | |
f5c0b4f3 | 1059 | return set_cpuid_mode(arg2); |
db8268df CB |
1060 | case ARCH_GET_XCOMP_SUPP: |
1061 | case ARCH_GET_XCOMP_PERM: | |
1062 | case ARCH_REQ_XCOMP_PERM: | |
980fe2fd TG |
1063 | case ARCH_GET_XCOMP_GUEST_PERM: |
1064 | case ARCH_REQ_XCOMP_GUEST_PERM: | |
f5c0b4f3 | 1065 | return fpu_xstate_prctl(option, arg2); |
e9ea1e7f KH |
1066 | } |
1067 | ||
b0b9b014 KH |
1068 | return -EINVAL; |
1069 | } |