Commit | Line | Data |
---|---|---|
c767a54b JP |
1 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
2 | ||
61c4628b SS |
3 | #include <linux/errno.h> |
4 | #include <linux/kernel.h> | |
5 | #include <linux/mm.h> | |
6 | #include <linux/smp.h> | |
389d1fb1 | 7 | #include <linux/prctl.h> |
61c4628b SS |
8 | #include <linux/slab.h> |
9 | #include <linux/sched.h> | |
4c822698 | 10 | #include <linux/sched/idle.h> |
b17b0153 | 11 | #include <linux/sched/debug.h> |
29930025 | 12 | #include <linux/sched/task.h> |
68db0cf1 | 13 | #include <linux/sched/task_stack.h> |
186f4360 PG |
14 | #include <linux/init.h> |
15 | #include <linux/export.h> | |
7f424a8b | 16 | #include <linux/pm.h> |
162a688e | 17 | #include <linux/tick.h> |
9d62dcdf | 18 | #include <linux/random.h> |
7c68af6e | 19 | #include <linux/user-return-notifier.h> |
814e2c84 AI |
20 | #include <linux/dmi.h> |
21 | #include <linux/utsname.h> | |
90e24014 RW |
22 | #include <linux/stackprotector.h> |
23 | #include <linux/tick.h> | |
24 | #include <linux/cpuidle.h> | |
61613521 | 25 | #include <trace/events/power.h> |
24f1e32c | 26 | #include <linux/hw_breakpoint.h> |
93789b32 | 27 | #include <asm/cpu.h> |
d3ec5cae | 28 | #include <asm/apic.h> |
2c1b284e | 29 | #include <asm/syscalls.h> |
7c0f6ba6 | 30 | #include <linux/uaccess.h> |
b253149b | 31 | #include <asm/mwait.h> |
78f7f1e5 | 32 | #include <asm/fpu/internal.h> |
66cb5917 | 33 | #include <asm/debugreg.h> |
90e24014 | 34 | #include <asm/nmi.h> |
375074cc | 35 | #include <asm/tlbflush.h> |
8838eb6c | 36 | #include <asm/mce.h> |
9fda6a06 | 37 | #include <asm/vm86.h> |
7b32aead | 38 | #include <asm/switch_to.h> |
b7ffc44d | 39 | #include <asm/desc.h> |
e9ea1e7f | 40 | #include <asm/prctl.h> |
90e24014 | 41 | |
45046892 TG |
42 | /* |
43 | * per-CPU TSS segments. Threads are completely 'soft' on Linux, | |
44 | * no more per-task TSS's. The TSS size is kept cacheline-aligned | |
45 | * so they are allowed to end up in the .data..cacheline_aligned | |
46 | * section. Since TSS's are completely CPU-local, we want them | |
47 | * on exact cacheline boundaries, to eliminate cacheline ping-pong. | |
48 | */ | |
d0a0de21 AL |
49 | __visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss) = { |
50 | .x86_tss = { | |
d9e05cc5 | 51 | .sp0 = TOP_OF_INIT_STACK, |
d0a0de21 AL |
52 | #ifdef CONFIG_X86_32 |
53 | .ss0 = __KERNEL_DS, | |
54 | .ss1 = __KERNEL_CS, | |
55 | .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, | |
56 | #endif | |
57 | }, | |
58 | #ifdef CONFIG_X86_32 | |
59 | /* | |
60 | * Note that the .io_bitmap member must be extra-big. This is because | |
61 | * the CPU will access an additional byte beyond the end of the IO | |
62 | * permission bitmap. The extra byte must be all 1 bits, and must | |
63 | * be within the limit. | |
64 | */ | |
65 | .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, | |
66 | #endif | |
2a41aa4f AL |
67 | #ifdef CONFIG_X86_32 |
68 | .SYSENTER_stack_canary = STACK_END_MAGIC, | |
69 | #endif | |
d0a0de21 | 70 | }; |
de71ad2c | 71 | EXPORT_PER_CPU_SYMBOL(cpu_tss); |
45046892 | 72 | |
b7ceaec1 AL |
73 | DEFINE_PER_CPU(bool, __tss_limit_invalid); |
74 | EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid); | |
b7ffc44d | 75 | |
55ccf3fe SS |
76 | /* |
77 | * this gets called so that we can store lazy state into memory and copy the | |
78 | * current task into the new thread. | |
79 | */ | |
61c4628b SS |
80 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
81 | { | |
5aaeb5c0 | 82 | memcpy(dst, src, arch_task_struct_size); |
2459ee86 AL |
83 | #ifdef CONFIG_VM86 |
84 | dst->thread.vm86 = NULL; | |
85 | #endif | |
f1853505 | 86 | |
c69e098b | 87 | return fpu__copy(&dst->thread.fpu, &src->thread.fpu); |
61c4628b | 88 | } |
7f424a8b | 89 | |
389d1fb1 JF |
90 | /* |
91 | * Free current thread data structures etc.. | |
92 | */ | |
e6464694 | 93 | void exit_thread(struct task_struct *tsk) |
389d1fb1 | 94 | { |
e6464694 | 95 | struct thread_struct *t = &tsk->thread; |
250981e6 | 96 | unsigned long *bp = t->io_bitmap_ptr; |
ca6787ba | 97 | struct fpu *fpu = &t->fpu; |
389d1fb1 | 98 | |
250981e6 | 99 | if (bp) { |
24933b82 | 100 | struct tss_struct *tss = &per_cpu(cpu_tss, get_cpu()); |
389d1fb1 | 101 | |
389d1fb1 JF |
102 | t->io_bitmap_ptr = NULL; |
103 | clear_thread_flag(TIF_IO_BITMAP); | |
104 | /* | |
105 | * Careful, clear this in the TSS too: | |
106 | */ | |
107 | memset(tss->io_bitmap, 0xff, t->io_bitmap_max); | |
108 | t->io_bitmap_max = 0; | |
109 | put_cpu(); | |
250981e6 | 110 | kfree(bp); |
389d1fb1 | 111 | } |
1dcc8d7b | 112 | |
9fda6a06 BG |
113 | free_vm86(t); |
114 | ||
50338615 | 115 | fpu__drop(fpu); |
389d1fb1 JF |
116 | } |
117 | ||
118 | void flush_thread(void) | |
119 | { | |
120 | struct task_struct *tsk = current; | |
121 | ||
24f1e32c | 122 | flush_ptrace_hw_breakpoint(tsk); |
389d1fb1 | 123 | memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); |
110d7f75 | 124 | |
04c8e01d | 125 | fpu__clear(&tsk->thread.fpu); |
389d1fb1 JF |
126 | } |
127 | ||
389d1fb1 JF |
128 | void disable_TSC(void) |
129 | { | |
130 | preempt_disable(); | |
131 | if (!test_and_set_thread_flag(TIF_NOTSC)) | |
132 | /* | |
133 | * Must flip the CPU state synchronously with | |
134 | * TIF_NOTSC in the current running context. | |
135 | */ | |
5a920155 | 136 | cr4_set_bits(X86_CR4_TSD); |
389d1fb1 JF |
137 | preempt_enable(); |
138 | } | |
139 | ||
389d1fb1 JF |
140 | static void enable_TSC(void) |
141 | { | |
142 | preempt_disable(); | |
143 | if (test_and_clear_thread_flag(TIF_NOTSC)) | |
144 | /* | |
145 | * Must flip the CPU state synchronously with | |
146 | * TIF_NOTSC in the current running context. | |
147 | */ | |
5a920155 | 148 | cr4_clear_bits(X86_CR4_TSD); |
389d1fb1 JF |
149 | preempt_enable(); |
150 | } | |
151 | ||
152 | int get_tsc_mode(unsigned long adr) | |
153 | { | |
154 | unsigned int val; | |
155 | ||
156 | if (test_thread_flag(TIF_NOTSC)) | |
157 | val = PR_TSC_SIGSEGV; | |
158 | else | |
159 | val = PR_TSC_ENABLE; | |
160 | ||
161 | return put_user(val, (unsigned int __user *)adr); | |
162 | } | |
163 | ||
164 | int set_tsc_mode(unsigned int val) | |
165 | { | |
166 | if (val == PR_TSC_SIGSEGV) | |
167 | disable_TSC(); | |
168 | else if (val == PR_TSC_ENABLE) | |
169 | enable_TSC(); | |
170 | else | |
171 | return -EINVAL; | |
172 | ||
173 | return 0; | |
174 | } | |
175 | ||
e9ea1e7f KH |
176 | DEFINE_PER_CPU(u64, msr_misc_features_shadow); |
177 | ||
178 | static void set_cpuid_faulting(bool on) | |
179 | { | |
180 | u64 msrval; | |
181 | ||
182 | msrval = this_cpu_read(msr_misc_features_shadow); | |
183 | msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT; | |
184 | msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT); | |
185 | this_cpu_write(msr_misc_features_shadow, msrval); | |
186 | wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval); | |
187 | } | |
188 | ||
189 | static void disable_cpuid(void) | |
190 | { | |
191 | preempt_disable(); | |
192 | if (!test_and_set_thread_flag(TIF_NOCPUID)) { | |
193 | /* | |
194 | * Must flip the CPU state synchronously with | |
195 | * TIF_NOCPUID in the current running context. | |
196 | */ | |
197 | set_cpuid_faulting(true); | |
198 | } | |
199 | preempt_enable(); | |
200 | } | |
201 | ||
202 | static void enable_cpuid(void) | |
203 | { | |
204 | preempt_disable(); | |
205 | if (test_and_clear_thread_flag(TIF_NOCPUID)) { | |
206 | /* | |
207 | * Must flip the CPU state synchronously with | |
208 | * TIF_NOCPUID in the current running context. | |
209 | */ | |
210 | set_cpuid_faulting(false); | |
211 | } | |
212 | preempt_enable(); | |
213 | } | |
214 | ||
215 | static int get_cpuid_mode(void) | |
216 | { | |
217 | return !test_thread_flag(TIF_NOCPUID); | |
218 | } | |
219 | ||
220 | static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled) | |
221 | { | |
222 | if (!static_cpu_has(X86_FEATURE_CPUID_FAULT)) | |
223 | return -ENODEV; | |
224 | ||
225 | if (cpuid_enabled) | |
226 | enable_cpuid(); | |
227 | else | |
228 | disable_cpuid(); | |
229 | ||
230 | return 0; | |
231 | } | |
232 | ||
233 | /* | |
234 | * Called immediately after a successful exec. | |
235 | */ | |
236 | void arch_setup_new_exec(void) | |
237 | { | |
238 | /* If cpuid was previously disabled for this task, re-enable it. */ | |
239 | if (test_thread_flag(TIF_NOCPUID)) | |
240 | enable_cpuid(); | |
241 | } | |
242 | ||
af8b3cd3 KH |
243 | static inline void switch_to_bitmap(struct tss_struct *tss, |
244 | struct thread_struct *prev, | |
245 | struct thread_struct *next, | |
246 | unsigned long tifp, unsigned long tifn) | |
247 | { | |
248 | if (tifn & _TIF_IO_BITMAP) { | |
249 | /* | |
250 | * Copy the relevant range of the IO bitmap. | |
251 | * Normally this is 128 bytes or less: | |
252 | */ | |
253 | memcpy(tss->io_bitmap, next->io_bitmap_ptr, | |
254 | max(prev->io_bitmap_max, next->io_bitmap_max)); | |
255 | /* | |
256 | * Make sure that the TSS limit is correct for the CPU | |
257 | * to notice the IO bitmap. | |
258 | */ | |
259 | refresh_tss_limit(); | |
260 | } else if (tifp & _TIF_IO_BITMAP) { | |
261 | /* | |
262 | * Clear any possible leftover bits: | |
263 | */ | |
264 | memset(tss->io_bitmap, 0xff, prev->io_bitmap_max); | |
265 | } | |
266 | } | |
267 | ||
389d1fb1 JF |
268 | void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, |
269 | struct tss_struct *tss) | |
270 | { | |
271 | struct thread_struct *prev, *next; | |
af8b3cd3 | 272 | unsigned long tifp, tifn; |
389d1fb1 JF |
273 | |
274 | prev = &prev_p->thread; | |
275 | next = &next_p->thread; | |
276 | ||
af8b3cd3 KH |
277 | tifn = READ_ONCE(task_thread_info(next_p)->flags); |
278 | tifp = READ_ONCE(task_thread_info(prev_p)->flags); | |
279 | switch_to_bitmap(tss, prev, next, tifp, tifn); | |
280 | ||
281 | propagate_user_return_notify(prev_p, next_p); | |
282 | ||
b9894a2f KH |
283 | if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) && |
284 | arch_has_block_step()) { | |
285 | unsigned long debugctl, msk; | |
ea8e61b7 | 286 | |
b9894a2f | 287 | rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); |
ea8e61b7 | 288 | debugctl &= ~DEBUGCTLMSR_BTF; |
b9894a2f KH |
289 | msk = tifn & _TIF_BLOCKSTEP; |
290 | debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT; | |
291 | wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); | |
ea8e61b7 | 292 | } |
389d1fb1 | 293 | |
5a920155 TG |
294 | if ((tifp ^ tifn) & _TIF_NOTSC) |
295 | cr4_toggle_bits(X86_CR4_TSD); | |
e9ea1e7f KH |
296 | |
297 | if ((tifp ^ tifn) & _TIF_NOCPUID) | |
298 | set_cpuid_faulting(!!(tifn & _TIF_NOCPUID)); | |
389d1fb1 JF |
299 | } |
300 | ||
00dba564 TG |
301 | /* |
302 | * Idle related variables and functions | |
303 | */ | |
d1896049 | 304 | unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; |
00dba564 TG |
305 | EXPORT_SYMBOL(boot_option_idle_override); |
306 | ||
a476bda3 | 307 | static void (*x86_idle)(void); |
00dba564 | 308 | |
90e24014 RW |
309 | #ifndef CONFIG_SMP |
310 | static inline void play_dead(void) | |
311 | { | |
312 | BUG(); | |
313 | } | |
314 | #endif | |
315 | ||
7d1a9417 TG |
316 | void arch_cpu_idle_enter(void) |
317 | { | |
6a369583 | 318 | tsc_verify_tsc_adjust(false); |
7d1a9417 | 319 | local_touch_nmi(); |
7d1a9417 | 320 | } |
90e24014 | 321 | |
7d1a9417 TG |
322 | void arch_cpu_idle_dead(void) |
323 | { | |
324 | play_dead(); | |
325 | } | |
90e24014 | 326 | |
7d1a9417 TG |
327 | /* |
328 | * Called from the generic idle code. | |
329 | */ | |
330 | void arch_cpu_idle(void) | |
331 | { | |
16f8b05a | 332 | x86_idle(); |
90e24014 RW |
333 | } |
334 | ||
00dba564 | 335 | /* |
7d1a9417 | 336 | * We use this if we don't have any better idle routine.. |
00dba564 | 337 | */ |
6727ad9e | 338 | void __cpuidle default_idle(void) |
00dba564 | 339 | { |
4d0e42cc | 340 | trace_cpu_idle_rcuidle(1, smp_processor_id()); |
7d1a9417 | 341 | safe_halt(); |
4d0e42cc | 342 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); |
00dba564 | 343 | } |
60b8b1de | 344 | #ifdef CONFIG_APM_MODULE |
00dba564 TG |
345 | EXPORT_SYMBOL(default_idle); |
346 | #endif | |
347 | ||
6a377ddc LB |
348 | #ifdef CONFIG_XEN |
349 | bool xen_set_default_idle(void) | |
e5fd47bf | 350 | { |
a476bda3 | 351 | bool ret = !!x86_idle; |
e5fd47bf | 352 | |
a476bda3 | 353 | x86_idle = default_idle; |
e5fd47bf KRW |
354 | |
355 | return ret; | |
356 | } | |
6a377ddc | 357 | #endif |
bba4ed01 | 358 | |
d3ec5cae IV |
359 | void stop_this_cpu(void *dummy) |
360 | { | |
361 | local_irq_disable(); | |
362 | /* | |
363 | * Remove this CPU: | |
364 | */ | |
4f062896 | 365 | set_cpu_online(smp_processor_id(), false); |
d3ec5cae | 366 | disable_local_APIC(); |
8838eb6c | 367 | mcheck_cpu_clear(this_cpu_ptr(&cpu_info)); |
d3ec5cae | 368 | |
bba4ed01 TL |
369 | for (;;) { |
370 | /* | |
371 | * Use wbinvd followed by hlt to stop the processor. This | |
372 | * provides support for kexec on a processor that supports | |
373 | * SME. With kexec, going from SME inactive to SME active | |
374 | * requires clearing cache entries so that addresses without | |
375 | * the encryption bit set don't corrupt the same physical | |
376 | * address that has the encryption bit set when caches are | |
377 | * flushed. To achieve this a wbinvd is performed followed by | |
378 | * a hlt. Even if the processor is not in the kexec/SME | |
379 | * scenario this only adds a wbinvd to a halting processor. | |
380 | */ | |
381 | asm volatile("wbinvd; hlt" : : : "memory"); | |
382 | } | |
7f424a8b PZ |
383 | } |
384 | ||
aa276e1c | 385 | /* |
07c94a38 BP |
386 | * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power |
387 | * states (local apic timer and TSC stop). | |
aa276e1c | 388 | */ |
02c68a02 | 389 | static void amd_e400_idle(void) |
aa276e1c | 390 | { |
07c94a38 BP |
391 | /* |
392 | * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E | |
393 | * gets set after static_cpu_has() places have been converted via | |
394 | * alternatives. | |
395 | */ | |
396 | if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { | |
397 | default_idle(); | |
398 | return; | |
aa276e1c TG |
399 | } |
400 | ||
07c94a38 | 401 | tick_broadcast_enter(); |
aa276e1c | 402 | |
07c94a38 | 403 | default_idle(); |
0beefa20 | 404 | |
07c94a38 BP |
405 | /* |
406 | * The switch back from broadcast mode needs to be called with | |
407 | * interrupts disabled. | |
408 | */ | |
409 | local_irq_disable(); | |
410 | tick_broadcast_exit(); | |
411 | local_irq_enable(); | |
aa276e1c TG |
412 | } |
413 | ||
b253149b LB |
414 | /* |
415 | * Intel Core2 and older machines prefer MWAIT over HALT for C1. | |
416 | * We can't rely on cpuidle installing MWAIT, because it will not load | |
417 | * on systems that support only C1 -- so the boot default must be MWAIT. | |
418 | * | |
419 | * Some AMD machines are the opposite, they depend on using HALT. | |
420 | * | |
421 | * So for default C1, which is used during boot until cpuidle loads, | |
422 | * use MWAIT-C1 on Intel HW that has it, else use HALT. | |
423 | */ | |
424 | static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c) | |
425 | { | |
426 | if (c->x86_vendor != X86_VENDOR_INTEL) | |
427 | return 0; | |
428 | ||
08e237fa | 429 | if (!cpu_has(c, X86_FEATURE_MWAIT) || static_cpu_has_bug(X86_BUG_MONITOR)) |
b253149b LB |
430 | return 0; |
431 | ||
432 | return 1; | |
433 | } | |
434 | ||
435 | /* | |
0fb0328d HR |
436 | * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT |
437 | * with interrupts enabled and no flags, which is backwards compatible with the | |
438 | * original MWAIT implementation. | |
b253149b | 439 | */ |
6727ad9e | 440 | static __cpuidle void mwait_idle(void) |
b253149b | 441 | { |
f8e617f4 | 442 | if (!current_set_polling_and_test()) { |
e43d0189 | 443 | trace_cpu_idle_rcuidle(1, smp_processor_id()); |
f8e617f4 | 444 | if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) { |
ca59809f | 445 | mb(); /* quirk */ |
b253149b | 446 | clflush((void *)¤t_thread_info()->flags); |
ca59809f | 447 | mb(); /* quirk */ |
f8e617f4 | 448 | } |
b253149b LB |
449 | |
450 | __monitor((void *)¤t_thread_info()->flags, 0, 0); | |
b253149b LB |
451 | if (!need_resched()) |
452 | __sti_mwait(0, 0); | |
453 | else | |
454 | local_irq_enable(); | |
e43d0189 | 455 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); |
f8e617f4 | 456 | } else { |
b253149b | 457 | local_irq_enable(); |
f8e617f4 MG |
458 | } |
459 | __current_clr_polling(); | |
b253149b LB |
460 | } |
461 | ||
148f9bb8 | 462 | void select_idle_routine(const struct cpuinfo_x86 *c) |
7f424a8b | 463 | { |
3e5095d1 | 464 | #ifdef CONFIG_SMP |
7d1a9417 | 465 | if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1) |
c767a54b | 466 | pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n"); |
7f424a8b | 467 | #endif |
7d1a9417 | 468 | if (x86_idle || boot_option_idle_override == IDLE_POLL) |
6ddd2a27 TG |
469 | return; |
470 | ||
3344ed30 | 471 | if (boot_cpu_has_bug(X86_BUG_AMD_E400)) { |
c767a54b | 472 | pr_info("using AMD E400 aware idle routine\n"); |
a476bda3 | 473 | x86_idle = amd_e400_idle; |
b253149b LB |
474 | } else if (prefer_mwait_c1_over_halt(c)) { |
475 | pr_info("using mwait in idle threads\n"); | |
476 | x86_idle = mwait_idle; | |
6ddd2a27 | 477 | } else |
a476bda3 | 478 | x86_idle = default_idle; |
7f424a8b PZ |
479 | } |
480 | ||
07c94a38 | 481 | void amd_e400_c1e_apic_setup(void) |
30e1e6d1 | 482 | { |
07c94a38 BP |
483 | if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { |
484 | pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id()); | |
485 | local_irq_disable(); | |
486 | tick_broadcast_force(); | |
487 | local_irq_enable(); | |
488 | } | |
30e1e6d1 RR |
489 | } |
490 | ||
e7ff3a47 TG |
491 | void __init arch_post_acpi_subsys_init(void) |
492 | { | |
493 | u32 lo, hi; | |
494 | ||
495 | if (!boot_cpu_has_bug(X86_BUG_AMD_E400)) | |
496 | return; | |
497 | ||
498 | /* | |
499 | * AMD E400 detection needs to happen after ACPI has been enabled. If | |
500 | * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in | |
501 | * MSR_K8_INT_PENDING_MSG. | |
502 | */ | |
503 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); | |
504 | if (!(lo & K8_INTP_C1E_ACTIVE_MASK)) | |
505 | return; | |
506 | ||
507 | boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E); | |
508 | ||
509 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) | |
510 | mark_tsc_unstable("TSC halt in AMD C1E"); | |
511 | pr_info("System has AMD C1E enabled\n"); | |
512 | } | |
513 | ||
7f424a8b PZ |
514 | static int __init idle_setup(char *str) |
515 | { | |
ab6bc3e3 CG |
516 | if (!str) |
517 | return -EINVAL; | |
518 | ||
7f424a8b | 519 | if (!strcmp(str, "poll")) { |
c767a54b | 520 | pr_info("using polling idle threads\n"); |
d1896049 | 521 | boot_option_idle_override = IDLE_POLL; |
7d1a9417 | 522 | cpu_idle_poll_ctrl(true); |
d1896049 | 523 | } else if (!strcmp(str, "halt")) { |
c1e3b377 ZY |
524 | /* |
525 | * When the boot option of idle=halt is added, halt is | |
526 | * forced to be used for CPU idle. In such case CPU C2/C3 | |
527 | * won't be used again. | |
528 | * To continue to load the CPU idle driver, don't touch | |
529 | * the boot_option_idle_override. | |
530 | */ | |
a476bda3 | 531 | x86_idle = default_idle; |
d1896049 | 532 | boot_option_idle_override = IDLE_HALT; |
da5e09a1 ZY |
533 | } else if (!strcmp(str, "nomwait")) { |
534 | /* | |
535 | * If the boot option of "idle=nomwait" is added, | |
536 | * it means that mwait will be disabled for CPU C2/C3 | |
537 | * states. In such case it won't touch the variable | |
538 | * of boot_option_idle_override. | |
539 | */ | |
d1896049 | 540 | boot_option_idle_override = IDLE_NOMWAIT; |
c1e3b377 | 541 | } else |
7f424a8b PZ |
542 | return -1; |
543 | ||
7f424a8b PZ |
544 | return 0; |
545 | } | |
546 | early_param("idle", idle_setup); | |
547 | ||
9d62dcdf AW |
548 | unsigned long arch_align_stack(unsigned long sp) |
549 | { | |
550 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
551 | sp -= get_random_int() % 8192; | |
552 | return sp & ~0xf; | |
553 | } | |
554 | ||
555 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
556 | { | |
9c6f0902 | 557 | return randomize_page(mm->brk, 0x02000000); |
9d62dcdf AW |
558 | } |
559 | ||
7ba78053 TG |
560 | /* |
561 | * Called from fs/proc with a reference on @p to find the function | |
562 | * which called into schedule(). This needs to be done carefully | |
563 | * because the task might wake up and we might look at a stack | |
564 | * changing under us. | |
565 | */ | |
566 | unsigned long get_wchan(struct task_struct *p) | |
567 | { | |
74327a3e | 568 | unsigned long start, bottom, top, sp, fp, ip, ret = 0; |
7ba78053 TG |
569 | int count = 0; |
570 | ||
571 | if (!p || p == current || p->state == TASK_RUNNING) | |
572 | return 0; | |
573 | ||
74327a3e AL |
574 | if (!try_get_task_stack(p)) |
575 | return 0; | |
576 | ||
7ba78053 TG |
577 | start = (unsigned long)task_stack_page(p); |
578 | if (!start) | |
74327a3e | 579 | goto out; |
7ba78053 TG |
580 | |
581 | /* | |
582 | * Layout of the stack page: | |
583 | * | |
584 | * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long) | |
585 | * PADDING | |
586 | * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING | |
587 | * stack | |
15f4eae7 | 588 | * ----------- bottom = start |
7ba78053 TG |
589 | * |
590 | * The tasks stack pointer points at the location where the | |
591 | * framepointer is stored. The data on the stack is: | |
592 | * ... IP FP ... IP FP | |
593 | * | |
594 | * We need to read FP and IP, so we need to adjust the upper | |
595 | * bound by another unsigned long. | |
596 | */ | |
597 | top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; | |
598 | top -= 2 * sizeof(unsigned long); | |
15f4eae7 | 599 | bottom = start; |
7ba78053 TG |
600 | |
601 | sp = READ_ONCE(p->thread.sp); | |
602 | if (sp < bottom || sp > top) | |
74327a3e | 603 | goto out; |
7ba78053 | 604 | |
7b32aead | 605 | fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp); |
7ba78053 TG |
606 | do { |
607 | if (fp < bottom || fp > top) | |
74327a3e | 608 | goto out; |
f7d27c35 | 609 | ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long))); |
74327a3e AL |
610 | if (!in_sched_functions(ip)) { |
611 | ret = ip; | |
612 | goto out; | |
613 | } | |
f7d27c35 | 614 | fp = READ_ONCE_NOCHECK(*(unsigned long *)fp); |
7ba78053 | 615 | } while (count++ < 16 && p->state != TASK_RUNNING); |
74327a3e AL |
616 | |
617 | out: | |
618 | put_task_stack(p); | |
619 | return ret; | |
7ba78053 | 620 | } |
b0b9b014 KH |
621 | |
622 | long do_arch_prctl_common(struct task_struct *task, int option, | |
623 | unsigned long cpuid_enabled) | |
624 | { | |
e9ea1e7f KH |
625 | switch (option) { |
626 | case ARCH_GET_CPUID: | |
627 | return get_cpuid_mode(); | |
628 | case ARCH_SET_CPUID: | |
629 | return set_cpuid_mode(task, cpuid_enabled); | |
630 | } | |
631 | ||
b0b9b014 KH |
632 | return -EINVAL; |
633 | } |