Commit | Line | Data |
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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
c767a54b JP |
2 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
3 | ||
61c4628b SS |
4 | #include <linux/errno.h> |
5 | #include <linux/kernel.h> | |
6 | #include <linux/mm.h> | |
7 | #include <linux/smp.h> | |
b4c108d7 | 8 | #include <linux/cpu.h> |
389d1fb1 | 9 | #include <linux/prctl.h> |
61c4628b SS |
10 | #include <linux/slab.h> |
11 | #include <linux/sched.h> | |
4c822698 | 12 | #include <linux/sched/idle.h> |
b17b0153 | 13 | #include <linux/sched/debug.h> |
29930025 | 14 | #include <linux/sched/task.h> |
68db0cf1 | 15 | #include <linux/sched/task_stack.h> |
186f4360 PG |
16 | #include <linux/init.h> |
17 | #include <linux/export.h> | |
7f424a8b | 18 | #include <linux/pm.h> |
162a688e | 19 | #include <linux/tick.h> |
9d62dcdf | 20 | #include <linux/random.h> |
7c68af6e | 21 | #include <linux/user-return-notifier.h> |
814e2c84 AI |
22 | #include <linux/dmi.h> |
23 | #include <linux/utsname.h> | |
90e24014 | 24 | #include <linux/stackprotector.h> |
90e24014 | 25 | #include <linux/cpuidle.h> |
89f579ce YW |
26 | #include <linux/acpi.h> |
27 | #include <linux/elf-randomize.h> | |
aaa3896b | 28 | #include <linux/static_call.h> |
61613521 | 29 | #include <trace/events/power.h> |
24f1e32c | 30 | #include <linux/hw_breakpoint.h> |
93789b32 | 31 | #include <asm/cpu.h> |
d3ec5cae | 32 | #include <asm/apic.h> |
7c0f6ba6 | 33 | #include <linux/uaccess.h> |
b253149b | 34 | #include <asm/mwait.h> |
db8268df | 35 | #include <asm/fpu/api.h> |
63e81807 | 36 | #include <asm/fpu/sched.h> |
500afbf6 | 37 | #include <asm/fpu/xstate.h> |
66cb5917 | 38 | #include <asm/debugreg.h> |
90e24014 | 39 | #include <asm/nmi.h> |
375074cc | 40 | #include <asm/tlbflush.h> |
8838eb6c | 41 | #include <asm/mce.h> |
9fda6a06 | 42 | #include <asm/vm86.h> |
7b32aead | 43 | #include <asm/switch_to.h> |
b7ffc44d | 44 | #include <asm/desc.h> |
e9ea1e7f | 45 | #include <asm/prctl.h> |
885f82bf | 46 | #include <asm/spec-ctrl.h> |
577d5cd7 | 47 | #include <asm/io_bitmap.h> |
89f579ce | 48 | #include <asm/proto.h> |
6f9885a3 | 49 | #include <asm/frame.h> |
5d1ceb39 | 50 | #include <asm/unwind.h> |
bfe6ed0c | 51 | #include <asm/tdx.h> |
74c228d2 | 52 | #include <asm/mmu_context.h> |
90e24014 | 53 | |
ff16701a TG |
54 | #include "process.h" |
55 | ||
45046892 TG |
56 | /* |
57 | * per-CPU TSS segments. Threads are completely 'soft' on Linux, | |
58 | * no more per-task TSS's. The TSS size is kept cacheline-aligned | |
59 | * so they are allowed to end up in the .data..cacheline_aligned | |
60 | * section. Since TSS's are completely CPU-local, we want them | |
61 | * on exact cacheline boundaries, to eliminate cacheline ping-pong. | |
62 | */ | |
2fd9c41a | 63 | __visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = { |
d0a0de21 | 64 | .x86_tss = { |
20bb8344 AL |
65 | /* |
66 | * .sp0 is only used when entering ring 0 from a lower | |
67 | * privilege level. Since the init task never runs anything | |
68 | * but ring 0 code, there is no need for a valid value here. | |
69 | * Poison it. | |
70 | */ | |
71 | .sp0 = (1UL << (BITS_PER_LONG-1)) + 1, | |
9aaefe7b | 72 | |
1591584e | 73 | #ifdef CONFIG_X86_32 |
9aaefe7b | 74 | .sp1 = TOP_OF_INIT_STACK, |
9aaefe7b | 75 | |
d0a0de21 AL |
76 | .ss0 = __KERNEL_DS, |
77 | .ss1 = __KERNEL_CS, | |
d0a0de21 | 78 | #endif |
ecc7e37d | 79 | .io_bitmap_base = IO_BITMAP_OFFSET_INVALID, |
d0a0de21 | 80 | }, |
d0a0de21 | 81 | }; |
c482feef | 82 | EXPORT_PER_CPU_SYMBOL(cpu_tss_rw); |
45046892 | 83 | |
b7ceaec1 AL |
84 | DEFINE_PER_CPU(bool, __tss_limit_invalid); |
85 | EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid); | |
b7ffc44d | 86 | |
55ccf3fe SS |
87 | /* |
88 | * this gets called so that we can store lazy state into memory and copy the | |
89 | * current task into the new thread. | |
90 | */ | |
61c4628b SS |
91 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
92 | { | |
5aaeb5c0 | 93 | memcpy(dst, src, arch_task_struct_size); |
2459ee86 AL |
94 | #ifdef CONFIG_VM86 |
95 | dst->thread.vm86 = NULL; | |
96 | #endif | |
f0cbc8b3 TG |
97 | /* Drop the copied pointer to current's fpstate */ |
98 | dst->thread.fpu.fpstate = NULL; | |
500afbf6 | 99 | |
2d16a187 | 100 | return 0; |
61c4628b | 101 | } |
7f424a8b | 102 | |
500afbf6 CB |
103 | #ifdef CONFIG_X86_64 |
104 | void arch_release_task_struct(struct task_struct *tsk) | |
105 | { | |
106 | if (fpu_state_size_dynamic()) | |
107 | fpstate_free(&tsk->thread.fpu); | |
61c4628b | 108 | } |
500afbf6 | 109 | #endif |
7f424a8b | 110 | |
389d1fb1 | 111 | /* |
4bfe6cce | 112 | * Free thread data structures etc.. |
389d1fb1 | 113 | */ |
e6464694 | 114 | void exit_thread(struct task_struct *tsk) |
389d1fb1 | 115 | { |
e6464694 | 116 | struct thread_struct *t = &tsk->thread; |
ca6787ba | 117 | struct fpu *fpu = &t->fpu; |
ea5f1cd7 TG |
118 | |
119 | if (test_thread_flag(TIF_IO_BITMAP)) | |
4bfe6cce | 120 | io_bitmap_exit(tsk); |
1dcc8d7b | 121 | |
9fda6a06 BG |
122 | free_vm86(t); |
123 | ||
50338615 | 124 | fpu__drop(fpu); |
389d1fb1 JF |
125 | } |
126 | ||
2fff071d TG |
127 | static int set_new_tls(struct task_struct *p, unsigned long tls) |
128 | { | |
129 | struct user_desc __user *utls = (struct user_desc __user *)tls; | |
130 | ||
131 | if (in_ia32_syscall()) | |
132 | return do_set_thread_area(p, -1, utls, 0); | |
133 | else | |
134 | return do_set_thread_area_64(p, ARCH_SET_FS, tls); | |
135 | } | |
136 | ||
c5febea0 | 137 | int copy_thread(struct task_struct *p, const struct kernel_clone_args *args) |
2fff071d | 138 | { |
c5febea0 EB |
139 | unsigned long clone_flags = args->flags; |
140 | unsigned long sp = args->stack; | |
c5febea0 | 141 | unsigned long tls = args->tls; |
2fff071d TG |
142 | struct inactive_task_frame *frame; |
143 | struct fork_frame *fork_frame; | |
144 | struct pt_regs *childregs; | |
4804e382 | 145 | int ret = 0; |
2fff071d TG |
146 | |
147 | childregs = task_pt_regs(p); | |
148 | fork_frame = container_of(childregs, struct fork_frame, regs); | |
149 | frame = &fork_frame->frame; | |
150 | ||
6f9885a3 | 151 | frame->bp = encode_frame_pointer(childregs); |
2fff071d TG |
152 | frame->ret_addr = (unsigned long) ret_from_fork; |
153 | p->thread.sp = (unsigned long) fork_frame; | |
577d5cd7 | 154 | p->thread.io_bitmap = NULL; |
b968e84b | 155 | p->thread.iopl_warn = 0; |
2fff071d TG |
156 | memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps)); |
157 | ||
158 | #ifdef CONFIG_X86_64 | |
005f141e CB |
159 | current_save_fsgs(); |
160 | p->thread.fsindex = current->thread.fsindex; | |
161 | p->thread.fsbase = current->thread.fsbase; | |
162 | p->thread.gsindex = current->thread.gsindex; | |
163 | p->thread.gsbase = current->thread.gsbase; | |
164 | ||
2fff071d TG |
165 | savesegment(es, p->thread.es); |
166 | savesegment(ds, p->thread.ds); | |
2f8794bd KS |
167 | |
168 | if (p->mm && (clone_flags & (CLONE_VM | CLONE_VFORK)) == CLONE_VM) | |
169 | set_bit(MM_CONTEXT_LOCK_LAM, &p->mm->context.flags); | |
2fff071d TG |
170 | #else |
171 | p->thread.sp0 = (unsigned long) (childregs + 1); | |
3a24a608 | 172 | savesegment(gs, p->thread.gs); |
2fff071d TG |
173 | /* |
174 | * Clear all status flags including IF and set fixed bit. 64bit | |
175 | * does not have this initialization as the frame does not contain | |
176 | * flags. The flags consistency (especially vs. AC) is there | |
177 | * ensured via objtool, which lacks 32bit support. | |
178 | */ | |
179 | frame->flags = X86_EFLAGS_FIXED; | |
180 | #endif | |
181 | ||
5bd2e97c | 182 | fpu_clone(p, clone_flags, args->fn); |
2d16a187 | 183 | |
2fff071d | 184 | /* Kernel thread ? */ |
50b7b6f2 | 185 | if (unlikely(p->flags & PF_KTHREAD)) { |
9782a712 | 186 | p->thread.pkru = pkru_get_init_value(); |
2fff071d | 187 | memset(childregs, 0, sizeof(struct pt_regs)); |
5bd2e97c | 188 | kthread_frame_init(frame, args->fn, args->fn_arg); |
2fff071d TG |
189 | return 0; |
190 | } | |
191 | ||
9782a712 DH |
192 | /* |
193 | * Clone current's PKRU value from hardware. tsk->thread.pkru | |
194 | * is only valid when scheduled out. | |
195 | */ | |
196 | p->thread.pkru = read_pkru(); | |
197 | ||
2fff071d TG |
198 | frame->bx = 0; |
199 | *childregs = *current_pt_regs(); | |
200 | childregs->ax = 0; | |
201 | if (sp) | |
202 | childregs->sp = sp; | |
203 | ||
5bd2e97c | 204 | if (unlikely(args->fn)) { |
50b7b6f2 | 205 | /* |
5bd2e97c EB |
206 | * A user space thread, but it doesn't return to |
207 | * ret_after_fork(). | |
50b7b6f2 SM |
208 | * |
209 | * In order to indicate that to tools like gdb, | |
210 | * we reset the stack and instruction pointers. | |
211 | * | |
212 | * It does the same kernel frame setup to return to a kernel | |
213 | * function that a kernel thread does. | |
214 | */ | |
215 | childregs->sp = 0; | |
216 | childregs->ip = 0; | |
5bd2e97c | 217 | kthread_frame_init(frame, args->fn, args->fn_arg); |
50b7b6f2 SM |
218 | return 0; |
219 | } | |
220 | ||
2fff071d | 221 | /* Set a new TLS for the child thread? */ |
4804e382 | 222 | if (clone_flags & CLONE_SETTLS) |
2fff071d | 223 | ret = set_new_tls(p, tls); |
4804e382 TG |
224 | |
225 | if (!ret && unlikely(test_tsk_thread_flag(current, TIF_IO_BITMAP))) | |
226 | io_bitmap_share(p); | |
227 | ||
2fff071d TG |
228 | return ret; |
229 | } | |
230 | ||
33344368 AL |
231 | static void pkru_flush_thread(void) |
232 | { | |
233 | /* | |
234 | * If PKRU is enabled the default PKRU value has to be loaded into | |
235 | * the hardware right here (similar to context switch). | |
236 | */ | |
237 | pkru_write_default(); | |
238 | } | |
239 | ||
389d1fb1 JF |
240 | void flush_thread(void) |
241 | { | |
242 | struct task_struct *tsk = current; | |
243 | ||
24f1e32c | 244 | flush_ptrace_hw_breakpoint(tsk); |
389d1fb1 | 245 | memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); |
110d7f75 | 246 | |
e7ecad17 | 247 | fpu_flush_thread(); |
33344368 | 248 | pkru_flush_thread(); |
389d1fb1 JF |
249 | } |
250 | ||
389d1fb1 JF |
251 | void disable_TSC(void) |
252 | { | |
253 | preempt_disable(); | |
254 | if (!test_and_set_thread_flag(TIF_NOTSC)) | |
255 | /* | |
256 | * Must flip the CPU state synchronously with | |
257 | * TIF_NOTSC in the current running context. | |
258 | */ | |
5a920155 | 259 | cr4_set_bits(X86_CR4_TSD); |
389d1fb1 JF |
260 | preempt_enable(); |
261 | } | |
262 | ||
389d1fb1 JF |
263 | static void enable_TSC(void) |
264 | { | |
265 | preempt_disable(); | |
266 | if (test_and_clear_thread_flag(TIF_NOTSC)) | |
267 | /* | |
268 | * Must flip the CPU state synchronously with | |
269 | * TIF_NOTSC in the current running context. | |
270 | */ | |
5a920155 | 271 | cr4_clear_bits(X86_CR4_TSD); |
389d1fb1 JF |
272 | preempt_enable(); |
273 | } | |
274 | ||
275 | int get_tsc_mode(unsigned long adr) | |
276 | { | |
277 | unsigned int val; | |
278 | ||
279 | if (test_thread_flag(TIF_NOTSC)) | |
280 | val = PR_TSC_SIGSEGV; | |
281 | else | |
282 | val = PR_TSC_ENABLE; | |
283 | ||
284 | return put_user(val, (unsigned int __user *)adr); | |
285 | } | |
286 | ||
287 | int set_tsc_mode(unsigned int val) | |
288 | { | |
289 | if (val == PR_TSC_SIGSEGV) | |
290 | disable_TSC(); | |
291 | else if (val == PR_TSC_ENABLE) | |
292 | enable_TSC(); | |
293 | else | |
294 | return -EINVAL; | |
295 | ||
296 | return 0; | |
297 | } | |
298 | ||
e9ea1e7f KH |
299 | DEFINE_PER_CPU(u64, msr_misc_features_shadow); |
300 | ||
301 | static void set_cpuid_faulting(bool on) | |
302 | { | |
303 | u64 msrval; | |
304 | ||
305 | msrval = this_cpu_read(msr_misc_features_shadow); | |
306 | msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT; | |
307 | msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT); | |
308 | this_cpu_write(msr_misc_features_shadow, msrval); | |
309 | wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval); | |
310 | } | |
311 | ||
312 | static void disable_cpuid(void) | |
313 | { | |
314 | preempt_disable(); | |
315 | if (!test_and_set_thread_flag(TIF_NOCPUID)) { | |
316 | /* | |
317 | * Must flip the CPU state synchronously with | |
318 | * TIF_NOCPUID in the current running context. | |
319 | */ | |
320 | set_cpuid_faulting(true); | |
321 | } | |
322 | preempt_enable(); | |
323 | } | |
324 | ||
325 | static void enable_cpuid(void) | |
326 | { | |
327 | preempt_disable(); | |
328 | if (test_and_clear_thread_flag(TIF_NOCPUID)) { | |
329 | /* | |
330 | * Must flip the CPU state synchronously with | |
331 | * TIF_NOCPUID in the current running context. | |
332 | */ | |
333 | set_cpuid_faulting(false); | |
334 | } | |
335 | preempt_enable(); | |
336 | } | |
337 | ||
338 | static int get_cpuid_mode(void) | |
339 | { | |
340 | return !test_thread_flag(TIF_NOCPUID); | |
341 | } | |
342 | ||
f5c0b4f3 | 343 | static int set_cpuid_mode(unsigned long cpuid_enabled) |
e9ea1e7f | 344 | { |
67e87d43 | 345 | if (!boot_cpu_has(X86_FEATURE_CPUID_FAULT)) |
e9ea1e7f KH |
346 | return -ENODEV; |
347 | ||
348 | if (cpuid_enabled) | |
349 | enable_cpuid(); | |
350 | else | |
351 | disable_cpuid(); | |
352 | ||
353 | return 0; | |
354 | } | |
355 | ||
356 | /* | |
357 | * Called immediately after a successful exec. | |
358 | */ | |
359 | void arch_setup_new_exec(void) | |
360 | { | |
361 | /* If cpuid was previously disabled for this task, re-enable it. */ | |
362 | if (test_thread_flag(TIF_NOCPUID)) | |
363 | enable_cpuid(); | |
71368af9 WL |
364 | |
365 | /* | |
366 | * Don't inherit TIF_SSBD across exec boundary when | |
367 | * PR_SPEC_DISABLE_NOEXEC is used. | |
368 | */ | |
369 | if (test_thread_flag(TIF_SSBD) && | |
370 | task_spec_ssb_noexec(current)) { | |
371 | clear_thread_flag(TIF_SSBD); | |
372 | task_clear_spec_ssb_disable(current); | |
373 | task_clear_spec_ssb_noexec(current); | |
dca99fb6 | 374 | speculation_ctrl_update(read_thread_flags()); |
71368af9 | 375 | } |
74c228d2 KS |
376 | |
377 | mm_reset_untag_mask(current->mm); | |
e9ea1e7f KH |
378 | } |
379 | ||
111e7b15 | 380 | #ifdef CONFIG_X86_IOPL_IOPERM |
22fe5b04 TG |
381 | static inline void switch_to_bitmap(unsigned long tifp) |
382 | { | |
383 | /* | |
384 | * Invalidate I/O bitmap if the previous task used it. This prevents | |
385 | * any possible leakage of an active I/O bitmap. | |
386 | * | |
387 | * If the next task has an I/O bitmap it will handle it on exit to | |
388 | * user mode. | |
389 | */ | |
390 | if (tifp & _TIF_IO_BITMAP) | |
cadfad87 | 391 | tss_invalidate_io_bitmap(); |
22fe5b04 TG |
392 | } |
393 | ||
394 | static void tss_copy_io_bitmap(struct tss_struct *tss, struct io_bitmap *iobm) | |
060aa16f TG |
395 | { |
396 | /* | |
397 | * Copy at least the byte range of the incoming tasks bitmap which | |
398 | * covers the permitted I/O ports. | |
399 | * | |
400 | * If the previous task which used an I/O bitmap had more bits | |
401 | * permitted, then the copy needs to cover those as well so they | |
402 | * get turned off. | |
403 | */ | |
404 | memcpy(tss->io_bitmap.bitmap, iobm->bitmap, | |
405 | max(tss->io_bitmap.prev_max, iobm->max)); | |
406 | ||
407 | /* | |
408 | * Store the new max and the sequence number of this bitmap | |
409 | * and a pointer to the bitmap itself. | |
410 | */ | |
411 | tss->io_bitmap.prev_max = iobm->max; | |
412 | tss->io_bitmap.prev_sequence = iobm->sequence; | |
413 | } | |
414 | ||
22fe5b04 | 415 | /** |
dbb5ab6d | 416 | * native_tss_update_io_bitmap - Update I/O bitmap before exiting to user mode |
22fe5b04 | 417 | */ |
99bcd4a6 | 418 | void native_tss_update_io_bitmap(void) |
af8b3cd3 | 419 | { |
ff16701a | 420 | struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); |
7b0b8cfd | 421 | struct thread_struct *t = ¤t->thread; |
c8137ace | 422 | u16 *base = &tss->x86_tss.io_bitmap_base; |
ff16701a | 423 | |
7b0b8cfd | 424 | if (!test_thread_flag(TIF_IO_BITMAP)) { |
cadfad87 | 425 | native_tss_invalidate_io_bitmap(); |
7b0b8cfd BP |
426 | return; |
427 | } | |
428 | ||
429 | if (IS_ENABLED(CONFIG_X86_IOPL_IOPERM) && t->iopl_emul == 3) { | |
430 | *base = IO_BITMAP_OFFSET_VALID_ALL; | |
431 | } else { | |
432 | struct io_bitmap *iobm = t->io_bitmap; | |
433 | ||
af8b3cd3 | 434 | /* |
7b0b8cfd BP |
435 | * Only copy bitmap data when the sequence number differs. The |
436 | * update time is accounted to the incoming task. | |
af8b3cd3 | 437 | */ |
7b0b8cfd BP |
438 | if (tss->io_bitmap.prev_sequence != iobm->sequence) |
439 | tss_copy_io_bitmap(tss, iobm); | |
440 | ||
441 | /* Enable the bitmap */ | |
442 | *base = IO_BITMAP_OFFSET_VALID_MAP; | |
af8b3cd3 | 443 | } |
7b0b8cfd BP |
444 | |
445 | /* | |
446 | * Make sure that the TSS limit is covering the IO bitmap. It might have | |
447 | * been cut down by a VMEXIT to 0x67 which would cause a subsequent I/O | |
448 | * access from user space to trigger a #GP because tbe bitmap is outside | |
449 | * the TSS limit. | |
450 | */ | |
451 | refresh_tss_limit(); | |
af8b3cd3 | 452 | } |
111e7b15 TG |
453 | #else /* CONFIG_X86_IOPL_IOPERM */ |
454 | static inline void switch_to_bitmap(unsigned long tifp) { } | |
455 | #endif | |
af8b3cd3 | 456 | |
1f50ddb4 TG |
457 | #ifdef CONFIG_SMP |
458 | ||
459 | struct ssb_state { | |
460 | struct ssb_state *shared_state; | |
461 | raw_spinlock_t lock; | |
462 | unsigned int disable_state; | |
463 | unsigned long local_state; | |
464 | }; | |
465 | ||
466 | #define LSTATE_SSB 0 | |
467 | ||
468 | static DEFINE_PER_CPU(struct ssb_state, ssb_state); | |
469 | ||
470 | void speculative_store_bypass_ht_init(void) | |
885f82bf | 471 | { |
1f50ddb4 TG |
472 | struct ssb_state *st = this_cpu_ptr(&ssb_state); |
473 | unsigned int this_cpu = smp_processor_id(); | |
474 | unsigned int cpu; | |
475 | ||
476 | st->local_state = 0; | |
477 | ||
478 | /* | |
479 | * Shared state setup happens once on the first bringup | |
480 | * of the CPU. It's not destroyed on CPU hotunplug. | |
481 | */ | |
482 | if (st->shared_state) | |
483 | return; | |
484 | ||
485 | raw_spin_lock_init(&st->lock); | |
486 | ||
487 | /* | |
488 | * Go over HT siblings and check whether one of them has set up the | |
489 | * shared state pointer already. | |
490 | */ | |
491 | for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) { | |
492 | if (cpu == this_cpu) | |
493 | continue; | |
494 | ||
495 | if (!per_cpu(ssb_state, cpu).shared_state) | |
496 | continue; | |
497 | ||
498 | /* Link it to the state of the sibling: */ | |
499 | st->shared_state = per_cpu(ssb_state, cpu).shared_state; | |
500 | return; | |
501 | } | |
502 | ||
503 | /* | |
504 | * First HT sibling to come up on the core. Link shared state of | |
505 | * the first HT sibling to itself. The siblings on the same core | |
506 | * which come up later will see the shared state pointer and link | |
d9f6e12f | 507 | * themselves to the state of this CPU. |
1f50ddb4 TG |
508 | */ |
509 | st->shared_state = st; | |
510 | } | |
885f82bf | 511 | |
1f50ddb4 TG |
512 | /* |
513 | * Logic is: First HT sibling enables SSBD for both siblings in the core | |
514 | * and last sibling to disable it, disables it for the whole core. This how | |
515 | * MSR_SPEC_CTRL works in "hardware": | |
516 | * | |
517 | * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL | |
518 | */ | |
519 | static __always_inline void amd_set_core_ssb_state(unsigned long tifn) | |
520 | { | |
521 | struct ssb_state *st = this_cpu_ptr(&ssb_state); | |
522 | u64 msr = x86_amd_ls_cfg_base; | |
523 | ||
524 | if (!static_cpu_has(X86_FEATURE_ZEN)) { | |
525 | msr |= ssbd_tif_to_amd_ls_cfg(tifn); | |
885f82bf | 526 | wrmsrl(MSR_AMD64_LS_CFG, msr); |
1f50ddb4 TG |
527 | return; |
528 | } | |
529 | ||
530 | if (tifn & _TIF_SSBD) { | |
531 | /* | |
532 | * Since this can race with prctl(), block reentry on the | |
533 | * same CPU. | |
534 | */ | |
535 | if (__test_and_set_bit(LSTATE_SSB, &st->local_state)) | |
536 | return; | |
537 | ||
538 | msr |= x86_amd_ls_cfg_ssbd_mask; | |
539 | ||
540 | raw_spin_lock(&st->shared_state->lock); | |
541 | /* First sibling enables SSBD: */ | |
542 | if (!st->shared_state->disable_state) | |
543 | wrmsrl(MSR_AMD64_LS_CFG, msr); | |
544 | st->shared_state->disable_state++; | |
545 | raw_spin_unlock(&st->shared_state->lock); | |
885f82bf | 546 | } else { |
1f50ddb4 TG |
547 | if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state)) |
548 | return; | |
549 | ||
550 | raw_spin_lock(&st->shared_state->lock); | |
551 | st->shared_state->disable_state--; | |
552 | if (!st->shared_state->disable_state) | |
553 | wrmsrl(MSR_AMD64_LS_CFG, msr); | |
554 | raw_spin_unlock(&st->shared_state->lock); | |
885f82bf TG |
555 | } |
556 | } | |
1f50ddb4 TG |
557 | #else |
558 | static __always_inline void amd_set_core_ssb_state(unsigned long tifn) | |
559 | { | |
560 | u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn); | |
561 | ||
562 | wrmsrl(MSR_AMD64_LS_CFG, msr); | |
563 | } | |
564 | #endif | |
565 | ||
11fb0683 TL |
566 | static __always_inline void amd_set_ssb_virt_state(unsigned long tifn) |
567 | { | |
568 | /* | |
569 | * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL, | |
570 | * so ssbd_tif_to_spec_ctrl() just works. | |
571 | */ | |
572 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn)); | |
573 | } | |
574 | ||
01daf568 TC |
575 | /* |
576 | * Update the MSRs managing speculation control, during context switch. | |
577 | * | |
578 | * tifp: Previous task's thread flags | |
579 | * tifn: Next task's thread flags | |
580 | */ | |
581 | static __always_inline void __speculation_ctrl_update(unsigned long tifp, | |
582 | unsigned long tifn) | |
1f50ddb4 | 583 | { |
5bfbe3ad | 584 | unsigned long tif_diff = tifp ^ tifn; |
01daf568 TC |
585 | u64 msr = x86_spec_ctrl_base; |
586 | bool updmsr = false; | |
587 | ||
2f5fb193 TG |
588 | lockdep_assert_irqs_disabled(); |
589 | ||
dbbe2ad0 AS |
590 | /* Handle change of TIF_SSBD depending on the mitigation method. */ |
591 | if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) { | |
592 | if (tif_diff & _TIF_SSBD) | |
01daf568 | 593 | amd_set_ssb_virt_state(tifn); |
dbbe2ad0 AS |
594 | } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) { |
595 | if (tif_diff & _TIF_SSBD) | |
01daf568 | 596 | amd_set_core_ssb_state(tifn); |
dbbe2ad0 AS |
597 | } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || |
598 | static_cpu_has(X86_FEATURE_AMD_SSBD)) { | |
599 | updmsr |= !!(tif_diff & _TIF_SSBD); | |
600 | msr |= ssbd_tif_to_spec_ctrl(tifn); | |
01daf568 | 601 | } |
1f50ddb4 | 602 | |
dbbe2ad0 | 603 | /* Only evaluate TIF_SPEC_IB if conditional STIBP is enabled. */ |
5bfbe3ad TC |
604 | if (IS_ENABLED(CONFIG_SMP) && |
605 | static_branch_unlikely(&switch_to_cond_stibp)) { | |
606 | updmsr |= !!(tif_diff & _TIF_SPEC_IB); | |
607 | msr |= stibp_tif_to_spec_ctrl(tifn); | |
608 | } | |
609 | ||
01daf568 | 610 | if (updmsr) |
66065157 | 611 | update_spec_ctrl_cond(msr); |
1f50ddb4 TG |
612 | } |
613 | ||
6d991ba5 | 614 | static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk) |
1f50ddb4 | 615 | { |
6d991ba5 TG |
616 | if (test_and_clear_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE)) { |
617 | if (task_spec_ssb_disable(tsk)) | |
618 | set_tsk_thread_flag(tsk, TIF_SSBD); | |
619 | else | |
620 | clear_tsk_thread_flag(tsk, TIF_SSBD); | |
9137bb27 TG |
621 | |
622 | if (task_spec_ib_disable(tsk)) | |
623 | set_tsk_thread_flag(tsk, TIF_SPEC_IB); | |
624 | else | |
625 | clear_tsk_thread_flag(tsk, TIF_SPEC_IB); | |
6d991ba5 TG |
626 | } |
627 | /* Return the updated threadinfo flags*/ | |
dca99fb6 | 628 | return read_task_thread_flags(tsk); |
1f50ddb4 | 629 | } |
885f82bf | 630 | |
26c4d75b | 631 | void speculation_ctrl_update(unsigned long tif) |
885f82bf | 632 | { |
2f5fb193 TG |
633 | unsigned long flags; |
634 | ||
01daf568 | 635 | /* Forced update. Make sure all relevant TIF flags are different */ |
2f5fb193 | 636 | local_irq_save(flags); |
01daf568 | 637 | __speculation_ctrl_update(~tif, tif); |
2f5fb193 | 638 | local_irq_restore(flags); |
885f82bf TG |
639 | } |
640 | ||
6d991ba5 TG |
641 | /* Called from seccomp/prctl update */ |
642 | void speculation_ctrl_update_current(void) | |
643 | { | |
644 | preempt_disable(); | |
645 | speculation_ctrl_update(speculation_ctrl_update_tif(current)); | |
646 | preempt_enable(); | |
647 | } | |
648 | ||
d8f0b353 TG |
649 | static inline void cr4_toggle_bits_irqsoff(unsigned long mask) |
650 | { | |
651 | unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4); | |
652 | ||
653 | newval = cr4 ^ mask; | |
654 | if (newval != cr4) { | |
655 | this_cpu_write(cpu_tlbstate.cr4, newval); | |
656 | __write_cr4(newval); | |
657 | } | |
658 | } | |
659 | ||
ff16701a | 660 | void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p) |
389d1fb1 | 661 | { |
af8b3cd3 | 662 | unsigned long tifp, tifn; |
389d1fb1 | 663 | |
dca99fb6 MR |
664 | tifn = read_task_thread_flags(next_p); |
665 | tifp = read_task_thread_flags(prev_p); | |
22fe5b04 TG |
666 | |
667 | switch_to_bitmap(tifp); | |
af8b3cd3 KH |
668 | |
669 | propagate_user_return_notify(prev_p, next_p); | |
670 | ||
b9894a2f KH |
671 | if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) && |
672 | arch_has_block_step()) { | |
673 | unsigned long debugctl, msk; | |
ea8e61b7 | 674 | |
b9894a2f | 675 | rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); |
ea8e61b7 | 676 | debugctl &= ~DEBUGCTLMSR_BTF; |
b9894a2f KH |
677 | msk = tifn & _TIF_BLOCKSTEP; |
678 | debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT; | |
679 | wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); | |
ea8e61b7 | 680 | } |
389d1fb1 | 681 | |
5a920155 | 682 | if ((tifp ^ tifn) & _TIF_NOTSC) |
9d0b6232 | 683 | cr4_toggle_bits_irqsoff(X86_CR4_TSD); |
e9ea1e7f KH |
684 | |
685 | if ((tifp ^ tifn) & _TIF_NOCPUID) | |
686 | set_cpuid_faulting(!!(tifn & _TIF_NOCPUID)); | |
885f82bf | 687 | |
6d991ba5 TG |
688 | if (likely(!((tifp | tifn) & _TIF_SPEC_FORCE_UPDATE))) { |
689 | __speculation_ctrl_update(tifp, tifn); | |
690 | } else { | |
691 | speculation_ctrl_update_tif(prev_p); | |
692 | tifn = speculation_ctrl_update_tif(next_p); | |
693 | ||
694 | /* Enforce MSR update to ensure consistent state */ | |
695 | __speculation_ctrl_update(~tifn, tifn); | |
696 | } | |
389d1fb1 JF |
697 | } |
698 | ||
00dba564 TG |
699 | /* |
700 | * Idle related variables and functions | |
701 | */ | |
d1896049 | 702 | unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; |
00dba564 TG |
703 | EXPORT_SYMBOL(boot_option_idle_override); |
704 | ||
aaa3896b PZ |
705 | /* |
706 | * We use this if we don't have any better idle routine.. | |
707 | */ | |
708 | void __cpuidle default_idle(void) | |
709 | { | |
710 | raw_safe_halt(); | |
89b30987 | 711 | raw_local_irq_disable(); |
aaa3896b PZ |
712 | } |
713 | #if defined(CONFIG_APM_MODULE) || defined(CONFIG_HALTPOLL_CPUIDLE_MODULE) | |
714 | EXPORT_SYMBOL(default_idle); | |
715 | #endif | |
716 | ||
717 | DEFINE_STATIC_CALL_NULL(x86_idle, default_idle); | |
718 | ||
719 | static bool x86_idle_set(void) | |
720 | { | |
721 | return !!static_call_query(x86_idle); | |
722 | } | |
00dba564 | 723 | |
90e24014 | 724 | #ifndef CONFIG_SMP |
eab89405 | 725 | static inline void __noreturn play_dead(void) |
90e24014 RW |
726 | { |
727 | BUG(); | |
728 | } | |
729 | #endif | |
730 | ||
7d1a9417 TG |
731 | void arch_cpu_idle_enter(void) |
732 | { | |
6a369583 | 733 | tsc_verify_tsc_adjust(false); |
7d1a9417 | 734 | local_touch_nmi(); |
7d1a9417 | 735 | } |
90e24014 | 736 | |
071c44e4 | 737 | void __noreturn arch_cpu_idle_dead(void) |
7d1a9417 TG |
738 | { |
739 | play_dead(); | |
740 | } | |
90e24014 | 741 | |
7d1a9417 TG |
742 | /* |
743 | * Called from the generic idle code. | |
744 | */ | |
aaa3896b | 745 | void __cpuidle arch_cpu_idle(void) |
00dba564 | 746 | { |
aaa3896b | 747 | static_call(x86_idle)(); |
00dba564 | 748 | } |
716ff71a | 749 | EXPORT_SYMBOL_GPL(arch_cpu_idle); |
00dba564 | 750 | |
6a377ddc LB |
751 | #ifdef CONFIG_XEN |
752 | bool xen_set_default_idle(void) | |
e5fd47bf | 753 | { |
aaa3896b | 754 | bool ret = x86_idle_set(); |
e5fd47bf | 755 | |
aaa3896b | 756 | static_call_update(x86_idle, default_idle); |
e5fd47bf KRW |
757 | |
758 | return ret; | |
759 | } | |
6a377ddc | 760 | #endif |
bba4ed01 | 761 | |
f9cdf7ca | 762 | void __noreturn stop_this_cpu(void *dummy) |
d3ec5cae IV |
763 | { |
764 | local_irq_disable(); | |
765 | /* | |
766 | * Remove this CPU: | |
767 | */ | |
4f062896 | 768 | set_cpu_online(smp_processor_id(), false); |
d3ec5cae | 769 | disable_local_APIC(); |
8838eb6c | 770 | mcheck_cpu_clear(this_cpu_ptr(&cpu_info)); |
d3ec5cae | 771 | |
f23d74f6 TL |
772 | /* |
773 | * Use wbinvd on processors that support SME. This provides support | |
774 | * for performing a successful kexec when going from SME inactive | |
775 | * to SME active (or vice-versa). The cache must be cleared so that | |
776 | * if there are entries with the same physical address, both with and | |
777 | * without the encryption bit, they don't race each other when flushed | |
778 | * and potentially end up with the wrong entry being committed to | |
779 | * memory. | |
08f253ec ML |
780 | * |
781 | * Test the CPUID bit directly because the machine might've cleared | |
782 | * X86_FEATURE_SME due to cmdline options. | |
f23d74f6 | 783 | */ |
08f253ec | 784 | if (cpuid_eax(0x8000001f) & BIT(0)) |
f23d74f6 | 785 | native_wbinvd(); |
bba4ed01 TL |
786 | for (;;) { |
787 | /* | |
f23d74f6 TL |
788 | * Use native_halt() so that memory contents don't change |
789 | * (stack usage and variables) after possibly issuing the | |
790 | * native_wbinvd() above. | |
bba4ed01 | 791 | */ |
f23d74f6 | 792 | native_halt(); |
bba4ed01 | 793 | } |
7f424a8b PZ |
794 | } |
795 | ||
aa276e1c | 796 | /* |
07c94a38 BP |
797 | * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power |
798 | * states (local apic timer and TSC stop). | |
58c644ba PZ |
799 | * |
800 | * XXX this function is completely buggered vs RCU and tracing. | |
aa276e1c | 801 | */ |
02c68a02 | 802 | static void amd_e400_idle(void) |
aa276e1c | 803 | { |
07c94a38 BP |
804 | /* |
805 | * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E | |
806 | * gets set after static_cpu_has() places have been converted via | |
807 | * alternatives. | |
808 | */ | |
809 | if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { | |
810 | default_idle(); | |
811 | return; | |
aa276e1c TG |
812 | } |
813 | ||
07c94a38 | 814 | tick_broadcast_enter(); |
aa276e1c | 815 | |
07c94a38 | 816 | default_idle(); |
0beefa20 | 817 | |
07c94a38 | 818 | tick_broadcast_exit(); |
aa276e1c TG |
819 | } |
820 | ||
b253149b | 821 | /* |
aebef63c WK |
822 | * Prefer MWAIT over HALT if MWAIT is supported, MWAIT_CPUID leaf |
823 | * exists and whenever MONITOR/MWAIT extensions are present there is at | |
824 | * least one C1 substate. | |
b253149b | 825 | * |
aebef63c WK |
826 | * Do not prefer MWAIT if MONITOR instruction has a bug or idle=nomwait |
827 | * is passed to kernel commandline parameter. | |
b253149b LB |
828 | */ |
829 | static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c) | |
830 | { | |
aebef63c WK |
831 | u32 eax, ebx, ecx, edx; |
832 | ||
8bcedb4c WK |
833 | /* User has disallowed the use of MWAIT. Fallback to HALT */ |
834 | if (boot_option_idle_override == IDLE_NOMWAIT) | |
b253149b LB |
835 | return 0; |
836 | ||
aebef63c WK |
837 | /* MWAIT is not supported on this platform. Fallback to HALT */ |
838 | if (!cpu_has(c, X86_FEATURE_MWAIT)) | |
b253149b LB |
839 | return 0; |
840 | ||
aebef63c WK |
841 | /* Monitor has a bug. Fallback to HALT */ |
842 | if (boot_cpu_has_bug(X86_BUG_MONITOR)) | |
b253149b LB |
843 | return 0; |
844 | ||
aebef63c WK |
845 | cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx); |
846 | ||
847 | /* | |
848 | * If MWAIT extensions are not available, it is safe to use MWAIT | |
849 | * with EAX=0, ECX=0. | |
850 | */ | |
851 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) | |
852 | return 1; | |
853 | ||
854 | /* | |
855 | * If MWAIT extensions are available, there should be at least one | |
856 | * MWAIT C1 substate present. | |
857 | */ | |
858 | return (edx & MWAIT_C1_SUBSTATE_MASK); | |
b253149b LB |
859 | } |
860 | ||
861 | /* | |
0fb0328d HR |
862 | * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT |
863 | * with interrupts enabled and no flags, which is backwards compatible with the | |
864 | * original MWAIT implementation. | |
b253149b | 865 | */ |
6727ad9e | 866 | static __cpuidle void mwait_idle(void) |
b253149b | 867 | { |
f8e617f4 MG |
868 | if (!current_set_polling_and_test()) { |
869 | if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) { | |
ca59809f | 870 | mb(); /* quirk */ |
b253149b | 871 | clflush((void *)¤t_thread_info()->flags); |
ca59809f | 872 | mb(); /* quirk */ |
f8e617f4 | 873 | } |
b253149b LB |
874 | |
875 | __monitor((void *)¤t_thread_info()->flags, 0, 0); | |
89b30987 | 876 | if (!need_resched()) { |
b253149b | 877 | __sti_mwait(0, 0); |
89b30987 PZ |
878 | raw_local_irq_disable(); |
879 | } | |
f8e617f4 MG |
880 | } |
881 | __current_clr_polling(); | |
b253149b LB |
882 | } |
883 | ||
148f9bb8 | 884 | void select_idle_routine(const struct cpuinfo_x86 *c) |
7f424a8b | 885 | { |
3e5095d1 | 886 | #ifdef CONFIG_SMP |
7d1a9417 | 887 | if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1) |
c767a54b | 888 | pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n"); |
7f424a8b | 889 | #endif |
aaa3896b | 890 | if (x86_idle_set() || boot_option_idle_override == IDLE_POLL) |
6ddd2a27 TG |
891 | return; |
892 | ||
3344ed30 | 893 | if (boot_cpu_has_bug(X86_BUG_AMD_E400)) { |
c767a54b | 894 | pr_info("using AMD E400 aware idle routine\n"); |
aaa3896b | 895 | static_call_update(x86_idle, amd_e400_idle); |
b253149b LB |
896 | } else if (prefer_mwait_c1_over_halt(c)) { |
897 | pr_info("using mwait in idle threads\n"); | |
aaa3896b | 898 | static_call_update(x86_idle, mwait_idle); |
bfe6ed0c KS |
899 | } else if (cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) { |
900 | pr_info("using TDX aware idle routine\n"); | |
aaa3896b | 901 | static_call_update(x86_idle, tdx_safe_halt); |
6ddd2a27 | 902 | } else |
aaa3896b | 903 | static_call_update(x86_idle, default_idle); |
7f424a8b PZ |
904 | } |
905 | ||
07c94a38 | 906 | void amd_e400_c1e_apic_setup(void) |
30e1e6d1 | 907 | { |
07c94a38 BP |
908 | if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) { |
909 | pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id()); | |
910 | local_irq_disable(); | |
911 | tick_broadcast_force(); | |
912 | local_irq_enable(); | |
913 | } | |
30e1e6d1 RR |
914 | } |
915 | ||
e7ff3a47 TG |
916 | void __init arch_post_acpi_subsys_init(void) |
917 | { | |
918 | u32 lo, hi; | |
919 | ||
920 | if (!boot_cpu_has_bug(X86_BUG_AMD_E400)) | |
921 | return; | |
922 | ||
923 | /* | |
924 | * AMD E400 detection needs to happen after ACPI has been enabled. If | |
925 | * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in | |
926 | * MSR_K8_INT_PENDING_MSG. | |
927 | */ | |
928 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); | |
929 | if (!(lo & K8_INTP_C1E_ACTIVE_MASK)) | |
930 | return; | |
931 | ||
932 | boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E); | |
933 | ||
934 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) | |
935 | mark_tsc_unstable("TSC halt in AMD C1E"); | |
936 | pr_info("System has AMD C1E enabled\n"); | |
937 | } | |
938 | ||
7f424a8b PZ |
939 | static int __init idle_setup(char *str) |
940 | { | |
ab6bc3e3 CG |
941 | if (!str) |
942 | return -EINVAL; | |
943 | ||
7f424a8b | 944 | if (!strcmp(str, "poll")) { |
c767a54b | 945 | pr_info("using polling idle threads\n"); |
d1896049 | 946 | boot_option_idle_override = IDLE_POLL; |
7d1a9417 | 947 | cpu_idle_poll_ctrl(true); |
d1896049 | 948 | } else if (!strcmp(str, "halt")) { |
c1e3b377 ZY |
949 | /* |
950 | * When the boot option of idle=halt is added, halt is | |
951 | * forced to be used for CPU idle. In such case CPU C2/C3 | |
952 | * won't be used again. | |
953 | * To continue to load the CPU idle driver, don't touch | |
954 | * the boot_option_idle_override. | |
955 | */ | |
aaa3896b | 956 | static_call_update(x86_idle, default_idle); |
d1896049 | 957 | boot_option_idle_override = IDLE_HALT; |
da5e09a1 ZY |
958 | } else if (!strcmp(str, "nomwait")) { |
959 | /* | |
960 | * If the boot option of "idle=nomwait" is added, | |
8bcedb4c WK |
961 | * it means that mwait will be disabled for CPU C1/C2/C3 |
962 | * states. | |
da5e09a1 | 963 | */ |
d1896049 | 964 | boot_option_idle_override = IDLE_NOMWAIT; |
c1e3b377 | 965 | } else |
7f424a8b PZ |
966 | return -1; |
967 | ||
7f424a8b PZ |
968 | return 0; |
969 | } | |
970 | early_param("idle", idle_setup); | |
971 | ||
9d62dcdf AW |
972 | unsigned long arch_align_stack(unsigned long sp) |
973 | { | |
974 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
8032bf12 | 975 | sp -= get_random_u32_below(8192); |
9d62dcdf AW |
976 | return sp & ~0xf; |
977 | } | |
978 | ||
979 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
980 | { | |
9c6f0902 | 981 | return randomize_page(mm->brk, 0x02000000); |
9d62dcdf AW |
982 | } |
983 | ||
7ba78053 TG |
984 | /* |
985 | * Called from fs/proc with a reference on @p to find the function | |
986 | * which called into schedule(). This needs to be done carefully | |
987 | * because the task might wake up and we might look at a stack | |
988 | * changing under us. | |
989 | */ | |
42a20f86 | 990 | unsigned long __get_wchan(struct task_struct *p) |
7ba78053 | 991 | { |
5d1ceb39 PZ |
992 | struct unwind_state state; |
993 | unsigned long addr = 0; | |
7ba78053 | 994 | |
0dc636b3 PZ |
995 | if (!try_get_task_stack(p)) |
996 | return 0; | |
997 | ||
5d1ceb39 PZ |
998 | for (unwind_start(&state, p, NULL, NULL); !unwind_done(&state); |
999 | unwind_next_frame(&state)) { | |
1000 | addr = unwind_get_return_address(&state); | |
1001 | if (!addr) | |
1002 | break; | |
1003 | if (in_sched_functions(addr)) | |
1004 | continue; | |
1005 | break; | |
1006 | } | |
1007 | ||
0dc636b3 PZ |
1008 | put_task_stack(p); |
1009 | ||
5d1ceb39 | 1010 | return addr; |
7ba78053 | 1011 | } |
b0b9b014 | 1012 | |
f5c0b4f3 | 1013 | long do_arch_prctl_common(int option, unsigned long arg2) |
b0b9b014 | 1014 | { |
e9ea1e7f KH |
1015 | switch (option) { |
1016 | case ARCH_GET_CPUID: | |
1017 | return get_cpuid_mode(); | |
1018 | case ARCH_SET_CPUID: | |
f5c0b4f3 | 1019 | return set_cpuid_mode(arg2); |
db8268df CB |
1020 | case ARCH_GET_XCOMP_SUPP: |
1021 | case ARCH_GET_XCOMP_PERM: | |
1022 | case ARCH_REQ_XCOMP_PERM: | |
980fe2fd TG |
1023 | case ARCH_GET_XCOMP_GUEST_PERM: |
1024 | case ARCH_REQ_XCOMP_GUEST_PERM: | |
f5c0b4f3 | 1025 | return fpu_xstate_prctl(option, arg2); |
e9ea1e7f KH |
1026 | } |
1027 | ||
b0b9b014 KH |
1028 | return -EINVAL; |
1029 | } |