Commit | Line | Data |
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61c4628b SS |
1 | #include <linux/errno.h> |
2 | #include <linux/kernel.h> | |
3 | #include <linux/mm.h> | |
4 | #include <linux/smp.h> | |
389d1fb1 | 5 | #include <linux/prctl.h> |
61c4628b SS |
6 | #include <linux/slab.h> |
7 | #include <linux/sched.h> | |
7f424a8b PZ |
8 | #include <linux/module.h> |
9 | #include <linux/pm.h> | |
aa276e1c | 10 | #include <linux/clockchips.h> |
9d62dcdf | 11 | #include <linux/random.h> |
61613521 | 12 | #include <trace/events/power.h> |
24f1e32c | 13 | #include <linux/hw_breakpoint.h> |
c1e3b377 | 14 | #include <asm/system.h> |
d3ec5cae | 15 | #include <asm/apic.h> |
2c1b284e | 16 | #include <asm/syscalls.h> |
389d1fb1 JF |
17 | #include <asm/idle.h> |
18 | #include <asm/uaccess.h> | |
19 | #include <asm/i387.h> | |
2311f0de | 20 | #include <asm/ds.h> |
66cb5917 | 21 | #include <asm/debugreg.h> |
c1e3b377 ZY |
22 | |
23 | unsigned long idle_halt; | |
24 | EXPORT_SYMBOL(idle_halt); | |
da5e09a1 ZY |
25 | unsigned long idle_nomwait; |
26 | EXPORT_SYMBOL(idle_nomwait); | |
61c4628b | 27 | |
aa283f49 | 28 | struct kmem_cache *task_xstate_cachep; |
61c4628b SS |
29 | |
30 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) | |
31 | { | |
32 | *dst = *src; | |
aa283f49 SS |
33 | if (src->thread.xstate) { |
34 | dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep, | |
35 | GFP_KERNEL); | |
36 | if (!dst->thread.xstate) | |
37 | return -ENOMEM; | |
38 | WARN_ON((unsigned long)dst->thread.xstate & 15); | |
39 | memcpy(dst->thread.xstate, src->thread.xstate, xstate_size); | |
40 | } | |
61c4628b SS |
41 | return 0; |
42 | } | |
43 | ||
aa283f49 | 44 | void free_thread_xstate(struct task_struct *tsk) |
61c4628b | 45 | { |
aa283f49 SS |
46 | if (tsk->thread.xstate) { |
47 | kmem_cache_free(task_xstate_cachep, tsk->thread.xstate); | |
48 | tsk->thread.xstate = NULL; | |
49 | } | |
2311f0de MM |
50 | |
51 | WARN(tsk->thread.ds_ctx, "leaking DS context\n"); | |
aa283f49 SS |
52 | } |
53 | ||
aa283f49 SS |
54 | void free_thread_info(struct thread_info *ti) |
55 | { | |
56 | free_thread_xstate(ti->task); | |
1679f271 | 57 | free_pages((unsigned long)ti, get_order(THREAD_SIZE)); |
61c4628b SS |
58 | } |
59 | ||
60 | void arch_task_cache_init(void) | |
61 | { | |
62 | task_xstate_cachep = | |
63 | kmem_cache_create("task_xstate", xstate_size, | |
64 | __alignof__(union thread_xstate), | |
2dff4405 | 65 | SLAB_PANIC | SLAB_NOTRACK, NULL); |
61c4628b | 66 | } |
7f424a8b | 67 | |
389d1fb1 JF |
68 | /* |
69 | * Free current thread data structures etc.. | |
70 | */ | |
71 | void exit_thread(void) | |
72 | { | |
73 | struct task_struct *me = current; | |
74 | struct thread_struct *t = &me->thread; | |
250981e6 | 75 | unsigned long *bp = t->io_bitmap_ptr; |
389d1fb1 | 76 | |
250981e6 | 77 | if (bp) { |
389d1fb1 JF |
78 | struct tss_struct *tss = &per_cpu(init_tss, get_cpu()); |
79 | ||
389d1fb1 JF |
80 | t->io_bitmap_ptr = NULL; |
81 | clear_thread_flag(TIF_IO_BITMAP); | |
82 | /* | |
83 | * Careful, clear this in the TSS too: | |
84 | */ | |
85 | memset(tss->io_bitmap, 0xff, t->io_bitmap_max); | |
86 | t->io_bitmap_max = 0; | |
87 | put_cpu(); | |
250981e6 | 88 | kfree(bp); |
389d1fb1 | 89 | } |
389d1fb1 JF |
90 | } |
91 | ||
92 | void flush_thread(void) | |
93 | { | |
94 | struct task_struct *tsk = current; | |
95 | ||
96 | #ifdef CONFIG_X86_64 | |
97 | if (test_tsk_thread_flag(tsk, TIF_ABI_PENDING)) { | |
98 | clear_tsk_thread_flag(tsk, TIF_ABI_PENDING); | |
99 | if (test_tsk_thread_flag(tsk, TIF_IA32)) { | |
100 | clear_tsk_thread_flag(tsk, TIF_IA32); | |
101 | } else { | |
102 | set_tsk_thread_flag(tsk, TIF_IA32); | |
103 | current_thread_info()->status |= TS_COMPAT; | |
104 | } | |
105 | } | |
106 | #endif | |
107 | ||
24f1e32c | 108 | flush_ptrace_hw_breakpoint(tsk); |
389d1fb1 JF |
109 | memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); |
110 | /* | |
111 | * Forget coprocessor state.. | |
112 | */ | |
113 | tsk->fpu_counter = 0; | |
114 | clear_fpu(tsk); | |
115 | clear_used_math(); | |
116 | } | |
117 | ||
118 | static void hard_disable_TSC(void) | |
119 | { | |
120 | write_cr4(read_cr4() | X86_CR4_TSD); | |
121 | } | |
122 | ||
123 | void disable_TSC(void) | |
124 | { | |
125 | preempt_disable(); | |
126 | if (!test_and_set_thread_flag(TIF_NOTSC)) | |
127 | /* | |
128 | * Must flip the CPU state synchronously with | |
129 | * TIF_NOTSC in the current running context. | |
130 | */ | |
131 | hard_disable_TSC(); | |
132 | preempt_enable(); | |
133 | } | |
134 | ||
135 | static void hard_enable_TSC(void) | |
136 | { | |
137 | write_cr4(read_cr4() & ~X86_CR4_TSD); | |
138 | } | |
139 | ||
140 | static void enable_TSC(void) | |
141 | { | |
142 | preempt_disable(); | |
143 | if (test_and_clear_thread_flag(TIF_NOTSC)) | |
144 | /* | |
145 | * Must flip the CPU state synchronously with | |
146 | * TIF_NOTSC in the current running context. | |
147 | */ | |
148 | hard_enable_TSC(); | |
149 | preempt_enable(); | |
150 | } | |
151 | ||
152 | int get_tsc_mode(unsigned long adr) | |
153 | { | |
154 | unsigned int val; | |
155 | ||
156 | if (test_thread_flag(TIF_NOTSC)) | |
157 | val = PR_TSC_SIGSEGV; | |
158 | else | |
159 | val = PR_TSC_ENABLE; | |
160 | ||
161 | return put_user(val, (unsigned int __user *)adr); | |
162 | } | |
163 | ||
164 | int set_tsc_mode(unsigned int val) | |
165 | { | |
166 | if (val == PR_TSC_SIGSEGV) | |
167 | disable_TSC(); | |
168 | else if (val == PR_TSC_ENABLE) | |
169 | enable_TSC(); | |
170 | else | |
171 | return -EINVAL; | |
172 | ||
173 | return 0; | |
174 | } | |
175 | ||
176 | void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, | |
177 | struct tss_struct *tss) | |
178 | { | |
179 | struct thread_struct *prev, *next; | |
180 | ||
181 | prev = &prev_p->thread; | |
182 | next = &next_p->thread; | |
183 | ||
184 | if (test_tsk_thread_flag(next_p, TIF_DS_AREA_MSR) || | |
185 | test_tsk_thread_flag(prev_p, TIF_DS_AREA_MSR)) | |
186 | ds_switch_to(prev_p, next_p); | |
187 | else if (next->debugctlmsr != prev->debugctlmsr) | |
188 | update_debugctlmsr(next->debugctlmsr); | |
189 | ||
389d1fb1 JF |
190 | if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^ |
191 | test_tsk_thread_flag(next_p, TIF_NOTSC)) { | |
192 | /* prev and next are different */ | |
193 | if (test_tsk_thread_flag(next_p, TIF_NOTSC)) | |
194 | hard_disable_TSC(); | |
195 | else | |
196 | hard_enable_TSC(); | |
197 | } | |
198 | ||
199 | if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) { | |
200 | /* | |
201 | * Copy the relevant range of the IO bitmap. | |
202 | * Normally this is 128 bytes or less: | |
203 | */ | |
204 | memcpy(tss->io_bitmap, next->io_bitmap_ptr, | |
205 | max(prev->io_bitmap_max, next->io_bitmap_max)); | |
206 | } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) { | |
207 | /* | |
208 | * Clear any possible leftover bits: | |
209 | */ | |
210 | memset(tss->io_bitmap, 0xff, prev->io_bitmap_max); | |
211 | } | |
212 | } | |
213 | ||
214 | int sys_fork(struct pt_regs *regs) | |
215 | { | |
216 | return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL); | |
217 | } | |
218 | ||
219 | /* | |
220 | * This is trivial, and on the face of it looks like it | |
221 | * could equally well be done in user mode. | |
222 | * | |
223 | * Not so, for quite unobvious reasons - register pressure. | |
224 | * In user mode vfork() cannot have a stack frame, and if | |
225 | * done by calling the "clone()" system call directly, you | |
226 | * do not have enough call-clobbered registers to hold all | |
227 | * the information you need. | |
228 | */ | |
229 | int sys_vfork(struct pt_regs *regs) | |
230 | { | |
231 | return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0, | |
232 | NULL, NULL); | |
233 | } | |
234 | ||
235 | ||
00dba564 TG |
236 | /* |
237 | * Idle related variables and functions | |
238 | */ | |
239 | unsigned long boot_option_idle_override = 0; | |
240 | EXPORT_SYMBOL(boot_option_idle_override); | |
241 | ||
242 | /* | |
243 | * Powermanagement idle function, if any.. | |
244 | */ | |
245 | void (*pm_idle)(void); | |
246 | EXPORT_SYMBOL(pm_idle); | |
247 | ||
248 | #ifdef CONFIG_X86_32 | |
249 | /* | |
250 | * This halt magic was a workaround for ancient floppy DMA | |
251 | * wreckage. It should be safe to remove. | |
252 | */ | |
253 | static int hlt_counter; | |
254 | void disable_hlt(void) | |
255 | { | |
256 | hlt_counter++; | |
257 | } | |
258 | EXPORT_SYMBOL(disable_hlt); | |
259 | ||
260 | void enable_hlt(void) | |
261 | { | |
262 | hlt_counter--; | |
263 | } | |
264 | EXPORT_SYMBOL(enable_hlt); | |
265 | ||
266 | static inline int hlt_use_halt(void) | |
267 | { | |
268 | return (!hlt_counter && boot_cpu_data.hlt_works_ok); | |
269 | } | |
270 | #else | |
271 | static inline int hlt_use_halt(void) | |
272 | { | |
273 | return 1; | |
274 | } | |
275 | #endif | |
276 | ||
277 | /* | |
278 | * We use this if we don't have any better | |
279 | * idle routine.. | |
280 | */ | |
281 | void default_idle(void) | |
282 | { | |
283 | if (hlt_use_halt()) { | |
61613521 | 284 | trace_power_start(POWER_CSTATE, 1); |
00dba564 TG |
285 | current_thread_info()->status &= ~TS_POLLING; |
286 | /* | |
287 | * TS_POLLING-cleared state must be visible before we | |
288 | * test NEED_RESCHED: | |
289 | */ | |
290 | smp_mb(); | |
291 | ||
292 | if (!need_resched()) | |
293 | safe_halt(); /* enables interrupts racelessly */ | |
294 | else | |
295 | local_irq_enable(); | |
296 | current_thread_info()->status |= TS_POLLING; | |
297 | } else { | |
298 | local_irq_enable(); | |
299 | /* loop is done by the caller */ | |
300 | cpu_relax(); | |
301 | } | |
302 | } | |
303 | #ifdef CONFIG_APM_MODULE | |
304 | EXPORT_SYMBOL(default_idle); | |
305 | #endif | |
306 | ||
d3ec5cae IV |
307 | void stop_this_cpu(void *dummy) |
308 | { | |
309 | local_irq_disable(); | |
310 | /* | |
311 | * Remove this CPU: | |
312 | */ | |
4f062896 | 313 | set_cpu_online(smp_processor_id(), false); |
d3ec5cae IV |
314 | disable_local_APIC(); |
315 | ||
316 | for (;;) { | |
317 | if (hlt_works(smp_processor_id())) | |
318 | halt(); | |
319 | } | |
320 | } | |
321 | ||
7f424a8b PZ |
322 | static void do_nothing(void *unused) |
323 | { | |
324 | } | |
325 | ||
326 | /* | |
327 | * cpu_idle_wait - Used to ensure that all the CPUs discard old value of | |
328 | * pm_idle and update to new pm_idle value. Required while changing pm_idle | |
329 | * handler on SMP systems. | |
330 | * | |
331 | * Caller must have changed pm_idle to the new value before the call. Old | |
332 | * pm_idle value will not be used by any CPU after the return of this function. | |
333 | */ | |
334 | void cpu_idle_wait(void) | |
335 | { | |
336 | smp_mb(); | |
337 | /* kick all the CPUs so that they exit out of pm_idle */ | |
127a237a | 338 | smp_call_function(do_nothing, NULL, 1); |
7f424a8b PZ |
339 | } |
340 | EXPORT_SYMBOL_GPL(cpu_idle_wait); | |
341 | ||
342 | /* | |
343 | * This uses new MONITOR/MWAIT instructions on P4 processors with PNI, | |
344 | * which can obviate IPI to trigger checking of need_resched. | |
345 | * We execute MONITOR against need_resched and enter optimized wait state | |
346 | * through MWAIT. Whenever someone changes need_resched, we would be woken | |
347 | * up from MWAIT (without an IPI). | |
348 | * | |
349 | * New with Core Duo processors, MWAIT can take some hints based on CPU | |
350 | * capability. | |
351 | */ | |
352 | void mwait_idle_with_hints(unsigned long ax, unsigned long cx) | |
353 | { | |
61613521 | 354 | trace_power_start(POWER_CSTATE, (ax>>4)+1); |
7f424a8b | 355 | if (!need_resched()) { |
e736ad54 PV |
356 | if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR)) |
357 | clflush((void *)¤t_thread_info()->flags); | |
358 | ||
7f424a8b PZ |
359 | __monitor((void *)¤t_thread_info()->flags, 0, 0); |
360 | smp_mb(); | |
361 | if (!need_resched()) | |
362 | __mwait(ax, cx); | |
363 | } | |
364 | } | |
365 | ||
366 | /* Default MONITOR/MWAIT with no hints, used for default C1 state */ | |
367 | static void mwait_idle(void) | |
368 | { | |
369 | if (!need_resched()) { | |
61613521 | 370 | trace_power_start(POWER_CSTATE, 1); |
e736ad54 PV |
371 | if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR)) |
372 | clflush((void *)¤t_thread_info()->flags); | |
373 | ||
7f424a8b PZ |
374 | __monitor((void *)¤t_thread_info()->flags, 0, 0); |
375 | smp_mb(); | |
376 | if (!need_resched()) | |
377 | __sti_mwait(0, 0); | |
378 | else | |
379 | local_irq_enable(); | |
380 | } else | |
381 | local_irq_enable(); | |
382 | } | |
383 | ||
7f424a8b PZ |
384 | /* |
385 | * On SMP it's slightly faster (but much more power-consuming!) | |
386 | * to poll the ->work.need_resched flag instead of waiting for the | |
387 | * cross-CPU IPI to arrive. Use this option with caution. | |
388 | */ | |
389 | static void poll_idle(void) | |
390 | { | |
61613521 | 391 | trace_power_start(POWER_CSTATE, 0); |
7f424a8b | 392 | local_irq_enable(); |
2c7e9fd4 JK |
393 | while (!need_resched()) |
394 | cpu_relax(); | |
61613521 | 395 | trace_power_end(0); |
7f424a8b PZ |
396 | } |
397 | ||
e9623b35 TG |
398 | /* |
399 | * mwait selection logic: | |
400 | * | |
401 | * It depends on the CPU. For AMD CPUs that support MWAIT this is | |
402 | * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings | |
403 | * then depend on a clock divisor and current Pstate of the core. If | |
404 | * all cores of a processor are in halt state (C1) the processor can | |
405 | * enter the C1E (C1 enhanced) state. If mwait is used this will never | |
406 | * happen. | |
407 | * | |
408 | * idle=mwait overrides this decision and forces the usage of mwait. | |
409 | */ | |
08ad8afa | 410 | static int __cpuinitdata force_mwait; |
09fd4b4e TG |
411 | |
412 | #define MWAIT_INFO 0x05 | |
413 | #define MWAIT_ECX_EXTENDED_INFO 0x01 | |
414 | #define MWAIT_EDX_C1 0xf0 | |
415 | ||
e9623b35 TG |
416 | static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c) |
417 | { | |
09fd4b4e TG |
418 | u32 eax, ebx, ecx, edx; |
419 | ||
e9623b35 TG |
420 | if (force_mwait) |
421 | return 1; | |
422 | ||
09fd4b4e TG |
423 | if (c->cpuid_level < MWAIT_INFO) |
424 | return 0; | |
425 | ||
426 | cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx); | |
427 | /* Check, whether EDX has extended info about MWAIT */ | |
428 | if (!(ecx & MWAIT_ECX_EXTENDED_INFO)) | |
429 | return 1; | |
430 | ||
431 | /* | |
432 | * edx enumeratios MONITOR/MWAIT extensions. Check, whether | |
433 | * C1 supports MWAIT | |
434 | */ | |
435 | return (edx & MWAIT_EDX_C1); | |
e9623b35 TG |
436 | } |
437 | ||
aa276e1c TG |
438 | /* |
439 | * Check for AMD CPUs, which have potentially C1E support | |
440 | */ | |
441 | static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c) | |
442 | { | |
443 | if (c->x86_vendor != X86_VENDOR_AMD) | |
444 | return 0; | |
445 | ||
446 | if (c->x86 < 0x0F) | |
447 | return 0; | |
448 | ||
449 | /* Family 0x0f models < rev F do not have C1E */ | |
450 | if (c->x86 == 0x0f && c->x86_model < 0x40) | |
451 | return 0; | |
452 | ||
453 | return 1; | |
454 | } | |
455 | ||
bc9b83dd | 456 | static cpumask_var_t c1e_mask; |
4faac97d TG |
457 | static int c1e_detected; |
458 | ||
459 | void c1e_remove_cpu(int cpu) | |
460 | { | |
30e1e6d1 RR |
461 | if (c1e_mask != NULL) |
462 | cpumask_clear_cpu(cpu, c1e_mask); | |
4faac97d TG |
463 | } |
464 | ||
aa276e1c TG |
465 | /* |
466 | * C1E aware idle routine. We check for C1E active in the interrupt | |
467 | * pending message MSR. If we detect C1E, then we handle it the same | |
468 | * way as C3 power states (local apic timer and TSC stop) | |
469 | */ | |
470 | static void c1e_idle(void) | |
471 | { | |
aa276e1c TG |
472 | if (need_resched()) |
473 | return; | |
474 | ||
475 | if (!c1e_detected) { | |
476 | u32 lo, hi; | |
477 | ||
478 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); | |
479 | if (lo & K8_INTP_C1E_ACTIVE_MASK) { | |
480 | c1e_detected = 1; | |
40fb1715 | 481 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
09bfeea1 AH |
482 | mark_tsc_unstable("TSC halt in AMD C1E"); |
483 | printk(KERN_INFO "System has AMD C1E enabled\n"); | |
a8d68290 | 484 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E); |
aa276e1c TG |
485 | } |
486 | } | |
487 | ||
488 | if (c1e_detected) { | |
489 | int cpu = smp_processor_id(); | |
490 | ||
bc9b83dd RR |
491 | if (!cpumask_test_cpu(cpu, c1e_mask)) { |
492 | cpumask_set_cpu(cpu, c1e_mask); | |
0beefa20 | 493 | /* |
f833bab8 | 494 | * Force broadcast so ACPI can not interfere. |
0beefa20 | 495 | */ |
aa276e1c TG |
496 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE, |
497 | &cpu); | |
498 | printk(KERN_INFO "Switch to broadcast mode on CPU%d\n", | |
499 | cpu); | |
500 | } | |
501 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu); | |
0beefa20 | 502 | |
aa276e1c | 503 | default_idle(); |
0beefa20 TG |
504 | |
505 | /* | |
506 | * The switch back from broadcast mode needs to be | |
507 | * called with interrupts disabled. | |
508 | */ | |
509 | local_irq_disable(); | |
510 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu); | |
511 | local_irq_enable(); | |
aa276e1c TG |
512 | } else |
513 | default_idle(); | |
514 | } | |
515 | ||
7f424a8b PZ |
516 | void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c) |
517 | { | |
3e5095d1 | 518 | #ifdef CONFIG_SMP |
7f424a8b PZ |
519 | if (pm_idle == poll_idle && smp_num_siblings > 1) { |
520 | printk(KERN_WARNING "WARNING: polling idle and HT enabled," | |
521 | " performance may degrade.\n"); | |
522 | } | |
523 | #endif | |
6ddd2a27 TG |
524 | if (pm_idle) |
525 | return; | |
526 | ||
e9623b35 | 527 | if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) { |
7f424a8b | 528 | /* |
7f424a8b PZ |
529 | * One CPU supports mwait => All CPUs supports mwait |
530 | */ | |
6ddd2a27 TG |
531 | printk(KERN_INFO "using mwait in idle threads.\n"); |
532 | pm_idle = mwait_idle; | |
aa276e1c TG |
533 | } else if (check_c1e_idle(c)) { |
534 | printk(KERN_INFO "using C1E aware idle routine\n"); | |
535 | pm_idle = c1e_idle; | |
6ddd2a27 TG |
536 | } else |
537 | pm_idle = default_idle; | |
7f424a8b PZ |
538 | } |
539 | ||
30e1e6d1 RR |
540 | void __init init_c1e_mask(void) |
541 | { | |
542 | /* If we're using c1e_idle, we need to allocate c1e_mask. */ | |
79f55997 LZ |
543 | if (pm_idle == c1e_idle) |
544 | zalloc_cpumask_var(&c1e_mask, GFP_KERNEL); | |
30e1e6d1 RR |
545 | } |
546 | ||
7f424a8b PZ |
547 | static int __init idle_setup(char *str) |
548 | { | |
ab6bc3e3 CG |
549 | if (!str) |
550 | return -EINVAL; | |
551 | ||
7f424a8b PZ |
552 | if (!strcmp(str, "poll")) { |
553 | printk("using polling idle threads.\n"); | |
554 | pm_idle = poll_idle; | |
555 | } else if (!strcmp(str, "mwait")) | |
556 | force_mwait = 1; | |
c1e3b377 ZY |
557 | else if (!strcmp(str, "halt")) { |
558 | /* | |
559 | * When the boot option of idle=halt is added, halt is | |
560 | * forced to be used for CPU idle. In such case CPU C2/C3 | |
561 | * won't be used again. | |
562 | * To continue to load the CPU idle driver, don't touch | |
563 | * the boot_option_idle_override. | |
564 | */ | |
565 | pm_idle = default_idle; | |
566 | idle_halt = 1; | |
567 | return 0; | |
da5e09a1 ZY |
568 | } else if (!strcmp(str, "nomwait")) { |
569 | /* | |
570 | * If the boot option of "idle=nomwait" is added, | |
571 | * it means that mwait will be disabled for CPU C2/C3 | |
572 | * states. In such case it won't touch the variable | |
573 | * of boot_option_idle_override. | |
574 | */ | |
575 | idle_nomwait = 1; | |
576 | return 0; | |
c1e3b377 | 577 | } else |
7f424a8b PZ |
578 | return -1; |
579 | ||
580 | boot_option_idle_override = 1; | |
581 | return 0; | |
582 | } | |
583 | early_param("idle", idle_setup); | |
584 | ||
9d62dcdf AW |
585 | unsigned long arch_align_stack(unsigned long sp) |
586 | { | |
587 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
588 | sp -= get_random_int() % 8192; | |
589 | return sp & ~0xf; | |
590 | } | |
591 | ||
592 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
593 | { | |
594 | unsigned long range_end = mm->brk + 0x02000000; | |
595 | return randomize_range(mm->brk, range_end, 0) ? : mm->brk; | |
596 | } | |
597 |