x86: fold apic_ops into genapic
[linux-2.6-block.git] / arch / x86 / kernel / probe_32.c
CommitLineData
9b0c5028 1/*
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2 * Default generic APIC driver. This handles up to 8 CPUs.
3 *
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4 * Copyright 2003 Andi Kleen, SuSE Labs.
5 * Subject to the GNU Public License, v.2
6 *
1da177e4 7 * Generic x86 APIC driver probe layer.
9b0c5028 8 */
1da177e4
LT
9#include <linux/threads.h>
10#include <linux/cpumask.h>
11#include <linux/string.h>
12#include <linux/kernel.h>
13#include <linux/ctype.h>
14#include <linux/init.h>
1a3f239d 15#include <linux/errno.h>
1da177e4
LT
16#include <asm/fixmap.h>
17#include <asm/mpspec.h>
18#include <asm/apicdef.h>
19#include <asm/genapic.h>
54ac14a8 20#include <asm/setup.h>
1da177e4 21
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22#include <linux/threads.h>
23#include <linux/cpumask.h>
24#include <asm/mpspec.h>
25#include <asm/genapic.h>
26#include <asm/fixmap.h>
27#include <asm/apicdef.h>
28#include <linux/kernel.h>
29#include <linux/string.h>
30#include <linux/smp.h>
31#include <linux/init.h>
32#include <asm/genapic.h>
33#include <asm/ipi.h>
34
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35#include <linux/smp.h>
36#include <linux/init.h>
37#include <linux/interrupt.h>
38#include <asm/acpi.h>
39#include <asm/arch_hooks.h>
40#include <asm/e820.h>
41#include <asm/setup.h>
42
43#include <asm/genapic.h>
44
45#ifdef CONFIG_HOTPLUG_CPU
46#define DEFAULT_SEND_IPI (1)
47#else
48#define DEFAULT_SEND_IPI (0)
49#endif
50
51int no_broadcast = DEFAULT_SEND_IPI;
52
53#ifdef CONFIG_X86_LOCAL_APIC
54
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55static void default_vector_allocation_domain(int cpu, struct cpumask *retmask)
56{
57 /*
58 * Careful. Some cpus do not strictly honor the set of cpus
59 * specified in the interrupt destination when using lowest
60 * priority interrupt delivery mode.
61 *
62 * In particular there was a hyperthreading cpu observed to
63 * deliver interrupts to the wrong hyperthread when only one
64 * hyperthread was specified in the interrupt desitination.
65 */
66 *retmask = (cpumask_t) { { [0] = APIC_ALL_CPUS } };
67}
68
69/* should be called last. */
70static int probe_default(void)
71{
72 return 1;
73}
74
75struct genapic apic_default = {
76
77 .name = "default",
78 .probe = probe_default,
79 .acpi_madt_oem_check = NULL,
80 .apic_id_registered = default_apic_id_registered,
81
82 .irq_delivery_mode = dest_LowestPrio,
83 /* logical delivery broadcast to all CPUs: */
84 .irq_dest_mode = 1,
85
86 .target_cpus = default_target_cpus,
87 .disable_esr = 0,
88 .dest_logical = APIC_DEST_LOGICAL,
89 .check_apicid_used = default_check_apicid_used,
90 .check_apicid_present = default_check_apicid_present,
91
92 .vector_allocation_domain = default_vector_allocation_domain,
93 .init_apic_ldr = default_init_apic_ldr,
94
95 .ioapic_phys_id_map = default_ioapic_phys_id_map,
96 .setup_apic_routing = default_setup_apic_routing,
97 .multi_timer_check = NULL,
98 .apicid_to_node = default_apicid_to_node,
99 .cpu_to_logical_apicid = default_cpu_to_logical_apicid,
100 .cpu_present_to_apicid = default_cpu_present_to_apicid,
101 .apicid_to_cpu_present = default_apicid_to_cpu_present,
102 .setup_portio_remap = NULL,
103 .check_phys_apicid_present = default_check_phys_apicid_present,
104 .enable_apic_mode = NULL,
105 .phys_pkg_id = default_phys_pkg_id,
106 .mps_oem_check = NULL,
107
108 .get_apic_id = default_get_apic_id,
109 .set_apic_id = NULL,
110 .apic_id_mask = 0x0F << 24,
111
112 .cpu_mask_to_apicid = default_cpu_mask_to_apicid,
113 .cpu_mask_to_apicid_and = default_cpu_mask_to_apicid_and,
114
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115 .send_IPI_mask = default_send_IPI_mask_logical,
116 .send_IPI_mask_allbutself = default_send_IPI_mask_allbutself_logical,
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117 .send_IPI_allbutself = default_send_IPI_allbutself,
118 .send_IPI_all = default_send_IPI_all,
6b64ee02 119 .send_IPI_self = default_send_IPI_self,
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120
121 .wakeup_cpu = NULL,
122 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
123 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
124
125 .wait_for_init_deassert = default_wait_for_init_deassert,
126
127 .smp_callin_clear_local_apic = NULL,
128 .store_NMI_vector = NULL,
129 .inquire_remote_apic = default_inquire_remote_apic,
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130
131 .read = native_apic_mem_read,
132 .write = native_apic_mem_write,
133 .icr_read = native_apic_icr_read,
134 .icr_write = native_apic_icr_write,
135 .wait_icr_idle = native_apic_wait_icr_idle,
136 .safe_wait_icr_idle = native_safe_apic_wait_icr_idle,
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137};
138
d49c4288 139extern struct genapic apic_numaq;
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140extern struct genapic apic_summit;
141extern struct genapic apic_bigsmp;
142extern struct genapic apic_es7000;
143extern struct genapic apic_default;
144
c8d46cf0 145struct genapic *apic = &apic_default;
1da177e4 146
96d55358 147static struct genapic *apic_probe[] __initdata = {
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148#ifdef CONFIG_X86_NUMAQ
149 &apic_numaq,
150#endif
151#ifdef CONFIG_X86_SUMMIT
1da177e4 152 &apic_summit,
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153#endif
154#ifdef CONFIG_X86_BIGSMP
9b0c5028 155 &apic_bigsmp,
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156#endif
157#ifdef CONFIG_X86_ES7000
1da177e4 158 &apic_es7000,
d49c4288 159#endif
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160 &apic_default, /* must be last */
161 NULL,
162};
163
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164static int cmdline_apic __initdata;
165static int __init parse_apic(char *arg)
166{
167 int i;
168
169 if (!arg)
170 return -EINVAL;
171
172 for (i = 0; apic_probe[i]; i++) {
173 if (!strcmp(apic_probe[i]->name, arg)) {
c8d46cf0 174 apic = apic_probe[i];
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175 cmdline_apic = 1;
176 return 0;
177 }
178 }
9a8cb626 179
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180 if (x86_quirks->update_genapic)
181 x86_quirks->update_genapic();
182
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183 /* Parsed again by __setup for debug/verbose */
184 return 0;
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185}
186early_param("apic", parse_apic);
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187
188void __init generic_bigsmp_probe(void)
189{
b20d70b7 190#ifdef CONFIG_X86_BIGSMP
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191 /*
192 * This routine is used to switch to bigsmp mode when
193 * - There is no apic= option specified by the user
27b46d76 194 * - generic_apic_probe() has chosen apic_default as the sub_arch
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195 * - we find more than 8 CPUs in acpi LAPIC listing with xAPIC support
196 */
197
c8d46cf0 198 if (!cmdline_apic && apic == &apic_default) {
911a62d4 199 if (apic_bigsmp.probe()) {
c8d46cf0 200 apic = &apic_bigsmp;
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201 if (x86_quirks->update_genapic)
202 x86_quirks->update_genapic();
911a62d4 203 printk(KERN_INFO "Overriding APIC driver with %s\n",
c8d46cf0 204 apic->name);
911a62d4 205 }
87f76065 206 }
d49c4288 207#endif
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208}
209
1a3f239d 210void __init generic_apic_probe(void)
9b0c5028 211{
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212 if (!cmdline_apic) {
213 int i;
214 for (i = 0; apic_probe[i]; i++) {
215 if (apic_probe[i]->probe()) {
c8d46cf0 216 apic = apic_probe[i];
1a3f239d 217 break;
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218 }
219 }
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220 /* Not visible without early console */
221 if (!apic_probe[i])
222 panic("Didn't find an APIC driver");
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223
224 if (x86_quirks->update_genapic)
225 x86_quirks->update_genapic();
1da177e4 226 }
c8d46cf0 227 printk(KERN_INFO "Using APIC driver %s\n", apic->name);
9b0c5028 228}
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229
230/* These functions can switch the APIC even after the initial ->probe() */
231
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232int __init
233generic_mps_oem_check(struct mpc_table *mpc, char *oem, char *productid)
9b0c5028 234{
1da177e4 235 int i;
5f836405 236
9b0c5028 237 for (i = 0; apic_probe[i]; ++i) {
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238 if (!apic_probe[i]->mps_oem_check)
239 continue;
240 if (!apic_probe[i]->mps_oem_check(mpc, oem, productid))
241 continue;
242
243 if (!cmdline_apic) {
244 apic = apic_probe[i];
245 if (x86_quirks->update_genapic)
246 x86_quirks->update_genapic();
247 printk(KERN_INFO "Switched to APIC driver `%s'.\n",
248 apic->name);
9b0c5028 249 }
5f836405 250 return 1;
9b0c5028 251 }
1da177e4 252 return 0;
9b0c5028 253}
1da177e4 254
306db03b 255int __init default_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
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256{
257 int i;
306db03b 258
9b0c5028 259 for (i = 0; apic_probe[i]; ++i) {
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260 if (!apic_probe[i]->acpi_madt_oem_check)
261 continue;
262 if (!apic_probe[i]->acpi_madt_oem_check(oem_id, oem_table_id))
263 continue;
264
265 if (!cmdline_apic) {
266 apic = apic_probe[i];
267 if (x86_quirks->update_genapic)
268 x86_quirks->update_genapic();
269 printk(KERN_INFO "Switched to APIC driver `%s'.\n",
270 apic->name);
9b0c5028 271 }
306db03b 272 return 1;
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273 }
274 return 0;
1da177e4 275}
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276
277#endif /* CONFIG_X86_LOCAL_APIC */
278
279/**
280 * pre_intr_init_hook - initialisation prior to setting up interrupt vectors
281 *
282 * Description:
283 * Perform any necessary interrupt initialisation prior to setting up
284 * the "ordinary" interrupt call gates. For legacy reasons, the ISA
285 * interrupts should be initialised here if the machine emulates a PC
286 * in any way.
287 **/
288void __init pre_intr_init_hook(void)
289{
290 if (x86_quirks->arch_pre_intr_init) {
291 if (x86_quirks->arch_pre_intr_init())
292 return;
293 }
294 init_ISA_irqs();
295}
296
297/**
298 * intr_init_hook - post gate setup interrupt initialisation
299 *
300 * Description:
301 * Fill in any interrupts that may have been left out by the general
302 * init_IRQ() routine. interrupts having to do with the machine rather
303 * than the devices on the I/O bus (like APIC interrupts in intel MP
304 * systems) are started here.
305 **/
306void __init intr_init_hook(void)
307{
308 if (x86_quirks->arch_intr_init) {
309 if (x86_quirks->arch_intr_init())
310 return;
311 }
312}
313
314/**
315 * pre_setup_arch_hook - hook called prior to any setup_arch() execution
316 *
317 * Description:
318 * generally used to activate any machine specific identification
319 * routines that may be needed before setup_arch() runs. On Voyager
320 * this is used to get the board revision and type.
321 **/
322void __init pre_setup_arch_hook(void)
323{
324}
325
326/**
327 * trap_init_hook - initialise system specific traps
328 *
329 * Description:
330 * Called as the final act of trap_init(). Used in VISWS to initialise
331 * the various board specific APIC traps.
332 **/
333void __init trap_init_hook(void)
334{
335 if (x86_quirks->arch_trap_init) {
336 if (x86_quirks->arch_trap_init())
337 return;
338 }
339}
340
341static struct irqaction irq0 = {
342 .handler = timer_interrupt,
343 .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_IRQPOLL,
344 .mask = CPU_MASK_NONE,
345 .name = "timer"
346};
347
348/**
349 * pre_time_init_hook - do any specific initialisations before.
350 *
351 **/
352void __init pre_time_init_hook(void)
353{
354 if (x86_quirks->arch_pre_time_init)
355 x86_quirks->arch_pre_time_init();
356}
357
358/**
359 * time_init_hook - do any specific initialisations for the system timer.
360 *
361 * Description:
362 * Must plug the system timer interrupt source at HZ into the IRQ listed
363 * in irq_vectors.h:TIMER_IRQ
364 **/
365void __init time_init_hook(void)
366{
367 if (x86_quirks->arch_time_init) {
368 /*
369 * A nonzero return code does not mean failure, it means
370 * that the architecture quirk does not want any
371 * generic (timer) setup to be performed after this:
372 */
373 if (x86_quirks->arch_time_init())
374 return;
375 }
376
377 irq0.mask = cpumask_of_cpu(0);
378 setup_irq(0, &irq0);
379}
380
381#ifdef CONFIG_MCA
382/**
383 * mca_nmi_hook - hook into MCA specific NMI chain
384 *
385 * Description:
386 * The MCA (Microchannel Architecture) has an NMI chain for NMI sources
387 * along the MCA bus. Use this to hook into that chain if you will need
388 * it.
389 **/
390void mca_nmi_hook(void)
391{
392 /*
393 * If I recall correctly, there's a whole bunch of other things that
394 * we can do to check for NMI problems, but that's all I know about
395 * at the moment.
396 */
397 pr_warning("NMI generated from unknown source!\n");
398}
399#endif
400
401static __init int no_ipi_broadcast(char *str)
402{
403 get_option(&str, &no_broadcast);
404 pr_info("Using %s mode\n",
405 no_broadcast ? "No IPI Broadcast" : "IPI Broadcast");
406 return 1;
407}
408__setup("no_ipi_broadcast=", no_ipi_broadcast);
409
410static int __init print_ipi_mode(void)
411{
412 pr_info("Using IPI %s mode\n",
413 no_broadcast ? "No-Shortcut" : "Shortcut");
414 return 0;
415}
416
417late_initcall(print_ipi_mode);
418