Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Dynamic DMA mapping support for AMD Hammer. | |
05fccb0e | 3 | * |
1da177e4 LT |
4 | * Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI. |
5 | * This allows to use PCI devices that only support 32bit addresses on systems | |
05fccb0e | 6 | * with more than 4GB. |
1da177e4 | 7 | * |
5872fb94 | 8 | * See Documentation/PCI/PCI-DMA-mapping.txt for the interface specification. |
05fccb0e | 9 | * |
1da177e4 | 10 | * Copyright 2002 Andi Kleen, SuSE Labs. |
ff7f3649 | 11 | * Subject to the GNU General Public License v2 only. |
1da177e4 LT |
12 | */ |
13 | ||
1da177e4 LT |
14 | #include <linux/types.h> |
15 | #include <linux/ctype.h> | |
16 | #include <linux/agp_backend.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/mm.h> | |
d43c36dc | 19 | #include <linux/sched.h> |
1da177e4 LT |
20 | #include <linux/string.h> |
21 | #include <linux/spinlock.h> | |
22 | #include <linux/pci.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/topology.h> | |
25 | #include <linux/interrupt.h> | |
a66022c4 | 26 | #include <linux/bitmap.h> |
1eeb66a1 | 27 | #include <linux/kdebug.h> |
9ee1bea4 | 28 | #include <linux/scatterlist.h> |
fde9a109 | 29 | #include <linux/iommu-helper.h> |
cd76374e | 30 | #include <linux/sysdev.h> |
237a6224 | 31 | #include <linux/io.h> |
5a0e3ad6 | 32 | #include <linux/gfp.h> |
1da177e4 | 33 | #include <asm/atomic.h> |
1da177e4 LT |
34 | #include <asm/mtrr.h> |
35 | #include <asm/pgtable.h> | |
36 | #include <asm/proto.h> | |
46a7fa27 | 37 | #include <asm/iommu.h> |
395624fc | 38 | #include <asm/gart.h> |
1da177e4 | 39 | #include <asm/cacheflush.h> |
17a941d8 MBY |
40 | #include <asm/swiotlb.h> |
41 | #include <asm/dma.h> | |
a32073bf | 42 | #include <asm/k8.h> |
338bac52 | 43 | #include <asm/x86_init.h> |
1da177e4 | 44 | |
79da0874 | 45 | static unsigned long iommu_bus_base; /* GART remapping area (physical) */ |
05fccb0e | 46 | static unsigned long iommu_size; /* size of remapping area bytes */ |
1da177e4 LT |
47 | static unsigned long iommu_pages; /* .. and in pages */ |
48 | ||
05fccb0e | 49 | static u32 *iommu_gatt_base; /* Remapping table */ |
1da177e4 | 50 | |
42109197 FT |
51 | static dma_addr_t bad_dma_addr; |
52 | ||
05fccb0e IM |
53 | /* |
54 | * If this is disabled the IOMMU will use an optimized flushing strategy | |
55 | * of only flushing when an mapping is reused. With it true the GART is | |
56 | * flushed for every mapping. Problem is that doing the lazy flush seems | |
57 | * to trigger bugs with some popular PCI cards, in particular 3ware (but | |
58 | * has been also also seen with Qlogic at least). | |
59 | */ | |
c854c919 | 60 | static int iommu_fullflush = 1; |
1da177e4 | 61 | |
05fccb0e | 62 | /* Allocation bitmap for the remapping area: */ |
1da177e4 | 63 | static DEFINE_SPINLOCK(iommu_bitmap_lock); |
05fccb0e IM |
64 | /* Guarded by iommu_bitmap_lock: */ |
65 | static unsigned long *iommu_gart_bitmap; | |
1da177e4 | 66 | |
05fccb0e | 67 | static u32 gart_unmapped_entry; |
1da177e4 LT |
68 | |
69 | #define GPTE_VALID 1 | |
70 | #define GPTE_COHERENT 2 | |
71 | #define GPTE_ENCODE(x) \ | |
72 | (((x) & 0xfffff000) | (((x) >> 32) << 4) | GPTE_VALID | GPTE_COHERENT) | |
73 | #define GPTE_DECODE(x) (((x) & 0xfffff000) | (((u64)(x) & 0xff0) << 28)) | |
74 | ||
05fccb0e | 75 | #define EMERGENCY_PAGES 32 /* = 128KB */ |
1da177e4 LT |
76 | |
77 | #ifdef CONFIG_AGP | |
78 | #define AGPEXTERN extern | |
79 | #else | |
80 | #define AGPEXTERN | |
81 | #endif | |
82 | ||
83 | /* backdoor interface to AGP driver */ | |
84 | AGPEXTERN int agp_memory_reserved; | |
85 | AGPEXTERN __u32 *agp_gatt_table; | |
86 | ||
87 | static unsigned long next_bit; /* protected by iommu_bitmap_lock */ | |
3610f211 | 88 | static bool need_flush; /* global flush state. set for each gart wrap */ |
1da177e4 | 89 | |
7b22ff53 FT |
90 | static unsigned long alloc_iommu(struct device *dev, int size, |
91 | unsigned long align_mask) | |
05fccb0e | 92 | { |
1da177e4 | 93 | unsigned long offset, flags; |
fde9a109 FT |
94 | unsigned long boundary_size; |
95 | unsigned long base_index; | |
96 | ||
97 | base_index = ALIGN(iommu_bus_base & dma_get_seg_boundary(dev), | |
98 | PAGE_SIZE) >> PAGE_SHIFT; | |
123bf0e2 | 99 | boundary_size = ALIGN((u64)dma_get_seg_boundary(dev) + 1, |
fde9a109 | 100 | PAGE_SIZE) >> PAGE_SHIFT; |
1da177e4 | 101 | |
05fccb0e | 102 | spin_lock_irqsave(&iommu_bitmap_lock, flags); |
fde9a109 | 103 | offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, next_bit, |
7b22ff53 | 104 | size, base_index, boundary_size, align_mask); |
1da177e4 | 105 | if (offset == -1) { |
3610f211 | 106 | need_flush = true; |
fde9a109 | 107 | offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, 0, |
7b22ff53 FT |
108 | size, base_index, boundary_size, |
109 | align_mask); | |
1da177e4 | 110 | } |
05fccb0e | 111 | if (offset != -1) { |
05fccb0e IM |
112 | next_bit = offset+size; |
113 | if (next_bit >= iommu_pages) { | |
1da177e4 | 114 | next_bit = 0; |
3610f211 | 115 | need_flush = true; |
05fccb0e IM |
116 | } |
117 | } | |
1da177e4 | 118 | if (iommu_fullflush) |
3610f211 | 119 | need_flush = true; |
05fccb0e IM |
120 | spin_unlock_irqrestore(&iommu_bitmap_lock, flags); |
121 | ||
1da177e4 | 122 | return offset; |
05fccb0e | 123 | } |
1da177e4 LT |
124 | |
125 | static void free_iommu(unsigned long offset, int size) | |
05fccb0e | 126 | { |
1da177e4 | 127 | unsigned long flags; |
05fccb0e | 128 | |
1da177e4 | 129 | spin_lock_irqsave(&iommu_bitmap_lock, flags); |
a66022c4 | 130 | bitmap_clear(iommu_gart_bitmap, offset, size); |
70d7d357 JR |
131 | if (offset >= next_bit) |
132 | next_bit = offset + size; | |
1da177e4 | 133 | spin_unlock_irqrestore(&iommu_bitmap_lock, flags); |
05fccb0e | 134 | } |
1da177e4 | 135 | |
05fccb0e | 136 | /* |
1da177e4 LT |
137 | * Use global flush state to avoid races with multiple flushers. |
138 | */ | |
a32073bf | 139 | static void flush_gart(void) |
05fccb0e | 140 | { |
1da177e4 | 141 | unsigned long flags; |
05fccb0e | 142 | |
1da177e4 | 143 | spin_lock_irqsave(&iommu_bitmap_lock, flags); |
a32073bf AK |
144 | if (need_flush) { |
145 | k8_flush_garts(); | |
3610f211 | 146 | need_flush = false; |
05fccb0e | 147 | } |
1da177e4 | 148 | spin_unlock_irqrestore(&iommu_bitmap_lock, flags); |
05fccb0e | 149 | } |
1da177e4 | 150 | |
1da177e4 | 151 | #ifdef CONFIG_IOMMU_LEAK |
1da177e4 | 152 | /* Debugging aid for drivers that don't free their IOMMU tables */ |
1da177e4 | 153 | static int leak_trace; |
79da0874 | 154 | static int iommu_leak_pages = 20; |
05fccb0e | 155 | |
79da0874 | 156 | static void dump_leak(void) |
1da177e4 | 157 | { |
05fccb0e IM |
158 | static int dump; |
159 | ||
19c1a6f5 | 160 | if (dump) |
05fccb0e | 161 | return; |
1da177e4 | 162 | dump = 1; |
05fccb0e | 163 | |
19c1a6f5 FT |
164 | show_stack(NULL, NULL); |
165 | debug_dma_dump_mappings(NULL); | |
1da177e4 | 166 | } |
1da177e4 LT |
167 | #endif |
168 | ||
17a941d8 | 169 | static void iommu_full(struct device *dev, size_t size, int dir) |
1da177e4 | 170 | { |
05fccb0e | 171 | /* |
1da177e4 LT |
172 | * Ran out of IOMMU space for this operation. This is very bad. |
173 | * Unfortunately the drivers cannot handle this operation properly. | |
05fccb0e | 174 | * Return some non mapped prereserved space in the aperture and |
1da177e4 LT |
175 | * let the Northbridge deal with it. This will result in garbage |
176 | * in the IO operation. When the size exceeds the prereserved space | |
05fccb0e | 177 | * memory corruption will occur or random memory will be DMAed |
1da177e4 | 178 | * out. Hopefully no network devices use single mappings that big. |
05fccb0e IM |
179 | */ |
180 | ||
fc3a8828 | 181 | dev_err(dev, "PCI-DMA: Out of IOMMU space for %lu bytes\n", size); |
1da177e4 | 182 | |
17a941d8 | 183 | if (size > PAGE_SIZE*EMERGENCY_PAGES) { |
1da177e4 LT |
184 | if (dir == PCI_DMA_FROMDEVICE || dir == PCI_DMA_BIDIRECTIONAL) |
185 | panic("PCI-DMA: Memory would be corrupted\n"); | |
05fccb0e IM |
186 | if (dir == PCI_DMA_TODEVICE || dir == PCI_DMA_BIDIRECTIONAL) |
187 | panic(KERN_ERR | |
188 | "PCI-DMA: Random memory would be DMAed\n"); | |
189 | } | |
1da177e4 | 190 | #ifdef CONFIG_IOMMU_LEAK |
05fccb0e | 191 | dump_leak(); |
1da177e4 | 192 | #endif |
05fccb0e | 193 | } |
1da177e4 | 194 | |
05fccb0e IM |
195 | static inline int |
196 | need_iommu(struct device *dev, unsigned long addr, size_t size) | |
197 | { | |
a4c2baa6 | 198 | return force_iommu || !dma_capable(dev, addr, size); |
1da177e4 LT |
199 | } |
200 | ||
05fccb0e IM |
201 | static inline int |
202 | nonforced_iommu(struct device *dev, unsigned long addr, size_t size) | |
203 | { | |
a4c2baa6 | 204 | return !dma_capable(dev, addr, size); |
1da177e4 LT |
205 | } |
206 | ||
207 | /* Map a single continuous physical area into the IOMMU. | |
208 | * Caller needs to check if the iommu is needed and flush. | |
209 | */ | |
17a941d8 | 210 | static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem, |
7b22ff53 | 211 | size_t size, int dir, unsigned long align_mask) |
05fccb0e | 212 | { |
1477b8e5 | 213 | unsigned long npages = iommu_num_pages(phys_mem, size, PAGE_SIZE); |
7b22ff53 | 214 | unsigned long iommu_page = alloc_iommu(dev, npages, align_mask); |
1da177e4 | 215 | int i; |
05fccb0e | 216 | |
1da177e4 LT |
217 | if (iommu_page == -1) { |
218 | if (!nonforced_iommu(dev, phys_mem, size)) | |
05fccb0e | 219 | return phys_mem; |
1da177e4 LT |
220 | if (panic_on_overflow) |
221 | panic("dma_map_area overflow %lu bytes\n", size); | |
17a941d8 | 222 | iommu_full(dev, size, dir); |
42109197 | 223 | return bad_dma_addr; |
1da177e4 LT |
224 | } |
225 | ||
226 | for (i = 0; i < npages; i++) { | |
227 | iommu_gatt_base[iommu_page + i] = GPTE_ENCODE(phys_mem); | |
1da177e4 LT |
228 | phys_mem += PAGE_SIZE; |
229 | } | |
230 | return iommu_bus_base + iommu_page*PAGE_SIZE + (phys_mem & ~PAGE_MASK); | |
231 | } | |
232 | ||
233 | /* Map a single area into the IOMMU */ | |
052aedbf FT |
234 | static dma_addr_t gart_map_page(struct device *dev, struct page *page, |
235 | unsigned long offset, size_t size, | |
236 | enum dma_data_direction dir, | |
237 | struct dma_attrs *attrs) | |
1da177e4 | 238 | { |
2be62149 | 239 | unsigned long bus; |
052aedbf | 240 | phys_addr_t paddr = page_to_phys(page) + offset; |
1da177e4 | 241 | |
1da177e4 | 242 | if (!dev) |
6c505ce3 | 243 | dev = &x86_dma_fallback_dev; |
1da177e4 | 244 | |
2be62149 IM |
245 | if (!need_iommu(dev, paddr, size)) |
246 | return paddr; | |
1da177e4 | 247 | |
7b22ff53 FT |
248 | bus = dma_map_area(dev, paddr, size, dir, 0); |
249 | flush_gart(); | |
05fccb0e IM |
250 | |
251 | return bus; | |
17a941d8 MBY |
252 | } |
253 | ||
7c2d9cd2 JM |
254 | /* |
255 | * Free a DMA mapping. | |
256 | */ | |
052aedbf FT |
257 | static void gart_unmap_page(struct device *dev, dma_addr_t dma_addr, |
258 | size_t size, enum dma_data_direction dir, | |
259 | struct dma_attrs *attrs) | |
7c2d9cd2 JM |
260 | { |
261 | unsigned long iommu_page; | |
262 | int npages; | |
263 | int i; | |
264 | ||
265 | if (dma_addr < iommu_bus_base + EMERGENCY_PAGES*PAGE_SIZE || | |
266 | dma_addr >= iommu_bus_base + iommu_size) | |
267 | return; | |
05fccb0e | 268 | |
7c2d9cd2 | 269 | iommu_page = (dma_addr - iommu_bus_base)>>PAGE_SHIFT; |
1477b8e5 | 270 | npages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
7c2d9cd2 JM |
271 | for (i = 0; i < npages; i++) { |
272 | iommu_gatt_base[iommu_page + i] = gart_unmapped_entry; | |
7c2d9cd2 JM |
273 | } |
274 | free_iommu(iommu_page, npages); | |
275 | } | |
276 | ||
17a941d8 MBY |
277 | /* |
278 | * Wrapper for pci_unmap_single working with scatterlists. | |
279 | */ | |
160c1d8e FT |
280 | static void gart_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, |
281 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
17a941d8 | 282 | { |
9ee1bea4 | 283 | struct scatterlist *s; |
17a941d8 MBY |
284 | int i; |
285 | ||
9ee1bea4 | 286 | for_each_sg(sg, s, nents, i) { |
60b08c67 | 287 | if (!s->dma_length || !s->length) |
17a941d8 | 288 | break; |
d7dff840 | 289 | gart_unmap_page(dev, s->dma_address, s->dma_length, dir, NULL); |
17a941d8 MBY |
290 | } |
291 | } | |
1da177e4 LT |
292 | |
293 | /* Fallback for dma_map_sg in case of overflow */ | |
294 | static int dma_map_sg_nonforce(struct device *dev, struct scatterlist *sg, | |
295 | int nents, int dir) | |
296 | { | |
9ee1bea4 | 297 | struct scatterlist *s; |
1da177e4 LT |
298 | int i; |
299 | ||
300 | #ifdef CONFIG_IOMMU_DEBUG | |
123bf0e2 | 301 | pr_debug("dma_map_sg overflow\n"); |
1da177e4 LT |
302 | #endif |
303 | ||
9ee1bea4 | 304 | for_each_sg(sg, s, nents, i) { |
58b053e4 | 305 | unsigned long addr = sg_phys(s); |
05fccb0e IM |
306 | |
307 | if (nonforced_iommu(dev, addr, s->length)) { | |
7b22ff53 | 308 | addr = dma_map_area(dev, addr, s->length, dir, 0); |
42109197 | 309 | if (addr == bad_dma_addr) { |
05fccb0e | 310 | if (i > 0) |
160c1d8e | 311 | gart_unmap_sg(dev, sg, i, dir, NULL); |
05fccb0e | 312 | nents = 0; |
1da177e4 LT |
313 | sg[0].dma_length = 0; |
314 | break; | |
315 | } | |
316 | } | |
317 | s->dma_address = addr; | |
318 | s->dma_length = s->length; | |
319 | } | |
a32073bf | 320 | flush_gart(); |
05fccb0e | 321 | |
1da177e4 LT |
322 | return nents; |
323 | } | |
324 | ||
325 | /* Map multiple scatterlist entries continuous into the first. */ | |
fde9a109 FT |
326 | static int __dma_map_cont(struct device *dev, struct scatterlist *start, |
327 | int nelems, struct scatterlist *sout, | |
328 | unsigned long pages) | |
1da177e4 | 329 | { |
7b22ff53 | 330 | unsigned long iommu_start = alloc_iommu(dev, pages, 0); |
05fccb0e | 331 | unsigned long iommu_page = iommu_start; |
9ee1bea4 | 332 | struct scatterlist *s; |
1da177e4 LT |
333 | int i; |
334 | ||
335 | if (iommu_start == -1) | |
336 | return -1; | |
9ee1bea4 JA |
337 | |
338 | for_each_sg(start, s, nelems, i) { | |
1da177e4 LT |
339 | unsigned long pages, addr; |
340 | unsigned long phys_addr = s->dma_address; | |
05fccb0e | 341 | |
9ee1bea4 JA |
342 | BUG_ON(s != start && s->offset); |
343 | if (s == start) { | |
1da177e4 LT |
344 | sout->dma_address = iommu_bus_base; |
345 | sout->dma_address += iommu_page*PAGE_SIZE + s->offset; | |
346 | sout->dma_length = s->length; | |
05fccb0e IM |
347 | } else { |
348 | sout->dma_length += s->length; | |
1da177e4 LT |
349 | } |
350 | ||
351 | addr = phys_addr; | |
1477b8e5 | 352 | pages = iommu_num_pages(s->offset, s->length, PAGE_SIZE); |
05fccb0e IM |
353 | while (pages--) { |
354 | iommu_gatt_base[iommu_page] = GPTE_ENCODE(addr); | |
1da177e4 LT |
355 | addr += PAGE_SIZE; |
356 | iommu_page++; | |
0d541064 | 357 | } |
05fccb0e IM |
358 | } |
359 | BUG_ON(iommu_page - iommu_start != pages); | |
360 | ||
1da177e4 LT |
361 | return 0; |
362 | } | |
363 | ||
05fccb0e | 364 | static inline int |
fde9a109 FT |
365 | dma_map_cont(struct device *dev, struct scatterlist *start, int nelems, |
366 | struct scatterlist *sout, unsigned long pages, int need) | |
1da177e4 | 367 | { |
9ee1bea4 JA |
368 | if (!need) { |
369 | BUG_ON(nelems != 1); | |
e88a39de | 370 | sout->dma_address = start->dma_address; |
9ee1bea4 | 371 | sout->dma_length = start->length; |
1da177e4 | 372 | return 0; |
9ee1bea4 | 373 | } |
fde9a109 | 374 | return __dma_map_cont(dev, start, nelems, sout, pages); |
1da177e4 | 375 | } |
05fccb0e | 376 | |
1da177e4 LT |
377 | /* |
378 | * DMA map all entries in a scatterlist. | |
05fccb0e | 379 | * Merge chunks that have page aligned sizes into a continuous mapping. |
1da177e4 | 380 | */ |
160c1d8e FT |
381 | static int gart_map_sg(struct device *dev, struct scatterlist *sg, int nents, |
382 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
1da177e4 | 383 | { |
9ee1bea4 | 384 | struct scatterlist *s, *ps, *start_sg, *sgmap; |
05fccb0e IM |
385 | int need = 0, nextneed, i, out, start; |
386 | unsigned long pages = 0; | |
42d00284 FT |
387 | unsigned int seg_size; |
388 | unsigned int max_seg_size; | |
1da177e4 | 389 | |
05fccb0e | 390 | if (nents == 0) |
1da177e4 LT |
391 | return 0; |
392 | ||
1da177e4 | 393 | if (!dev) |
6c505ce3 | 394 | dev = &x86_dma_fallback_dev; |
1da177e4 | 395 | |
123bf0e2 IM |
396 | out = 0; |
397 | start = 0; | |
398 | start_sg = sg; | |
399 | sgmap = sg; | |
400 | seg_size = 0; | |
401 | max_seg_size = dma_get_max_seg_size(dev); | |
402 | ps = NULL; /* shut up gcc */ | |
403 | ||
9ee1bea4 | 404 | for_each_sg(sg, s, nents, i) { |
58b053e4 | 405 | dma_addr_t addr = sg_phys(s); |
05fccb0e | 406 | |
1da177e4 | 407 | s->dma_address = addr; |
05fccb0e | 408 | BUG_ON(s->length == 0); |
1da177e4 | 409 | |
05fccb0e | 410 | nextneed = need_iommu(dev, addr, s->length); |
1da177e4 LT |
411 | |
412 | /* Handle the previous not yet processed entries */ | |
413 | if (i > start) { | |
05fccb0e IM |
414 | /* |
415 | * Can only merge when the last chunk ends on a | |
416 | * page boundary and the new one doesn't have an | |
417 | * offset. | |
418 | */ | |
1da177e4 | 419 | if (!iommu_merge || !nextneed || !need || s->offset || |
42d00284 | 420 | (s->length + seg_size > max_seg_size) || |
9ee1bea4 | 421 | (ps->offset + ps->length) % PAGE_SIZE) { |
fde9a109 FT |
422 | if (dma_map_cont(dev, start_sg, i - start, |
423 | sgmap, pages, need) < 0) | |
1da177e4 LT |
424 | goto error; |
425 | out++; | |
123bf0e2 IM |
426 | |
427 | seg_size = 0; | |
428 | sgmap = sg_next(sgmap); | |
429 | pages = 0; | |
430 | start = i; | |
431 | start_sg = s; | |
1da177e4 LT |
432 | } |
433 | } | |
434 | ||
42d00284 | 435 | seg_size += s->length; |
1da177e4 | 436 | need = nextneed; |
1477b8e5 | 437 | pages += iommu_num_pages(s->offset, s->length, PAGE_SIZE); |
9ee1bea4 | 438 | ps = s; |
1da177e4 | 439 | } |
fde9a109 | 440 | if (dma_map_cont(dev, start_sg, i - start, sgmap, pages, need) < 0) |
1da177e4 LT |
441 | goto error; |
442 | out++; | |
a32073bf | 443 | flush_gart(); |
9ee1bea4 JA |
444 | if (out < nents) { |
445 | sgmap = sg_next(sgmap); | |
446 | sgmap->dma_length = 0; | |
447 | } | |
1da177e4 LT |
448 | return out; |
449 | ||
450 | error: | |
a32073bf | 451 | flush_gart(); |
160c1d8e | 452 | gart_unmap_sg(dev, sg, out, dir, NULL); |
05fccb0e | 453 | |
a1002a48 KV |
454 | /* When it was forced or merged try again in a dumb way */ |
455 | if (force_iommu || iommu_merge) { | |
456 | out = dma_map_sg_nonforce(dev, sg, nents, dir); | |
457 | if (out > 0) | |
458 | return out; | |
459 | } | |
1da177e4 LT |
460 | if (panic_on_overflow) |
461 | panic("dma_map_sg: overflow on %lu pages\n", pages); | |
05fccb0e | 462 | |
17a941d8 | 463 | iommu_full(dev, pages << PAGE_SHIFT, dir); |
9ee1bea4 | 464 | for_each_sg(sg, s, nents, i) |
42109197 | 465 | s->dma_address = bad_dma_addr; |
1da177e4 | 466 | return 0; |
05fccb0e | 467 | } |
1da177e4 | 468 | |
94581094 JR |
469 | /* allocate and map a coherent mapping */ |
470 | static void * | |
471 | gart_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_addr, | |
472 | gfp_t flag) | |
473 | { | |
f6a32a36 | 474 | dma_addr_t paddr; |
421076e2 | 475 | unsigned long align_mask; |
1d990882 FT |
476 | struct page *page; |
477 | ||
478 | if (force_iommu && !(flag & GFP_DMA)) { | |
479 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
480 | page = alloc_pages(flag | __GFP_ZERO, get_order(size)); | |
481 | if (!page) | |
482 | return NULL; | |
483 | ||
484 | align_mask = (1UL << get_order(size)) - 1; | |
485 | paddr = dma_map_area(dev, page_to_phys(page), size, | |
486 | DMA_BIDIRECTIONAL, align_mask); | |
487 | ||
488 | flush_gart(); | |
42109197 | 489 | if (paddr != bad_dma_addr) { |
1d990882 FT |
490 | *dma_addr = paddr; |
491 | return page_address(page); | |
492 | } | |
493 | __free_pages(page, get_order(size)); | |
494 | } else | |
495 | return dma_generic_alloc_coherent(dev, size, dma_addr, flag); | |
94581094 JR |
496 | |
497 | return NULL; | |
498 | } | |
499 | ||
43a5a5a0 JR |
500 | /* free a coherent mapping */ |
501 | static void | |
502 | gart_free_coherent(struct device *dev, size_t size, void *vaddr, | |
503 | dma_addr_t dma_addr) | |
504 | { | |
d7dff840 | 505 | gart_unmap_page(dev, dma_addr, size, DMA_BIDIRECTIONAL, NULL); |
43a5a5a0 JR |
506 | free_pages((unsigned long)vaddr, get_order(size)); |
507 | } | |
508 | ||
42109197 FT |
509 | static int gart_mapping_error(struct device *dev, dma_addr_t dma_addr) |
510 | { | |
511 | return (dma_addr == bad_dma_addr); | |
512 | } | |
513 | ||
17a941d8 | 514 | static int no_agp; |
1da177e4 LT |
515 | |
516 | static __init unsigned long check_iommu_size(unsigned long aper, u64 aper_size) | |
05fccb0e IM |
517 | { |
518 | unsigned long a; | |
519 | ||
520 | if (!iommu_size) { | |
521 | iommu_size = aper_size; | |
522 | if (!no_agp) | |
523 | iommu_size /= 2; | |
524 | } | |
525 | ||
526 | a = aper + iommu_size; | |
31422c51 | 527 | iommu_size -= round_up(a, PMD_PAGE_SIZE) - a; |
1da177e4 | 528 | |
05fccb0e | 529 | if (iommu_size < 64*1024*1024) { |
123bf0e2 | 530 | pr_warning( |
05fccb0e IM |
531 | "PCI-DMA: Warning: Small IOMMU %luMB." |
532 | " Consider increasing the AGP aperture in BIOS\n", | |
533 | iommu_size >> 20); | |
534 | } | |
535 | ||
1da177e4 | 536 | return iommu_size; |
05fccb0e | 537 | } |
1da177e4 | 538 | |
05fccb0e IM |
539 | static __init unsigned read_aperture(struct pci_dev *dev, u32 *size) |
540 | { | |
541 | unsigned aper_size = 0, aper_base_32, aper_order; | |
1da177e4 | 542 | u64 aper_base; |
1da177e4 | 543 | |
3bb6fbf9 PM |
544 | pci_read_config_dword(dev, AMD64_GARTAPERTUREBASE, &aper_base_32); |
545 | pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &aper_order); | |
05fccb0e | 546 | aper_order = (aper_order >> 1) & 7; |
1da177e4 | 547 | |
05fccb0e | 548 | aper_base = aper_base_32 & 0x7fff; |
1da177e4 LT |
549 | aper_base <<= 25; |
550 | ||
05fccb0e IM |
551 | aper_size = (32 * 1024 * 1024) << aper_order; |
552 | if (aper_base + aper_size > 0x100000000UL || !aper_size) | |
1da177e4 LT |
553 | aper_base = 0; |
554 | ||
555 | *size = aper_size; | |
556 | return aper_base; | |
05fccb0e | 557 | } |
1da177e4 | 558 | |
6703f6d1 RW |
559 | static void enable_gart_translations(void) |
560 | { | |
561 | int i; | |
562 | ||
563 | for (i = 0; i < num_k8_northbridges; i++) { | |
564 | struct pci_dev *dev = k8_northbridges[i]; | |
565 | ||
566 | enable_gart_translation(dev, __pa(agp_gatt_table)); | |
567 | } | |
568 | } | |
569 | ||
570 | /* | |
571 | * If fix_up_north_bridges is set, the north bridges have to be fixed up on | |
572 | * resume in the same way as they are handled in gart_iommu_hole_init(). | |
573 | */ | |
574 | static bool fix_up_north_bridges; | |
575 | static u32 aperture_order; | |
576 | static u32 aperture_alloc; | |
577 | ||
578 | void set_up_gart_resume(u32 aper_order, u32 aper_alloc) | |
579 | { | |
580 | fix_up_north_bridges = true; | |
581 | aperture_order = aper_order; | |
582 | aperture_alloc = aper_alloc; | |
583 | } | |
584 | ||
123bf0e2 | 585 | static void gart_fixup_northbridges(struct sys_device *dev) |
cd76374e | 586 | { |
123bf0e2 | 587 | int i; |
6703f6d1 | 588 | |
123bf0e2 IM |
589 | if (!fix_up_north_bridges) |
590 | return; | |
6703f6d1 | 591 | |
123bf0e2 | 592 | pr_info("PCI-DMA: Restoring GART aperture settings\n"); |
6703f6d1 | 593 | |
123bf0e2 IM |
594 | for (i = 0; i < num_k8_northbridges; i++) { |
595 | struct pci_dev *dev = k8_northbridges[i]; | |
6703f6d1 | 596 | |
123bf0e2 IM |
597 | /* |
598 | * Don't enable translations just yet. That is the next | |
599 | * step. Restore the pre-suspend aperture settings. | |
600 | */ | |
601 | pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, aperture_order << 1); | |
602 | pci_write_config_dword(dev, AMD64_GARTAPERTUREBASE, aperture_alloc >> 25); | |
6703f6d1 | 603 | } |
123bf0e2 IM |
604 | } |
605 | ||
606 | static int gart_resume(struct sys_device *dev) | |
607 | { | |
608 | pr_info("PCI-DMA: Resuming GART IOMMU\n"); | |
609 | ||
610 | gart_fixup_northbridges(dev); | |
6703f6d1 RW |
611 | |
612 | enable_gart_translations(); | |
613 | ||
cd76374e PM |
614 | return 0; |
615 | } | |
616 | ||
617 | static int gart_suspend(struct sys_device *dev, pm_message_t state) | |
618 | { | |
6703f6d1 | 619 | return 0; |
cd76374e PM |
620 | } |
621 | ||
622 | static struct sysdev_class gart_sysdev_class = { | |
123bf0e2 IM |
623 | .name = "gart", |
624 | .suspend = gart_suspend, | |
625 | .resume = gart_resume, | |
cd76374e PM |
626 | |
627 | }; | |
628 | ||
629 | static struct sys_device device_gart = { | |
123bf0e2 | 630 | .cls = &gart_sysdev_class, |
cd76374e PM |
631 | }; |
632 | ||
05fccb0e | 633 | /* |
1da177e4 | 634 | * Private Northbridge GATT initialization in case we cannot use the |
05fccb0e | 635 | * AGP driver for some reason. |
1da177e4 LT |
636 | */ |
637 | static __init int init_k8_gatt(struct agp_kern_info *info) | |
05fccb0e IM |
638 | { |
639 | unsigned aper_size, gatt_size, new_aper_size; | |
640 | unsigned aper_base, new_aper_base; | |
1da177e4 LT |
641 | struct pci_dev *dev; |
642 | void *gatt; | |
cd76374e | 643 | int i, error; |
a32073bf | 644 | |
123bf0e2 IM |
645 | pr_info("PCI-DMA: Disabling AGP.\n"); |
646 | ||
1da177e4 | 647 | aper_size = aper_base = info->aper_size = 0; |
a32073bf AK |
648 | dev = NULL; |
649 | for (i = 0; i < num_k8_northbridges; i++) { | |
650 | dev = k8_northbridges[i]; | |
05fccb0e IM |
651 | new_aper_base = read_aperture(dev, &new_aper_size); |
652 | if (!new_aper_base) | |
653 | goto nommu; | |
654 | ||
655 | if (!aper_base) { | |
1da177e4 LT |
656 | aper_size = new_aper_size; |
657 | aper_base = new_aper_base; | |
05fccb0e IM |
658 | } |
659 | if (aper_size != new_aper_size || aper_base != new_aper_base) | |
1da177e4 LT |
660 | goto nommu; |
661 | } | |
662 | if (!aper_base) | |
05fccb0e | 663 | goto nommu; |
123bf0e2 | 664 | |
1da177e4 | 665 | info->aper_base = aper_base; |
05fccb0e | 666 | info->aper_size = aper_size >> 20; |
1da177e4 | 667 | |
05fccb0e | 668 | gatt_size = (aper_size >> PAGE_SHIFT) * sizeof(u32); |
0114267b JR |
669 | gatt = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
670 | get_order(gatt_size)); | |
05fccb0e | 671 | if (!gatt) |
cf6387da | 672 | panic("Cannot allocate GATT table"); |
6d238cc4 | 673 | if (set_memory_uc((unsigned long)gatt, gatt_size >> PAGE_SHIFT)) |
cf6387da | 674 | panic("Could not set GART PTEs to uncacheable pages"); |
cf6387da | 675 | |
1da177e4 | 676 | agp_gatt_table = gatt; |
a32073bf | 677 | |
cd76374e PM |
678 | error = sysdev_class_register(&gart_sysdev_class); |
679 | if (!error) | |
680 | error = sysdev_register(&device_gart); | |
681 | if (error) | |
237a6224 JR |
682 | panic("Could not register gart_sysdev -- " |
683 | "would corrupt data on next suspend"); | |
6703f6d1 | 684 | |
a32073bf | 685 | flush_gart(); |
05fccb0e | 686 | |
123bf0e2 | 687 | pr_info("PCI-DMA: aperture base @ %x size %u KB\n", |
05fccb0e | 688 | aper_base, aper_size>>10); |
7ab073b6 | 689 | |
1da177e4 LT |
690 | return 0; |
691 | ||
692 | nommu: | |
05fccb0e | 693 | /* Should not happen anymore */ |
123bf0e2 | 694 | pr_warning("PCI-DMA: More than 4GB of RAM and no IOMMU\n" |
ad361c98 | 695 | "falling back to iommu=soft.\n"); |
05fccb0e IM |
696 | return -1; |
697 | } | |
1da177e4 | 698 | |
160c1d8e | 699 | static struct dma_map_ops gart_dma_ops = { |
05fccb0e IM |
700 | .map_sg = gart_map_sg, |
701 | .unmap_sg = gart_unmap_sg, | |
052aedbf FT |
702 | .map_page = gart_map_page, |
703 | .unmap_page = gart_unmap_page, | |
94581094 | 704 | .alloc_coherent = gart_alloc_coherent, |
43a5a5a0 | 705 | .free_coherent = gart_free_coherent, |
42109197 | 706 | .mapping_error = gart_mapping_error, |
17a941d8 MBY |
707 | }; |
708 | ||
338bac52 | 709 | static void gart_iommu_shutdown(void) |
bc2cea6a YL |
710 | { |
711 | struct pci_dev *dev; | |
712 | int i; | |
713 | ||
f3eee542 YL |
714 | /* don't shutdown it if there is AGP installed */ |
715 | if (!no_agp) | |
bc2cea6a YL |
716 | return; |
717 | ||
05fccb0e IM |
718 | for (i = 0; i < num_k8_northbridges; i++) { |
719 | u32 ctl; | |
bc2cea6a | 720 | |
05fccb0e | 721 | dev = k8_northbridges[i]; |
3bb6fbf9 | 722 | pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl); |
bc2cea6a | 723 | |
3bb6fbf9 | 724 | ctl &= ~GARTEN; |
bc2cea6a | 725 | |
3bb6fbf9 | 726 | pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl); |
05fccb0e | 727 | } |
bc2cea6a YL |
728 | } |
729 | ||
de957628 | 730 | int __init gart_iommu_init(void) |
05fccb0e | 731 | { |
1da177e4 | 732 | struct agp_kern_info info; |
1da177e4 | 733 | unsigned long iommu_start; |
d99e9016 YL |
734 | unsigned long aper_base, aper_size; |
735 | unsigned long start_pfn, end_pfn; | |
1da177e4 LT |
736 | unsigned long scratch; |
737 | long i; | |
738 | ||
0e152cd7 | 739 | if (num_k8_northbridges == 0) |
de957628 | 740 | return 0; |
a32073bf | 741 | |
1da177e4 | 742 | #ifndef CONFIG_AGP_AMD64 |
05fccb0e | 743 | no_agp = 1; |
1da177e4 LT |
744 | #else |
745 | /* Makefile puts PCI initialization via subsys_initcall first. */ | |
746 | /* Add other K8 AGP bridge drivers here */ | |
05fccb0e IM |
747 | no_agp = no_agp || |
748 | (agp_amd64_init() < 0) || | |
1da177e4 | 749 | (agp_copy_info(agp_bridge, &info) < 0); |
05fccb0e | 750 | #endif |
1da177e4 | 751 | |
1da177e4 | 752 | if (no_iommu || |
c987d12f | 753 | (!force_iommu && max_pfn <= MAX_DMA32_PFN) || |
0440d4c0 | 754 | !gart_iommu_aperture || |
1da177e4 | 755 | (no_agp && init_k8_gatt(&info) < 0)) { |
c987d12f | 756 | if (max_pfn > MAX_DMA32_PFN) { |
123bf0e2 IM |
757 | pr_warning("More than 4GB of memory but GART IOMMU not available.\n"); |
758 | pr_warning("falling back to iommu=soft.\n"); | |
5b7b644c | 759 | } |
de957628 | 760 | return 0; |
1da177e4 LT |
761 | } |
762 | ||
d99e9016 | 763 | /* need to map that range */ |
123bf0e2 IM |
764 | aper_size = info.aper_size << 20; |
765 | aper_base = info.aper_base; | |
766 | end_pfn = (aper_base>>PAGE_SHIFT) + (aper_size>>PAGE_SHIFT); | |
767 | ||
d99e9016 YL |
768 | if (end_pfn > max_low_pfn_mapped) { |
769 | start_pfn = (aper_base>>PAGE_SHIFT); | |
770 | init_memory_mapping(start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT); | |
771 | } | |
772 | ||
123bf0e2 | 773 | pr_info("PCI-DMA: using GART IOMMU.\n"); |
05fccb0e IM |
774 | iommu_size = check_iommu_size(info.aper_base, aper_size); |
775 | iommu_pages = iommu_size >> PAGE_SHIFT; | |
776 | ||
0114267b | 777 | iommu_gart_bitmap = (void *) __get_free_pages(GFP_KERNEL | __GFP_ZERO, |
05fccb0e IM |
778 | get_order(iommu_pages/8)); |
779 | if (!iommu_gart_bitmap) | |
780 | panic("Cannot allocate iommu bitmap\n"); | |
1da177e4 LT |
781 | |
782 | #ifdef CONFIG_IOMMU_LEAK | |
05fccb0e | 783 | if (leak_trace) { |
19c1a6f5 FT |
784 | int ret; |
785 | ||
786 | ret = dma_debug_resize_entries(iommu_pages); | |
787 | if (ret) | |
123bf0e2 | 788 | pr_debug("PCI-DMA: Cannot trace all the entries\n"); |
05fccb0e | 789 | } |
1da177e4 LT |
790 | #endif |
791 | ||
05fccb0e | 792 | /* |
1da177e4 | 793 | * Out of IOMMU space handling. |
05fccb0e IM |
794 | * Reserve some invalid pages at the beginning of the GART. |
795 | */ | |
a66022c4 | 796 | bitmap_set(iommu_gart_bitmap, 0, EMERGENCY_PAGES); |
1da177e4 | 797 | |
123bf0e2 | 798 | pr_info("PCI-DMA: Reserving %luMB of IOMMU area in the AGP aperture\n", |
05fccb0e | 799 | iommu_size >> 20); |
1da177e4 | 800 | |
123bf0e2 IM |
801 | agp_memory_reserved = iommu_size; |
802 | iommu_start = aper_size - iommu_size; | |
803 | iommu_bus_base = info.aper_base + iommu_start; | |
804 | bad_dma_addr = iommu_bus_base; | |
805 | iommu_gatt_base = agp_gatt_table + (iommu_start>>PAGE_SHIFT); | |
1da177e4 | 806 | |
05fccb0e | 807 | /* |
1da177e4 LT |
808 | * Unmap the IOMMU part of the GART. The alias of the page is |
809 | * always mapped with cache enabled and there is no full cache | |
810 | * coherency across the GART remapping. The unmapping avoids | |
811 | * automatic prefetches from the CPU allocating cache lines in | |
812 | * there. All CPU accesses are done via the direct mapping to | |
813 | * the backing memory. The GART address is only used by PCI | |
05fccb0e | 814 | * devices. |
1da177e4 | 815 | */ |
28d6ee41 AK |
816 | set_memory_np((unsigned long)__va(iommu_bus_base), |
817 | iommu_size >> PAGE_SHIFT); | |
184652eb IM |
818 | /* |
819 | * Tricky. The GART table remaps the physical memory range, | |
820 | * so the CPU wont notice potential aliases and if the memory | |
821 | * is remapped to UC later on, we might surprise the PCI devices | |
822 | * with a stray writeout of a cacheline. So play it sure and | |
823 | * do an explicit, full-scale wbinvd() _after_ having marked all | |
824 | * the pages as Not-Present: | |
825 | */ | |
826 | wbinvd(); | |
123bf0e2 | 827 | |
fe2245c9 ML |
828 | /* |
829 | * Now all caches are flushed and we can safely enable | |
830 | * GART hardware. Doing it early leaves the possibility | |
831 | * of stale cache entries that can lead to GART PTE | |
832 | * errors. | |
833 | */ | |
834 | enable_gart_translations(); | |
1da177e4 | 835 | |
05fccb0e | 836 | /* |
fa3d319a | 837 | * Try to workaround a bug (thanks to BenH): |
05fccb0e | 838 | * Set unmapped entries to a scratch page instead of 0. |
1da177e4 | 839 | * Any prefetches that hit unmapped entries won't get an bus abort |
fa3d319a | 840 | * then. (P2P bridge may be prefetching on DMA reads). |
1da177e4 | 841 | */ |
05fccb0e IM |
842 | scratch = get_zeroed_page(GFP_KERNEL); |
843 | if (!scratch) | |
1da177e4 LT |
844 | panic("Cannot allocate iommu scratch page"); |
845 | gart_unmapped_entry = GPTE_ENCODE(__pa(scratch)); | |
05fccb0e | 846 | for (i = EMERGENCY_PAGES; i < iommu_pages; i++) |
1da177e4 LT |
847 | iommu_gatt_base[i] = gart_unmapped_entry; |
848 | ||
a32073bf | 849 | flush_gart(); |
17a941d8 | 850 | dma_ops = &gart_dma_ops; |
338bac52 | 851 | x86_platform.iommu_shutdown = gart_iommu_shutdown; |
75f1cdf1 | 852 | swiotlb = 0; |
de957628 FT |
853 | |
854 | return 0; | |
05fccb0e | 855 | } |
1da177e4 | 856 | |
43999d9e | 857 | void __init gart_parse_options(char *p) |
17a941d8 MBY |
858 | { |
859 | int arg; | |
860 | ||
1da177e4 | 861 | #ifdef CONFIG_IOMMU_LEAK |
05fccb0e | 862 | if (!strncmp(p, "leak", 4)) { |
17a941d8 MBY |
863 | leak_trace = 1; |
864 | p += 4; | |
237a6224 JR |
865 | if (*p == '=') |
866 | ++p; | |
17a941d8 MBY |
867 | if (isdigit(*p) && get_option(&p, &arg)) |
868 | iommu_leak_pages = arg; | |
869 | } | |
1da177e4 | 870 | #endif |
17a941d8 MBY |
871 | if (isdigit(*p) && get_option(&p, &arg)) |
872 | iommu_size = arg; | |
41855b77 | 873 | if (!strncmp(p, "fullflush", 9)) |
17a941d8 | 874 | iommu_fullflush = 1; |
05fccb0e | 875 | if (!strncmp(p, "nofullflush", 11)) |
17a941d8 | 876 | iommu_fullflush = 0; |
05fccb0e | 877 | if (!strncmp(p, "noagp", 5)) |
17a941d8 | 878 | no_agp = 1; |
05fccb0e | 879 | if (!strncmp(p, "noaperture", 10)) |
17a941d8 MBY |
880 | fix_aperture = 0; |
881 | /* duplicated from pci-dma.c */ | |
05fccb0e | 882 | if (!strncmp(p, "force", 5)) |
0440d4c0 | 883 | gart_iommu_aperture_allowed = 1; |
05fccb0e | 884 | if (!strncmp(p, "allowed", 7)) |
0440d4c0 | 885 | gart_iommu_aperture_allowed = 1; |
17a941d8 MBY |
886 | if (!strncmp(p, "memaper", 7)) { |
887 | fallback_aper_force = 1; | |
888 | p += 7; | |
889 | if (*p == '=') { | |
890 | ++p; | |
891 | if (get_option(&p, &arg)) | |
892 | fallback_aper_order = arg; | |
893 | } | |
894 | } | |
895 | } |