[linux-block.git] / arch / x86 / kernel / pci-dma.c

#include <linux/dma-mapping.h>
#include <linux/dma-debug.h>
#include <linux/dmar.h>
#include <linux/bootmem.h>
#include <linux/pci.h>

#include <asm/proto.h>
#include <asm/dma.h>
#include <asm/iommu.h>
#include <asm/gart.h>
#include <asm/calgary.h>
#include <asm/amd_iommu.h>

static int forbid_dac __read_mostly;

struct dma_map_ops *dma_ops;
EXPORT_SYMBOL(dma_ops);

static int iommu_sac_force __read_mostly;

#ifdef CONFIG_IOMMU_DEBUG
int panic_on_overflow __read_mostly = 1;
int force_iommu __read_mostly = 1;
#else
int panic_on_overflow __read_mostly = 0;
int force_iommu __read_mostly = 0;
#endif

int iommu_merge __read_mostly = 0;

int no_iommu __read_mostly;
/* Set this to 1 if there is a HW IOMMU in the system */
int iommu_detected __read_mostly = 0;

dma_addr_t bad_dma_address __read_mostly = 0;
EXPORT_SYMBOL(bad_dma_address);

/* Dummy device used for NULL arguments (normally ISA). Better would
   be probably a smaller DMA mask, but this is bug-to-bug compatible
   to older i386. */
struct device x86_dma_fallback_dev = {
	.init_name = "fallback device",
	.coherent_dma_mask = DMA_BIT_MASK(32),
	.dma_mask = &x86_dma_fallback_dev.coherent_dma_mask,
};
EXPORT_SYMBOL(x86_dma_fallback_dev);

/* Number of entries preallocated for DMA-API debugging */
#define PREALLOC_DMA_DEBUG_ENTRIES       32768

int dma_set_mask(struct device *dev, u64 mask)
{
	if (!dev->dma_mask || !dma_supported(dev, mask))
		return -EIO;

	*dev->dma_mask = mask;

	return 0;
}
EXPORT_SYMBOL(dma_set_mask);

#ifdef CONFIG_X86_64
static __initdata void *dma32_bootmem_ptr;
static unsigned long dma32_bootmem_size __initdata = (128ULL<<20);

static int __init parse_dma32_size_opt(char *p)
{
	if (!p)
		return -EINVAL;
	dma32_bootmem_size = memparse(p, &p);
	return 0;
}
early_param("dma32_size", parse_dma32_size_opt);

void __init dma32_reserve_bootmem(void)
{
	unsigned long size, align;
	if (max_pfn <= MAX_DMA32_PFN)
		return;

	/*
	 * check aperture_64.c allocate_aperture() for reason about
	 * using 512M as goal
	 */
	align = 64ULL<<20;
	size = roundup(dma32_bootmem_size, align);
	dma32_bootmem_ptr = __alloc_bootmem_nopanic(size, align,
				 512ULL<<20);
	if (dma32_bootmem_ptr)
		dma32_bootmem_size = size;
	else
		dma32_bootmem_size = 0;
}
static void __init dma32_free_bootmem(void)
{

	if (max_pfn <= MAX_DMA32_PFN)
		return;

	if (!dma32_bootmem_ptr)
		return;

	free_bootmem(__pa(dma32_bootmem_ptr), dma32_bootmem_size);

	dma32_bootmem_ptr = NULL;
	dma32_bootmem_size = 0;
}
#endif

void __init pci_iommu_alloc(void)
{
#ifdef CONFIG_X86_64
	/* free the range so iommu could get some range less than 4G */
	dma32_free_bootmem();
#endif

	/*
	 * The order of these functions is important for
	 * fall-back/fail-over reasons
	 */
	gart_iommu_hole_init();

	detect_calgary();

	detect_intel_iommu();

	amd_iommu_detect();

	pci_swiotlb_init();
}

void *dma_generic_alloc_coherent(struct device *dev, size_t size,
				 dma_addr_t *dma_addr, gfp_t flag)
{
	unsigned long dma_mask;
	struct page *page;
	dma_addr_t addr;

	dma_mask = dma_alloc_coherent_mask(dev, flag);

	flag |= __GFP_ZERO;
again:
	page = alloc_pages_node(dev_to_node(dev), flag, get_order(size));
	if (!page)
		return NULL;

	addr = page_to_phys(page);
	if (!is_buffer_dma_capable(dma_mask, addr, size)) {
		__free_pages(page, get_order(size));

		if (dma_mask < DMA_BIT_MASK(32) && !(flag & GFP_DMA)) {
			flag = (flag & ~GFP_DMA32) | GFP_DMA;
			goto again;
		}

		return NULL;
	}

	*dma_addr = addr;
	return page_address(page);
}

extern int iommu_pass_through;

/*
 * See <Documentation/x86_64/boot-options.txt> for the iommu kernel parameter
 * documentation.
 */
static __init int iommu_setup(char *p)
{
	iommu_merge = 1;

	if (!p)
		return -EINVAL;

	while (*p) {
		if (!strncmp(p, "off", 3))
			no_iommu = 1;
		/* gart_parse_options has more force support */
		if (!strncmp(p, "force", 5))
			force_iommu = 1;
		if (!strncmp(p, "noforce", 7)) {
			iommu_merge = 0;
			force_iommu = 0;
		}

		if (!strncmp(p, "biomerge", 8)) {
			iommu_merge = 1;
			force_iommu = 1;
		}
		if (!strncmp(p, "panic", 5))
			panic_on_overflow = 1;
		if (!strncmp(p, "nopanic", 7))
			panic_on_overflow = 0;
		if (!strncmp(p, "merge", 5)) {
			iommu_merge = 1;
			force_iommu = 1;
		}
		if (!strncmp(p, "nomerge", 7))
			iommu_merge = 0;
		if (!strncmp(p, "forcesac", 8))
			iommu_sac_force = 1;
		if (!strncmp(p, "allowdac", 8))
			forbid_dac = 0;
		if (!strncmp(p, "nodac", 5))
			forbid_dac = -1;
		if (!strncmp(p, "usedac", 6)) {
			forbid_dac = -1;
			return 1;
		}
#ifdef CONFIG_SWIOTLB
		if (!strncmp(p, "soft", 4))
			swiotlb = 1;
		if (!strncmp(p, "pt", 2)) {
			iommu_pass_through = 1;
			return 1;
		}
#endif

		gart_parse_options(p);

#ifdef CONFIG_CALGARY_IOMMU
		if (!strncmp(p, "calgary", 7))
			use_calgary = 1;
#endif /* CONFIG_CALGARY_IOMMU */

		p += strcspn(p, ",");
		if (*p == ',')
			++p;
	}
	return 0;
}
early_param("iommu", iommu_setup);

int dma_supported(struct device *dev, u64 mask)
{
	struct dma_map_ops *ops = get_dma_ops(dev);

#ifdef CONFIG_PCI
	if (mask > 0xffffffff && forbid_dac > 0) {
		dev_info(dev, "PCI: Disallowing DAC for device\n");
		return 0;
	}
#endif

	if (ops->dma_supported)
		return ops->dma_supported(dev, mask);

	/* Copied from i386. Doesn't make much sense, because it will
	   only work for pci_alloc_coherent.
	   The caller just has to use GFP_DMA in this case. */
	if (mask < DMA_BIT_MASK(24))
		return 0;

	/* Tell the device to use SAC when IOMMU force is on.  This
	   allows the driver to use cheaper accesses in some cases.

	   Problem with this is that if we overflow the IOMMU area and
	   return DAC as fallback address the device may not handle it
	   correctly.

	   As a special case some controllers have a 39bit address
	   mode that is as efficient as 32bit (aic79xx). Don't force
	   SAC for these.  Assume all masks <= 40 bits are of this
	   type. Normally this doesn't make any difference, but gives
	   more gentle handling of IOMMU overflow. */
	if (iommu_sac_force && (mask >= DMA_BIT_MASK(40))) {
		dev_info(dev, "Force SAC with mask %Lx\n", mask);
		return 0;
	}

	return 1;
}
EXPORT_SYMBOL(dma_supported);

static int __init pci_iommu_init(void)
{
	dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);

#ifdef CONFIG_PCI
	dma_debug_add_bus(&pci_bus_type);
#endif

	calgary_iommu_init();

	intel_iommu_init();

	amd_iommu_init();

	gart_iommu_init();

	no_iommu_init();
	return 0;
}

void pci_iommu_shutdown(void)
{
	gart_iommu_shutdown();
}
/* Must execute after PCI subsystem */
fs_initcall(pci_iommu_init);

#ifdef CONFIG_PCI
/* Many VIA bridges seem to corrupt data for DAC. Disable it here */

static __devinit void via_no_dac(struct pci_dev *dev)
{
	if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI && forbid_dac == 0) {
		dev_info(&dev->dev, "disabling DAC on VIA PCI bridge\n");
		forbid_dac = 1;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_ANY_ID, via_no_dac);
#endif
Commit	Line	Data
459121c9	1	#include <linux/dma-mapping.h>
2118d0c5	2	#include <linux/dma-debug.h>
cb5867a5	3	#include <linux/dmar.h>
116890d5	4	#include <linux/bootmem.h>
bca5c096	5	#include <linux/pci.h>
cb5867a5	6
116890d5 GC	7	#include <asm/proto.h>
116890d5 GC	8	#include <asm/dma.h>
46a7fa27	9	#include <asm/iommu.h>
1d9b16d1	10	#include <asm/gart.h>
cb5867a5	11	#include <asm/calgary.h>
a69ca340	12	#include <asm/amd_iommu.h>
459121c9	13
3b15e581 FY	14	static int forbid_dac __read_mostly;
3b15e581 FY	15
160c1d8e	16	struct dma_map_ops *dma_ops;
85c246ee GC	17	EXPORT_SYMBOL(dma_ops);
85c246ee GC	18
b4cdc430	19	static int iommu_sac_force __read_mostly;
8e0c3797	20
f9c258de GC	21	#ifdef CONFIG_IOMMU_DEBUG
	22	int panic_on_overflow __read_mostly = 1;
	23	int force_iommu __read_mostly = 1;
	24	#else
	25	int panic_on_overflow __read_mostly = 0;
	26	int force_iommu __read_mostly = 0;
	27	#endif
	28
fae9a0d8 GC	29	int iommu_merge __read_mostly = 0;
	30
	31	int no_iommu __read_mostly;
	32	/* Set this to 1 if there is a HW IOMMU in the system */
	33	int iommu_detected __read_mostly = 0;
	34
cac67877 GC	35	dma_addr_t bad_dma_address __read_mostly = 0;
cac67877 GC	36	EXPORT_SYMBOL(bad_dma_address);
fae9a0d8	37
098cb7f2 GC	38	/* Dummy device used for NULL arguments (normally ISA). Better would
	39	be probably a smaller DMA mask, but this is bug-to-bug compatible
	40	to older i386. */
6c505ce3	41	struct device x86_dma_fallback_dev = {
1a927133	42	.init_name = "fallback device",
284901a9	43	.coherent_dma_mask = DMA_BIT_MASK(32),
6c505ce3	44	.dma_mask = &x86_dma_fallback_dev.coherent_dma_mask,
098cb7f2	45	};
6c505ce3	46	EXPORT_SYMBOL(x86_dma_fallback_dev);
098cb7f2	47
2118d0c5 JR	48	/* Number of entries preallocated for DMA-API debugging */
	49	#define PREALLOC_DMA_DEBUG_ENTRIES 32768
	50
459121c9 GC	51	int dma_set_mask(struct device *dev, u64 mask)
	52	{
	53	if (!dev->dma_mask \|\| !dma_supported(dev, mask))
	54	return -EIO;
	55
	56	*dev->dma_mask = mask;
	57
	58	return 0;
	59	}
	60	EXPORT_SYMBOL(dma_set_mask);
	61
116890d5 GC	62	#ifdef CONFIG_X86_64
	63	static __initdata void *dma32_bootmem_ptr;
	64	static unsigned long dma32_bootmem_size __initdata = (128ULL<<20);
	65
	66	static int __init parse_dma32_size_opt(char *p)
	67	{
	68	if (!p)
	69	return -EINVAL;
	70	dma32_bootmem_size = memparse(p, &p);
	71	return 0;
	72	}
	73	early_param("dma32_size", parse_dma32_size_opt);
	74
	75	void __init dma32_reserve_bootmem(void)
	76	{
	77	unsigned long size, align;
c987d12f	78	if (max_pfn <= MAX_DMA32_PFN)
116890d5 GC	79	return;
116890d5 GC	80
7677b2ef YL	81	/*
	82	* check aperture_64.c allocate_aperture() for reason about
	83	* using 512M as goal
	84	*/
116890d5	85	align = 64ULL<<20;
1ddb5518	86	size = roundup(dma32_bootmem_size, align);
116890d5	87	dma32_bootmem_ptr = __alloc_bootmem_nopanic(size, align,
7677b2ef	88	512ULL<<20);
116890d5 GC	89	if (dma32_bootmem_ptr)
	90	dma32_bootmem_size = size;
	91	else
	92	dma32_bootmem_size = 0;
	93	}
	94	static void __init dma32_free_bootmem(void)
	95	{
116890d5	96
c987d12f	97	if (max_pfn <= MAX_DMA32_PFN)
116890d5 GC	98	return;
	99
	100	if (!dma32_bootmem_ptr)
	101	return;
	102
330fce23	103	free_bootmem(__pa(dma32_bootmem_ptr), dma32_bootmem_size);
116890d5 GC	104
	105	dma32_bootmem_ptr = NULL;
	106	dma32_bootmem_size = 0;
	107	}
cfb80c9e	108	#endif
116890d5 GC	109
	110	void __init pci_iommu_alloc(void)
	111	{
cfb80c9e	112	#ifdef CONFIG_X86_64
116890d5 GC	113	/* free the range so iommu could get some range less than 4G */
116890d5 GC	114	dma32_free_bootmem();
cfb80c9e JF	115	#endif
cfb80c9e JF	116
116890d5 GC	117	/*
	118	* The order of these functions is important for
	119	* fall-back/fail-over reasons
	120	*/
116890d5	121	gart_iommu_hole_init();
116890d5	122
116890d5	123	detect_calgary();
116890d5 GC	124
	125	detect_intel_iommu();
	126
a69ca340 JR	127	amd_iommu_detect();
a69ca340 JR	128
116890d5	129	pci_swiotlb_init();
116890d5	130	}
8978b742	131
9f6ac577 FT	132	void dma_generic_alloc_coherent(struct device dev, size_t size,
	133	dma_addr_t *dma_addr, gfp_t flag)
	134	{
	135	unsigned long dma_mask;
	136	struct page *page;
	137	dma_addr_t addr;
	138
	139	dma_mask = dma_alloc_coherent_mask(dev, flag);
	140
	141	flag \|= __GFP_ZERO;
	142	again:
	143	page = alloc_pages_node(dev_to_node(dev), flag, get_order(size));
	144	if (!page)
	145	return NULL;
	146
	147	addr = page_to_phys(page);
	148	if (!is_buffer_dma_capable(dma_mask, addr, size)) {
	149	__free_pages(page, get_order(size));
	150
284901a9	151	if (dma_mask < DMA_BIT_MASK(32) && !(flag & GFP_DMA)) {
9f6ac577 FT	152	flag = (flag & ~GFP_DMA32) \| GFP_DMA;
	153	goto again;
	154	}
	155
	156	return NULL;
	157	}
	158
	159	*dma_addr = addr;
	160	return page_address(page);
	161	}
	162
4ed0d3e6 FY	163	extern int iommu_pass_through;
4ed0d3e6 FY	164
fae9a0d8 GC	165	/*
	166	* See <Documentation/x86_64/boot-options.txt> for the iommu kernel parameter
	167	* documentation.
	168	*/
	169	static __init int iommu_setup(char *p)
	170	{
	171	iommu_merge = 1;
	172
	173	if (!p)
	174	return -EINVAL;
	175
	176	while (*p) {
	177	if (!strncmp(p, "off", 3))
	178	no_iommu = 1;
	179	/* gart_parse_options has more force support */
	180	if (!strncmp(p, "force", 5))
	181	force_iommu = 1;
	182	if (!strncmp(p, "noforce", 7)) {
	183	iommu_merge = 0;
	184	force_iommu = 0;
	185	}
	186
	187	if (!strncmp(p, "biomerge", 8)) {
fae9a0d8 GC	188	iommu_merge = 1;
	189	force_iommu = 1;
	190	}
	191	if (!strncmp(p, "panic", 5))
	192	panic_on_overflow = 1;
	193	if (!strncmp(p, "nopanic", 7))
	194	panic_on_overflow = 0;
	195	if (!strncmp(p, "merge", 5)) {
	196	iommu_merge = 1;
	197	force_iommu = 1;
	198	}
	199	if (!strncmp(p, "nomerge", 7))
	200	iommu_merge = 0;
	201	if (!strncmp(p, "forcesac", 8))
	202	iommu_sac_force = 1;
	203	if (!strncmp(p, "allowdac", 8))
	204	forbid_dac = 0;
	205	if (!strncmp(p, "nodac", 5))
	206	forbid_dac = -1;
	207	if (!strncmp(p, "usedac", 6)) {
	208	forbid_dac = -1;
	209	return 1;
	210	}
	211	#ifdef CONFIG_SWIOTLB
	212	if (!strncmp(p, "soft", 4))
	213	swiotlb = 1;
4ed0d3e6 FY	214	if (!strncmp(p, "pt", 2)) {
	215	iommu_pass_through = 1;
	216	return 1;
	217	}
fae9a0d8 GC	218	#endif
fae9a0d8 GC	219
fae9a0d8	220	gart_parse_options(p);
fae9a0d8 GC	221
	222	#ifdef CONFIG_CALGARY_IOMMU
	223	if (!strncmp(p, "calgary", 7))
	224	use_calgary = 1;
	225	#endif /* CONFIG_CALGARY_IOMMU */
	226
	227	p += strcspn(p, ",");
	228	if (*p == ',')
	229	++p;
	230	}
	231	return 0;
	232	}
	233	early_param("iommu", iommu_setup);
	234
8e0c3797 GC	235	int dma_supported(struct device *dev, u64 mask)
8e0c3797 GC	236	{
160c1d8e	237	struct dma_map_ops *ops = get_dma_ops(dev);
8d8bb39b	238
8e0c3797 GC	239	#ifdef CONFIG_PCI
8e0c3797 GC	240	if (mask > 0xffffffff && forbid_dac > 0) {
fc3a8828	241	dev_info(dev, "PCI: Disallowing DAC for device\n");
8e0c3797 GC	242	return 0;
	243	}
	244	#endif
	245
8d8bb39b FT	246	if (ops->dma_supported)
8d8bb39b FT	247	return ops->dma_supported(dev, mask);
8e0c3797 GC	248
	249	/* Copied from i386. Doesn't make much sense, because it will
	250	only work for pci_alloc_coherent.
	251	The caller just has to use GFP_DMA in this case. */
2f4f27d4	252	if (mask < DMA_BIT_MASK(24))
8e0c3797 GC	253	return 0;
	254
	255	/* Tell the device to use SAC when IOMMU force is on. This
	256	allows the driver to use cheaper accesses in some cases.
	257
	258	Problem with this is that if we overflow the IOMMU area and
	259	return DAC as fallback address the device may not handle it
	260	correctly.
	261
	262	As a special case some controllers have a 39bit address
	263	mode that is as efficient as 32bit (aic79xx). Don't force
	264	SAC for these. Assume all masks <= 40 bits are of this
	265	type. Normally this doesn't make any difference, but gives
	266	more gentle handling of IOMMU overflow. */
50cf156a	267	if (iommu_sac_force && (mask >= DMA_BIT_MASK(40))) {
fc3a8828	268	dev_info(dev, "Force SAC with mask %Lx\n", mask);
8e0c3797 GC	269	return 0;
	270	}
	271
	272	return 1;
	273	}
	274	EXPORT_SYMBOL(dma_supported);
	275
cb5867a5 GC	276	static int __init pci_iommu_init(void)
cb5867a5 GC	277	{
2118d0c5 JR	278	dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
2118d0c5 JR	279
86f31952 JR	280	#ifdef CONFIG_PCI
	281	dma_debug_add_bus(&pci_bus_type);
	282	#endif
	283
cb5867a5	284	calgary_iommu_init();
cb5867a5 GC	285
	286	intel_iommu_init();
	287
a69ca340 JR	288	amd_iommu_init();
a69ca340 JR	289
cb5867a5	290	gart_iommu_init();
459121c9	291
cb5867a5 GC	292	no_iommu_init();
	293	return 0;
	294	}
	295
	296	void pci_iommu_shutdown(void)
	297	{
	298	gart_iommu_shutdown();
	299	}
	300	/* Must execute after PCI subsystem */
	301	fs_initcall(pci_iommu_init);
3b15e581 FY	302
	303	#ifdef CONFIG_PCI
	304	/* Many VIA bridges seem to corrupt data for DAC. Disable it here */
	305
	306	static __devinit void via_no_dac(struct pci_dev *dev)
	307	{
	308	if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI && forbid_dac == 0) {
13bf7576	309	dev_info(&dev->dev, "disabling DAC on VIA PCI bridge\n");
3b15e581 FY	310	forbid_dac = 1;
	311	}
	312	}
	313	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_ANY_ID, via_no_dac);
	314	#endif