x86: add specific support for Intel Atom architecture
[linux-2.6-block.git] / arch / x86 / kernel / paravirt.c
CommitLineData
d3561b7f
RR
1/* Paravirtualization interfaces
2 Copyright (C) 2006 Rusty Russell IBM Corporation
3
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
b1df07bd
GOC
17
18 2007 - x86_64 support added by Glauber de Oliveira Costa, Red Hat Inc
d3561b7f 19*/
b1df07bd 20
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21#include <linux/errno.h>
22#include <linux/module.h>
23#include <linux/efi.h>
24#include <linux/bcd.h>
ce6234b5 25#include <linux/highmem.h>
d3561b7f
RR
26
27#include <asm/bug.h>
28#include <asm/paravirt.h>
29#include <asm/desc.h>
30#include <asm/setup.h>
a312b37b 31#include <asm/pgtable.h>
d3561b7f 32#include <asm/time.h>
eba0045f 33#include <asm/pgalloc.h>
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34#include <asm/irq.h>
35#include <asm/delay.h>
13623d79
RR
36#include <asm/fixmap.h>
37#include <asm/apic.h>
da181a8b 38#include <asm/tlbflush.h>
6cb9a835 39#include <asm/timer.h>
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40
41/* nop stub */
45876233 42void _paravirt_nop(void)
d3561b7f
RR
43{
44}
45
41edafdb
JF
46/* identity function, which can be inlined */
47u32 _paravirt_ident_32(u32 x)
48{
49 return x;
50}
51
52u64 _paravirt_ident_64(u64 x)
53{
54 return x;
55}
56
d3561b7f
RR
57static void __init default_banner(void)
58{
59 printk(KERN_INFO "Booting paravirtualized kernel on %s\n",
93b1eab3 60 pv_info.name);
d3561b7f
RR
61}
62
63char *memory_setup(void)
64{
93b1eab3 65 return pv_init_ops.memory_setup();
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RR
66}
67
139ec7c4 68/* Simple instruction patching code. */
93b1eab3
JF
69#define DEF_NATIVE(ops, name, code) \
70 extern const char start_##ops##_##name[], end_##ops##_##name[]; \
71 asm("start_" #ops "_" #name ": " code "; end_" #ops "_" #name ":")
72
93b1eab3
JF
73/* Undefined instruction for dealing with missing ops pointers. */
74static const unsigned char ud2a[] = { 0x0f, 0x0b };
139ec7c4 75
63f70270
JF
76unsigned paravirt_patch_nop(void)
77{
78 return 0;
79}
80
81unsigned paravirt_patch_ignore(unsigned len)
82{
83 return len;
84}
85
19d36ccd
AK
86struct branch {
87 unsigned char opcode;
88 u32 delta;
89} __attribute__((packed));
90
ab144f5e
AK
91unsigned paravirt_patch_call(void *insnbuf,
92 const void *target, u16 tgt_clobbers,
93 unsigned long addr, u16 site_clobbers,
63f70270
JF
94 unsigned len)
95{
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AK
96 struct branch *b = insnbuf;
97 unsigned long delta = (unsigned long)target - (addr+5);
63f70270
JF
98
99 if (tgt_clobbers & ~site_clobbers)
100 return len; /* target would clobber too much for this site */
101 if (len < 5)
102 return len; /* call too long for patch site */
139ec7c4 103
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AK
104 b->opcode = 0xe8; /* call */
105 b->delta = delta;
106 BUILD_BUG_ON(sizeof(*b) != 5);
139ec7c4 107
63f70270
JF
108 return 5;
109}
110
93b1eab3 111unsigned paravirt_patch_jmp(void *insnbuf, const void *target,
ab144f5e 112 unsigned long addr, unsigned len)
63f70270 113{
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AK
114 struct branch *b = insnbuf;
115 unsigned long delta = (unsigned long)target - (addr+5);
63f70270
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116
117 if (len < 5)
118 return len; /* call too long for patch site */
119
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AK
120 b->opcode = 0xe9; /* jmp */
121 b->delta = delta;
63f70270
JF
122
123 return 5;
124}
125
93b1eab3
JF
126/* Neat trick to map patch type back to the call within the
127 * corresponding structure. */
128static void *get_call_destination(u8 type)
129{
130 struct paravirt_patch_template tmpl = {
131 .pv_init_ops = pv_init_ops,
93b1eab3
JF
132 .pv_time_ops = pv_time_ops,
133 .pv_cpu_ops = pv_cpu_ops,
134 .pv_irq_ops = pv_irq_ops,
135 .pv_apic_ops = pv_apic_ops,
136 .pv_mmu_ops = pv_mmu_ops,
b4ecc126 137#ifdef CONFIG_PARAVIRT_SPINLOCKS
74d4affd 138 .pv_lock_ops = pv_lock_ops,
b4ecc126 139#endif
93b1eab3
JF
140 };
141 return *((void **)&tmpl + type);
142}
143
ab144f5e
AK
144unsigned paravirt_patch_default(u8 type, u16 clobbers, void *insnbuf,
145 unsigned long addr, unsigned len)
63f70270 146{
93b1eab3 147 void *opfunc = get_call_destination(type);
63f70270
JF
148 unsigned ret;
149
150 if (opfunc == NULL)
151 /* If there's no function, patch it with a ud2a (BUG) */
93b1eab3 152 ret = paravirt_patch_insns(insnbuf, len, ud2a, ud2a+sizeof(ud2a));
41edafdb 153 else if (opfunc == _paravirt_nop)
63f70270
JF
154 /* If the operation is a nop, then nop the callsite */
155 ret = paravirt_patch_nop();
41edafdb
JF
156
157 /* identity functions just return their single argument */
158 else if (opfunc == _paravirt_ident_32)
159 ret = paravirt_patch_ident_32(insnbuf, len);
160 else if (opfunc == _paravirt_ident_64)
161 ret = paravirt_patch_ident_64(insnbuf, len);
162
93b1eab3 163 else if (type == PARAVIRT_PATCH(pv_cpu_ops.iret) ||
d75cd22f 164 type == PARAVIRT_PATCH(pv_cpu_ops.irq_enable_sysexit) ||
2be29982
JF
165 type == PARAVIRT_PATCH(pv_cpu_ops.usergs_sysret32) ||
166 type == PARAVIRT_PATCH(pv_cpu_ops.usergs_sysret64))
63f70270 167 /* If operation requires a jmp, then jmp */
93b1eab3 168 ret = paravirt_patch_jmp(insnbuf, opfunc, addr, len);
63f70270
JF
169 else
170 /* Otherwise call the function; assume target could
171 clobber any caller-save reg */
ab144f5e
AK
172 ret = paravirt_patch_call(insnbuf, opfunc, CLBR_ANY,
173 addr, clobbers, len);
63f70270
JF
174
175 return ret;
176}
177
ab144f5e 178unsigned paravirt_patch_insns(void *insnbuf, unsigned len,
63f70270
JF
179 const char *start, const char *end)
180{
181 unsigned insn_len = end - start;
139ec7c4 182
63f70270
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183 if (insn_len > len || start == NULL)
184 insn_len = len;
185 else
ab144f5e 186 memcpy(insnbuf, start, insn_len);
139ec7c4 187
139ec7c4
RR
188 return insn_len;
189}
190
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191void init_IRQ(void)
192{
93b1eab3 193 pv_irq_ops.init_IRQ();
d3561b7f
RR
194}
195
1a1eecd1 196static void native_flush_tlb(void)
da181a8b
RR
197{
198 __native_flush_tlb();
199}
200
201/*
202 * Global pages have to be flushed a bit differently. Not a real
203 * performance problem because this does not happen often.
204 */
1a1eecd1 205static void native_flush_tlb_global(void)
da181a8b
RR
206{
207 __native_flush_tlb_global();
208}
209
63f70270 210static void native_flush_tlb_single(unsigned long addr)
da181a8b
RR
211{
212 __native_flush_tlb_single(addr);
213}
214
d3561b7f 215/* These are in entry.S */
1a1eecd1 216extern void native_iret(void);
d75cd22f 217extern void native_irq_enable_sysexit(void);
2be29982
JF
218extern void native_usergs_sysret32(void);
219extern void native_usergs_sysret64(void);
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220
221static int __init print_banner(void)
222{
93b1eab3 223 pv_init_ops.banner();
d3561b7f
RR
224 return 0;
225}
226core_initcall(print_banner);
227
d572929c
JF
228static struct resource reserve_ioports = {
229 .start = 0,
230 .end = IO_SPACE_LIMIT,
231 .name = "paravirt-ioport",
232 .flags = IORESOURCE_IO | IORESOURCE_BUSY,
233};
234
d572929c
JF
235/*
236 * Reserve the whole legacy IO space to prevent any legacy drivers
237 * from wasting time probing for their hardware. This is a fairly
238 * brute-force approach to disabling all non-virtual drivers.
239 *
240 * Note that this must be called very early to have any effect.
241 */
242int paravirt_disable_iospace(void)
243{
f7743fe6 244 return request_resource(&ioport_resource, &reserve_ioports);
d572929c
JF
245}
246
8965c1c0
JF
247static DEFINE_PER_CPU(enum paravirt_lazy_mode, paravirt_lazy_mode) = PARAVIRT_LAZY_NONE;
248
249static inline void enter_lazy(enum paravirt_lazy_mode mode)
250{
ab2f75f0 251 BUG_ON(percpu_read(paravirt_lazy_mode) != PARAVIRT_LAZY_NONE);
8965c1c0 252
ab2f75f0 253 percpu_write(paravirt_lazy_mode, mode);
8965c1c0
JF
254}
255
b407fc57 256static void leave_lazy(enum paravirt_lazy_mode mode)
8965c1c0 257{
ab2f75f0 258 BUG_ON(percpu_read(paravirt_lazy_mode) != mode);
8965c1c0 259
ab2f75f0 260 percpu_write(paravirt_lazy_mode, PARAVIRT_LAZY_NONE);
8965c1c0
JF
261}
262
263void paravirt_enter_lazy_mmu(void)
264{
265 enter_lazy(PARAVIRT_LAZY_MMU);
266}
267
268void paravirt_leave_lazy_mmu(void)
269{
b407fc57 270 leave_lazy(PARAVIRT_LAZY_MMU);
8965c1c0
JF
271}
272
224101ed 273void paravirt_start_context_switch(struct task_struct *prev)
8965c1c0 274{
2829b449
JF
275 BUG_ON(preemptible());
276
b407fc57
JF
277 if (percpu_read(paravirt_lazy_mode) == PARAVIRT_LAZY_MMU) {
278 arch_leave_lazy_mmu_mode();
224101ed 279 set_ti_thread_flag(task_thread_info(prev), TIF_LAZY_MMU_UPDATES);
b407fc57 280 }
8965c1c0
JF
281 enter_lazy(PARAVIRT_LAZY_CPU);
282}
283
224101ed 284void paravirt_end_context_switch(struct task_struct *next)
8965c1c0 285{
2829b449
JF
286 BUG_ON(preemptible());
287
b407fc57
JF
288 leave_lazy(PARAVIRT_LAZY_CPU);
289
224101ed 290 if (test_and_clear_ti_thread_flag(task_thread_info(next), TIF_LAZY_MMU_UPDATES))
b407fc57 291 arch_enter_lazy_mmu_mode();
8965c1c0
JF
292}
293
294enum paravirt_lazy_mode paravirt_get_lazy_mode(void)
295{
b8bcfe99
JF
296 if (in_interrupt())
297 return PARAVIRT_LAZY_NONE;
298
ab2f75f0 299 return percpu_read(paravirt_lazy_mode);
8965c1c0
JF
300}
301
d85cf93d
JF
302void arch_flush_lazy_mmu_mode(void)
303{
304 preempt_disable();
305
306 if (paravirt_get_lazy_mode() == PARAVIRT_LAZY_MMU) {
307 arch_leave_lazy_mmu_mode();
308 arch_enter_lazy_mmu_mode();
309 }
310
311 preempt_enable();
312}
313
93b1eab3 314struct pv_info pv_info = {
d3561b7f
RR
315 .name = "bare hardware",
316 .paravirt_enabled = 0,
317 .kernel_rpl = 0,
5311ab62 318 .shared_kernel_pmd = 1, /* Only used when CONFIG_X86_PAE is set */
93b1eab3 319};
d3561b7f 320
93b1eab3
JF
321struct pv_init_ops pv_init_ops = {
322 .patch = native_patch,
d3561b7f 323 .banner = default_banner,
45876233 324 .arch_setup = paravirt_nop,
d3561b7f 325 .memory_setup = machine_specific_memory_setup,
93b1eab3
JF
326};
327
328struct pv_time_ops pv_time_ops = {
329 .time_init = hpet_time_init,
d3561b7f
RR
330 .get_wallclock = native_get_wallclock,
331 .set_wallclock = native_set_wallclock,
93b1eab3 332 .sched_clock = native_sched_clock,
e93ef949 333 .get_tsc_khz = native_calibrate_tsc,
93b1eab3
JF
334};
335
336struct pv_irq_ops pv_irq_ops = {
d3561b7f 337 .init_IRQ = native_init_IRQ,
ecb93d1c
JF
338 .save_fl = __PV_IS_CALLEE_SAVE(native_save_fl),
339 .restore_fl = __PV_IS_CALLEE_SAVE(native_restore_fl),
340 .irq_disable = __PV_IS_CALLEE_SAVE(native_irq_disable),
341 .irq_enable = __PV_IS_CALLEE_SAVE(native_irq_enable),
93b1eab3
JF
342 .safe_halt = native_safe_halt,
343 .halt = native_halt,
fab58420
JF
344#ifdef CONFIG_X86_64
345 .adjust_exception_frame = paravirt_nop,
346#endif
93b1eab3 347};
d3561b7f 348
93b1eab3 349struct pv_cpu_ops pv_cpu_ops = {
d3561b7f
RR
350 .cpuid = native_cpuid,
351 .get_debugreg = native_get_debugreg,
352 .set_debugreg = native_set_debugreg,
353 .clts = native_clts,
354 .read_cr0 = native_read_cr0,
355 .write_cr0 = native_write_cr0,
d3561b7f
RR
356 .read_cr4 = native_read_cr4,
357 .read_cr4_safe = native_read_cr4_safe,
358 .write_cr4 = native_write_cr4,
88b4755f
GOC
359#ifdef CONFIG_X86_64
360 .read_cr8 = native_read_cr8,
361 .write_cr8 = native_write_cr8,
362#endif
d3561b7f 363 .wbinvd = native_wbinvd,
90a0a06a 364 .read_msr = native_read_msr_safe,
b05f78f5 365 .read_msr_amd = native_read_msr_amd_safe,
90a0a06a 366 .write_msr = native_write_msr_safe,
d3561b7f
RR
367 .read_tsc = native_read_tsc,
368 .read_pmc = native_read_pmc,
e5aaac44 369 .read_tscp = native_read_tscp,
d3561b7f
RR
370 .load_tr_desc = native_load_tr_desc,
371 .set_ldt = native_set_ldt,
372 .load_gdt = native_load_gdt,
373 .load_idt = native_load_idt,
374 .store_gdt = native_store_gdt,
375 .store_idt = native_store_idt,
376 .store_tr = native_store_tr,
377 .load_tls = native_load_tls,
9f9d489a
JF
378#ifdef CONFIG_X86_64
379 .load_gs_index = native_load_gs_index,
380#endif
75b8bb3e 381 .write_ldt_entry = native_write_ldt_entry,
014b15be 382 .write_gdt_entry = native_write_gdt_entry,
8d947344 383 .write_idt_entry = native_write_idt_entry,
38ffbe66
JF
384
385 .alloc_ldt = paravirt_nop,
386 .free_ldt = paravirt_nop,
387
faca6227 388 .load_sp0 = native_load_sp0,
d3561b7f 389
102d0a4b 390#if defined(CONFIG_X86_32) || defined(CONFIG_IA32_EMULATION)
d75cd22f 391 .irq_enable_sysexit = native_irq_enable_sysexit,
102d0a4b 392#endif
2be29982 393#ifdef CONFIG_X86_64
102d0a4b 394#ifdef CONFIG_IA32_EMULATION
2be29982 395 .usergs_sysret32 = native_usergs_sysret32,
102d0a4b 396#endif
2be29982 397 .usergs_sysret64 = native_usergs_sysret64,
d75cd22f 398#endif
93b1eab3 399 .iret = native_iret,
e801f864 400 .swapgs = native_swapgs,
93b1eab3 401
d3561b7f
RR
402 .set_iopl_mask = native_set_iopl_mask,
403 .io_delay = native_io_delay,
8965c1c0 404
224101ed
JF
405 .start_context_switch = paravirt_nop,
406 .end_context_switch = paravirt_nop,
93b1eab3 407};
d3561b7f 408
93b1eab3 409struct pv_apic_ops pv_apic_ops = {
13623d79 410#ifdef CONFIG_X86_LOCAL_APIC
bbab4f3b
ZA
411 .setup_boot_clock = setup_boot_APIC_clock,
412 .setup_secondary_clock = setup_secondary_APIC_clock,
0260c196 413 .startup_ipi_hook = paravirt_nop,
13623d79 414#endif
93b1eab3
JF
415};
416
41edafdb
JF
417#if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
418/* 32-bit pagetable entries */
da5de7c2 419#define PTE_IDENT __PV_IS_CALLEE_SAVE(_paravirt_ident_32)
41edafdb
JF
420#else
421/* 64-bit pagetable entries */
da5de7c2 422#define PTE_IDENT __PV_IS_CALLEE_SAVE(_paravirt_ident_64)
41edafdb
JF
423#endif
424
93b1eab3 425struct pv_mmu_ops pv_mmu_ops = {
d8dd8eec 426#ifndef CONFIG_X86_64
b239fb25
JF
427 .pagetable_setup_start = native_pagetable_setup_start,
428 .pagetable_setup_done = native_pagetable_setup_done,
a312b37b
EH
429#else
430 .pagetable_setup_start = paravirt_nop,
431 .pagetable_setup_done = paravirt_nop,
d8dd8eec 432#endif
b239fb25 433
93b1eab3
JF
434 .read_cr2 = native_read_cr2,
435 .write_cr2 = native_write_cr2,
436 .read_cr3 = native_read_cr3,
437 .write_cr3 = native_write_cr3,
438
da181a8b
RR
439 .flush_tlb_user = native_flush_tlb,
440 .flush_tlb_kernel = native_flush_tlb_global,
441 .flush_tlb_single = native_flush_tlb_single,
d4c10477 442 .flush_tlb_others = native_flush_tlb_others,
da181a8b 443
eba0045f
JF
444 .pgd_alloc = __paravirt_pgd_alloc,
445 .pgd_free = paravirt_nop,
446
6944a9c8
JF
447 .alloc_pte = paravirt_nop,
448 .alloc_pmd = paravirt_nop,
449 .alloc_pmd_clone = paravirt_nop,
2761fa09 450 .alloc_pud = paravirt_nop,
6944a9c8
JF
451 .release_pte = paravirt_nop,
452 .release_pmd = paravirt_nop,
2761fa09 453 .release_pud = paravirt_nop,
c119ecce 454
da181a8b
RR
455 .set_pte = native_set_pte,
456 .set_pte_at = native_set_pte_at,
457 .set_pmd = native_set_pmd,
45876233
JF
458 .pte_update = paravirt_nop,
459 .pte_update_defer = paravirt_nop,
3dc494e8 460
08b882c6
JF
461 .ptep_modify_prot_start = __ptep_modify_prot_start,
462 .ptep_modify_prot_commit = __ptep_modify_prot_commit,
463
ce6234b5
JF
464#ifdef CONFIG_HIGHPTE
465 .kmap_atomic_pte = kmap_atomic,
466#endif
467
f95f2f7b 468#if PAGETABLE_LEVELS >= 3
da181a8b
RR
469#ifdef CONFIG_X86_PAE
470 .set_pte_atomic = native_set_pte_atomic,
da181a8b
RR
471 .pte_clear = native_pte_clear,
472 .pmd_clear = native_pmd_clear,
f95f2f7b
EH
473#endif
474 .set_pud = native_set_pud,
da5de7c2
JF
475
476 .pmd_val = PTE_IDENT,
477 .make_pmd = PTE_IDENT,
f95f2f7b
EH
478
479#if PAGETABLE_LEVELS == 4
da5de7c2
JF
480 .pud_val = PTE_IDENT,
481 .make_pud = PTE_IDENT,
482
f95f2f7b 483 .set_pgd = native_set_pgd,
da181a8b 484#endif
f95f2f7b 485#endif /* PAGETABLE_LEVELS >= 3 */
da181a8b 486
da5de7c2
JF
487 .pte_val = PTE_IDENT,
488 .pgd_val = PTE_IDENT,
3dc494e8 489
da5de7c2
JF
490 .make_pte = PTE_IDENT,
491 .make_pgd = PTE_IDENT,
3dc494e8 492
d6dd61c8
JF
493 .dup_mmap = paravirt_nop,
494 .exit_mmap = paravirt_nop,
495 .activate_mm = paravirt_nop,
8965c1c0
JF
496
497 .lazy_mode = {
498 .enter = paravirt_nop,
499 .leave = paravirt_nop,
500 },
aeaaa59c
JF
501
502 .set_fixmap = native_set_fixmap,
d3561b7f 503};
0dbe5a11 504
93b1eab3 505EXPORT_SYMBOL_GPL(pv_time_ops);
f97b8954
JF
506EXPORT_SYMBOL (pv_cpu_ops);
507EXPORT_SYMBOL (pv_mmu_ops);
93b1eab3
JF
508EXPORT_SYMBOL_GPL(pv_apic_ops);
509EXPORT_SYMBOL_GPL(pv_info);
510EXPORT_SYMBOL (pv_irq_ops);