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457c8996 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
1d48922c DZ |
2 | /* |
3 | * Copyright (C) 1991, 1992 Linus Torvalds | |
4 | * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs | |
9c48f1c6 | 5 | * Copyright (C) 2011 Don Zickus Red Hat, Inc. |
1d48922c DZ |
6 | * |
7 | * Pentium III FXSR, SSE support | |
8 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
9 | */ | |
10 | ||
11 | /* | |
12 | * Handle hardware traps and faults. | |
13 | */ | |
14 | #include <linux/spinlock.h> | |
15 | #include <linux/kprobes.h> | |
16 | #include <linux/kdebug.h> | |
b17b0153 | 17 | #include <linux/sched/debug.h> |
1d48922c | 18 | #include <linux/nmi.h> |
2ab00456 | 19 | #include <linux/debugfs.h> |
c9126b2e DZ |
20 | #include <linux/delay.h> |
21 | #include <linux/hardirq.h> | |
c361db5c | 22 | #include <linux/ratelimit.h> |
c9126b2e | 23 | #include <linux/slab.h> |
69c60c88 | 24 | #include <linux/export.h> |
2a594d4c | 25 | #include <linux/atomic.h> |
e6017571 | 26 | #include <linux/sched/clock.h> |
1d48922c DZ |
27 | |
28 | #if defined(CONFIG_EDAC) | |
29 | #include <linux/edac.h> | |
30 | #endif | |
31 | ||
2a594d4c | 32 | #include <asm/cpu_entry_area.h> |
1d48922c DZ |
33 | #include <asm/traps.h> |
34 | #include <asm/mach_traps.h> | |
c9126b2e | 35 | #include <asm/nmi.h> |
6fd36ba0 | 36 | #include <asm/x86_init.h> |
b279d67d | 37 | #include <asm/reboot.h> |
8e2a7f5b | 38 | #include <asm/cache.h> |
04dcbdb8 | 39 | #include <asm/nospec-branch.h> |
c9126b2e | 40 | |
0c4df02d DH |
41 | #define CREATE_TRACE_POINTS |
42 | #include <trace/events/nmi.h> | |
43 | ||
c9126b2e | 44 | struct nmi_desc { |
c455fd92 | 45 | raw_spinlock_t lock; |
c9126b2e DZ |
46 | struct list_head head; |
47 | }; | |
48 | ||
49 | static struct nmi_desc nmi_desc[NMI_MAX] = | |
50 | { | |
51 | { | |
c455fd92 | 52 | .lock = __RAW_SPIN_LOCK_UNLOCKED(&nmi_desc[0].lock), |
c9126b2e DZ |
53 | .head = LIST_HEAD_INIT(nmi_desc[0].head), |
54 | }, | |
55 | { | |
c455fd92 | 56 | .lock = __RAW_SPIN_LOCK_UNLOCKED(&nmi_desc[1].lock), |
c9126b2e DZ |
57 | .head = LIST_HEAD_INIT(nmi_desc[1].head), |
58 | }, | |
553222f3 | 59 | { |
c455fd92 | 60 | .lock = __RAW_SPIN_LOCK_UNLOCKED(&nmi_desc[2].lock), |
553222f3 DZ |
61 | .head = LIST_HEAD_INIT(nmi_desc[2].head), |
62 | }, | |
63 | { | |
c455fd92 | 64 | .lock = __RAW_SPIN_LOCK_UNLOCKED(&nmi_desc[3].lock), |
553222f3 DZ |
65 | .head = LIST_HEAD_INIT(nmi_desc[3].head), |
66 | }, | |
c9126b2e DZ |
67 | |
68 | }; | |
1d48922c | 69 | |
efc3aac5 DZ |
70 | struct nmi_stats { |
71 | unsigned int normal; | |
72 | unsigned int unknown; | |
73 | unsigned int external; | |
74 | unsigned int swallow; | |
75 | }; | |
76 | ||
77 | static DEFINE_PER_CPU(struct nmi_stats, nmi_stats); | |
78 | ||
8e2a7f5b | 79 | static int ignore_nmis __read_mostly; |
1d48922c DZ |
80 | |
81 | int unknown_nmi_panic; | |
82 | /* | |
83 | * Prevent NMI reason port (0x61) being accessed simultaneously, can | |
84 | * only be used in NMI handler. | |
85 | */ | |
86 | static DEFINE_RAW_SPINLOCK(nmi_reason_lock); | |
87 | ||
88 | static int __init setup_unknown_nmi_panic(char *str) | |
89 | { | |
90 | unknown_nmi_panic = 1; | |
91 | return 1; | |
92 | } | |
93 | __setup("unknown_nmi_panic", setup_unknown_nmi_panic); | |
94 | ||
c9126b2e DZ |
95 | #define nmi_to_desc(type) (&nmi_desc[type]) |
96 | ||
2ab00456 | 97 | static u64 nmi_longest_ns = 1 * NSEC_PER_MSEC; |
e90c7853 | 98 | |
2ab00456 DH |
99 | static int __init nmi_warning_debugfs(void) |
100 | { | |
101 | debugfs_create_u64("nmi_longest_ns", 0644, | |
102 | arch_debugfs_dir, &nmi_longest_ns); | |
103 | return 0; | |
104 | } | |
105 | fs_initcall(nmi_warning_debugfs); | |
106 | ||
e90c7853 PZ |
107 | static void nmi_max_handler(struct irq_work *w) |
108 | { | |
109 | struct nmiaction *a = container_of(w, struct nmiaction, irq_work); | |
110 | int remainder_ns, decimal_msecs; | |
6aa7de05 | 111 | u64 whole_msecs = READ_ONCE(a->max_duration); |
e90c7853 PZ |
112 | |
113 | remainder_ns = do_div(whole_msecs, (1000 * 1000)); | |
114 | decimal_msecs = remainder_ns / 1000; | |
115 | ||
116 | printk_ratelimited(KERN_INFO | |
117 | "INFO: NMI handler (%ps) took too long to run: %lld.%03d msecs\n", | |
118 | a->handler, whole_msecs, decimal_msecs); | |
119 | } | |
120 | ||
bf9f2ee2 | 121 | static int nmi_handle(unsigned int type, struct pt_regs *regs) |
c9126b2e DZ |
122 | { |
123 | struct nmi_desc *desc = nmi_to_desc(type); | |
124 | struct nmiaction *a; | |
125 | int handled=0; | |
126 | ||
127 | rcu_read_lock(); | |
128 | ||
129 | /* | |
130 | * NMIs are edge-triggered, which means if you have enough | |
131 | * of them concurrently, you can lose some because only one | |
132 | * can be latched at any given time. Walk the whole list | |
133 | * to handle those situations. | |
134 | */ | |
2ab00456 | 135 | list_for_each_entry_rcu(a, &desc->head, list) { |
e90c7853 PZ |
136 | int thishandled; |
137 | u64 delta; | |
2ab00456 | 138 | |
e90c7853 | 139 | delta = sched_clock(); |
0c4df02d DH |
140 | thishandled = a->handler(type, regs); |
141 | handled += thishandled; | |
e90c7853 | 142 | delta = sched_clock() - delta; |
0c4df02d | 143 | trace_nmi_handler(a->handler, (int)delta, thishandled); |
2ab00456 | 144 | |
e90c7853 | 145 | if (delta < nmi_longest_ns || delta < a->max_duration) |
2ab00456 DH |
146 | continue; |
147 | ||
e90c7853 PZ |
148 | a->max_duration = delta; |
149 | irq_work_queue(&a->irq_work); | |
2ab00456 | 150 | } |
c9126b2e | 151 | |
c9126b2e DZ |
152 | rcu_read_unlock(); |
153 | ||
154 | /* return total number of NMI events handled */ | |
155 | return handled; | |
156 | } | |
9326638c | 157 | NOKPROBE_SYMBOL(nmi_handle); |
c9126b2e | 158 | |
72b3fb24 | 159 | int __register_nmi_handler(unsigned int type, struct nmiaction *action) |
c9126b2e DZ |
160 | { |
161 | struct nmi_desc *desc = nmi_to_desc(type); | |
162 | unsigned long flags; | |
163 | ||
72b3fb24 LZ |
164 | if (!action->handler) |
165 | return -EINVAL; | |
166 | ||
e90c7853 PZ |
167 | init_irq_work(&action->irq_work, nmi_max_handler); |
168 | ||
c455fd92 | 169 | raw_spin_lock_irqsave(&desc->lock, flags); |
c9126b2e | 170 | |
b227e233 | 171 | /* |
0d443b70 MT |
172 | * Indicate if there are multiple registrations on the |
173 | * internal NMI handler call chains (SERR and IO_CHECK). | |
b227e233 | 174 | */ |
553222f3 DZ |
175 | WARN_ON_ONCE(type == NMI_SERR && !list_empty(&desc->head)); |
176 | WARN_ON_ONCE(type == NMI_IO_CHECK && !list_empty(&desc->head)); | |
b227e233 | 177 | |
c9126b2e DZ |
178 | /* |
179 | * some handlers need to be executed first otherwise a fake | |
180 | * event confuses some handlers (kdump uses this flag) | |
181 | */ | |
182 | if (action->flags & NMI_FLAG_FIRST) | |
183 | list_add_rcu(&action->list, &desc->head); | |
184 | else | |
185 | list_add_tail_rcu(&action->list, &desc->head); | |
186 | ||
c455fd92 | 187 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
c9126b2e DZ |
188 | return 0; |
189 | } | |
72b3fb24 | 190 | EXPORT_SYMBOL(__register_nmi_handler); |
c9126b2e | 191 | |
72b3fb24 | 192 | void unregister_nmi_handler(unsigned int type, const char *name) |
c9126b2e DZ |
193 | { |
194 | struct nmi_desc *desc = nmi_to_desc(type); | |
195 | struct nmiaction *n; | |
196 | unsigned long flags; | |
197 | ||
c455fd92 | 198 | raw_spin_lock_irqsave(&desc->lock, flags); |
c9126b2e DZ |
199 | |
200 | list_for_each_entry_rcu(n, &desc->head, list) { | |
201 | /* | |
202 | * the name passed in to describe the nmi handler | |
203 | * is used as the lookup key | |
204 | */ | |
205 | if (!strcmp(n->name, name)) { | |
206 | WARN(in_nmi(), | |
207 | "Trying to free NMI (%s) from NMI context!\n", n->name); | |
208 | list_del_rcu(&n->list); | |
209 | break; | |
210 | } | |
211 | } | |
212 | ||
c455fd92 | 213 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
c9126b2e | 214 | synchronize_rcu(); |
c9126b2e | 215 | } |
c9126b2e DZ |
216 | EXPORT_SYMBOL_GPL(unregister_nmi_handler); |
217 | ||
9326638c | 218 | static void |
1d48922c DZ |
219 | pci_serr_error(unsigned char reason, struct pt_regs *regs) |
220 | { | |
553222f3 | 221 | /* check to see if anyone registered against these types of errors */ |
bf9f2ee2 | 222 | if (nmi_handle(NMI_SERR, regs)) |
553222f3 DZ |
223 | return; |
224 | ||
1d48922c DZ |
225 | pr_emerg("NMI: PCI system error (SERR) for reason %02x on CPU %d.\n", |
226 | reason, smp_processor_id()); | |
227 | ||
1d48922c | 228 | if (panic_on_unrecovered_nmi) |
58c5661f | 229 | nmi_panic(regs, "NMI: Not continuing"); |
1d48922c DZ |
230 | |
231 | pr_emerg("Dazed and confused, but trying to continue\n"); | |
232 | ||
233 | /* Clear and disable the PCI SERR error line. */ | |
234 | reason = (reason & NMI_REASON_CLEAR_MASK) | NMI_REASON_CLEAR_SERR; | |
235 | outb(reason, NMI_REASON_PORT); | |
236 | } | |
9326638c | 237 | NOKPROBE_SYMBOL(pci_serr_error); |
1d48922c | 238 | |
9326638c | 239 | static void |
1d48922c DZ |
240 | io_check_error(unsigned char reason, struct pt_regs *regs) |
241 | { | |
242 | unsigned long i; | |
243 | ||
553222f3 | 244 | /* check to see if anyone registered against these types of errors */ |
bf9f2ee2 | 245 | if (nmi_handle(NMI_IO_CHECK, regs)) |
553222f3 DZ |
246 | return; |
247 | ||
1d48922c DZ |
248 | pr_emerg( |
249 | "NMI: IOCK error (debug interrupt?) for reason %02x on CPU %d.\n", | |
250 | reason, smp_processor_id()); | |
57da8b96 | 251 | show_regs(regs); |
1d48922c | 252 | |
1717f209 | 253 | if (panic_on_io_nmi) { |
58c5661f | 254 | nmi_panic(regs, "NMI IOCK error: Not continuing"); |
1717f209 HK |
255 | |
256 | /* | |
257 | * If we end up here, it means we have received an NMI while | |
258 | * processing panic(). Simply return without delaying and | |
259 | * re-enabling NMIs. | |
260 | */ | |
261 | return; | |
262 | } | |
1d48922c DZ |
263 | |
264 | /* Re-enable the IOCK line, wait for a few seconds */ | |
265 | reason = (reason & NMI_REASON_CLEAR_MASK) | NMI_REASON_CLEAR_IOCHK; | |
266 | outb(reason, NMI_REASON_PORT); | |
267 | ||
268 | i = 20000; | |
269 | while (--i) { | |
270 | touch_nmi_watchdog(); | |
271 | udelay(100); | |
272 | } | |
273 | ||
274 | reason &= ~NMI_REASON_CLEAR_IOCHK; | |
275 | outb(reason, NMI_REASON_PORT); | |
276 | } | |
9326638c | 277 | NOKPROBE_SYMBOL(io_check_error); |
1d48922c | 278 | |
9326638c | 279 | static void |
1d48922c DZ |
280 | unknown_nmi_error(unsigned char reason, struct pt_regs *regs) |
281 | { | |
9c48f1c6 DZ |
282 | int handled; |
283 | ||
b227e233 DZ |
284 | /* |
285 | * Use 'false' as back-to-back NMIs are dealt with one level up. | |
286 | * Of course this makes having multiple 'unknown' handlers useless | |
287 | * as only the first one is ever run (unless it can actually determine | |
288 | * if it caused the NMI) | |
289 | */ | |
bf9f2ee2 | 290 | handled = nmi_handle(NMI_UNKNOWN, regs); |
efc3aac5 DZ |
291 | if (handled) { |
292 | __this_cpu_add(nmi_stats.unknown, handled); | |
1d48922c | 293 | return; |
efc3aac5 DZ |
294 | } |
295 | ||
296 | __this_cpu_add(nmi_stats.unknown, 1); | |
297 | ||
1d48922c DZ |
298 | pr_emerg("Uhhuh. NMI received for unknown reason %02x on CPU %d.\n", |
299 | reason, smp_processor_id()); | |
300 | ||
301 | pr_emerg("Do you have a strange power saving mode enabled?\n"); | |
302 | if (unknown_nmi_panic || panic_on_unrecovered_nmi) | |
58c5661f | 303 | nmi_panic(regs, "NMI: Not continuing"); |
1d48922c DZ |
304 | |
305 | pr_emerg("Dazed and confused, but trying to continue\n"); | |
306 | } | |
9326638c | 307 | NOKPROBE_SYMBOL(unknown_nmi_error); |
1d48922c | 308 | |
b227e233 DZ |
309 | static DEFINE_PER_CPU(bool, swallow_nmi); |
310 | static DEFINE_PER_CPU(unsigned long, last_nmi_rip); | |
311 | ||
9326638c | 312 | static void default_do_nmi(struct pt_regs *regs) |
1d48922c DZ |
313 | { |
314 | unsigned char reason = 0; | |
9c48f1c6 | 315 | int handled; |
b227e233 | 316 | bool b2b = false; |
1d48922c DZ |
317 | |
318 | /* | |
319 | * CPU-specific NMI must be processed before non-CPU-specific | |
320 | * NMI, otherwise we may lose it, because the CPU-specific | |
321 | * NMI can not be detected/processed on other CPUs. | |
322 | */ | |
b227e233 DZ |
323 | |
324 | /* | |
325 | * Back-to-back NMIs are interesting because they can either | |
326 | * be two NMI or more than two NMIs (any thing over two is dropped | |
327 | * due to NMI being edge-triggered). If this is the second half | |
328 | * of the back-to-back NMI, assume we dropped things and process | |
329 | * more handlers. Otherwise reset the 'swallow' NMI behaviour | |
330 | */ | |
331 | if (regs->ip == __this_cpu_read(last_nmi_rip)) | |
332 | b2b = true; | |
333 | else | |
334 | __this_cpu_write(swallow_nmi, false); | |
335 | ||
336 | __this_cpu_write(last_nmi_rip, regs->ip); | |
337 | ||
bf9f2ee2 | 338 | handled = nmi_handle(NMI_LOCAL, regs); |
efc3aac5 | 339 | __this_cpu_add(nmi_stats.normal, handled); |
b227e233 DZ |
340 | if (handled) { |
341 | /* | |
342 | * There are cases when a NMI handler handles multiple | |
343 | * events in the current NMI. One of these events may | |
344 | * be queued for in the next NMI. Because the event is | |
345 | * already handled, the next NMI will result in an unknown | |
346 | * NMI. Instead lets flag this for a potential NMI to | |
347 | * swallow. | |
348 | */ | |
349 | if (handled > 1) | |
350 | __this_cpu_write(swallow_nmi, true); | |
1d48922c | 351 | return; |
b227e233 | 352 | } |
1d48922c | 353 | |
b279d67d HK |
354 | /* |
355 | * Non-CPU-specific NMI: NMI sources can be processed on any CPU. | |
356 | * | |
357 | * Another CPU may be processing panic routines while holding | |
358 | * nmi_reason_lock. Check if the CPU issued the IPI for crash dumping, | |
359 | * and if so, call its callback directly. If there is no CPU preparing | |
360 | * crash dump, we simply loop here. | |
361 | */ | |
362 | while (!raw_spin_trylock(&nmi_reason_lock)) { | |
363 | run_crash_ipi_callback(regs); | |
364 | cpu_relax(); | |
365 | } | |
366 | ||
064a59b6 | 367 | reason = x86_platform.get_nmi_reason(); |
1d48922c DZ |
368 | |
369 | if (reason & NMI_REASON_MASK) { | |
370 | if (reason & NMI_REASON_SERR) | |
371 | pci_serr_error(reason, regs); | |
372 | else if (reason & NMI_REASON_IOCHK) | |
373 | io_check_error(reason, regs); | |
374 | #ifdef CONFIG_X86_32 | |
375 | /* | |
376 | * Reassert NMI in case it became active | |
377 | * meanwhile as it's edge-triggered: | |
378 | */ | |
379 | reassert_nmi(); | |
380 | #endif | |
efc3aac5 | 381 | __this_cpu_add(nmi_stats.external, 1); |
1d48922c DZ |
382 | raw_spin_unlock(&nmi_reason_lock); |
383 | return; | |
384 | } | |
385 | raw_spin_unlock(&nmi_reason_lock); | |
386 | ||
b227e233 DZ |
387 | /* |
388 | * Only one NMI can be latched at a time. To handle | |
389 | * this we may process multiple nmi handlers at once to | |
390 | * cover the case where an NMI is dropped. The downside | |
391 | * to this approach is we may process an NMI prematurely, | |
392 | * while its real NMI is sitting latched. This will cause | |
393 | * an unknown NMI on the next run of the NMI processing. | |
394 | * | |
395 | * We tried to flag that condition above, by setting the | |
396 | * swallow_nmi flag when we process more than one event. | |
397 | * This condition is also only present on the second half | |
398 | * of a back-to-back NMI, so we flag that condition too. | |
399 | * | |
400 | * If both are true, we assume we already processed this | |
401 | * NMI previously and we swallow it. Otherwise we reset | |
402 | * the logic. | |
403 | * | |
404 | * There are scenarios where we may accidentally swallow | |
405 | * a 'real' unknown NMI. For example, while processing | |
406 | * a perf NMI another perf NMI comes in along with a | |
407 | * 'real' unknown NMI. These two NMIs get combined into | |
408 | * one (as descibed above). When the next NMI gets | |
409 | * processed, it will be flagged by perf as handled, but | |
410 | * noone will know that there was a 'real' unknown NMI sent | |
411 | * also. As a result it gets swallowed. Or if the first | |
412 | * perf NMI returns two events handled then the second | |
413 | * NMI will get eaten by the logic below, again losing a | |
414 | * 'real' unknown NMI. But this is the best we can do | |
415 | * for now. | |
416 | */ | |
417 | if (b2b && __this_cpu_read(swallow_nmi)) | |
efc3aac5 | 418 | __this_cpu_add(nmi_stats.swallow, 1); |
b227e233 DZ |
419 | else |
420 | unknown_nmi_error(reason, regs); | |
1d48922c | 421 | } |
9326638c | 422 | NOKPROBE_SYMBOL(default_do_nmi); |
1d48922c | 423 | |
ccd49c23 | 424 | /* |
0b22930e AL |
425 | * NMIs can page fault or hit breakpoints which will cause it to lose |
426 | * its NMI context with the CPU when the breakpoint or page fault does an IRET. | |
9d050416 AL |
427 | * |
428 | * As a result, NMIs can nest if NMIs get unmasked due an IRET during | |
429 | * NMI processing. On x86_64, the asm glue protects us from nested NMIs | |
430 | * if the outer NMI came from kernel mode, but we can still nest if the | |
431 | * outer NMI came from user mode. | |
432 | * | |
433 | * To handle these nested NMIs, we have three states: | |
ccd49c23 SR |
434 | * |
435 | * 1) not running | |
436 | * 2) executing | |
437 | * 3) latched | |
438 | * | |
439 | * When no NMI is in progress, it is in the "not running" state. | |
440 | * When an NMI comes in, it goes into the "executing" state. | |
441 | * Normally, if another NMI is triggered, it does not interrupt | |
442 | * the running NMI and the HW will simply latch it so that when | |
443 | * the first NMI finishes, it will restart the second NMI. | |
444 | * (Note, the latch is binary, thus multiple NMIs triggering, | |
445 | * when one is running, are ignored. Only one NMI is restarted.) | |
446 | * | |
9d050416 AL |
447 | * If an NMI executes an iret, another NMI can preempt it. We do not |
448 | * want to allow this new NMI to run, but we want to execute it when the | |
449 | * first one finishes. We set the state to "latched", and the exit of | |
450 | * the first NMI will perform a dec_return, if the result is zero | |
451 | * (NOT_RUNNING), then it will simply exit the NMI handler. If not, the | |
452 | * dec_return would have set the state to NMI_EXECUTING (what we want it | |
453 | * to be when we are running). In this case, we simply jump back to | |
454 | * rerun the NMI handler again, and restart the 'latched' NMI. | |
c7d65a78 SR |
455 | * |
456 | * No trap (breakpoint or page fault) should be hit before nmi_restart, | |
457 | * thus there is no race between the first check of state for NOT_RUNNING | |
458 | * and setting it to NMI_EXECUTING. The HW will prevent nested NMIs | |
459 | * at this point. | |
70fb74a5 SR |
460 | * |
461 | * In case the NMI takes a page fault, we need to save off the CR2 | |
462 | * because the NMI could have preempted another page fault and corrupt | |
463 | * the CR2 that is about to be read. As nested NMIs must be restarted | |
464 | * and they can not take breakpoints or page faults, the update of the | |
465 | * CR2 must be done before converting the nmi state back to NOT_RUNNING. | |
466 | * Otherwise, there would be a race of another nested NMI coming in | |
467 | * after setting state to NOT_RUNNING but before updating the nmi_cr2. | |
ccd49c23 SR |
468 | */ |
469 | enum nmi_states { | |
c7d65a78 | 470 | NMI_NOT_RUNNING = 0, |
ccd49c23 SR |
471 | NMI_EXECUTING, |
472 | NMI_LATCHED, | |
473 | }; | |
474 | static DEFINE_PER_CPU(enum nmi_states, nmi_state); | |
70fb74a5 | 475 | static DEFINE_PER_CPU(unsigned long, nmi_cr2); |
ccd49c23 | 476 | |
9d050416 | 477 | #ifdef CONFIG_X86_64 |
ccd49c23 | 478 | /* |
9d050416 AL |
479 | * In x86_64, we need to handle breakpoint -> NMI -> breakpoint. Without |
480 | * some care, the inner breakpoint will clobber the outer breakpoint's | |
481 | * stack. | |
ccd49c23 | 482 | * |
9d050416 AL |
483 | * If a breakpoint is being processed, and the debug stack is being |
484 | * used, if an NMI comes in and also hits a breakpoint, the stack | |
485 | * pointer will be set to the same fixed address as the breakpoint that | |
486 | * was interrupted, causing that stack to be corrupted. To handle this | |
487 | * case, check if the stack that was interrupted is the debug stack, and | |
488 | * if so, change the IDT so that new breakpoints will use the current | |
489 | * stack and not switch to the fixed address. On return of the NMI, | |
490 | * switch back to the original IDT. | |
ccd49c23 SR |
491 | */ |
492 | static DEFINE_PER_CPU(int, update_debug_stack); | |
2a594d4c TG |
493 | |
494 | static bool notrace is_debug_stack(unsigned long addr) | |
495 | { | |
496 | struct cea_exception_stacks *cs = __this_cpu_read(cea_exception_stacks); | |
497 | unsigned long top = CEA_ESTACK_TOP(cs, DB); | |
498 | unsigned long bot = CEA_ESTACK_BOT(cs, DB1); | |
499 | ||
500 | if (__this_cpu_read(debug_stack_usage)) | |
501 | return true; | |
502 | /* | |
503 | * Note, this covers the guard page between DB and DB1 as well to | |
504 | * avoid two checks. But by all means @addr can never point into | |
505 | * the guard page. | |
506 | */ | |
507 | return addr >= bot && addr < top; | |
508 | } | |
509 | NOKPROBE_SYMBOL(is_debug_stack); | |
9d050416 | 510 | #endif |
228bdaa9 | 511 | |
9d050416 AL |
512 | dotraplinkage notrace void |
513 | do_nmi(struct pt_regs *regs, long error_code) | |
ccd49c23 | 514 | { |
9d050416 AL |
515 | if (this_cpu_read(nmi_state) != NMI_NOT_RUNNING) { |
516 | this_cpu_write(nmi_state, NMI_LATCHED); | |
517 | return; | |
518 | } | |
519 | this_cpu_write(nmi_state, NMI_EXECUTING); | |
520 | this_cpu_write(nmi_cr2, read_cr2()); | |
521 | nmi_restart: | |
522 | ||
523 | #ifdef CONFIG_X86_64 | |
228bdaa9 SR |
524 | /* |
525 | * If we interrupted a breakpoint, it is possible that | |
526 | * the nmi handler will have breakpoints too. We need to | |
527 | * change the IDT such that breakpoints that happen here | |
528 | * continue to use the NMI stack. | |
529 | */ | |
530 | if (unlikely(is_debug_stack(regs->sp))) { | |
531 | debug_stack_set_zero(); | |
c0525a69 | 532 | this_cpu_write(update_debug_stack, 1); |
228bdaa9 | 533 | } |
ccd49c23 SR |
534 | #endif |
535 | ||
1d48922c DZ |
536 | nmi_enter(); |
537 | ||
538 | inc_irq_stat(__nmi_count); | |
539 | ||
540 | if (!ignore_nmis) | |
541 | default_do_nmi(regs); | |
542 | ||
543 | nmi_exit(); | |
228bdaa9 | 544 | |
9d050416 AL |
545 | #ifdef CONFIG_X86_64 |
546 | if (unlikely(this_cpu_read(update_debug_stack))) { | |
547 | debug_stack_reset(); | |
548 | this_cpu_write(update_debug_stack, 0); | |
549 | } | |
550 | #endif | |
551 | ||
552 | if (unlikely(this_cpu_read(nmi_cr2) != read_cr2())) | |
553 | write_cr2(this_cpu_read(nmi_cr2)); | |
554 | if (this_cpu_dec_return(nmi_state)) | |
555 | goto nmi_restart; | |
04dcbdb8 TG |
556 | |
557 | if (user_mode(regs)) | |
558 | mds_user_clear_cpu_buffers(); | |
1d48922c | 559 | } |
9326638c | 560 | NOKPROBE_SYMBOL(do_nmi); |
1d48922c DZ |
561 | |
562 | void stop_nmi(void) | |
563 | { | |
564 | ignore_nmis++; | |
565 | } | |
566 | ||
567 | void restart_nmi(void) | |
568 | { | |
569 | ignore_nmis--; | |
570 | } | |
b227e233 DZ |
571 | |
572 | /* reset the back-to-back NMI logic */ | |
573 | void local_touch_nmi(void) | |
574 | { | |
575 | __this_cpu_write(last_nmi_rip, 0); | |
576 | } | |
29c6fb7b | 577 | EXPORT_SYMBOL_GPL(local_touch_nmi); |