Commit | Line | Data |
---|---|---|
b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 | 2 | /* |
11113f84 | 3 | * Intel Multiprocessor Specification 1.1 and 1.4 |
1da177e4 LT |
4 | * compliant MP-table parsing routines. |
5 | * | |
87c6fe26 | 6 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 7 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
85bdddec | 8 | * (c) 2008 Alexey Starikovskiy <astarikovskiy@suse.de> |
1da177e4 LT |
9 | */ |
10 | ||
11 | #include <linux/mm.h> | |
1da177e4 | 12 | #include <linux/init.h> |
1da177e4 | 13 | #include <linux/delay.h> |
72d7c3b3 | 14 | #include <linux/memblock.h> |
1da177e4 LT |
15 | #include <linux/kernel_stat.h> |
16 | #include <linux/mc146818rtc.h> | |
17 | #include <linux/bitops.h> | |
85bdddec | 18 | #include <linux/acpi.h> |
103ceffb | 19 | #include <linux/smp.h> |
629e15d2 | 20 | #include <linux/pci.h> |
1da177e4 | 21 | |
13c01139 IM |
22 | #include <asm/io_apic.h> |
23 | #include <asm/acpi.h> | |
f7a0c786 | 24 | #include <asm/irqdomain.h> |
1da177e4 LT |
25 | #include <asm/mtrr.h> |
26 | #include <asm/mpspec.h> | |
27 | #include <asm/io_apic.h> | |
85bdddec | 28 | #include <asm/proto.h> |
ce3fe6b2 | 29 | #include <asm/bios_ebda.h> |
66441bd3 | 30 | #include <asm/e820/api.h> |
3c9cb6de | 31 | #include <asm/setup.h> |
4884d8e6 | 32 | #include <asm/smp.h> |
1da177e4 | 33 | |
7b6aa335 | 34 | #include <asm/apic.h> |
1da177e4 LT |
35 | /* |
36 | * Checksum an MP configuration block. | |
37 | */ | |
38 | ||
39 | static int __init mpf_checksum(unsigned char *mp, int len) | |
40 | { | |
41 | int sum = 0; | |
42 | ||
43 | while (len--) | |
44 | sum += *mp++; | |
45 | ||
46 | return sum & 0xFF; | |
47 | } | |
48 | ||
fd6c6661 TG |
49 | int __init default_mpc_apic_id(struct mpc_cpu *m) |
50 | { | |
51 | return m->apicid; | |
52 | } | |
53 | ||
f4f21b71 | 54 | static void __init MP_processor_info(struct mpc_cpu *m) |
c853c676 AS |
55 | { |
56 | int apicid; | |
746f2244 | 57 | char *bootup_cpu = ""; |
c853c676 | 58 | |
c4563826 | 59 | if (!(m->cpuflag & CPU_ENABLED)) { |
7b1292e2 | 60 | disabled_cpus++; |
1da177e4 | 61 | return; |
7b1292e2 | 62 | } |
64898a8b | 63 | |
fd6c6661 | 64 | apicid = x86_init.mpparse.mpc_apic_id(m); |
64898a8b | 65 | |
c4563826 | 66 | if (m->cpuflag & CPU_BOOTPROCESSOR) { |
746f2244 | 67 | bootup_cpu = " (Bootup-CPU)"; |
c4563826 | 68 | boot_cpu_physical_apicid = m->apicid; |
1da177e4 LT |
69 | } |
70 | ||
b1bfd5ea | 71 | pr_info("Processor #%d%s\n", m->apicid, bootup_cpu); |
c4563826 | 72 | generic_processor_info(apicid, m->apicver); |
1da177e4 LT |
73 | } |
74 | ||
85cc35fa | 75 | #ifdef CONFIG_X86_IO_APIC |
90e1c696 | 76 | void __init default_mpc_oem_bus_info(struct mpc_bus *m, char *str) |
1da177e4 | 77 | { |
d4c715fa | 78 | memcpy(str, m->bustype, 6); |
1da177e4 | 79 | str[6] = 0; |
90e1c696 TG |
80 | apic_printk(APIC_VERBOSE, "Bus #%d is %s\n", m->busid, str); |
81 | } | |
1da177e4 | 82 | |
90e1c696 TG |
83 | static void __init MP_bus_info(struct mpc_bus *m) |
84 | { | |
85 | char str[7]; | |
1da177e4 | 86 | |
90e1c696 | 87 | x86_init.mpparse.mpc_oem_bus_info(m, str); |
1da177e4 | 88 | |
5e4edbb7 | 89 | #if MAX_MP_BUSSES < 256 |
d4c715fa | 90 | if (m->busid >= MAX_MP_BUSSES) { |
b1bfd5ea JL |
91 | pr_warn("MP table busid value (%d) for bustype %s is too large, max. supported is %d\n", |
92 | m->busid, str, MAX_MP_BUSSES - 1); | |
c0ec31ad RD |
93 | return; |
94 | } | |
5e4edbb7 | 95 | #endif |
c0ec31ad | 96 | |
9e686668 | 97 | set_bit(m->busid, mp_bus_not_pci); |
f8924e77 | 98 | if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA) - 1) == 0) { |
bb8187d3 | 99 | #ifdef CONFIG_EISA |
d4c715fa | 100 | mp_bus_id_to_type[m->busid] = MP_BUS_ISA; |
f8924e77 AS |
101 | #endif |
102 | } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI) - 1) == 0) { | |
52fdb568 TG |
103 | if (x86_init.mpparse.mpc_oem_pci_bus) |
104 | x86_init.mpparse.mpc_oem_pci_bus(m); | |
64898a8b | 105 | |
d4c715fa | 106 | clear_bit(m->busid, mp_bus_not_pci); |
bb8187d3 | 107 | #ifdef CONFIG_EISA |
d4c715fa | 108 | mp_bus_id_to_type[m->busid] = MP_BUS_PCI; |
4ef81297 | 109 | } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA) - 1) == 0) { |
d4c715fa | 110 | mp_bus_id_to_type[m->busid] = MP_BUS_EISA; |
c0a282c2 | 111 | #endif |
f8924e77 | 112 | } else |
b1bfd5ea | 113 | pr_warn("Unknown bustype %s - ignoring\n", str); |
1da177e4 | 114 | } |
61048c63 | 115 | |
2b85b5fb | 116 | static void __init MP_ioapic_info(struct mpc_ioapic *m) |
1da177e4 | 117 | { |
74501edc JL |
118 | struct ioapic_domain_cfg cfg = { |
119 | .type = IOAPIC_DOMAIN_LEGACY, | |
120 | .ops = &mp_ioapic_irqdomain_ops, | |
121 | }; | |
122 | ||
0e3fa13f | 123 | if (m->flags & MPC_APIC_USABLE) |
74501edc | 124 | mp_register_ioapic(m->apicid, m->apicaddr, gsi_top, &cfg); |
2944e16b YL |
125 | } |
126 | ||
c2c21745 | 127 | static void __init print_mp_irq_info(struct mpc_intsrc *mp_irq) |
2944e16b | 128 | { |
b1bfd5ea JL |
129 | apic_printk(APIC_VERBOSE, |
130 | "Int: type %d, pol %d, trig %d, bus %02x, IRQ %02x, APIC ID %x, APIC INT %02x\n", | |
c2c21745 JSR |
131 | mp_irq->irqtype, mp_irq->irqflag & 3, |
132 | (mp_irq->irqflag >> 2) & 3, mp_irq->srcbus, | |
133 | mp_irq->srcbusirq, mp_irq->dstapic, mp_irq->dstirq); | |
2944e16b YL |
134 | } |
135 | ||
a6830278 JSR |
136 | #else /* CONFIG_X86_IO_APIC */ |
137 | static inline void __init MP_bus_info(struct mpc_bus *m) {} | |
138 | static inline void __init MP_ioapic_info(struct mpc_ioapic *m) {} | |
a6830278 | 139 | #endif /* CONFIG_X86_IO_APIC */ |
1da177e4 | 140 | |
8fb2952b | 141 | static void __init MP_lintsrc_info(struct mpc_lintsrc *m) |
1da177e4 | 142 | { |
b1bfd5ea JL |
143 | apic_printk(APIC_VERBOSE, |
144 | "Lint: type %d, pol %d, trig %d, bus %02x, IRQ %02x, APIC ID %x, APIC LINT %02x\n", | |
b5ced7cd JSR |
145 | m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbusid, |
146 | m->srcbusirq, m->destapic, m->destapiclint); | |
1da177e4 LT |
147 | } |
148 | ||
1da177e4 LT |
149 | /* |
150 | * Read/parse the MPC | |
151 | */ | |
f29521e4 | 152 | static int __init smp_check_mpc(struct mpc_table *mpc, char *oem, char *str) |
1da177e4 | 153 | { |
1da177e4 | 154 | |
6c65da50 | 155 | if (memcmp(mpc->signature, MPC_SIGNATURE, 4)) { |
b1bfd5ea | 156 | pr_err("MPTABLE: bad signature [%c%c%c%c]!\n", |
6c65da50 JSR |
157 | mpc->signature[0], mpc->signature[1], |
158 | mpc->signature[2], mpc->signature[3]); | |
1da177e4 LT |
159 | return 0; |
160 | } | |
6c65da50 | 161 | if (mpf_checksum((unsigned char *)mpc, mpc->length)) { |
b1bfd5ea | 162 | pr_err("MPTABLE: checksum error!\n"); |
1da177e4 LT |
163 | return 0; |
164 | } | |
6c65da50 | 165 | if (mpc->spec != 0x01 && mpc->spec != 0x04) { |
b1bfd5ea | 166 | pr_err("MPTABLE: bad table version (%d)!!\n", mpc->spec); |
1da177e4 LT |
167 | return 0; |
168 | } | |
6c65da50 | 169 | if (!mpc->lapic) { |
b1bfd5ea | 170 | pr_err("MPTABLE: null local APIC address!\n"); |
1da177e4 LT |
171 | return 0; |
172 | } | |
6c65da50 | 173 | memcpy(oem, mpc->oem, 8); |
4ef81297 | 174 | oem[8] = 0; |
b1bfd5ea | 175 | pr_info("MPTABLE: OEM ID: %s\n", oem); |
1da177e4 | 176 | |
6c65da50 | 177 | memcpy(str, mpc->productid, 12); |
4ef81297 | 178 | str[12] = 0; |
1da177e4 | 179 | |
b1bfd5ea | 180 | pr_info("MPTABLE: Product ID: %s\n", str); |
1da177e4 | 181 | |
b1bfd5ea | 182 | pr_info("MPTABLE: APIC at: 0x%X\n", mpc->lapic); |
1da177e4 | 183 | |
2944e16b YL |
184 | return 1; |
185 | } | |
186 | ||
a6830278 JSR |
187 | static void skip_entry(unsigned char **ptr, int *count, int size) |
188 | { | |
189 | *ptr += size; | |
190 | *count += size; | |
191 | } | |
192 | ||
5a5737ea JSR |
193 | static void __init smp_dump_mptable(struct mpc_table *mpc, unsigned char *mpt) |
194 | { | |
b1bfd5ea JL |
195 | pr_err("Your mptable is wrong, contact your HW vendor!\n"); |
196 | pr_cont("type %x\n", *mpt); | |
5a5737ea JSR |
197 | print_hex_dump(KERN_ERR, " ", DUMP_PREFIX_ADDRESS, 16, |
198 | 1, mpc, mpc->length, 1); | |
199 | } | |
200 | ||
72302142 TG |
201 | void __init default_smp_read_mpc_oem(struct mpc_table *mpc) { } |
202 | ||
f29521e4 | 203 | static int __init smp_read_mpc(struct mpc_table *mpc, unsigned early) |
2944e16b YL |
204 | { |
205 | char str[16]; | |
206 | char oem[10]; | |
207 | ||
208 | int count = sizeof(*mpc); | |
209 | unsigned char *mpt = ((unsigned char *)mpc) + count; | |
210 | ||
211 | if (!smp_check_mpc(mpc, oem, str)) | |
212 | return 0; | |
213 | ||
f1157141 | 214 | /* Initialize the lapic mapping */ |
1da177e4 | 215 | if (!acpi_lapic) |
f1157141 | 216 | register_lapic_address(mpc->lapic); |
1da177e4 | 217 | |
888032cd AS |
218 | if (early) |
219 | return 1; | |
220 | ||
72302142 TG |
221 | if (mpc->oemptr) |
222 | x86_init.mpparse.smp_read_mpc_oem(mpc); | |
64898a8b | 223 | |
1da177e4 | 224 | /* |
4ef81297 | 225 | * Now process the configuration blocks. |
1da177e4 | 226 | */ |
f4848472 | 227 | x86_init.mpparse.mpc_record(0); |
64898a8b | 228 | |
6c65da50 | 229 | while (count < mpc->length) { |
4ef81297 AS |
230 | switch (*mpt) { |
231 | case MP_PROCESSOR: | |
a6830278 JSR |
232 | /* ACPI may have already provided this data */ |
233 | if (!acpi_lapic) | |
c58603e8 | 234 | MP_processor_info((struct mpc_cpu *)mpt); |
a6830278 JSR |
235 | skip_entry(&mpt, &count, sizeof(struct mpc_cpu)); |
236 | break; | |
4ef81297 | 237 | case MP_BUS: |
c58603e8 | 238 | MP_bus_info((struct mpc_bus *)mpt); |
a6830278 JSR |
239 | skip_entry(&mpt, &count, sizeof(struct mpc_bus)); |
240 | break; | |
4ef81297 | 241 | case MP_IOAPIC: |
c58603e8 | 242 | MP_ioapic_info((struct mpc_ioapic *)mpt); |
a6830278 JSR |
243 | skip_entry(&mpt, &count, sizeof(struct mpc_ioapic)); |
244 | break; | |
4ef81297 | 245 | case MP_INTSRC: |
2d8009ba | 246 | mp_save_irq((struct mpc_intsrc *)mpt); |
a6830278 JSR |
247 | skip_entry(&mpt, &count, sizeof(struct mpc_intsrc)); |
248 | break; | |
4ef81297 | 249 | case MP_LINTSRC: |
c58603e8 | 250 | MP_lintsrc_info((struct mpc_lintsrc *)mpt); |
a6830278 JSR |
251 | skip_entry(&mpt, &count, sizeof(struct mpc_lintsrc)); |
252 | break; | |
4ef81297 | 253 | default: |
711554db | 254 | /* wrong mptable */ |
5a5737ea | 255 | smp_dump_mptable(mpc, mpt); |
6c65da50 | 256 | count = mpc->length; |
711554db | 257 | break; |
1da177e4 | 258 | } |
f4848472 | 259 | x86_init.mpparse.mpc_record(1); |
1da177e4 | 260 | } |
e0da3364 | 261 | |
1da177e4 | 262 | if (!num_processors) |
b1bfd5ea | 263 | pr_err("MPTABLE: no processors registered!\n"); |
1da177e4 LT |
264 | return num_processors; |
265 | } | |
266 | ||
61048c63 AS |
267 | #ifdef CONFIG_X86_IO_APIC |
268 | ||
1da177e4 LT |
269 | static int __init ELCR_trigger(unsigned int irq) |
270 | { | |
271 | unsigned int port; | |
272 | ||
273 | port = 0x4d0 + (irq >> 3); | |
274 | return (inb(port) >> (irq & 7)) & 1; | |
275 | } | |
276 | ||
277 | static void __init construct_default_ioirq_mptable(int mpc_default_type) | |
278 | { | |
540d4e72 | 279 | struct mpc_intsrc intsrc; |
1da177e4 LT |
280 | int i; |
281 | int ELCR_fallback = 0; | |
282 | ||
e253b396 | 283 | intsrc.type = MP_INTSRC; |
a09c5ec0 | 284 | intsrc.irqflag = MP_IRQTRIG_DEFAULT | MP_IRQPOL_DEFAULT; |
e253b396 | 285 | intsrc.srcbus = 0; |
d5371430 | 286 | intsrc.dstapic = mpc_ioapic_id(0); |
1da177e4 | 287 | |
e253b396 | 288 | intsrc.irqtype = mp_INT; |
1da177e4 LT |
289 | |
290 | /* | |
291 | * If true, we have an ISA/PCI system with no IRQ entries | |
292 | * in the MP table. To prevent the PCI interrupts from being set up | |
293 | * incorrectly, we try to use the ELCR. The sanity check to see if | |
294 | * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can | |
295 | * never be level sensitive, so we simply see if the ELCR agrees. | |
296 | * If it does, we assume it's valid. | |
297 | */ | |
298 | if (mpc_default_type == 5) { | |
b1bfd5ea | 299 | pr_info("ISA/PCI bus type with no IRQ information... falling back to ELCR\n"); |
1da177e4 | 300 | |
62441bf1 AS |
301 | if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || |
302 | ELCR_trigger(13)) | |
b1bfd5ea | 303 | pr_err("ELCR contains invalid data... not using ELCR\n"); |
1da177e4 | 304 | else { |
b1bfd5ea | 305 | pr_info("Using ELCR to identify PCI interrupts\n"); |
1da177e4 LT |
306 | ELCR_fallback = 1; |
307 | } | |
308 | } | |
309 | ||
310 | for (i = 0; i < 16; i++) { | |
311 | switch (mpc_default_type) { | |
312 | case 2: | |
313 | if (i == 0 || i == 13) | |
314 | continue; /* IRQ0 & IRQ13 not connected */ | |
df561f66 | 315 | fallthrough; |
1da177e4 LT |
316 | default: |
317 | if (i == 2) | |
318 | continue; /* IRQ2 is never connected */ | |
319 | } | |
320 | ||
321 | if (ELCR_fallback) { | |
322 | /* | |
323 | * If the ELCR indicates a level-sensitive interrupt, we | |
324 | * copy that information over to the MP table in the | |
325 | * irqflag field (level sensitive, active high polarity). | |
326 | */ | |
a09c5ec0 JK |
327 | if (ELCR_trigger(i)) { |
328 | intsrc.irqflag = MP_IRQTRIG_LEVEL | | |
329 | MP_IRQPOL_ACTIVE_HIGH; | |
330 | } else { | |
331 | intsrc.irqflag = MP_IRQTRIG_DEFAULT | | |
332 | MP_IRQPOL_DEFAULT; | |
333 | } | |
1da177e4 LT |
334 | } |
335 | ||
e253b396 JSR |
336 | intsrc.srcbusirq = i; |
337 | intsrc.dstirq = i ? i : 2; /* IRQ0 to INTIN2 */ | |
2d8009ba | 338 | mp_save_irq(&intsrc); |
1da177e4 LT |
339 | } |
340 | ||
e253b396 JSR |
341 | intsrc.irqtype = mp_ExtINT; |
342 | intsrc.srcbusirq = 0; | |
343 | intsrc.dstirq = 0; /* 8259A to INTIN0 */ | |
2d8009ba | 344 | mp_save_irq(&intsrc); |
1da177e4 LT |
345 | } |
346 | ||
61048c63 | 347 | |
39e00fe2 | 348 | static void __init construct_ioapic_table(int mpc_default_type) |
1da177e4 | 349 | { |
2b85b5fb | 350 | struct mpc_ioapic ioapic; |
00fb8606 | 351 | struct mpc_bus bus; |
1da177e4 | 352 | |
d4c715fa JSR |
353 | bus.type = MP_BUS; |
354 | bus.busid = 0; | |
1da177e4 | 355 | switch (mpc_default_type) { |
4ef81297 | 356 | default: |
b1bfd5ea | 357 | pr_err("???\nUnknown standard configuration %d\n", |
4ef81297 | 358 | mpc_default_type); |
df561f66 | 359 | fallthrough; |
4ef81297 AS |
360 | case 1: |
361 | case 5: | |
d4c715fa | 362 | memcpy(bus.bustype, "ISA ", 6); |
4ef81297 AS |
363 | break; |
364 | case 2: | |
365 | case 6: | |
366 | case 3: | |
d4c715fa | 367 | memcpy(bus.bustype, "EISA ", 6); |
4ef81297 | 368 | break; |
1da177e4 LT |
369 | } |
370 | MP_bus_info(&bus); | |
371 | if (mpc_default_type > 4) { | |
d4c715fa JSR |
372 | bus.busid = 1; |
373 | memcpy(bus.bustype, "PCI ", 6); | |
1da177e4 LT |
374 | MP_bus_info(&bus); |
375 | } | |
376 | ||
8f3e1df4 CG |
377 | ioapic.type = MP_IOAPIC; |
378 | ioapic.apicid = 2; | |
379 | ioapic.apicver = mpc_default_type > 4 ? 0x10 : 0x01; | |
380 | ioapic.flags = MPC_APIC_USABLE; | |
381 | ioapic.apicaddr = IO_APIC_DEFAULT_PHYS_BASE; | |
1da177e4 LT |
382 | MP_ioapic_info(&ioapic); |
383 | ||
384 | /* | |
385 | * We set up most of the low 16 IO-APIC pins according to MPS rules. | |
386 | */ | |
387 | construct_default_ioirq_mptable(mpc_default_type); | |
85cc35fa TG |
388 | } |
389 | #else | |
39e00fe2 | 390 | static inline void __init construct_ioapic_table(int mpc_default_type) { } |
61048c63 | 391 | #endif |
85cc35fa TG |
392 | |
393 | static inline void __init construct_default_ISA_mptable(int mpc_default_type) | |
394 | { | |
f4f21b71 | 395 | struct mpc_cpu processor; |
8fb2952b | 396 | struct mpc_lintsrc lintsrc; |
85cc35fa TG |
397 | int linttypes[2] = { mp_ExtINT, mp_NMI }; |
398 | int i; | |
399 | ||
400 | /* | |
401 | * local APIC has default address | |
402 | */ | |
403 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
404 | ||
405 | /* | |
406 | * 2 CPUs, numbered 0 & 1. | |
407 | */ | |
c4563826 | 408 | processor.type = MP_PROCESSOR; |
85cc35fa | 409 | /* Either an integrated APIC or a discrete 82489DX. */ |
c4563826 JSR |
410 | processor.apicver = mpc_default_type > 4 ? 0x10 : 0x01; |
411 | processor.cpuflag = CPU_ENABLED; | |
412 | processor.cpufeature = (boot_cpu_data.x86 << 8) | | |
b399151c | 413 | (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_stepping; |
16aaa537 | 414 | processor.featureflag = boot_cpu_data.x86_capability[CPUID_1_EDX]; |
c4563826 JSR |
415 | processor.reserved[0] = 0; |
416 | processor.reserved[1] = 0; | |
85cc35fa | 417 | for (i = 0; i < 2; i++) { |
c4563826 | 418 | processor.apicid = i; |
85cc35fa TG |
419 | MP_processor_info(&processor); |
420 | } | |
421 | ||
422 | construct_ioapic_table(mpc_default_type); | |
423 | ||
b5ced7cd | 424 | lintsrc.type = MP_LINTSRC; |
a09c5ec0 | 425 | lintsrc.irqflag = MP_IRQTRIG_DEFAULT | MP_IRQPOL_DEFAULT; |
b5ced7cd JSR |
426 | lintsrc.srcbusid = 0; |
427 | lintsrc.srcbusirq = 0; | |
428 | lintsrc.destapic = MP_APIC_ALL; | |
1da177e4 | 429 | for (i = 0; i < 2; i++) { |
b5ced7cd JSR |
430 | lintsrc.irqtype = linttypes[i]; |
431 | lintsrc.destapiclint = i; | |
1da177e4 LT |
432 | MP_lintsrc_info(&lintsrc); |
433 | } | |
434 | } | |
435 | ||
5997efb9 | 436 | static unsigned long mpf_base; |
ac5292e9 | 437 | static bool mpf_found; |
1da177e4 | 438 | |
8d4dd919 YL |
439 | static unsigned long __init get_mpc_size(unsigned long physptr) |
440 | { | |
441 | struct mpc_table *mpc; | |
442 | unsigned long size; | |
443 | ||
f7750a79 | 444 | mpc = early_memremap(physptr, PAGE_SIZE); |
8d4dd919 | 445 | size = mpc->length; |
f7750a79 | 446 | early_memunmap(mpc, PAGE_SIZE); |
8d4dd919 YL |
447 | apic_printk(APIC_VERBOSE, " mpc: %lx-%lx\n", physptr, physptr + size); |
448 | ||
449 | return size; | |
450 | } | |
451 | ||
0b3ba0c3 JSR |
452 | static int __init check_physptr(struct mpf_intel *mpf, unsigned int early) |
453 | { | |
454 | struct mpc_table *mpc; | |
455 | unsigned long size; | |
456 | ||
457 | size = get_mpc_size(mpf->physptr); | |
f7750a79 | 458 | mpc = early_memremap(mpf->physptr, size); |
5997efb9 | 459 | |
0b3ba0c3 JSR |
460 | /* |
461 | * Read the physical hardware table. Anything here will | |
462 | * override the defaults. | |
463 | */ | |
464 | if (!smp_read_mpc(mpc, early)) { | |
465 | #ifdef CONFIG_X86_LOCAL_APIC | |
466 | smp_found_config = 0; | |
467 | #endif | |
b1bfd5ea JL |
468 | pr_err("BIOS bug, MP table errors detected!...\n"); |
469 | pr_cont("... disabling SMP support. (tell your hw vendor)\n"); | |
f7750a79 | 470 | early_memunmap(mpc, size); |
0b3ba0c3 JSR |
471 | return -1; |
472 | } | |
f7750a79 | 473 | early_memunmap(mpc, size); |
0b3ba0c3 JSR |
474 | |
475 | if (early) | |
476 | return -1; | |
477 | ||
478 | #ifdef CONFIG_X86_IO_APIC | |
479 | /* | |
480 | * If there are no explicit MP IRQ entries, then we are | |
481 | * broken. We set up most of the low 16 IO-APIC pins to | |
482 | * ISA defaults and hope it will work. | |
483 | */ | |
484 | if (!mp_irq_entries) { | |
485 | struct mpc_bus bus; | |
486 | ||
b1bfd5ea | 487 | pr_err("BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n"); |
0b3ba0c3 JSR |
488 | |
489 | bus.type = MP_BUS; | |
490 | bus.busid = 0; | |
491 | memcpy(bus.bustype, "ISA ", 6); | |
492 | MP_bus_info(&bus); | |
493 | ||
494 | construct_default_ioirq_mptable(0); | |
495 | } | |
496 | #endif | |
497 | ||
498 | return 0; | |
499 | } | |
500 | ||
1da177e4 LT |
501 | /* |
502 | * Scan the memory blocks for an SMP configuration block. | |
503 | */ | |
b3f1b617 | 504 | void __init default_get_smp_config(unsigned int early) |
1da177e4 | 505 | { |
5997efb9 | 506 | struct mpf_intel *mpf; |
1da177e4 | 507 | |
a91bf718 BH |
508 | if (!smp_found_config) |
509 | return; | |
510 | ||
ac5292e9 | 511 | if (!mpf_found) |
69b88afa YL |
512 | return; |
513 | ||
888032cd AS |
514 | if (acpi_lapic && early) |
515 | return; | |
69b88afa | 516 | |
1da177e4 | 517 | /* |
69b88afa YL |
518 | * MPS doesn't support hyperthreading, aka only have |
519 | * thread 0 apic id in MPS table | |
1da177e4 | 520 | */ |
69b88afa | 521 | if (acpi_lapic && acpi_ioapic) |
1da177e4 | 522 | return; |
1da177e4 | 523 | |
5997efb9 TL |
524 | mpf = early_memremap(mpf_base, sizeof(*mpf)); |
525 | if (!mpf) { | |
526 | pr_err("MPTABLE: error mapping MP table\n"); | |
527 | return; | |
528 | } | |
529 | ||
b1bfd5ea JL |
530 | pr_info("Intel MultiProcessor Specification v1.%d\n", |
531 | mpf->specification); | |
b3e24164 | 532 | #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) |
1eb1b3b6 | 533 | if (mpf->feature2 & (1 << 7)) { |
b1bfd5ea | 534 | pr_info(" IMCR and PIC compatibility mode.\n"); |
1da177e4 LT |
535 | pic_mode = 1; |
536 | } else { | |
b1bfd5ea | 537 | pr_info(" Virtual Wire compatibility mode.\n"); |
1da177e4 LT |
538 | pic_mode = 0; |
539 | } | |
4421b1c8 | 540 | #endif |
1da177e4 LT |
541 | /* |
542 | * Now see if we need to read further. | |
543 | */ | |
5997efb9 | 544 | if (mpf->feature1) { |
888032cd AS |
545 | if (early) { |
546 | /* | |
547 | * local APIC has default address | |
548 | */ | |
549 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
e74bd969 | 550 | goto out; |
888032cd | 551 | } |
1da177e4 | 552 | |
b1bfd5ea | 553 | pr_info("Default MP configuration #%d\n", mpf->feature1); |
1eb1b3b6 | 554 | construct_default_ISA_mptable(mpf->feature1); |
1da177e4 | 555 | |
1eb1b3b6 | 556 | } else if (mpf->physptr) { |
e74bd969 DR |
557 | if (check_physptr(mpf, early)) |
558 | goto out; | |
1da177e4 LT |
559 | } else |
560 | BUG(); | |
561 | ||
888032cd | 562 | if (!early) |
b1bfd5ea | 563 | pr_info("Processors: %d\n", num_processors); |
1da177e4 LT |
564 | /* |
565 | * Only use the first configuration found. | |
566 | */ | |
e74bd969 | 567 | out: |
5997efb9 | 568 | early_memunmap(mpf, sizeof(*mpf)); |
1da177e4 LT |
569 | } |
570 | ||
b24c2a92 | 571 | static void __init smp_reserve_memory(struct mpf_intel *mpf) |
a6830278 | 572 | { |
24aa0788 | 573 | memblock_reserve(mpf->physptr, get_mpc_size(mpf->physptr)); |
a6830278 JSR |
574 | } |
575 | ||
b24c2a92 | 576 | static int __init smp_scan_config(unsigned long base, unsigned long length) |
1da177e4 | 577 | { |
5997efb9 | 578 | unsigned int *bp; |
41401db6 | 579 | struct mpf_intel *mpf; |
5997efb9 | 580 | int ret = 0; |
1da177e4 | 581 | |
365811d6 BH |
582 | apic_printk(APIC_VERBOSE, "Scan for SMP in [mem %#010lx-%#010lx]\n", |
583 | base, base + length - 1); | |
5d47a271 | 584 | BUILD_BUG_ON(sizeof(*mpf) != 16); |
1da177e4 LT |
585 | |
586 | while (length > 0) { | |
5997efb9 | 587 | bp = early_memremap(base, length); |
41401db6 | 588 | mpf = (struct mpf_intel *)bp; |
1da177e4 | 589 | if ((*bp == SMP_MAGIC_IDENT) && |
1eb1b3b6 | 590 | (mpf->length == 1) && |
4ef81297 | 591 | !mpf_checksum((unsigned char *)bp, 16) && |
1eb1b3b6 JSR |
592 | ((mpf->specification == 1) |
593 | || (mpf->specification == 4))) { | |
bab4b27c | 594 | #ifdef CONFIG_X86_LOCAL_APIC |
1da177e4 | 595 | smp_found_config = 1; |
bab4b27c | 596 | #endif |
5997efb9 | 597 | mpf_base = base; |
ac5292e9 | 598 | mpf_found = true; |
b1f006b6 | 599 | |
a3151724 MC |
600 | pr_info("found SMP MP-table at [mem %#010lx-%#010lx]\n", |
601 | base, base + sizeof(*mpf) - 1); | |
b1f006b6 | 602 | |
5997efb9 | 603 | memblock_reserve(base, sizeof(*mpf)); |
a6830278 | 604 | if (mpf->physptr) |
b24c2a92 | 605 | smp_reserve_memory(mpf); |
1da177e4 | 606 | |
5997efb9 | 607 | ret = 1; |
1da177e4 | 608 | } |
5997efb9 TL |
609 | early_memunmap(bp, length); |
610 | ||
611 | if (ret) | |
612 | break; | |
613 | ||
614 | base += 16; | |
1da177e4 LT |
615 | length -= 16; |
616 | } | |
5997efb9 | 617 | return ret; |
1da177e4 LT |
618 | } |
619 | ||
b24c2a92 | 620 | void __init default_find_smp_config(void) |
1da177e4 LT |
621 | { |
622 | unsigned int address; | |
623 | ||
624 | /* | |
625 | * FIXME: Linux assumes you have 640K of base ram.. | |
626 | * this continues the error... | |
627 | * | |
628 | * 1) Scan the bottom 1K for a signature | |
629 | * 2) Scan the top 1K of base RAM | |
630 | * 3) Scan the 64K of bios | |
631 | */ | |
b24c2a92 YL |
632 | if (smp_scan_config(0x0, 0x400) || |
633 | smp_scan_config(639 * 0x400, 0x400) || | |
634 | smp_scan_config(0xF0000, 0x10000)) | |
1da177e4 LT |
635 | return; |
636 | /* | |
637 | * If it is an SMP machine we should know now, unless the | |
bb8187d3 | 638 | * configuration is in an EISA bus machine with an |
1da177e4 LT |
639 | * extended bios data area. |
640 | * | |
641 | * there is a real-mode segmented pointer pointing to the | |
642 | * 4K EBDA area at 0x40E, calculate and scan it here. | |
643 | * | |
644 | * NOTE! There are Linux loaders that will corrupt the EBDA | |
645 | * area, and as such this kind of SMP config may be less | |
646 | * trustworthy, simply because the SMP table may have been | |
647 | * stomped on during early boot. These loaders are buggy and | |
648 | * should be fixed. | |
649 | * | |
650 | * MP1.4 SPEC states to only scan first 1K of 4K EBDA. | |
651 | */ | |
652 | ||
653 | address = get_bios_ebda(); | |
654 | if (address) | |
b24c2a92 | 655 | smp_scan_config(address, 0x400); |
888032cd AS |
656 | } |
657 | ||
2944e16b YL |
658 | #ifdef CONFIG_X86_IO_APIC |
659 | static u8 __initdata irq_used[MAX_IRQ_SOURCES]; | |
660 | ||
540d4e72 | 661 | static int __init get_MP_intsrc_index(struct mpc_intsrc *m) |
2944e16b YL |
662 | { |
663 | int i; | |
664 | ||
e253b396 | 665 | if (m->irqtype != mp_INT) |
2944e16b YL |
666 | return 0; |
667 | ||
a09c5ec0 | 668 | if (m->irqflag != (MP_IRQTRIG_LEVEL | MP_IRQPOL_ACTIVE_LOW)) |
2944e16b YL |
669 | return 0; |
670 | ||
671 | /* not legacy */ | |
672 | ||
673 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 674 | if (mp_irqs[i].irqtype != mp_INT) |
2944e16b YL |
675 | continue; |
676 | ||
a09c5ec0 JK |
677 | if (mp_irqs[i].irqflag != (MP_IRQTRIG_LEVEL | |
678 | MP_IRQPOL_ACTIVE_LOW)) | |
2944e16b YL |
679 | continue; |
680 | ||
c2c21745 | 681 | if (mp_irqs[i].srcbus != m->srcbus) |
2944e16b | 682 | continue; |
c2c21745 | 683 | if (mp_irqs[i].srcbusirq != m->srcbusirq) |
2944e16b YL |
684 | continue; |
685 | if (irq_used[i]) { | |
686 | /* already claimed */ | |
687 | return -2; | |
688 | } | |
689 | irq_used[i] = 1; | |
690 | return i; | |
691 | } | |
692 | ||
693 | /* not found */ | |
694 | return -1; | |
695 | } | |
696 | ||
697 | #define SPARE_SLOT_NUM 20 | |
698 | ||
540d4e72 | 699 | static struct mpc_intsrc __initdata *m_spare[SPARE_SLOT_NUM]; |
a6830278 | 700 | |
57592224 | 701 | static void __init check_irq_src(struct mpc_intsrc *m, int *nr_m_spare) |
a6830278 JSR |
702 | { |
703 | int i; | |
704 | ||
705 | apic_printk(APIC_VERBOSE, "OLD "); | |
0e3fa13f | 706 | print_mp_irq_info(m); |
a6830278 JSR |
707 | |
708 | i = get_MP_intsrc_index(m); | |
709 | if (i > 0) { | |
0e3fa13f | 710 | memcpy(m, &mp_irqs[i], sizeof(*m)); |
a6830278 JSR |
711 | apic_printk(APIC_VERBOSE, "NEW "); |
712 | print_mp_irq_info(&mp_irqs[i]); | |
713 | return; | |
714 | } | |
715 | if (!i) { | |
716 | /* legacy, do nothing */ | |
717 | return; | |
718 | } | |
719 | if (*nr_m_spare < SPARE_SLOT_NUM) { | |
720 | /* | |
721 | * not found (-1), or duplicated (-2) are invalid entries, | |
722 | * we need to use the slot later | |
723 | */ | |
724 | m_spare[*nr_m_spare] = m; | |
725 | *nr_m_spare += 1; | |
726 | } | |
727 | } | |
a6830278 | 728 | |
64d21fc1 | 729 | static int __init |
ee214558 | 730 | check_slot(unsigned long mpc_new_phys, unsigned long mpc_new_length, int count) |
a6830278 | 731 | { |
ee214558 YL |
732 | if (!mpc_new_phys || count <= mpc_new_length) { |
733 | WARN(1, "update_mptable: No spare slots (length: %x)\n", count); | |
734 | return -1; | |
a6830278 JSR |
735 | } |
736 | ||
9f1f1bfd | 737 | return 0; |
a6830278 | 738 | } |
cbb84c4c RM |
739 | #else /* CONFIG_X86_IO_APIC */ |
740 | static | |
741 | inline void __init check_irq_src(struct mpc_intsrc *m, int *nr_m_spare) {} | |
742 | #endif /* CONFIG_X86_IO_APIC */ | |
2944e16b | 743 | |
f29521e4 | 744 | static int __init replace_intsrc_all(struct mpc_table *mpc, |
2944e16b YL |
745 | unsigned long mpc_new_phys, |
746 | unsigned long mpc_new_length) | |
747 | { | |
748 | #ifdef CONFIG_X86_IO_APIC | |
749 | int i; | |
2944e16b | 750 | #endif |
2944e16b | 751 | int count = sizeof(*mpc); |
a6830278 | 752 | int nr_m_spare = 0; |
2944e16b YL |
753 | unsigned char *mpt = ((unsigned char *)mpc) + count; |
754 | ||
b1bfd5ea | 755 | pr_info("mpc_length %x\n", mpc->length); |
6c65da50 | 756 | while (count < mpc->length) { |
2944e16b YL |
757 | switch (*mpt) { |
758 | case MP_PROCESSOR: | |
a6830278 JSR |
759 | skip_entry(&mpt, &count, sizeof(struct mpc_cpu)); |
760 | break; | |
2944e16b | 761 | case MP_BUS: |
a6830278 JSR |
762 | skip_entry(&mpt, &count, sizeof(struct mpc_bus)); |
763 | break; | |
2944e16b | 764 | case MP_IOAPIC: |
a6830278 JSR |
765 | skip_entry(&mpt, &count, sizeof(struct mpc_ioapic)); |
766 | break; | |
2944e16b | 767 | case MP_INTSRC: |
c58603e8 | 768 | check_irq_src((struct mpc_intsrc *)mpt, &nr_m_spare); |
a6830278 JSR |
769 | skip_entry(&mpt, &count, sizeof(struct mpc_intsrc)); |
770 | break; | |
2944e16b | 771 | case MP_LINTSRC: |
a6830278 JSR |
772 | skip_entry(&mpt, &count, sizeof(struct mpc_lintsrc)); |
773 | break; | |
2944e16b YL |
774 | default: |
775 | /* wrong mptable */ | |
5a5737ea | 776 | smp_dump_mptable(mpc, mpt); |
2944e16b YL |
777 | goto out; |
778 | } | |
779 | } | |
780 | ||
781 | #ifdef CONFIG_X86_IO_APIC | |
782 | for (i = 0; i < mp_irq_entries; i++) { | |
783 | if (irq_used[i]) | |
784 | continue; | |
785 | ||
c2c21745 | 786 | if (mp_irqs[i].irqtype != mp_INT) |
2944e16b YL |
787 | continue; |
788 | ||
a09c5ec0 JK |
789 | if (mp_irqs[i].irqflag != (MP_IRQTRIG_LEVEL | |
790 | MP_IRQPOL_ACTIVE_LOW)) | |
2944e16b YL |
791 | continue; |
792 | ||
793 | if (nr_m_spare > 0) { | |
82034d6f | 794 | apic_printk(APIC_VERBOSE, "*NEW* found\n"); |
2944e16b | 795 | nr_m_spare--; |
0e3fa13f | 796 | memcpy(m_spare[nr_m_spare], &mp_irqs[i], sizeof(mp_irqs[i])); |
2944e16b YL |
797 | m_spare[nr_m_spare] = NULL; |
798 | } else { | |
540d4e72 JSR |
799 | struct mpc_intsrc *m = (struct mpc_intsrc *)mpt; |
800 | count += sizeof(struct mpc_intsrc); | |
ee214558 | 801 | if (check_slot(mpc_new_phys, mpc_new_length, count) < 0) |
a6830278 | 802 | goto out; |
0e3fa13f | 803 | memcpy(m, &mp_irqs[i], sizeof(*m)); |
6c65da50 | 804 | mpc->length = count; |
540d4e72 | 805 | mpt += sizeof(struct mpc_intsrc); |
2944e16b YL |
806 | } |
807 | print_mp_irq_info(&mp_irqs[i]); | |
808 | } | |
809 | #endif | |
810 | out: | |
811 | /* update checksum */ | |
6c65da50 JSR |
812 | mpc->checksum = 0; |
813 | mpc->checksum -= mpf_checksum((unsigned char *)mpc, mpc->length); | |
2944e16b YL |
814 | |
815 | return 0; | |
816 | } | |
817 | ||
f1bdb523 | 818 | int enable_update_mptable; |
fcfa146e | 819 | |
2944e16b YL |
820 | static int __init update_mptable_setup(char *str) |
821 | { | |
822 | enable_update_mptable = 1; | |
629e15d2 YL |
823 | #ifdef CONFIG_PCI |
824 | pci_routeirq = 1; | |
825 | #endif | |
2944e16b YL |
826 | return 0; |
827 | } | |
828 | early_param("update_mptable", update_mptable_setup); | |
829 | ||
830 | static unsigned long __initdata mpc_new_phys; | |
831 | static unsigned long mpc_new_length __initdata = 4096; | |
832 | ||
833 | /* alloc_mptable or alloc_mptable=4k */ | |
834 | static int __initdata alloc_mptable; | |
835 | static int __init parse_alloc_mptable_opt(char *p) | |
836 | { | |
837 | enable_update_mptable = 1; | |
629e15d2 YL |
838 | #ifdef CONFIG_PCI |
839 | pci_routeirq = 1; | |
840 | #endif | |
2944e16b YL |
841 | alloc_mptable = 1; |
842 | if (!p) | |
843 | return 0; | |
844 | mpc_new_length = memparse(p, &p); | |
845 | return 0; | |
846 | } | |
847 | early_param("alloc_mptable", parse_alloc_mptable_opt); | |
848 | ||
5da217ca | 849 | void __init e820__memblock_alloc_reserved_mpc_new(void) |
2944e16b | 850 | { |
ab5d140b | 851 | if (enable_update_mptable && alloc_mptable) |
5da217ca | 852 | mpc_new_phys = e820__memblock_alloc_reserved(mpc_new_length, 4); |
2944e16b YL |
853 | } |
854 | ||
855 | static int __init update_mp_table(void) | |
856 | { | |
857 | char str[16]; | |
858 | char oem[10]; | |
41401db6 | 859 | struct mpf_intel *mpf; |
f29521e4 | 860 | struct mpc_table *mpc, *mpc_new; |
5997efb9 | 861 | unsigned long size; |
2944e16b YL |
862 | |
863 | if (!enable_update_mptable) | |
864 | return 0; | |
865 | ||
ac5292e9 | 866 | if (!mpf_found) |
5997efb9 TL |
867 | return 0; |
868 | ||
869 | mpf = early_memremap(mpf_base, sizeof(*mpf)); | |
870 | if (!mpf) { | |
871 | pr_err("MPTABLE: mpf early_memremap() failed\n"); | |
2944e16b | 872 | return 0; |
5997efb9 | 873 | } |
2944e16b YL |
874 | |
875 | /* | |
876 | * Now see if we need to go further. | |
877 | */ | |
5997efb9 TL |
878 | if (mpf->feature1) |
879 | goto do_unmap_mpf; | |
2944e16b | 880 | |
1eb1b3b6 | 881 | if (!mpf->physptr) |
5997efb9 | 882 | goto do_unmap_mpf; |
2944e16b | 883 | |
5997efb9 TL |
884 | size = get_mpc_size(mpf->physptr); |
885 | mpc = early_memremap(mpf->physptr, size); | |
886 | if (!mpc) { | |
887 | pr_err("MPTABLE: mpc early_memremap() failed\n"); | |
888 | goto do_unmap_mpf; | |
889 | } | |
2944e16b YL |
890 | |
891 | if (!smp_check_mpc(mpc, oem, str)) | |
5997efb9 | 892 | goto do_unmap_mpc; |
2944e16b | 893 | |
5997efb9 | 894 | pr_info("mpf: %llx\n", (u64)mpf_base); |
b1bfd5ea | 895 | pr_info("physptr: %x\n", mpf->physptr); |
2944e16b | 896 | |
6c65da50 | 897 | if (mpc_new_phys && mpc->length > mpc_new_length) { |
2944e16b | 898 | mpc_new_phys = 0; |
b1bfd5ea JL |
899 | pr_info("mpc_new_length is %ld, please use alloc_mptable=8k\n", |
900 | mpc_new_length); | |
2944e16b YL |
901 | } |
902 | ||
903 | if (!mpc_new_phys) { | |
904 | unsigned char old, new; | |
0d2eb44f | 905 | /* check if we can change the position */ |
6c65da50 JSR |
906 | mpc->checksum = 0; |
907 | old = mpf_checksum((unsigned char *)mpc, mpc->length); | |
908 | mpc->checksum = 0xff; | |
909 | new = mpf_checksum((unsigned char *)mpc, mpc->length); | |
2944e16b | 910 | if (old == new) { |
b1bfd5ea | 911 | pr_info("mpc is readonly, please try alloc_mptable instead\n"); |
5997efb9 | 912 | goto do_unmap_mpc; |
2944e16b | 913 | } |
b1bfd5ea | 914 | pr_info("use in-position replacing\n"); |
2944e16b | 915 | } else { |
5997efb9 TL |
916 | mpc_new = early_memremap(mpc_new_phys, mpc_new_length); |
917 | if (!mpc_new) { | |
918 | pr_err("MPTABLE: new mpc early_memremap() failed\n"); | |
919 | goto do_unmap_mpc; | |
920 | } | |
1eb1b3b6 | 921 | mpf->physptr = mpc_new_phys; |
6c65da50 | 922 | memcpy(mpc_new, mpc, mpc->length); |
5997efb9 | 923 | early_memunmap(mpc, size); |
2944e16b | 924 | mpc = mpc_new; |
5997efb9 | 925 | size = mpc_new_length; |
2944e16b | 926 | /* check if we can modify that */ |
1eb1b3b6 | 927 | if (mpc_new_phys - mpf->physptr) { |
41401db6 | 928 | struct mpf_intel *mpf_new; |
2944e16b | 929 | /* steal 16 bytes from [0, 1k) */ |
5997efb9 TL |
930 | mpf_new = early_memremap(0x400 - 16, sizeof(*mpf_new)); |
931 | if (!mpf_new) { | |
932 | pr_err("MPTABLE: new mpf early_memremap() failed\n"); | |
933 | goto do_unmap_mpc; | |
934 | } | |
b1bfd5ea | 935 | pr_info("mpf new: %x\n", 0x400 - 16); |
2944e16b | 936 | memcpy(mpf_new, mpf, 16); |
5997efb9 | 937 | early_memunmap(mpf, sizeof(*mpf)); |
2944e16b | 938 | mpf = mpf_new; |
1eb1b3b6 | 939 | mpf->physptr = mpc_new_phys; |
2944e16b | 940 | } |
1eb1b3b6 JSR |
941 | mpf->checksum = 0; |
942 | mpf->checksum -= mpf_checksum((unsigned char *)mpf, 16); | |
b1bfd5ea | 943 | pr_info("physptr new: %x\n", mpf->physptr); |
2944e16b YL |
944 | } |
945 | ||
946 | /* | |
947 | * only replace the one with mp_INT and | |
948 | * MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, | |
949 | * already in mp_irqs , stored by ... and mp_config_acpi_gsi, | |
950 | * may need pci=routeirq for all coverage | |
951 | */ | |
952 | replace_intsrc_all(mpc, mpc_new_phys, mpc_new_length); | |
953 | ||
5997efb9 TL |
954 | do_unmap_mpc: |
955 | early_memunmap(mpc, size); | |
956 | ||
957 | do_unmap_mpf: | |
958 | early_memunmap(mpf, sizeof(*mpf)); | |
959 | ||
2944e16b YL |
960 | return 0; |
961 | } | |
962 | ||
963 | late_initcall(update_mp_table); |