Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
11113f84 | 2 | * Intel Multiprocessor Specification 1.1 and 1.4 |
1da177e4 LT |
3 | * compliant MP-table parsing routines. |
4 | * | |
87c6fe26 | 5 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 6 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
85bdddec | 7 | * (c) 2008 Alexey Starikovskiy <astarikovskiy@suse.de> |
1da177e4 LT |
8 | */ |
9 | ||
10 | #include <linux/mm.h> | |
1da177e4 | 11 | #include <linux/init.h> |
1da177e4 | 12 | #include <linux/delay.h> |
1da177e4 | 13 | #include <linux/bootmem.h> |
72d7c3b3 | 14 | #include <linux/memblock.h> |
1da177e4 LT |
15 | #include <linux/kernel_stat.h> |
16 | #include <linux/mc146818rtc.h> | |
17 | #include <linux/bitops.h> | |
85bdddec AS |
18 | #include <linux/acpi.h> |
19 | #include <linux/module.h> | |
103ceffb | 20 | #include <linux/smp.h> |
629e15d2 | 21 | #include <linux/pci.h> |
1da177e4 | 22 | |
1da177e4 LT |
23 | #include <asm/mtrr.h> |
24 | #include <asm/mpspec.h> | |
85bdddec | 25 | #include <asm/pgalloc.h> |
1da177e4 | 26 | #include <asm/io_apic.h> |
85bdddec | 27 | #include <asm/proto.h> |
ce3fe6b2 | 28 | #include <asm/bios_ebda.h> |
2944e16b | 29 | #include <asm/e820.h> |
3c9cb6de | 30 | #include <asm/setup.h> |
4884d8e6 | 31 | #include <asm/smp.h> |
1da177e4 | 32 | |
7b6aa335 | 33 | #include <asm/apic.h> |
1da177e4 LT |
34 | /* |
35 | * Checksum an MP configuration block. | |
36 | */ | |
37 | ||
38 | static int __init mpf_checksum(unsigned char *mp, int len) | |
39 | { | |
40 | int sum = 0; | |
41 | ||
42 | while (len--) | |
43 | sum += *mp++; | |
44 | ||
45 | return sum & 0xFF; | |
46 | } | |
47 | ||
fd6c6661 TG |
48 | int __init default_mpc_apic_id(struct mpc_cpu *m) |
49 | { | |
50 | return m->apicid; | |
51 | } | |
52 | ||
f4f21b71 | 53 | static void __init MP_processor_info(struct mpc_cpu *m) |
c853c676 AS |
54 | { |
55 | int apicid; | |
746f2244 | 56 | char *bootup_cpu = ""; |
c853c676 | 57 | |
c4563826 | 58 | if (!(m->cpuflag & CPU_ENABLED)) { |
7b1292e2 | 59 | disabled_cpus++; |
1da177e4 | 60 | return; |
7b1292e2 | 61 | } |
64898a8b | 62 | |
fd6c6661 | 63 | apicid = x86_init.mpparse.mpc_apic_id(m); |
64898a8b | 64 | |
c4563826 | 65 | if (m->cpuflag & CPU_BOOTPROCESSOR) { |
746f2244 | 66 | bootup_cpu = " (Bootup-CPU)"; |
c4563826 | 67 | boot_cpu_physical_apicid = m->apicid; |
1da177e4 LT |
68 | } |
69 | ||
c4563826 JSR |
70 | printk(KERN_INFO "Processor #%d%s\n", m->apicid, bootup_cpu); |
71 | generic_processor_info(apicid, m->apicver); | |
1da177e4 LT |
72 | } |
73 | ||
85cc35fa | 74 | #ifdef CONFIG_X86_IO_APIC |
90e1c696 | 75 | void __init default_mpc_oem_bus_info(struct mpc_bus *m, char *str) |
1da177e4 | 76 | { |
d4c715fa | 77 | memcpy(str, m->bustype, 6); |
1da177e4 | 78 | str[6] = 0; |
90e1c696 TG |
79 | apic_printk(APIC_VERBOSE, "Bus #%d is %s\n", m->busid, str); |
80 | } | |
1da177e4 | 81 | |
90e1c696 TG |
82 | static void __init MP_bus_info(struct mpc_bus *m) |
83 | { | |
84 | char str[7]; | |
1da177e4 | 85 | |
90e1c696 | 86 | x86_init.mpparse.mpc_oem_bus_info(m, str); |
1da177e4 | 87 | |
5e4edbb7 | 88 | #if MAX_MP_BUSSES < 256 |
d4c715fa | 89 | if (m->busid >= MAX_MP_BUSSES) { |
c0ec31ad | 90 | printk(KERN_WARNING "MP table busid value (%d) for bustype %s " |
4ef81297 | 91 | " is too large, max. supported is %d\n", |
d4c715fa | 92 | m->busid, str, MAX_MP_BUSSES - 1); |
c0ec31ad RD |
93 | return; |
94 | } | |
5e4edbb7 | 95 | #endif |
c0ec31ad | 96 | |
9e686668 | 97 | set_bit(m->busid, mp_bus_not_pci); |
f8924e77 | 98 | if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA) - 1) == 0) { |
bb8187d3 | 99 | #ifdef CONFIG_EISA |
d4c715fa | 100 | mp_bus_id_to_type[m->busid] = MP_BUS_ISA; |
f8924e77 AS |
101 | #endif |
102 | } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI) - 1) == 0) { | |
52fdb568 TG |
103 | if (x86_init.mpparse.mpc_oem_pci_bus) |
104 | x86_init.mpparse.mpc_oem_pci_bus(m); | |
64898a8b | 105 | |
d4c715fa | 106 | clear_bit(m->busid, mp_bus_not_pci); |
bb8187d3 | 107 | #ifdef CONFIG_EISA |
d4c715fa | 108 | mp_bus_id_to_type[m->busid] = MP_BUS_PCI; |
4ef81297 | 109 | } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA) - 1) == 0) { |
d4c715fa | 110 | mp_bus_id_to_type[m->busid] = MP_BUS_EISA; |
c0a282c2 | 111 | #endif |
f8924e77 AS |
112 | } else |
113 | printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str); | |
1da177e4 | 114 | } |
61048c63 | 115 | |
2b85b5fb | 116 | static void __init MP_ioapic_info(struct mpc_ioapic *m) |
1da177e4 | 117 | { |
0e3fa13f FT |
118 | if (m->flags & MPC_APIC_USABLE) |
119 | mp_register_ioapic(m->apicid, m->apicaddr, gsi_top); | |
2944e16b YL |
120 | } |
121 | ||
c2c21745 | 122 | static void __init print_mp_irq_info(struct mpc_intsrc *mp_irq) |
2944e16b | 123 | { |
eeb0d7d1 | 124 | apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x," |
2944e16b | 125 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", |
c2c21745 JSR |
126 | mp_irq->irqtype, mp_irq->irqflag & 3, |
127 | (mp_irq->irqflag >> 2) & 3, mp_irq->srcbus, | |
128 | mp_irq->srcbusirq, mp_irq->dstapic, mp_irq->dstirq); | |
2944e16b YL |
129 | } |
130 | ||
a6830278 JSR |
131 | #else /* CONFIG_X86_IO_APIC */ |
132 | static inline void __init MP_bus_info(struct mpc_bus *m) {} | |
133 | static inline void __init MP_ioapic_info(struct mpc_ioapic *m) {} | |
a6830278 | 134 | #endif /* CONFIG_X86_IO_APIC */ |
1da177e4 | 135 | |
8fb2952b | 136 | static void __init MP_lintsrc_info(struct mpc_lintsrc *m) |
1da177e4 | 137 | { |
eeb0d7d1 | 138 | apic_printk(APIC_VERBOSE, "Lint: type %d, pol %d, trig %d, bus %02x," |
1da177e4 | 139 | " IRQ %02x, APIC ID %x, APIC LINT %02x\n", |
b5ced7cd JSR |
140 | m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbusid, |
141 | m->srcbusirq, m->destapic, m->destapiclint); | |
1da177e4 LT |
142 | } |
143 | ||
1da177e4 LT |
144 | /* |
145 | * Read/parse the MPC | |
146 | */ | |
f29521e4 | 147 | static int __init smp_check_mpc(struct mpc_table *mpc, char *oem, char *str) |
1da177e4 | 148 | { |
1da177e4 | 149 | |
6c65da50 | 150 | if (memcmp(mpc->signature, MPC_SIGNATURE, 4)) { |
e950bea8 | 151 | printk(KERN_ERR "MPTABLE: bad signature [%c%c%c%c]!\n", |
6c65da50 JSR |
152 | mpc->signature[0], mpc->signature[1], |
153 | mpc->signature[2], mpc->signature[3]); | |
1da177e4 LT |
154 | return 0; |
155 | } | |
6c65da50 | 156 | if (mpf_checksum((unsigned char *)mpc, mpc->length)) { |
e950bea8 | 157 | printk(KERN_ERR "MPTABLE: checksum error!\n"); |
1da177e4 LT |
158 | return 0; |
159 | } | |
6c65da50 | 160 | if (mpc->spec != 0x01 && mpc->spec != 0x04) { |
e950bea8 | 161 | printk(KERN_ERR "MPTABLE: bad table version (%d)!!\n", |
6c65da50 | 162 | mpc->spec); |
1da177e4 LT |
163 | return 0; |
164 | } | |
6c65da50 | 165 | if (!mpc->lapic) { |
e950bea8 | 166 | printk(KERN_ERR "MPTABLE: null local APIC address!\n"); |
1da177e4 LT |
167 | return 0; |
168 | } | |
6c65da50 | 169 | memcpy(oem, mpc->oem, 8); |
4ef81297 | 170 | oem[8] = 0; |
11a62a05 | 171 | printk(KERN_INFO "MPTABLE: OEM ID: %s\n", oem); |
1da177e4 | 172 | |
6c65da50 | 173 | memcpy(str, mpc->productid, 12); |
4ef81297 | 174 | str[12] = 0; |
1da177e4 | 175 | |
11a62a05 | 176 | printk(KERN_INFO "MPTABLE: Product ID: %s\n", str); |
1da177e4 | 177 | |
6c65da50 | 178 | printk(KERN_INFO "MPTABLE: APIC at: 0x%X\n", mpc->lapic); |
1da177e4 | 179 | |
2944e16b YL |
180 | return 1; |
181 | } | |
182 | ||
a6830278 JSR |
183 | static void skip_entry(unsigned char **ptr, int *count, int size) |
184 | { | |
185 | *ptr += size; | |
186 | *count += size; | |
187 | } | |
188 | ||
5a5737ea JSR |
189 | static void __init smp_dump_mptable(struct mpc_table *mpc, unsigned char *mpt) |
190 | { | |
191 | printk(KERN_ERR "Your mptable is wrong, contact your HW vendor!\n" | |
192 | "type %x\n", *mpt); | |
193 | print_hex_dump(KERN_ERR, " ", DUMP_PREFIX_ADDRESS, 16, | |
194 | 1, mpc, mpc->length, 1); | |
195 | } | |
196 | ||
72302142 TG |
197 | void __init default_smp_read_mpc_oem(struct mpc_table *mpc) { } |
198 | ||
f29521e4 | 199 | static int __init smp_read_mpc(struct mpc_table *mpc, unsigned early) |
2944e16b YL |
200 | { |
201 | char str[16]; | |
202 | char oem[10]; | |
203 | ||
204 | int count = sizeof(*mpc); | |
205 | unsigned char *mpt = ((unsigned char *)mpc) + count; | |
206 | ||
207 | if (!smp_check_mpc(mpc, oem, str)) | |
208 | return 0; | |
209 | ||
210 | #ifdef CONFIG_X86_32 | |
9c764247 | 211 | generic_mps_oem_check(mpc, oem, str); |
2944e16b | 212 | #endif |
f1157141 | 213 | /* Initialize the lapic mapping */ |
1da177e4 | 214 | if (!acpi_lapic) |
f1157141 | 215 | register_lapic_address(mpc->lapic); |
1da177e4 | 216 | |
888032cd AS |
217 | if (early) |
218 | return 1; | |
219 | ||
72302142 TG |
220 | if (mpc->oemptr) |
221 | x86_init.mpparse.smp_read_mpc_oem(mpc); | |
64898a8b | 222 | |
1da177e4 | 223 | /* |
4ef81297 | 224 | * Now process the configuration blocks. |
1da177e4 | 225 | */ |
f4848472 | 226 | x86_init.mpparse.mpc_record(0); |
64898a8b | 227 | |
6c65da50 | 228 | while (count < mpc->length) { |
4ef81297 AS |
229 | switch (*mpt) { |
230 | case MP_PROCESSOR: | |
a6830278 JSR |
231 | /* ACPI may have already provided this data */ |
232 | if (!acpi_lapic) | |
c58603e8 | 233 | MP_processor_info((struct mpc_cpu *)mpt); |
a6830278 JSR |
234 | skip_entry(&mpt, &count, sizeof(struct mpc_cpu)); |
235 | break; | |
4ef81297 | 236 | case MP_BUS: |
c58603e8 | 237 | MP_bus_info((struct mpc_bus *)mpt); |
a6830278 JSR |
238 | skip_entry(&mpt, &count, sizeof(struct mpc_bus)); |
239 | break; | |
4ef81297 | 240 | case MP_IOAPIC: |
c58603e8 | 241 | MP_ioapic_info((struct mpc_ioapic *)mpt); |
a6830278 JSR |
242 | skip_entry(&mpt, &count, sizeof(struct mpc_ioapic)); |
243 | break; | |
4ef81297 | 244 | case MP_INTSRC: |
2d8009ba | 245 | mp_save_irq((struct mpc_intsrc *)mpt); |
a6830278 JSR |
246 | skip_entry(&mpt, &count, sizeof(struct mpc_intsrc)); |
247 | break; | |
4ef81297 | 248 | case MP_LINTSRC: |
c58603e8 | 249 | MP_lintsrc_info((struct mpc_lintsrc *)mpt); |
a6830278 JSR |
250 | skip_entry(&mpt, &count, sizeof(struct mpc_lintsrc)); |
251 | break; | |
4ef81297 | 252 | default: |
711554db | 253 | /* wrong mptable */ |
5a5737ea | 254 | smp_dump_mptable(mpc, mpt); |
6c65da50 | 255 | count = mpc->length; |
711554db | 256 | break; |
1da177e4 | 257 | } |
f4848472 | 258 | x86_init.mpparse.mpc_record(1); |
1da177e4 | 259 | } |
e0da3364 | 260 | |
1da177e4 | 261 | if (!num_processors) |
e950bea8 | 262 | printk(KERN_ERR "MPTABLE: no processors registered!\n"); |
1da177e4 LT |
263 | return num_processors; |
264 | } | |
265 | ||
61048c63 AS |
266 | #ifdef CONFIG_X86_IO_APIC |
267 | ||
1da177e4 LT |
268 | static int __init ELCR_trigger(unsigned int irq) |
269 | { | |
270 | unsigned int port; | |
271 | ||
272 | port = 0x4d0 + (irq >> 3); | |
273 | return (inb(port) >> (irq & 7)) & 1; | |
274 | } | |
275 | ||
276 | static void __init construct_default_ioirq_mptable(int mpc_default_type) | |
277 | { | |
540d4e72 | 278 | struct mpc_intsrc intsrc; |
1da177e4 LT |
279 | int i; |
280 | int ELCR_fallback = 0; | |
281 | ||
e253b396 JSR |
282 | intsrc.type = MP_INTSRC; |
283 | intsrc.irqflag = 0; /* conforming */ | |
284 | intsrc.srcbus = 0; | |
d5371430 | 285 | intsrc.dstapic = mpc_ioapic_id(0); |
1da177e4 | 286 | |
e253b396 | 287 | intsrc.irqtype = mp_INT; |
1da177e4 LT |
288 | |
289 | /* | |
290 | * If true, we have an ISA/PCI system with no IRQ entries | |
291 | * in the MP table. To prevent the PCI interrupts from being set up | |
292 | * incorrectly, we try to use the ELCR. The sanity check to see if | |
293 | * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can | |
294 | * never be level sensitive, so we simply see if the ELCR agrees. | |
295 | * If it does, we assume it's valid. | |
296 | */ | |
297 | if (mpc_default_type == 5) { | |
62441bf1 AS |
298 | printk(KERN_INFO "ISA/PCI bus type with no IRQ information... " |
299 | "falling back to ELCR\n"); | |
1da177e4 | 300 | |
62441bf1 AS |
301 | if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || |
302 | ELCR_trigger(13)) | |
303 | printk(KERN_ERR "ELCR contains invalid data... " | |
304 | "not using ELCR\n"); | |
1da177e4 | 305 | else { |
4ef81297 AS |
306 | printk(KERN_INFO |
307 | "Using ELCR to identify PCI interrupts\n"); | |
1da177e4 LT |
308 | ELCR_fallback = 1; |
309 | } | |
310 | } | |
311 | ||
312 | for (i = 0; i < 16; i++) { | |
313 | switch (mpc_default_type) { | |
314 | case 2: | |
315 | if (i == 0 || i == 13) | |
316 | continue; /* IRQ0 & IRQ13 not connected */ | |
317 | /* fall through */ | |
318 | default: | |
319 | if (i == 2) | |
320 | continue; /* IRQ2 is never connected */ | |
321 | } | |
322 | ||
323 | if (ELCR_fallback) { | |
324 | /* | |
325 | * If the ELCR indicates a level-sensitive interrupt, we | |
326 | * copy that information over to the MP table in the | |
327 | * irqflag field (level sensitive, active high polarity). | |
328 | */ | |
329 | if (ELCR_trigger(i)) | |
e253b396 | 330 | intsrc.irqflag = 13; |
1da177e4 | 331 | else |
e253b396 | 332 | intsrc.irqflag = 0; |
1da177e4 LT |
333 | } |
334 | ||
e253b396 JSR |
335 | intsrc.srcbusirq = i; |
336 | intsrc.dstirq = i ? i : 2; /* IRQ0 to INTIN2 */ | |
2d8009ba | 337 | mp_save_irq(&intsrc); |
1da177e4 LT |
338 | } |
339 | ||
e253b396 JSR |
340 | intsrc.irqtype = mp_ExtINT; |
341 | intsrc.srcbusirq = 0; | |
342 | intsrc.dstirq = 0; /* 8259A to INTIN0 */ | |
2d8009ba | 343 | mp_save_irq(&intsrc); |
1da177e4 LT |
344 | } |
345 | ||
61048c63 | 346 | |
39e00fe2 | 347 | static void __init construct_ioapic_table(int mpc_default_type) |
1da177e4 | 348 | { |
2b85b5fb | 349 | struct mpc_ioapic ioapic; |
00fb8606 | 350 | struct mpc_bus bus; |
1da177e4 | 351 | |
d4c715fa JSR |
352 | bus.type = MP_BUS; |
353 | bus.busid = 0; | |
1da177e4 | 354 | switch (mpc_default_type) { |
4ef81297 | 355 | default: |
62441bf1 | 356 | printk(KERN_ERR "???\nUnknown standard configuration %d\n", |
4ef81297 AS |
357 | mpc_default_type); |
358 | /* fall through */ | |
359 | case 1: | |
360 | case 5: | |
d4c715fa | 361 | memcpy(bus.bustype, "ISA ", 6); |
4ef81297 AS |
362 | break; |
363 | case 2: | |
364 | case 6: | |
365 | case 3: | |
d4c715fa | 366 | memcpy(bus.bustype, "EISA ", 6); |
4ef81297 | 367 | break; |
1da177e4 LT |
368 | } |
369 | MP_bus_info(&bus); | |
370 | if (mpc_default_type > 4) { | |
d4c715fa JSR |
371 | bus.busid = 1; |
372 | memcpy(bus.bustype, "PCI ", 6); | |
1da177e4 LT |
373 | MP_bus_info(&bus); |
374 | } | |
375 | ||
8f3e1df4 CG |
376 | ioapic.type = MP_IOAPIC; |
377 | ioapic.apicid = 2; | |
378 | ioapic.apicver = mpc_default_type > 4 ? 0x10 : 0x01; | |
379 | ioapic.flags = MPC_APIC_USABLE; | |
380 | ioapic.apicaddr = IO_APIC_DEFAULT_PHYS_BASE; | |
1da177e4 LT |
381 | MP_ioapic_info(&ioapic); |
382 | ||
383 | /* | |
384 | * We set up most of the low 16 IO-APIC pins according to MPS rules. | |
385 | */ | |
386 | construct_default_ioirq_mptable(mpc_default_type); | |
85cc35fa TG |
387 | } |
388 | #else | |
39e00fe2 | 389 | static inline void __init construct_ioapic_table(int mpc_default_type) { } |
61048c63 | 390 | #endif |
85cc35fa TG |
391 | |
392 | static inline void __init construct_default_ISA_mptable(int mpc_default_type) | |
393 | { | |
f4f21b71 | 394 | struct mpc_cpu processor; |
8fb2952b | 395 | struct mpc_lintsrc lintsrc; |
85cc35fa TG |
396 | int linttypes[2] = { mp_ExtINT, mp_NMI }; |
397 | int i; | |
398 | ||
399 | /* | |
400 | * local APIC has default address | |
401 | */ | |
402 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
403 | ||
404 | /* | |
405 | * 2 CPUs, numbered 0 & 1. | |
406 | */ | |
c4563826 | 407 | processor.type = MP_PROCESSOR; |
85cc35fa | 408 | /* Either an integrated APIC or a discrete 82489DX. */ |
c4563826 JSR |
409 | processor.apicver = mpc_default_type > 4 ? 0x10 : 0x01; |
410 | processor.cpuflag = CPU_ENABLED; | |
411 | processor.cpufeature = (boot_cpu_data.x86 << 8) | | |
85cc35fa | 412 | (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask; |
c4563826 JSR |
413 | processor.featureflag = boot_cpu_data.x86_capability[0]; |
414 | processor.reserved[0] = 0; | |
415 | processor.reserved[1] = 0; | |
85cc35fa | 416 | for (i = 0; i < 2; i++) { |
c4563826 | 417 | processor.apicid = i; |
85cc35fa TG |
418 | MP_processor_info(&processor); |
419 | } | |
420 | ||
421 | construct_ioapic_table(mpc_default_type); | |
422 | ||
b5ced7cd JSR |
423 | lintsrc.type = MP_LINTSRC; |
424 | lintsrc.irqflag = 0; /* conforming */ | |
425 | lintsrc.srcbusid = 0; | |
426 | lintsrc.srcbusirq = 0; | |
427 | lintsrc.destapic = MP_APIC_ALL; | |
1da177e4 | 428 | for (i = 0; i < 2; i++) { |
b5ced7cd JSR |
429 | lintsrc.irqtype = linttypes[i]; |
430 | lintsrc.destapiclint = i; | |
1da177e4 LT |
431 | MP_lintsrc_info(&lintsrc); |
432 | } | |
433 | } | |
434 | ||
41401db6 | 435 | static struct mpf_intel *mpf_found; |
1da177e4 | 436 | |
8d4dd919 YL |
437 | static unsigned long __init get_mpc_size(unsigned long physptr) |
438 | { | |
439 | struct mpc_table *mpc; | |
440 | unsigned long size; | |
441 | ||
442 | mpc = early_ioremap(physptr, PAGE_SIZE); | |
443 | size = mpc->length; | |
444 | early_iounmap(mpc, PAGE_SIZE); | |
445 | apic_printk(APIC_VERBOSE, " mpc: %lx-%lx\n", physptr, physptr + size); | |
446 | ||
447 | return size; | |
448 | } | |
449 | ||
0b3ba0c3 JSR |
450 | static int __init check_physptr(struct mpf_intel *mpf, unsigned int early) |
451 | { | |
452 | struct mpc_table *mpc; | |
453 | unsigned long size; | |
454 | ||
455 | size = get_mpc_size(mpf->physptr); | |
456 | mpc = early_ioremap(mpf->physptr, size); | |
457 | /* | |
458 | * Read the physical hardware table. Anything here will | |
459 | * override the defaults. | |
460 | */ | |
461 | if (!smp_read_mpc(mpc, early)) { | |
462 | #ifdef CONFIG_X86_LOCAL_APIC | |
463 | smp_found_config = 0; | |
464 | #endif | |
465 | printk(KERN_ERR "BIOS bug, MP table errors detected!...\n" | |
466 | "... disabling SMP support. (tell your hw vendor)\n"); | |
467 | early_iounmap(mpc, size); | |
468 | return -1; | |
469 | } | |
470 | early_iounmap(mpc, size); | |
471 | ||
472 | if (early) | |
473 | return -1; | |
474 | ||
475 | #ifdef CONFIG_X86_IO_APIC | |
476 | /* | |
477 | * If there are no explicit MP IRQ entries, then we are | |
478 | * broken. We set up most of the low 16 IO-APIC pins to | |
479 | * ISA defaults and hope it will work. | |
480 | */ | |
481 | if (!mp_irq_entries) { | |
482 | struct mpc_bus bus; | |
483 | ||
484 | printk(KERN_ERR "BIOS bug, no explicit IRQ entries, " | |
485 | "using default mptable. (tell your hw vendor)\n"); | |
486 | ||
487 | bus.type = MP_BUS; | |
488 | bus.busid = 0; | |
489 | memcpy(bus.bustype, "ISA ", 6); | |
490 | MP_bus_info(&bus); | |
491 | ||
492 | construct_default_ioirq_mptable(0); | |
493 | } | |
494 | #endif | |
495 | ||
496 | return 0; | |
497 | } | |
498 | ||
1da177e4 LT |
499 | /* |
500 | * Scan the memory blocks for an SMP configuration block. | |
501 | */ | |
b3f1b617 | 502 | void __init default_get_smp_config(unsigned int early) |
1da177e4 | 503 | { |
41401db6 | 504 | struct mpf_intel *mpf = mpf_found; |
1da177e4 | 505 | |
69b88afa YL |
506 | if (!mpf) |
507 | return; | |
508 | ||
888032cd AS |
509 | if (acpi_lapic && early) |
510 | return; | |
69b88afa | 511 | |
1da177e4 | 512 | /* |
69b88afa YL |
513 | * MPS doesn't support hyperthreading, aka only have |
514 | * thread 0 apic id in MPS table | |
1da177e4 | 515 | */ |
69b88afa | 516 | if (acpi_lapic && acpi_ioapic) |
1da177e4 | 517 | return; |
1da177e4 | 518 | |
4ef81297 | 519 | printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", |
1eb1b3b6 | 520 | mpf->specification); |
b3e24164 | 521 | #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) |
1eb1b3b6 | 522 | if (mpf->feature2 & (1 << 7)) { |
1da177e4 LT |
523 | printk(KERN_INFO " IMCR and PIC compatibility mode.\n"); |
524 | pic_mode = 1; | |
525 | } else { | |
526 | printk(KERN_INFO " Virtual Wire compatibility mode.\n"); | |
527 | pic_mode = 0; | |
528 | } | |
4421b1c8 | 529 | #endif |
1da177e4 LT |
530 | /* |
531 | * Now see if we need to read further. | |
532 | */ | |
1eb1b3b6 | 533 | if (mpf->feature1 != 0) { |
888032cd AS |
534 | if (early) { |
535 | /* | |
536 | * local APIC has default address | |
537 | */ | |
538 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
539 | return; | |
540 | } | |
1da177e4 | 541 | |
4ef81297 | 542 | printk(KERN_INFO "Default MP configuration #%d\n", |
1eb1b3b6 JSR |
543 | mpf->feature1); |
544 | construct_default_ISA_mptable(mpf->feature1); | |
1da177e4 | 545 | |
1eb1b3b6 | 546 | } else if (mpf->physptr) { |
0b3ba0c3 | 547 | if (check_physptr(mpf, early)) |
1da177e4 | 548 | return; |
1da177e4 LT |
549 | } else |
550 | BUG(); | |
551 | ||
888032cd AS |
552 | if (!early) |
553 | printk(KERN_INFO "Processors: %d\n", num_processors); | |
1da177e4 LT |
554 | /* |
555 | * Only use the first configuration found. | |
556 | */ | |
557 | } | |
558 | ||
b24c2a92 | 559 | static void __init smp_reserve_memory(struct mpf_intel *mpf) |
a6830278 | 560 | { |
24aa0788 | 561 | memblock_reserve(mpf->physptr, get_mpc_size(mpf->physptr)); |
a6830278 JSR |
562 | } |
563 | ||
b24c2a92 | 564 | static int __init smp_scan_config(unsigned long base, unsigned long length) |
1da177e4 | 565 | { |
92fd4b7a | 566 | unsigned int *bp = phys_to_virt(base); |
41401db6 | 567 | struct mpf_intel *mpf; |
b24c2a92 | 568 | unsigned long mem; |
1da177e4 | 569 | |
365811d6 BH |
570 | apic_printk(APIC_VERBOSE, "Scan for SMP in [mem %#010lx-%#010lx]\n", |
571 | base, base + length - 1); | |
5d47a271 | 572 | BUILD_BUG_ON(sizeof(*mpf) != 16); |
1da177e4 LT |
573 | |
574 | while (length > 0) { | |
41401db6 | 575 | mpf = (struct mpf_intel *)bp; |
1da177e4 | 576 | if ((*bp == SMP_MAGIC_IDENT) && |
1eb1b3b6 | 577 | (mpf->length == 1) && |
4ef81297 | 578 | !mpf_checksum((unsigned char *)bp, 16) && |
1eb1b3b6 JSR |
579 | ((mpf->specification == 1) |
580 | || (mpf->specification == 4))) { | |
bab4b27c | 581 | #ifdef CONFIG_X86_LOCAL_APIC |
1da177e4 | 582 | smp_found_config = 1; |
bab4b27c | 583 | #endif |
92fd4b7a | 584 | mpf_found = mpf; |
b1f006b6 | 585 | |
365811d6 BH |
586 | printk(KERN_INFO "found SMP MP-table at [mem %#010llx-%#010llx] mapped at [%p]\n", |
587 | (unsigned long long) virt_to_phys(mpf), | |
588 | (unsigned long long) virt_to_phys(mpf) + | |
589 | sizeof(*mpf) - 1, mpf); | |
b1f006b6 | 590 | |
b24c2a92 | 591 | mem = virt_to_phys(mpf); |
24aa0788 | 592 | memblock_reserve(mem, sizeof(*mpf)); |
a6830278 | 593 | if (mpf->physptr) |
b24c2a92 | 594 | smp_reserve_memory(mpf); |
1da177e4 | 595 | |
d2dbf343 | 596 | return 1; |
1da177e4 LT |
597 | } |
598 | bp += 4; | |
599 | length -= 16; | |
600 | } | |
601 | return 0; | |
602 | } | |
603 | ||
b24c2a92 | 604 | void __init default_find_smp_config(void) |
1da177e4 LT |
605 | { |
606 | unsigned int address; | |
607 | ||
608 | /* | |
609 | * FIXME: Linux assumes you have 640K of base ram.. | |
610 | * this continues the error... | |
611 | * | |
612 | * 1) Scan the bottom 1K for a signature | |
613 | * 2) Scan the top 1K of base RAM | |
614 | * 3) Scan the 64K of bios | |
615 | */ | |
b24c2a92 YL |
616 | if (smp_scan_config(0x0, 0x400) || |
617 | smp_scan_config(639 * 0x400, 0x400) || | |
618 | smp_scan_config(0xF0000, 0x10000)) | |
1da177e4 LT |
619 | return; |
620 | /* | |
621 | * If it is an SMP machine we should know now, unless the | |
bb8187d3 | 622 | * configuration is in an EISA bus machine with an |
1da177e4 LT |
623 | * extended bios data area. |
624 | * | |
625 | * there is a real-mode segmented pointer pointing to the | |
626 | * 4K EBDA area at 0x40E, calculate and scan it here. | |
627 | * | |
628 | * NOTE! There are Linux loaders that will corrupt the EBDA | |
629 | * area, and as such this kind of SMP config may be less | |
630 | * trustworthy, simply because the SMP table may have been | |
631 | * stomped on during early boot. These loaders are buggy and | |
632 | * should be fixed. | |
633 | * | |
634 | * MP1.4 SPEC states to only scan first 1K of 4K EBDA. | |
635 | */ | |
636 | ||
637 | address = get_bios_ebda(); | |
638 | if (address) | |
b24c2a92 | 639 | smp_scan_config(address, 0x400); |
888032cd AS |
640 | } |
641 | ||
2944e16b YL |
642 | #ifdef CONFIG_X86_IO_APIC |
643 | static u8 __initdata irq_used[MAX_IRQ_SOURCES]; | |
644 | ||
540d4e72 | 645 | static int __init get_MP_intsrc_index(struct mpc_intsrc *m) |
2944e16b YL |
646 | { |
647 | int i; | |
648 | ||
e253b396 | 649 | if (m->irqtype != mp_INT) |
2944e16b YL |
650 | return 0; |
651 | ||
e253b396 | 652 | if (m->irqflag != 0x0f) |
2944e16b YL |
653 | return 0; |
654 | ||
655 | /* not legacy */ | |
656 | ||
657 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 658 | if (mp_irqs[i].irqtype != mp_INT) |
2944e16b YL |
659 | continue; |
660 | ||
c2c21745 | 661 | if (mp_irqs[i].irqflag != 0x0f) |
2944e16b YL |
662 | continue; |
663 | ||
c2c21745 | 664 | if (mp_irqs[i].srcbus != m->srcbus) |
2944e16b | 665 | continue; |
c2c21745 | 666 | if (mp_irqs[i].srcbusirq != m->srcbusirq) |
2944e16b YL |
667 | continue; |
668 | if (irq_used[i]) { | |
669 | /* already claimed */ | |
670 | return -2; | |
671 | } | |
672 | irq_used[i] = 1; | |
673 | return i; | |
674 | } | |
675 | ||
676 | /* not found */ | |
677 | return -1; | |
678 | } | |
679 | ||
680 | #define SPARE_SLOT_NUM 20 | |
681 | ||
540d4e72 | 682 | static struct mpc_intsrc __initdata *m_spare[SPARE_SLOT_NUM]; |
a6830278 | 683 | |
57592224 | 684 | static void __init check_irq_src(struct mpc_intsrc *m, int *nr_m_spare) |
a6830278 JSR |
685 | { |
686 | int i; | |
687 | ||
688 | apic_printk(APIC_VERBOSE, "OLD "); | |
0e3fa13f | 689 | print_mp_irq_info(m); |
a6830278 JSR |
690 | |
691 | i = get_MP_intsrc_index(m); | |
692 | if (i > 0) { | |
0e3fa13f | 693 | memcpy(m, &mp_irqs[i], sizeof(*m)); |
a6830278 JSR |
694 | apic_printk(APIC_VERBOSE, "NEW "); |
695 | print_mp_irq_info(&mp_irqs[i]); | |
696 | return; | |
697 | } | |
698 | if (!i) { | |
699 | /* legacy, do nothing */ | |
700 | return; | |
701 | } | |
702 | if (*nr_m_spare < SPARE_SLOT_NUM) { | |
703 | /* | |
704 | * not found (-1), or duplicated (-2) are invalid entries, | |
705 | * we need to use the slot later | |
706 | */ | |
707 | m_spare[*nr_m_spare] = m; | |
708 | *nr_m_spare += 1; | |
709 | } | |
710 | } | |
a6830278 | 711 | |
64d21fc1 | 712 | static int __init |
ee214558 | 713 | check_slot(unsigned long mpc_new_phys, unsigned long mpc_new_length, int count) |
a6830278 | 714 | { |
ee214558 YL |
715 | if (!mpc_new_phys || count <= mpc_new_length) { |
716 | WARN(1, "update_mptable: No spare slots (length: %x)\n", count); | |
717 | return -1; | |
a6830278 JSR |
718 | } |
719 | ||
9f1f1bfd | 720 | return 0; |
a6830278 | 721 | } |
cbb84c4c RM |
722 | #else /* CONFIG_X86_IO_APIC */ |
723 | static | |
724 | inline void __init check_irq_src(struct mpc_intsrc *m, int *nr_m_spare) {} | |
725 | #endif /* CONFIG_X86_IO_APIC */ | |
2944e16b | 726 | |
f29521e4 | 727 | static int __init replace_intsrc_all(struct mpc_table *mpc, |
2944e16b YL |
728 | unsigned long mpc_new_phys, |
729 | unsigned long mpc_new_length) | |
730 | { | |
731 | #ifdef CONFIG_X86_IO_APIC | |
732 | int i; | |
2944e16b | 733 | #endif |
2944e16b | 734 | int count = sizeof(*mpc); |
a6830278 | 735 | int nr_m_spare = 0; |
2944e16b YL |
736 | unsigned char *mpt = ((unsigned char *)mpc) + count; |
737 | ||
6c65da50 JSR |
738 | printk(KERN_INFO "mpc_length %x\n", mpc->length); |
739 | while (count < mpc->length) { | |
2944e16b YL |
740 | switch (*mpt) { |
741 | case MP_PROCESSOR: | |
a6830278 JSR |
742 | skip_entry(&mpt, &count, sizeof(struct mpc_cpu)); |
743 | break; | |
2944e16b | 744 | case MP_BUS: |
a6830278 JSR |
745 | skip_entry(&mpt, &count, sizeof(struct mpc_bus)); |
746 | break; | |
2944e16b | 747 | case MP_IOAPIC: |
a6830278 JSR |
748 | skip_entry(&mpt, &count, sizeof(struct mpc_ioapic)); |
749 | break; | |
2944e16b | 750 | case MP_INTSRC: |
c58603e8 | 751 | check_irq_src((struct mpc_intsrc *)mpt, &nr_m_spare); |
a6830278 JSR |
752 | skip_entry(&mpt, &count, sizeof(struct mpc_intsrc)); |
753 | break; | |
2944e16b | 754 | case MP_LINTSRC: |
a6830278 JSR |
755 | skip_entry(&mpt, &count, sizeof(struct mpc_lintsrc)); |
756 | break; | |
2944e16b YL |
757 | default: |
758 | /* wrong mptable */ | |
5a5737ea | 759 | smp_dump_mptable(mpc, mpt); |
2944e16b YL |
760 | goto out; |
761 | } | |
762 | } | |
763 | ||
764 | #ifdef CONFIG_X86_IO_APIC | |
765 | for (i = 0; i < mp_irq_entries; i++) { | |
766 | if (irq_used[i]) | |
767 | continue; | |
768 | ||
c2c21745 | 769 | if (mp_irqs[i].irqtype != mp_INT) |
2944e16b YL |
770 | continue; |
771 | ||
c2c21745 | 772 | if (mp_irqs[i].irqflag != 0x0f) |
2944e16b YL |
773 | continue; |
774 | ||
775 | if (nr_m_spare > 0) { | |
82034d6f | 776 | apic_printk(APIC_VERBOSE, "*NEW* found\n"); |
2944e16b | 777 | nr_m_spare--; |
0e3fa13f | 778 | memcpy(m_spare[nr_m_spare], &mp_irqs[i], sizeof(mp_irqs[i])); |
2944e16b YL |
779 | m_spare[nr_m_spare] = NULL; |
780 | } else { | |
540d4e72 JSR |
781 | struct mpc_intsrc *m = (struct mpc_intsrc *)mpt; |
782 | count += sizeof(struct mpc_intsrc); | |
ee214558 | 783 | if (check_slot(mpc_new_phys, mpc_new_length, count) < 0) |
a6830278 | 784 | goto out; |
0e3fa13f | 785 | memcpy(m, &mp_irqs[i], sizeof(*m)); |
6c65da50 | 786 | mpc->length = count; |
540d4e72 | 787 | mpt += sizeof(struct mpc_intsrc); |
2944e16b YL |
788 | } |
789 | print_mp_irq_info(&mp_irqs[i]); | |
790 | } | |
791 | #endif | |
792 | out: | |
793 | /* update checksum */ | |
6c65da50 JSR |
794 | mpc->checksum = 0; |
795 | mpc->checksum -= mpf_checksum((unsigned char *)mpc, mpc->length); | |
2944e16b YL |
796 | |
797 | return 0; | |
798 | } | |
799 | ||
f1bdb523 | 800 | int enable_update_mptable; |
fcfa146e | 801 | |
2944e16b YL |
802 | static int __init update_mptable_setup(char *str) |
803 | { | |
804 | enable_update_mptable = 1; | |
629e15d2 YL |
805 | #ifdef CONFIG_PCI |
806 | pci_routeirq = 1; | |
807 | #endif | |
2944e16b YL |
808 | return 0; |
809 | } | |
810 | early_param("update_mptable", update_mptable_setup); | |
811 | ||
812 | static unsigned long __initdata mpc_new_phys; | |
813 | static unsigned long mpc_new_length __initdata = 4096; | |
814 | ||
815 | /* alloc_mptable or alloc_mptable=4k */ | |
816 | static int __initdata alloc_mptable; | |
817 | static int __init parse_alloc_mptable_opt(char *p) | |
818 | { | |
819 | enable_update_mptable = 1; | |
629e15d2 YL |
820 | #ifdef CONFIG_PCI |
821 | pci_routeirq = 1; | |
822 | #endif | |
2944e16b YL |
823 | alloc_mptable = 1; |
824 | if (!p) | |
825 | return 0; | |
826 | mpc_new_length = memparse(p, &p); | |
827 | return 0; | |
828 | } | |
829 | early_param("alloc_mptable", parse_alloc_mptable_opt); | |
830 | ||
831 | void __init early_reserve_e820_mpc_new(void) | |
832 | { | |
ab5d140b TH |
833 | if (enable_update_mptable && alloc_mptable) |
834 | mpc_new_phys = early_reserve_e820(mpc_new_length, 4); | |
2944e16b YL |
835 | } |
836 | ||
837 | static int __init update_mp_table(void) | |
838 | { | |
839 | char str[16]; | |
840 | char oem[10]; | |
41401db6 | 841 | struct mpf_intel *mpf; |
f29521e4 | 842 | struct mpc_table *mpc, *mpc_new; |
2944e16b YL |
843 | |
844 | if (!enable_update_mptable) | |
845 | return 0; | |
846 | ||
847 | mpf = mpf_found; | |
848 | if (!mpf) | |
849 | return 0; | |
850 | ||
851 | /* | |
852 | * Now see if we need to go further. | |
853 | */ | |
1eb1b3b6 | 854 | if (mpf->feature1 != 0) |
2944e16b YL |
855 | return 0; |
856 | ||
1eb1b3b6 | 857 | if (!mpf->physptr) |
2944e16b YL |
858 | return 0; |
859 | ||
1eb1b3b6 | 860 | mpc = phys_to_virt(mpf->physptr); |
2944e16b YL |
861 | |
862 | if (!smp_check_mpc(mpc, oem, str)) | |
863 | return 0; | |
864 | ||
ba1511bf | 865 | printk(KERN_INFO "mpf: %llx\n", (u64)virt_to_phys(mpf)); |
1eb1b3b6 | 866 | printk(KERN_INFO "physptr: %x\n", mpf->physptr); |
2944e16b | 867 | |
6c65da50 | 868 | if (mpc_new_phys && mpc->length > mpc_new_length) { |
2944e16b YL |
869 | mpc_new_phys = 0; |
870 | printk(KERN_INFO "mpc_new_length is %ld, please use alloc_mptable=8k\n", | |
871 | mpc_new_length); | |
872 | } | |
873 | ||
874 | if (!mpc_new_phys) { | |
875 | unsigned char old, new; | |
0d2eb44f | 876 | /* check if we can change the position */ |
6c65da50 JSR |
877 | mpc->checksum = 0; |
878 | old = mpf_checksum((unsigned char *)mpc, mpc->length); | |
879 | mpc->checksum = 0xff; | |
880 | new = mpf_checksum((unsigned char *)mpc, mpc->length); | |
2944e16b YL |
881 | if (old == new) { |
882 | printk(KERN_INFO "mpc is readonly, please try alloc_mptable instead\n"); | |
883 | return 0; | |
884 | } | |
0d2eb44f | 885 | printk(KERN_INFO "use in-position replacing\n"); |
2944e16b | 886 | } else { |
1eb1b3b6 | 887 | mpf->physptr = mpc_new_phys; |
2944e16b | 888 | mpc_new = phys_to_virt(mpc_new_phys); |
6c65da50 | 889 | memcpy(mpc_new, mpc, mpc->length); |
2944e16b YL |
890 | mpc = mpc_new; |
891 | /* check if we can modify that */ | |
1eb1b3b6 | 892 | if (mpc_new_phys - mpf->physptr) { |
41401db6 | 893 | struct mpf_intel *mpf_new; |
2944e16b YL |
894 | /* steal 16 bytes from [0, 1k) */ |
895 | printk(KERN_INFO "mpf new: %x\n", 0x400 - 16); | |
896 | mpf_new = phys_to_virt(0x400 - 16); | |
897 | memcpy(mpf_new, mpf, 16); | |
898 | mpf = mpf_new; | |
1eb1b3b6 | 899 | mpf->physptr = mpc_new_phys; |
2944e16b | 900 | } |
1eb1b3b6 JSR |
901 | mpf->checksum = 0; |
902 | mpf->checksum -= mpf_checksum((unsigned char *)mpf, 16); | |
903 | printk(KERN_INFO "physptr new: %x\n", mpf->physptr); | |
2944e16b YL |
904 | } |
905 | ||
906 | /* | |
907 | * only replace the one with mp_INT and | |
908 | * MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, | |
909 | * already in mp_irqs , stored by ... and mp_config_acpi_gsi, | |
910 | * may need pci=routeirq for all coverage | |
911 | */ | |
912 | replace_intsrc_all(mpc, mpc_new_phys, mpc_new_length); | |
913 | ||
914 | return 0; | |
915 | } | |
916 | ||
917 | late_initcall(update_mp_table); |