x86, microcode rework, v2, fix
[linux-2.6-block.git] / arch / x86 / kernel / microcode_intel.c
CommitLineData
1da177e4
LT
1/*
2 * Intel CPU Microcode Update Driver for Linux
3 *
69688262 4 * Copyright (C) 2000-2006 Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
9a3110bf 5 * 2006 Shaohua Li <shaohua.li@intel.com>
1da177e4
LT
6 *
7 * This driver allows to upgrade microcode on Intel processors
bc4e0f9a 8 * belonging to IA-32 family - PentiumPro, Pentium II,
1da177e4
LT
9 * Pentium III, Xeon, Pentium 4, etc.
10 *
bc4e0f9a
BC
11 * Reference: Section 8.11 of Volume 3a, IA-32 Intel? Architecture
12 * Software Developer's Manual
13 * Order Number 253668 or free download from:
14 *
15 * http://developer.intel.com/design/pentium4/manuals/253668.htm
1da177e4
LT
16 *
17 * For more information, go to http://www.urbanmyth.org/microcode
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version
22 * 2 of the License, or (at your option) any later version.
23 *
24 * 1.0 16 Feb 2000, Tigran Aivazian <tigran@sco.com>
25 * Initial release.
26 * 1.01 18 Feb 2000, Tigran Aivazian <tigran@sco.com>
27 * Added read() support + cleanups.
28 * 1.02 21 Feb 2000, Tigran Aivazian <tigran@sco.com>
29 * Added 'device trimming' support. open(O_WRONLY) zeroes
30 * and frees the saved copy of applied microcode.
31 * 1.03 29 Feb 2000, Tigran Aivazian <tigran@sco.com>
32 * Made to use devfs (/dev/cpu/microcode) + cleanups.
33 * 1.04 06 Jun 2000, Simon Trimmer <simon@veritas.com>
34 * Added misc device support (now uses both devfs and misc).
35 * Added MICROCODE_IOCFREE ioctl to clear memory.
36 * 1.05 09 Jun 2000, Simon Trimmer <simon@veritas.com>
37 * Messages for error cases (non Intel & no suitable microcode).
38 * 1.06 03 Aug 2000, Tigran Aivazian <tigran@veritas.com>
39 * Removed ->release(). Removed exclusive open and status bitmap.
40 * Added microcode_rwsem to serialize read()/write()/ioctl().
41 * Removed global kernel lock usage.
42 * 1.07 07 Sep 2000, Tigran Aivazian <tigran@veritas.com>
43 * Write 0 to 0x8B msr and then cpuid before reading revision,
44 * so that it works even if there were no update done by the
45 * BIOS. Otherwise, reading from 0x8B gives junk (which happened
46 * to be 0 on my machine which is why it worked even when I
47 * disabled update by the BIOS)
48 * Thanks to Eric W. Biederman <ebiederman@lnxi.com> for the fix.
49 * 1.08 11 Dec 2000, Richard Schaal <richard.schaal@intel.com> and
50 * Tigran Aivazian <tigran@veritas.com>
51 * Intel Pentium 4 processor support and bugfixes.
52 * 1.09 30 Oct 2001, Tigran Aivazian <tigran@veritas.com>
53 * Bugfix for HT (Hyper-Threading) enabled processors
54 * whereby processor resources are shared by all logical processors
55 * in a single CPU package.
56 * 1.10 28 Feb 2002 Asit K Mallick <asit.k.mallick@intel.com> and
57 * Tigran Aivazian <tigran@veritas.com>,
f516526f
PO
58 * Serialize updates as required on HT processors due to
59 * speculative nature of implementation.
1da177e4
LT
60 * 1.11 22 Mar 2002 Tigran Aivazian <tigran@veritas.com>
61 * Fix the panic when writing zero-length microcode chunk.
bc4e0f9a 62 * 1.12 29 Sep 2003 Nitin Kamble <nitin.a.kamble@intel.com>,
1da177e4
LT
63 * Jun Nakajima <jun.nakajima@intel.com>
64 * Support for the microcode updates in the new format.
65 * 1.13 10 Oct 2003 Tigran Aivazian <tigran@veritas.com>
66 * Removed ->read() method and obsoleted MICROCODE_IOCFREE ioctl
bc4e0f9a 67 * because we no longer hold a copy of applied microcode
1da177e4
LT
68 * in kernel memory.
69 * 1.14 25 Jun 2004 Tigran Aivazian <tigran@veritas.com>
70 * Fix sigmatch() macro to handle old CPUs with pf == 0.
71 * Thanks to Stuart Swales for pointing out this bug.
72 */
a9415644 73#include <linux/capability.h>
1da177e4
LT
74#include <linux/kernel.h>
75#include <linux/init.h>
76#include <linux/sched.h>
77149367 77#include <linux/smp_lock.h>
5cf6c541 78#include <linux/cpumask.h>
1da177e4
LT
79#include <linux/module.h>
80#include <linux/slab.h>
81#include <linux/vmalloc.h>
82#include <linux/miscdevice.h>
83#include <linux/spinlock.h>
84#include <linux/mm.h>
4e950f6f 85#include <linux/fs.h>
14cc3e2b 86#include <linux/mutex.h>
a30a6a2c
SL
87#include <linux/cpu.h>
88#include <linux/firmware.h>
89#include <linux/platform_device.h>
1da177e4
LT
90
91#include <asm/msr.h>
92#include <asm/uaccess.h>
93#include <asm/processor.h>
9a56a0f8 94#include <asm/microcode.h>
1da177e4 95
3e135d88 96MODULE_DESCRIPTION("Microcode Update Driver");
69688262 97MODULE_AUTHOR("Tigran Aivazian <tigran@aivazian.fsnet.co.uk>");
1da177e4
LT
98MODULE_LICENSE("GPL");
99
f516526f
PO
100#define DEFAULT_UCODE_DATASIZE (2000)
101#define MC_HEADER_SIZE (sizeof(struct microcode_header_intel))
102#define DEFAULT_UCODE_TOTALSIZE (DEFAULT_UCODE_DATASIZE + MC_HEADER_SIZE)
103#define EXT_HEADER_SIZE (sizeof(struct extended_sigtable))
104#define EXT_SIGNATURE_SIZE (sizeof(struct extended_signature))
3e135d88 105#define DWSIZE (sizeof(u32))
1da177e4 106#define get_totalsize(mc) \
d4ee3668
PO
107 (((struct microcode_intel *)mc)->hdr.totalsize ? \
108 ((struct microcode_intel *)mc)->hdr.totalsize : \
109 DEFAULT_UCODE_TOTALSIZE)
110
1da177e4 111#define get_datasize(mc) \
d4ee3668
PO
112 (((struct microcode_intel *)mc)->hdr.datasize ? \
113 ((struct microcode_intel *)mc)->hdr.datasize : DEFAULT_UCODE_DATASIZE)
1da177e4
LT
114
115#define sigmatch(s1, s2, p1, p2) \
116 (((s1) == (s2)) && (((p1) & (p2)) || (((p1) == 0) && ((p2) == 0))))
117
118#define exttable_size(et) ((et)->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE)
119
120/* serialize access to the physical write to MSR 0x79 */
121static DEFINE_SPINLOCK(microcode_update_lock);
122
d45de409 123static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
1da177e4 124{
92cb7612 125 struct cpuinfo_x86 *c = &cpu_data(cpu_num);
1da177e4
LT
126 unsigned int val[2];
127
d45de409 128 memset(csig, 0, sizeof(*csig));
1da177e4
LT
129
130 if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 ||
3e135d88 131 cpu_has(c, X86_FEATURE_IA64)) {
9a3110bf
SL
132 printk(KERN_ERR "microcode: CPU%d not a capable Intel "
133 "processor\n", cpu_num);
d45de409 134 return -1;
9a3110bf 135 }
1da177e4 136
d45de409 137 csig->sig = cpuid_eax(0x00000001);
9a3110bf
SL
138
139 if ((c->x86_model >= 5) || (c->x86 > 6)) {
140 /* get processor flags from MSR 0x17 */
141 rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
d45de409 142 csig->pf = 1 << ((val[1] >> 18) & 7);
1da177e4
LT
143 }
144
145 wrmsr(MSR_IA32_UCODE_REV, 0, 0);
245067d1 146 /* see notes above for revision 1.07. Apparent chip bug */
487472bc 147 sync_core();
1da177e4 148 /* get the current revision from MSR 0x8B */
d45de409 149 rdmsr(MSR_IA32_UCODE_REV, val[0], csig->rev);
1da177e4 150 pr_debug("microcode: collect_cpu_info : sig=0x%x, pf=0x%x, rev=0x%x\n",
d45de409
DA
151 csig->sig, csig->pf, csig->rev);
152
153 return 0;
1da177e4
LT
154}
155
a0a29b62 156static inline int update_match_cpu(struct cpu_signature *csig, int sig, int pf)
1da177e4 157{
a0a29b62
DA
158 return (!sigmatch(sig, csig->sig, pf, csig->pf)) ? 0 : 1;
159}
1da177e4 160
a0a29b62
DA
161static inline int
162update_match_revision(struct microcode_header_intel *mc_header, int rev)
163{
164 return (mc_header->rev <= rev) ? 0 : 1;
1da177e4
LT
165}
166
8d86f390 167static int microcode_sanity_check(void *mc)
1da177e4 168{
d4ee3668 169 struct microcode_header_intel *mc_header = mc;
9a3110bf
SL
170 struct extended_sigtable *ext_header = NULL;
171 struct extended_signature *ext_sig;
172 unsigned long total_size, data_size, ext_table_size;
173 int sum, orig_sum, ext_sigcount = 0, i;
174
175 total_size = get_totalsize(mc_header);
176 data_size = get_datasize(mc_header);
bd8e39f9 177 if (data_size + MC_HEADER_SIZE > total_size) {
9a3110bf
SL
178 printk(KERN_ERR "microcode: error! "
179 "Bad data size in microcode data file\n");
180 return -EINVAL;
181 }
1da177e4 182
9a3110bf
SL
183 if (mc_header->ldrver != 1 || mc_header->hdrver != 1) {
184 printk(KERN_ERR "microcode: error! "
185 "Unknown microcode update format\n");
186 return -EINVAL;
187 }
188 ext_table_size = total_size - (MC_HEADER_SIZE + data_size);
189 if (ext_table_size) {
190 if ((ext_table_size < EXT_HEADER_SIZE)
191 || ((ext_table_size - EXT_HEADER_SIZE) % EXT_SIGNATURE_SIZE)) {
192 printk(KERN_ERR "microcode: error! "
193 "Small exttable size in microcode data file\n");
194 return -EINVAL;
1da177e4 195 }
9a3110bf
SL
196 ext_header = mc + MC_HEADER_SIZE + data_size;
197 if (ext_table_size != exttable_size(ext_header)) {
198 printk(KERN_ERR "microcode: error! "
199 "Bad exttable size in microcode data file\n");
200 return -EFAULT;
1da177e4 201 }
9a3110bf
SL
202 ext_sigcount = ext_header->count;
203 }
1da177e4 204
9a3110bf
SL
205 /* check extended table checksum */
206 if (ext_table_size) {
207 int ext_table_sum = 0;
9a4b9efa 208 int *ext_tablep = (int *)ext_header;
9a3110bf
SL
209
210 i = ext_table_size / DWSIZE;
211 while (i--)
212 ext_table_sum += ext_tablep[i];
213 if (ext_table_sum) {
214 printk(KERN_WARNING "microcode: aborting, "
215 "bad extended signature table checksum\n");
216 return -EINVAL;
1da177e4 217 }
9a3110bf 218 }
1da177e4 219
9a3110bf
SL
220 /* calculate the checksum */
221 orig_sum = 0;
222 i = (MC_HEADER_SIZE + data_size) / DWSIZE;
223 while (i--)
224 orig_sum += ((int *)mc)[i];
225 if (orig_sum) {
226 printk(KERN_ERR "microcode: aborting, bad checksum\n");
227 return -EINVAL;
228 }
229 if (!ext_table_size)
230 return 0;
231 /* check extended signature checksum */
232 for (i = 0; i < ext_sigcount; i++) {
ade1af77
JE
233 ext_sig = (void *)ext_header + EXT_HEADER_SIZE +
234 EXT_SIGNATURE_SIZE * i;
9a3110bf
SL
235 sum = orig_sum
236 - (mc_header->sig + mc_header->pf + mc_header->cksum)
237 + (ext_sig->sig + ext_sig->pf + ext_sig->cksum);
238 if (sum) {
239 printk(KERN_ERR "microcode: aborting, bad checksum\n");
240 return -EINVAL;
1da177e4 241 }
9a3110bf
SL
242 }
243 return 0;
244}
5cf6c541 245
9a3110bf
SL
246/*
247 * return 0 - no update found
248 * return 1 - found update
9a3110bf 249 */
a0a29b62
DA
250static int
251get_matching_microcode(struct cpu_signature *cpu_sig, void *mc, int rev)
9a3110bf 252{
d4ee3668 253 struct microcode_header_intel *mc_header = mc;
9a3110bf
SL
254 struct extended_sigtable *ext_header;
255 unsigned long total_size = get_totalsize(mc_header);
256 int ext_sigcount, i;
257 struct extended_signature *ext_sig;
9a3110bf 258
a0a29b62
DA
259 if (!update_match_revision(mc_header, rev))
260 return 0;
261
262 if (update_match_cpu(cpu_sig, mc_header->sig, mc_header->pf))
263 return 1;
9a3110bf 264
a0a29b62 265 /* Look for ext. headers: */
9a3110bf
SL
266 if (total_size <= get_datasize(mc_header) + MC_HEADER_SIZE)
267 return 0;
268
ade1af77 269 ext_header = mc + get_datasize(mc_header) + MC_HEADER_SIZE;
9a3110bf 270 ext_sigcount = ext_header->count;
ade1af77 271 ext_sig = (void *)ext_header + EXT_HEADER_SIZE;
a0a29b62 272
9a3110bf 273 for (i = 0; i < ext_sigcount; i++) {
a0a29b62
DA
274 if (update_match_cpu(cpu_sig, ext_sig->sig, ext_sig->pf))
275 return 1;
9a3110bf
SL
276 ext_sig++;
277 }
278 return 0;
1da177e4
LT
279}
280
8d86f390 281static void apply_microcode(int cpu)
1da177e4
LT
282{
283 unsigned long flags;
284 unsigned int val[2];
9a3110bf 285 int cpu_num = raw_smp_processor_id();
a0a29b62 286 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
1da177e4 287
9a3110bf
SL
288 /* We should bind the task to the CPU */
289 BUG_ON(cpu_num != cpu);
290
d4ee3668 291 if (uci->mc.mc_intel == NULL)
1da177e4 292 return;
1da177e4
LT
293
294 /* serialize access to the physical write to MSR 0x79 */
bc4e0f9a 295 spin_lock_irqsave(&microcode_update_lock, flags);
1da177e4
LT
296
297 /* write microcode via MSR 0x79 */
298 wrmsr(MSR_IA32_UCODE_WRITE,
d4ee3668
PO
299 (unsigned long) uci->mc.mc_intel->bits,
300 (unsigned long) uci->mc.mc_intel->bits >> 16 >> 16);
1da177e4
LT
301 wrmsr(MSR_IA32_UCODE_REV, 0, 0);
302
245067d1 303 /* see notes above for revision 1.07. Apparent chip bug */
487472bc 304 sync_core();
245067d1 305
1da177e4
LT
306 /* get the current revision from MSR 0x8B */
307 rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
308
1da177e4 309 spin_unlock_irqrestore(&microcode_update_lock, flags);
d4ee3668 310 if (val[1] != uci->mc.mc_intel->hdr.rev) {
fe176de0 311 printk(KERN_ERR "microcode: CPU%d update from revision "
d45de409 312 "0x%x to 0x%x failed\n", cpu_num, uci->cpu_sig.rev, val[1]);
9a3110bf
SL
313 return;
314 }
fe176de0 315 printk(KERN_INFO "microcode: CPU%d updated from revision "
34a1b9fc 316 "0x%x to 0x%x, date = %04x-%02x-%02x \n",
d45de409 317 cpu_num, uci->cpu_sig.rev, val[1],
34a1b9fc
DW
318 uci->mc.mc_intel->hdr.date & 0xffff,
319 uci->mc.mc_intel->hdr.date >> 24,
320 (uci->mc.mc_intel->hdr.date >> 16) & 0xff);
d45de409 321 uci->cpu_sig.rev = val[1];
1da177e4
LT
322}
323
a0a29b62
DA
324static int generic_load_microcode(int cpu, void *data, size_t size,
325 int (*get_ucode_data)(void *, const void *, size_t))
9a3110bf 326{
a0a29b62
DA
327 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
328 u8 *ucode_ptr = data, *new_mc = NULL, *mc;
329 int new_rev = uci->cpu_sig.rev;
330 unsigned int leftover = size;
9a3110bf 331
a0a29b62
DA
332 while (leftover) {
333 struct microcode_header_intel mc_header;
334 unsigned int mc_size;
9a3110bf 335
a0a29b62
DA
336 if (get_ucode_data(&mc_header, ucode_ptr, sizeof(mc_header)))
337 break;
a30a6a2c 338
a0a29b62
DA
339 mc_size = get_totalsize(&mc_header);
340 if (!mc_size || mc_size > leftover) {
341 printk(KERN_ERR "microcode: error!"
342 "Bad data in microcode data file\n");
343 break;
344 }
a30a6a2c 345
a0a29b62
DA
346 mc = vmalloc(mc_size);
347 if (!mc)
348 break;
349
350 if (get_ucode_data(mc, ucode_ptr, mc_size) ||
351 microcode_sanity_check(mc) < 0) {
352 vfree(mc);
353 break;
354 }
355
356 if (get_matching_microcode(&uci->cpu_sig, mc, new_rev)) {
a1c75cc5
IM
357 if (new_mc)
358 vfree(new_mc);
a0a29b62
DA
359 new_rev = mc_header.rev;
360 new_mc = mc;
361 } else
362 vfree(mc);
363
364 ucode_ptr += mc_size;
365 leftover -= mc_size;
a30a6a2c
SL
366 }
367
a0a29b62
DA
368 if (new_mc) {
369 if (!leftover) {
370 if (uci->mc.mc_intel)
371 vfree(uci->mc.mc_intel);
372 uci->mc.mc_intel = (struct microcode_intel *)new_mc;
373 pr_debug("microcode: CPU%d found a matching microcode update with"
374 " version 0x%x (current=0x%x)\n",
375 cpu, uci->mc.mc_intel->hdr.rev, uci->cpu_sig.rev);
376 } else
377 vfree(new_mc);
a30a6a2c 378 }
a0a29b62
DA
379
380 return (int)leftover;
a30a6a2c
SL
381}
382
a0a29b62
DA
383static int get_ucode_fw(void *to, const void *from, size_t n)
384{
385 memcpy(to, from, n);
386 return 0;
387}
a30a6a2c 388
a0a29b62 389static int request_microcode_fw(int cpu, struct device *device)
a30a6a2c
SL
390{
391 char name[30];
92cb7612 392 struct cpuinfo_x86 *c = &cpu_data(cpu);
a30a6a2c 393 const struct firmware *firmware;
a0a29b62 394 int ret;
a30a6a2c
SL
395
396 /* We should bind the task to the CPU */
397 BUG_ON(cpu != raw_smp_processor_id());
3e135d88 398 sprintf(name, "intel-ucode/%02x-%02x-%02x",
a30a6a2c 399 c->x86, c->x86_model, c->x86_mask);
a0a29b62
DA
400 ret = request_firmware(&firmware, name, device);
401 if (ret) {
bc4e0f9a 402 pr_debug("microcode: data file %s load failed\n", name);
a0a29b62 403 return ret;
a30a6a2c 404 }
a0a29b62
DA
405
406 ret = generic_load_microcode(cpu, (void*)firmware->data, firmware->size,
407 &get_ucode_fw);
408
a30a6a2c
SL
409 release_firmware(firmware);
410
a0a29b62
DA
411 return ret;
412}
413
414static int get_ucode_user(void *to, const void *from, size_t n)
415{
416 return copy_from_user(to, from, n);
417}
418
419static int request_microcode_user(int cpu, const void __user *buf, size_t size)
420{
421 /* We should bind the task to the CPU */
422 BUG_ON(cpu != raw_smp_processor_id());
423
424 return generic_load_microcode(cpu, (void*)buf, size, &get_ucode_user);
a30a6a2c
SL
425}
426
8d86f390 427static void microcode_fini_cpu(int cpu)
a30a6a2c
SL
428{
429 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
430
8d86f390 431 vfree(uci->mc.mc_intel);
d4ee3668 432 uci->mc.mc_intel = NULL;
a30a6a2c 433}
8d86f390
PO
434
435static struct microcode_ops microcode_intel_ops = {
a0a29b62
DA
436 .request_microcode_user = request_microcode_user,
437 .request_microcode_fw = request_microcode_fw,
8d86f390
PO
438 .collect_cpu_info = collect_cpu_info,
439 .apply_microcode = apply_microcode,
440 .microcode_fini_cpu = microcode_fini_cpu,
441};
442
443static int __init microcode_intel_module_init(void)
444{
8343ef24 445 struct cpuinfo_x86 *c = &cpu_data(0);
8d86f390 446
8343ef24
DA
447 if (c->x86_vendor != X86_VENDOR_INTEL) {
448 printk(KERN_ERR "microcode: CPU platform is not Intel-capable\n");
8d86f390 449 return -ENODEV;
8343ef24
DA
450 }
451
452 return microcode_init(&microcode_intel_ops, THIS_MODULE);
8d86f390
PO
453}
454
455static void __exit microcode_intel_module_exit(void)
456{
457 microcode_exit();
458}
459
460module_init(microcode_intel_module_init)
461module_exit(microcode_intel_module_exit)