Merge branches 'timers/clocksource', 'timers/hpet', 'timers/hrtimers', 'timers/nohz...
[linux-block.git] / arch / x86 / kernel / microcode_intel.c
CommitLineData
1da177e4
LT
1/*
2 * Intel CPU Microcode Update Driver for Linux
3 *
69688262 4 * Copyright (C) 2000-2006 Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
9a3110bf 5 * 2006 Shaohua Li <shaohua.li@intel.com>
1da177e4
LT
6 *
7 * This driver allows to upgrade microcode on Intel processors
bc4e0f9a 8 * belonging to IA-32 family - PentiumPro, Pentium II,
1da177e4
LT
9 * Pentium III, Xeon, Pentium 4, etc.
10 *
bc4e0f9a
BC
11 * Reference: Section 8.11 of Volume 3a, IA-32 Intel? Architecture
12 * Software Developer's Manual
13 * Order Number 253668 or free download from:
14 *
15 * http://developer.intel.com/design/pentium4/manuals/253668.htm
1da177e4
LT
16 *
17 * For more information, go to http://www.urbanmyth.org/microcode
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version
22 * 2 of the License, or (at your option) any later version.
23 *
24 * 1.0 16 Feb 2000, Tigran Aivazian <tigran@sco.com>
25 * Initial release.
26 * 1.01 18 Feb 2000, Tigran Aivazian <tigran@sco.com>
27 * Added read() support + cleanups.
28 * 1.02 21 Feb 2000, Tigran Aivazian <tigran@sco.com>
29 * Added 'device trimming' support. open(O_WRONLY) zeroes
30 * and frees the saved copy of applied microcode.
31 * 1.03 29 Feb 2000, Tigran Aivazian <tigran@sco.com>
32 * Made to use devfs (/dev/cpu/microcode) + cleanups.
33 * 1.04 06 Jun 2000, Simon Trimmer <simon@veritas.com>
34 * Added misc device support (now uses both devfs and misc).
35 * Added MICROCODE_IOCFREE ioctl to clear memory.
36 * 1.05 09 Jun 2000, Simon Trimmer <simon@veritas.com>
37 * Messages for error cases (non Intel & no suitable microcode).
38 * 1.06 03 Aug 2000, Tigran Aivazian <tigran@veritas.com>
39 * Removed ->release(). Removed exclusive open and status bitmap.
40 * Added microcode_rwsem to serialize read()/write()/ioctl().
41 * Removed global kernel lock usage.
42 * 1.07 07 Sep 2000, Tigran Aivazian <tigran@veritas.com>
43 * Write 0 to 0x8B msr and then cpuid before reading revision,
44 * so that it works even if there were no update done by the
45 * BIOS. Otherwise, reading from 0x8B gives junk (which happened
46 * to be 0 on my machine which is why it worked even when I
47 * disabled update by the BIOS)
48 * Thanks to Eric W. Biederman <ebiederman@lnxi.com> for the fix.
49 * 1.08 11 Dec 2000, Richard Schaal <richard.schaal@intel.com> and
50 * Tigran Aivazian <tigran@veritas.com>
51 * Intel Pentium 4 processor support and bugfixes.
52 * 1.09 30 Oct 2001, Tigran Aivazian <tigran@veritas.com>
53 * Bugfix for HT (Hyper-Threading) enabled processors
54 * whereby processor resources are shared by all logical processors
55 * in a single CPU package.
56 * 1.10 28 Feb 2002 Asit K Mallick <asit.k.mallick@intel.com> and
57 * Tigran Aivazian <tigran@veritas.com>,
f516526f
PO
58 * Serialize updates as required on HT processors due to
59 * speculative nature of implementation.
1da177e4
LT
60 * 1.11 22 Mar 2002 Tigran Aivazian <tigran@veritas.com>
61 * Fix the panic when writing zero-length microcode chunk.
bc4e0f9a 62 * 1.12 29 Sep 2003 Nitin Kamble <nitin.a.kamble@intel.com>,
1da177e4
LT
63 * Jun Nakajima <jun.nakajima@intel.com>
64 * Support for the microcode updates in the new format.
65 * 1.13 10 Oct 2003 Tigran Aivazian <tigran@veritas.com>
66 * Removed ->read() method and obsoleted MICROCODE_IOCFREE ioctl
bc4e0f9a 67 * because we no longer hold a copy of applied microcode
1da177e4
LT
68 * in kernel memory.
69 * 1.14 25 Jun 2004 Tigran Aivazian <tigran@veritas.com>
70 * Fix sigmatch() macro to handle old CPUs with pf == 0.
71 * Thanks to Stuart Swales for pointing out this bug.
72 */
a9415644 73#include <linux/capability.h>
1da177e4
LT
74#include <linux/kernel.h>
75#include <linux/init.h>
76#include <linux/sched.h>
77149367 77#include <linux/smp_lock.h>
5cf6c541 78#include <linux/cpumask.h>
1da177e4
LT
79#include <linux/module.h>
80#include <linux/slab.h>
81#include <linux/vmalloc.h>
82#include <linux/miscdevice.h>
83#include <linux/spinlock.h>
84#include <linux/mm.h>
4e950f6f 85#include <linux/fs.h>
14cc3e2b 86#include <linux/mutex.h>
a30a6a2c
SL
87#include <linux/cpu.h>
88#include <linux/firmware.h>
89#include <linux/platform_device.h>
1da177e4
LT
90
91#include <asm/msr.h>
92#include <asm/uaccess.h>
93#include <asm/processor.h>
9a56a0f8 94#include <asm/microcode.h>
1da177e4 95
3e135d88 96MODULE_DESCRIPTION("Microcode Update Driver");
69688262 97MODULE_AUTHOR("Tigran Aivazian <tigran@aivazian.fsnet.co.uk>");
1da177e4
LT
98MODULE_LICENSE("GPL");
99
18dbc916
DA
100struct microcode_header_intel {
101 unsigned int hdrver;
102 unsigned int rev;
103 unsigned int date;
104 unsigned int sig;
105 unsigned int cksum;
106 unsigned int ldrver;
107 unsigned int pf;
108 unsigned int datasize;
109 unsigned int totalsize;
110 unsigned int reserved[3];
111};
112
113struct microcode_intel {
114 struct microcode_header_intel hdr;
115 unsigned int bits[0];
116};
117
118/* microcode format is extended from prescott processors */
119struct extended_signature {
120 unsigned int sig;
121 unsigned int pf;
122 unsigned int cksum;
123};
124
125struct extended_sigtable {
126 unsigned int count;
127 unsigned int cksum;
128 unsigned int reserved[3];
129 struct extended_signature sigs[0];
130};
131
f516526f
PO
132#define DEFAULT_UCODE_DATASIZE (2000)
133#define MC_HEADER_SIZE (sizeof(struct microcode_header_intel))
134#define DEFAULT_UCODE_TOTALSIZE (DEFAULT_UCODE_DATASIZE + MC_HEADER_SIZE)
135#define EXT_HEADER_SIZE (sizeof(struct extended_sigtable))
136#define EXT_SIGNATURE_SIZE (sizeof(struct extended_signature))
3e135d88 137#define DWSIZE (sizeof(u32))
1da177e4 138#define get_totalsize(mc) \
d4ee3668
PO
139 (((struct microcode_intel *)mc)->hdr.totalsize ? \
140 ((struct microcode_intel *)mc)->hdr.totalsize : \
141 DEFAULT_UCODE_TOTALSIZE)
142
1da177e4 143#define get_datasize(mc) \
d4ee3668
PO
144 (((struct microcode_intel *)mc)->hdr.datasize ? \
145 ((struct microcode_intel *)mc)->hdr.datasize : DEFAULT_UCODE_DATASIZE)
1da177e4
LT
146
147#define sigmatch(s1, s2, p1, p2) \
148 (((s1) == (s2)) && (((p1) & (p2)) || (((p1) == 0) && ((p2) == 0))))
149
150#define exttable_size(et) ((et)->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE)
151
152/* serialize access to the physical write to MSR 0x79 */
153static DEFINE_SPINLOCK(microcode_update_lock);
154
d45de409 155static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
1da177e4 156{
92cb7612 157 struct cpuinfo_x86 *c = &cpu_data(cpu_num);
280a9ca5 158 unsigned long flags;
1da177e4
LT
159 unsigned int val[2];
160
d45de409 161 memset(csig, 0, sizeof(*csig));
1da177e4
LT
162
163 if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 ||
3e135d88 164 cpu_has(c, X86_FEATURE_IA64)) {
9a3110bf
SL
165 printk(KERN_ERR "microcode: CPU%d not a capable Intel "
166 "processor\n", cpu_num);
d45de409 167 return -1;
9a3110bf 168 }
1da177e4 169
d45de409 170 csig->sig = cpuid_eax(0x00000001);
9a3110bf
SL
171
172 if ((c->x86_model >= 5) || (c->x86 > 6)) {
173 /* get processor flags from MSR 0x17 */
174 rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
d45de409 175 csig->pf = 1 << ((val[1] >> 18) & 7);
1da177e4
LT
176 }
177
280a9ca5
DA
178 /* serialize access to the physical write to MSR 0x79 */
179 spin_lock_irqsave(&microcode_update_lock, flags);
180
1da177e4 181 wrmsr(MSR_IA32_UCODE_REV, 0, 0);
245067d1 182 /* see notes above for revision 1.07. Apparent chip bug */
487472bc 183 sync_core();
1da177e4 184 /* get the current revision from MSR 0x8B */
d45de409 185 rdmsr(MSR_IA32_UCODE_REV, val[0], csig->rev);
280a9ca5
DA
186 spin_unlock_irqrestore(&microcode_update_lock, flags);
187
1da177e4 188 pr_debug("microcode: collect_cpu_info : sig=0x%x, pf=0x%x, rev=0x%x\n",
d45de409
DA
189 csig->sig, csig->pf, csig->rev);
190
191 return 0;
1da177e4
LT
192}
193
a0a29b62 194static inline int update_match_cpu(struct cpu_signature *csig, int sig, int pf)
1da177e4 195{
a0a29b62
DA
196 return (!sigmatch(sig, csig->sig, pf, csig->pf)) ? 0 : 1;
197}
1da177e4 198
a0a29b62
DA
199static inline int
200update_match_revision(struct microcode_header_intel *mc_header, int rev)
201{
202 return (mc_header->rev <= rev) ? 0 : 1;
1da177e4
LT
203}
204
8d86f390 205static int microcode_sanity_check(void *mc)
1da177e4 206{
d4ee3668 207 struct microcode_header_intel *mc_header = mc;
9a3110bf
SL
208 struct extended_sigtable *ext_header = NULL;
209 struct extended_signature *ext_sig;
210 unsigned long total_size, data_size, ext_table_size;
211 int sum, orig_sum, ext_sigcount = 0, i;
212
213 total_size = get_totalsize(mc_header);
214 data_size = get_datasize(mc_header);
bd8e39f9 215 if (data_size + MC_HEADER_SIZE > total_size) {
9a3110bf
SL
216 printk(KERN_ERR "microcode: error! "
217 "Bad data size in microcode data file\n");
218 return -EINVAL;
219 }
1da177e4 220
9a3110bf
SL
221 if (mc_header->ldrver != 1 || mc_header->hdrver != 1) {
222 printk(KERN_ERR "microcode: error! "
223 "Unknown microcode update format\n");
224 return -EINVAL;
225 }
226 ext_table_size = total_size - (MC_HEADER_SIZE + data_size);
227 if (ext_table_size) {
228 if ((ext_table_size < EXT_HEADER_SIZE)
229 || ((ext_table_size - EXT_HEADER_SIZE) % EXT_SIGNATURE_SIZE)) {
230 printk(KERN_ERR "microcode: error! "
231 "Small exttable size in microcode data file\n");
232 return -EINVAL;
1da177e4 233 }
9a3110bf
SL
234 ext_header = mc + MC_HEADER_SIZE + data_size;
235 if (ext_table_size != exttable_size(ext_header)) {
236 printk(KERN_ERR "microcode: error! "
237 "Bad exttable size in microcode data file\n");
238 return -EFAULT;
1da177e4 239 }
9a3110bf
SL
240 ext_sigcount = ext_header->count;
241 }
1da177e4 242
9a3110bf
SL
243 /* check extended table checksum */
244 if (ext_table_size) {
245 int ext_table_sum = 0;
9a4b9efa 246 int *ext_tablep = (int *)ext_header;
9a3110bf
SL
247
248 i = ext_table_size / DWSIZE;
249 while (i--)
250 ext_table_sum += ext_tablep[i];
251 if (ext_table_sum) {
252 printk(KERN_WARNING "microcode: aborting, "
253 "bad extended signature table checksum\n");
254 return -EINVAL;
1da177e4 255 }
9a3110bf 256 }
1da177e4 257
9a3110bf
SL
258 /* calculate the checksum */
259 orig_sum = 0;
260 i = (MC_HEADER_SIZE + data_size) / DWSIZE;
261 while (i--)
262 orig_sum += ((int *)mc)[i];
263 if (orig_sum) {
264 printk(KERN_ERR "microcode: aborting, bad checksum\n");
265 return -EINVAL;
266 }
267 if (!ext_table_size)
268 return 0;
269 /* check extended signature checksum */
270 for (i = 0; i < ext_sigcount; i++) {
ade1af77
JE
271 ext_sig = (void *)ext_header + EXT_HEADER_SIZE +
272 EXT_SIGNATURE_SIZE * i;
9a3110bf
SL
273 sum = orig_sum
274 - (mc_header->sig + mc_header->pf + mc_header->cksum)
275 + (ext_sig->sig + ext_sig->pf + ext_sig->cksum);
276 if (sum) {
277 printk(KERN_ERR "microcode: aborting, bad checksum\n");
278 return -EINVAL;
1da177e4 279 }
9a3110bf
SL
280 }
281 return 0;
282}
5cf6c541 283
9a3110bf
SL
284/*
285 * return 0 - no update found
286 * return 1 - found update
9a3110bf 287 */
a0a29b62
DA
288static int
289get_matching_microcode(struct cpu_signature *cpu_sig, void *mc, int rev)
9a3110bf 290{
d4ee3668 291 struct microcode_header_intel *mc_header = mc;
9a3110bf
SL
292 struct extended_sigtable *ext_header;
293 unsigned long total_size = get_totalsize(mc_header);
294 int ext_sigcount, i;
295 struct extended_signature *ext_sig;
9a3110bf 296
a0a29b62
DA
297 if (!update_match_revision(mc_header, rev))
298 return 0;
299
300 if (update_match_cpu(cpu_sig, mc_header->sig, mc_header->pf))
301 return 1;
9a3110bf 302
a0a29b62 303 /* Look for ext. headers: */
9a3110bf
SL
304 if (total_size <= get_datasize(mc_header) + MC_HEADER_SIZE)
305 return 0;
306
ade1af77 307 ext_header = mc + get_datasize(mc_header) + MC_HEADER_SIZE;
9a3110bf 308 ext_sigcount = ext_header->count;
ade1af77 309 ext_sig = (void *)ext_header + EXT_HEADER_SIZE;
a0a29b62 310
9a3110bf 311 for (i = 0; i < ext_sigcount; i++) {
a0a29b62
DA
312 if (update_match_cpu(cpu_sig, ext_sig->sig, ext_sig->pf))
313 return 1;
9a3110bf
SL
314 ext_sig++;
315 }
316 return 0;
1da177e4
LT
317}
318
8d86f390 319static void apply_microcode(int cpu)
1da177e4
LT
320{
321 unsigned long flags;
322 unsigned int val[2];
9a3110bf 323 int cpu_num = raw_smp_processor_id();
a0a29b62 324 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
18dbc916 325 struct microcode_intel *mc_intel = uci->mc;
1da177e4 326
9a3110bf
SL
327 /* We should bind the task to the CPU */
328 BUG_ON(cpu_num != cpu);
329
18dbc916 330 if (mc_intel == NULL)
1da177e4 331 return;
1da177e4
LT
332
333 /* serialize access to the physical write to MSR 0x79 */
bc4e0f9a 334 spin_lock_irqsave(&microcode_update_lock, flags);
1da177e4
LT
335
336 /* write microcode via MSR 0x79 */
337 wrmsr(MSR_IA32_UCODE_WRITE,
18dbc916
DA
338 (unsigned long) mc_intel->bits,
339 (unsigned long) mc_intel->bits >> 16 >> 16);
1da177e4
LT
340 wrmsr(MSR_IA32_UCODE_REV, 0, 0);
341
245067d1 342 /* see notes above for revision 1.07. Apparent chip bug */
487472bc 343 sync_core();
245067d1 344
1da177e4
LT
345 /* get the current revision from MSR 0x8B */
346 rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
347
1da177e4 348 spin_unlock_irqrestore(&microcode_update_lock, flags);
18dbc916 349 if (val[1] != mc_intel->hdr.rev) {
fe176de0 350 printk(KERN_ERR "microcode: CPU%d update from revision "
d45de409 351 "0x%x to 0x%x failed\n", cpu_num, uci->cpu_sig.rev, val[1]);
9a3110bf
SL
352 return;
353 }
fe176de0 354 printk(KERN_INFO "microcode: CPU%d updated from revision "
34a1b9fc 355 "0x%x to 0x%x, date = %04x-%02x-%02x \n",
d45de409 356 cpu_num, uci->cpu_sig.rev, val[1],
18dbc916
DA
357 mc_intel->hdr.date & 0xffff,
358 mc_intel->hdr.date >> 24,
359 (mc_intel->hdr.date >> 16) & 0xff);
d45de409 360 uci->cpu_sig.rev = val[1];
1da177e4
LT
361}
362
a0a29b62
DA
363static int generic_load_microcode(int cpu, void *data, size_t size,
364 int (*get_ucode_data)(void *, const void *, size_t))
9a3110bf 365{
a0a29b62
DA
366 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
367 u8 *ucode_ptr = data, *new_mc = NULL, *mc;
368 int new_rev = uci->cpu_sig.rev;
369 unsigned int leftover = size;
9a3110bf 370
a0a29b62
DA
371 while (leftover) {
372 struct microcode_header_intel mc_header;
373 unsigned int mc_size;
9a3110bf 374
a0a29b62
DA
375 if (get_ucode_data(&mc_header, ucode_ptr, sizeof(mc_header)))
376 break;
a30a6a2c 377
a0a29b62
DA
378 mc_size = get_totalsize(&mc_header);
379 if (!mc_size || mc_size > leftover) {
380 printk(KERN_ERR "microcode: error!"
381 "Bad data in microcode data file\n");
382 break;
383 }
a30a6a2c 384
a0a29b62
DA
385 mc = vmalloc(mc_size);
386 if (!mc)
387 break;
388
389 if (get_ucode_data(mc, ucode_ptr, mc_size) ||
390 microcode_sanity_check(mc) < 0) {
391 vfree(mc);
392 break;
393 }
394
395 if (get_matching_microcode(&uci->cpu_sig, mc, new_rev)) {
a1c75cc5
IM
396 if (new_mc)
397 vfree(new_mc);
a0a29b62
DA
398 new_rev = mc_header.rev;
399 new_mc = mc;
400 } else
401 vfree(mc);
402
403 ucode_ptr += mc_size;
404 leftover -= mc_size;
a30a6a2c
SL
405 }
406
a0a29b62
DA
407 if (new_mc) {
408 if (!leftover) {
18dbc916
DA
409 if (uci->mc)
410 vfree(uci->mc);
411 uci->mc = (struct microcode_intel *)new_mc;
a0a29b62
DA
412 pr_debug("microcode: CPU%d found a matching microcode update with"
413 " version 0x%x (current=0x%x)\n",
18dbc916 414 cpu, new_rev, uci->cpu_sig.rev);
a0a29b62
DA
415 } else
416 vfree(new_mc);
a30a6a2c 417 }
a0a29b62
DA
418
419 return (int)leftover;
a30a6a2c
SL
420}
421
a0a29b62
DA
422static int get_ucode_fw(void *to, const void *from, size_t n)
423{
424 memcpy(to, from, n);
425 return 0;
426}
a30a6a2c 427
a0a29b62 428static int request_microcode_fw(int cpu, struct device *device)
a30a6a2c
SL
429{
430 char name[30];
92cb7612 431 struct cpuinfo_x86 *c = &cpu_data(cpu);
a30a6a2c 432 const struct firmware *firmware;
a0a29b62 433 int ret;
a30a6a2c
SL
434
435 /* We should bind the task to the CPU */
436 BUG_ON(cpu != raw_smp_processor_id());
3e135d88 437 sprintf(name, "intel-ucode/%02x-%02x-%02x",
a30a6a2c 438 c->x86, c->x86_model, c->x86_mask);
a0a29b62
DA
439 ret = request_firmware(&firmware, name, device);
440 if (ret) {
bc4e0f9a 441 pr_debug("microcode: data file %s load failed\n", name);
a0a29b62 442 return ret;
a30a6a2c 443 }
a0a29b62
DA
444
445 ret = generic_load_microcode(cpu, (void*)firmware->data, firmware->size,
446 &get_ucode_fw);
447
a30a6a2c
SL
448 release_firmware(firmware);
449
a0a29b62
DA
450 return ret;
451}
452
453static int get_ucode_user(void *to, const void *from, size_t n)
454{
455 return copy_from_user(to, from, n);
456}
457
458static int request_microcode_user(int cpu, const void __user *buf, size_t size)
459{
460 /* We should bind the task to the CPU */
461 BUG_ON(cpu != raw_smp_processor_id());
462
463 return generic_load_microcode(cpu, (void*)buf, size, &get_ucode_user);
a30a6a2c
SL
464}
465
8d86f390 466static void microcode_fini_cpu(int cpu)
a30a6a2c
SL
467{
468 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
469
18dbc916
DA
470 vfree(uci->mc);
471 uci->mc = NULL;
a30a6a2c 472}
8d86f390 473
18dbc916 474struct microcode_ops microcode_intel_ops = {
a0a29b62
DA
475 .request_microcode_user = request_microcode_user,
476 .request_microcode_fw = request_microcode_fw,
8d86f390
PO
477 .collect_cpu_info = collect_cpu_info,
478 .apply_microcode = apply_microcode,
479 .microcode_fini_cpu = microcode_fini_cpu,
480};
481
18dbc916 482struct microcode_ops * __init init_intel_microcode(void)
8d86f390 483{
18dbc916 484 return &microcode_intel_ops;
8d86f390
PO
485}
486