Commit | Line | Data |
---|---|---|
80cc9f10 PO |
1 | /* |
2 | * AMD CPU Microcode Update Driver for Linux | |
3 | * Copyright (C) 2008 Advanced Micro Devices Inc. | |
4 | * | |
5 | * Author: Peter Oruba <peter.oruba@amd.com> | |
6 | * | |
7 | * Based on work by: | |
8 | * Tigran Aivazian <tigran@aivazian.fsnet.co.uk> | |
9 | * | |
10 | * This driver allows to upgrade microcode on AMD | |
11 | * family 0x10 and 0x11 processors. | |
12 | * | |
2a3282a7 | 13 | * Licensed under the terms of the GNU General Public |
80cc9f10 | 14 | * License version 2. See file COPYING for details. |
4bae1967 | 15 | */ |
4bae1967 | 16 | #include <linux/firmware.h> |
4bae1967 IM |
17 | #include <linux/pci_ids.h> |
18 | #include <linux/uaccess.h> | |
19 | #include <linux/vmalloc.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/module.h> | |
80cc9f10 | 22 | #include <linux/pci.h> |
80cc9f10 | 23 | |
80cc9f10 | 24 | #include <asm/microcode.h> |
4bae1967 IM |
25 | #include <asm/processor.h> |
26 | #include <asm/msr.h> | |
80cc9f10 PO |
27 | |
28 | MODULE_DESCRIPTION("AMD Microcode Update Driver"); | |
3c52204b | 29 | MODULE_AUTHOR("Peter Oruba"); |
5d7b6052 | 30 | MODULE_LICENSE("GPL v2"); |
80cc9f10 PO |
31 | |
32 | #define UCODE_MAGIC 0x00414d44 | |
33 | #define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000 | |
34 | #define UCODE_UCODE_TYPE 0x00000001 | |
35 | ||
18dbc916 | 36 | struct equiv_cpu_entry { |
5549b94b AH |
37 | u32 installed_cpu; |
38 | u32 fixed_errata_mask; | |
39 | u32 fixed_errata_compare; | |
40 | u16 equiv_cpu; | |
41 | u16 res; | |
42 | } __attribute__((packed)); | |
18dbc916 DA |
43 | |
44 | struct microcode_header_amd { | |
5549b94b AH |
45 | u32 data_code; |
46 | u32 patch_id; | |
47 | u16 mc_patch_data_id; | |
48 | u8 mc_patch_data_len; | |
49 | u8 init_flag; | |
50 | u32 mc_patch_data_checksum; | |
51 | u32 nb_dev_id; | |
52 | u32 sb_dev_id; | |
53 | u16 processor_rev_id; | |
54 | u8 nb_rev_id; | |
55 | u8 sb_rev_id; | |
56 | u8 bios_api_rev; | |
57 | u8 reserved1[3]; | |
58 | u32 match_reg[8]; | |
59 | } __attribute__((packed)); | |
18dbc916 DA |
60 | |
61 | struct microcode_amd { | |
4bae1967 IM |
62 | struct microcode_header_amd hdr; |
63 | unsigned int mpb[0]; | |
18dbc916 DA |
64 | }; |
65 | ||
6cc9b6d9 AH |
66 | #define UCODE_MAX_SIZE 2048 |
67 | #define UCODE_CONTAINER_SECTION_HDR 8 | |
68 | #define UCODE_CONTAINER_HEADER_SIZE 12 | |
80cc9f10 | 69 | |
a0a29b62 | 70 | static struct equiv_cpu_entry *equiv_cpu_table; |
80cc9f10 | 71 | |
d45de409 | 72 | static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig) |
80cc9f10 PO |
73 | { |
74 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
29d0887f | 75 | u32 dummy; |
80cc9f10 | 76 | |
d45de409 | 77 | memset(csig, 0, sizeof(*csig)); |
80cc9f10 | 78 | if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) { |
df23cab5 AH |
79 | printk(KERN_WARNING "microcode: CPU%d: AMD CPU family 0x%x not " |
80 | "supported\n", cpu, c->x86); | |
d45de409 | 81 | return -1; |
80cc9f10 | 82 | } |
29d0887f | 83 | rdmsr(MSR_AMD64_PATCH_LEVEL, csig->rev, dummy); |
df23cab5 | 84 | printk(KERN_INFO "microcode: CPU%d: patch_level=0x%x\n", cpu, csig->rev); |
d45de409 | 85 | return 0; |
80cc9f10 PO |
86 | } |
87 | ||
a0a29b62 | 88 | static int get_matching_microcode(int cpu, void *mc, int rev) |
80cc9f10 | 89 | { |
80cc9f10 | 90 | struct microcode_header_amd *mc_header = mc; |
80cc9f10 | 91 | unsigned int current_cpu_id; |
5549b94b | 92 | u16 equiv_cpu_id = 0; |
80cc9f10 PO |
93 | unsigned int i = 0; |
94 | ||
a0a29b62 | 95 | BUG_ON(equiv_cpu_table == NULL); |
80cc9f10 PO |
96 | current_cpu_id = cpuid_eax(0x00000001); |
97 | ||
98 | while (equiv_cpu_table[i].installed_cpu != 0) { | |
99 | if (current_cpu_id == equiv_cpu_table[i].installed_cpu) { | |
5549b94b | 100 | equiv_cpu_id = equiv_cpu_table[i].equiv_cpu; |
80cc9f10 PO |
101 | break; |
102 | } | |
103 | i++; | |
104 | } | |
105 | ||
106 | if (!equiv_cpu_id) { | |
df23cab5 AH |
107 | printk(KERN_WARNING "microcode: CPU%d: cpu revision " |
108 | "not listed in equivalent cpu table\n", cpu); | |
80cc9f10 PO |
109 | return 0; |
110 | } | |
111 | ||
3c763fd7 | 112 | if (mc_header->processor_rev_id != equiv_cpu_id) { |
df23cab5 AH |
113 | printk(KERN_ERR "microcode: CPU%d: patch mismatch " |
114 | "(processor_rev_id: %x, equiv_cpu_id: %x)\n", | |
3c763fd7 | 115 | cpu, mc_header->processor_rev_id, equiv_cpu_id); |
80cc9f10 PO |
116 | return 0; |
117 | } | |
118 | ||
98415301 AH |
119 | /* ucode might be chipset specific -- currently we don't support this */ |
120 | if (mc_header->nb_dev_id || mc_header->sb_dev_id) { | |
df23cab5 | 121 | printk(KERN_ERR "microcode: CPU%d: loading of chipset " |
98415301 AH |
122 | "specific code not yet supported\n", cpu); |
123 | return 0; | |
80cc9f10 PO |
124 | } |
125 | ||
a0a29b62 | 126 | if (mc_header->patch_id <= rev) |
80cc9f10 PO |
127 | return 0; |
128 | ||
80cc9f10 PO |
129 | return 1; |
130 | } | |
131 | ||
871b72dd | 132 | static int apply_microcode_amd(int cpu) |
80cc9f10 | 133 | { |
29d0887f | 134 | u32 rev, dummy; |
80cc9f10 PO |
135 | int cpu_num = raw_smp_processor_id(); |
136 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu_num; | |
18dbc916 | 137 | struct microcode_amd *mc_amd = uci->mc; |
80cc9f10 PO |
138 | |
139 | /* We should bind the task to the CPU */ | |
140 | BUG_ON(cpu_num != cpu); | |
141 | ||
18dbc916 | 142 | if (mc_amd == NULL) |
871b72dd | 143 | return 0; |
80cc9f10 | 144 | |
f34a10bd | 145 | wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code); |
80cc9f10 | 146 | /* get patch id after patching */ |
29d0887f | 147 | rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); |
80cc9f10 PO |
148 | |
149 | /* check current patch id and patch's id for match */ | |
18dbc916 | 150 | if (rev != mc_amd->hdr.patch_id) { |
df23cab5 AH |
151 | printk(KERN_ERR "microcode: CPU%d: update failed " |
152 | "(for patch_level=0x%x)\n", cpu, mc_amd->hdr.patch_id); | |
871b72dd | 153 | return -1; |
80cc9f10 PO |
154 | } |
155 | ||
df23cab5 AH |
156 | printk(KERN_INFO "microcode: CPU%d: updated (new patch_level=0x%x)\n", |
157 | cpu, rev); | |
80cc9f10 | 158 | |
d45de409 | 159 | uci->cpu_sig.rev = rev; |
871b72dd DA |
160 | |
161 | return 0; | |
80cc9f10 PO |
162 | } |
163 | ||
0657d9eb AH |
164 | static int get_ucode_data(void *to, const u8 *from, size_t n) |
165 | { | |
166 | memcpy(to, from, n); | |
167 | return 0; | |
168 | } | |
169 | ||
4bae1967 IM |
170 | static void * |
171 | get_next_ucode(const u8 *buf, unsigned int size, unsigned int *mc_size) | |
80cc9f10 | 172 | { |
a0a29b62 | 173 | unsigned int total_size; |
d4738792 | 174 | u8 section_hdr[UCODE_CONTAINER_SECTION_HDR]; |
a0a29b62 | 175 | void *mc; |
80cc9f10 | 176 | |
d4738792 | 177 | if (get_ucode_data(section_hdr, buf, UCODE_CONTAINER_SECTION_HDR)) |
a0a29b62 | 178 | return NULL; |
80cc9f10 | 179 | |
d4738792 | 180 | if (section_hdr[0] != UCODE_UCODE_TYPE) { |
df23cab5 AH |
181 | printk(KERN_ERR "microcode: error: invalid type field in " |
182 | "container file section header\n"); | |
a0a29b62 | 183 | return NULL; |
80cc9f10 PO |
184 | } |
185 | ||
d4738792 | 186 | total_size = (unsigned long) (section_hdr[4] + (section_hdr[5] << 8)); |
80cc9f10 | 187 | |
df23cab5 AH |
188 | printk(KERN_DEBUG "microcode: size %u, total_size %u\n", |
189 | size, total_size); | |
80cc9f10 | 190 | |
a0a29b62 | 191 | if (total_size > size || total_size > UCODE_MAX_SIZE) { |
df23cab5 | 192 | printk(KERN_ERR "microcode: error: size mismatch\n"); |
a0a29b62 | 193 | return NULL; |
80cc9f10 PO |
194 | } |
195 | ||
a0a29b62 DA |
196 | mc = vmalloc(UCODE_MAX_SIZE); |
197 | if (mc) { | |
198 | memset(mc, 0, UCODE_MAX_SIZE); | |
be957763 AH |
199 | if (get_ucode_data(mc, buf + UCODE_CONTAINER_SECTION_HDR, |
200 | total_size)) { | |
a0a29b62 DA |
201 | vfree(mc); |
202 | mc = NULL; | |
203 | } else | |
d4738792 | 204 | *mc_size = total_size + UCODE_CONTAINER_SECTION_HDR; |
80cc9f10 | 205 | } |
a0a29b62 | 206 | return mc; |
80cc9f10 PO |
207 | } |
208 | ||
0657d9eb | 209 | static int install_equiv_cpu_table(const u8 *buf) |
80cc9f10 | 210 | { |
b6cffde1 PO |
211 | u8 *container_hdr[UCODE_CONTAINER_HEADER_SIZE]; |
212 | unsigned int *buf_pos = (unsigned int *)container_hdr; | |
a0a29b62 | 213 | unsigned long size; |
80cc9f10 | 214 | |
b6cffde1 | 215 | if (get_ucode_data(&container_hdr, buf, UCODE_CONTAINER_HEADER_SIZE)) |
80cc9f10 PO |
216 | return 0; |
217 | ||
a0a29b62 | 218 | size = buf_pos[2]; |
80cc9f10 | 219 | |
a0a29b62 | 220 | if (buf_pos[1] != UCODE_EQUIV_CPU_TABLE_TYPE || !size) { |
df23cab5 AH |
221 | printk(KERN_ERR "microcode: error: invalid type field in " |
222 | "container file section header\n"); | |
80cc9f10 PO |
223 | return 0; |
224 | } | |
225 | ||
226 | equiv_cpu_table = (struct equiv_cpu_entry *) vmalloc(size); | |
227 | if (!equiv_cpu_table) { | |
df23cab5 AH |
228 | printk(KERN_ERR "microcode: failed to allocate " |
229 | "equivalent CPU table\n"); | |
80cc9f10 PO |
230 | return 0; |
231 | } | |
232 | ||
b6cffde1 | 233 | buf += UCODE_CONTAINER_HEADER_SIZE; |
a0a29b62 DA |
234 | if (get_ucode_data(equiv_cpu_table, buf, size)) { |
235 | vfree(equiv_cpu_table); | |
236 | return 0; | |
237 | } | |
80cc9f10 | 238 | |
b6cffde1 | 239 | return size + UCODE_CONTAINER_HEADER_SIZE; /* add header length */ |
80cc9f10 PO |
240 | } |
241 | ||
a0a29b62 | 242 | static void free_equiv_cpu_table(void) |
80cc9f10 | 243 | { |
aeef50bc F |
244 | vfree(equiv_cpu_table); |
245 | equiv_cpu_table = NULL; | |
a0a29b62 | 246 | } |
80cc9f10 | 247 | |
871b72dd DA |
248 | static enum ucode_state |
249 | generic_load_microcode(int cpu, const u8 *data, size_t size) | |
a0a29b62 DA |
250 | { |
251 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; | |
8c135206 AH |
252 | const u8 *ucode_ptr = data; |
253 | void *new_mc = NULL; | |
254 | void *mc; | |
a0a29b62 DA |
255 | int new_rev = uci->cpu_sig.rev; |
256 | unsigned int leftover; | |
257 | unsigned long offset; | |
871b72dd | 258 | enum ucode_state state = UCODE_OK; |
80cc9f10 | 259 | |
0657d9eb | 260 | offset = install_equiv_cpu_table(ucode_ptr); |
80cc9f10 | 261 | if (!offset) { |
df23cab5 AH |
262 | printk(KERN_ERR "microcode: failed to create " |
263 | "equivalent cpu table\n"); | |
871b72dd | 264 | return UCODE_ERROR; |
80cc9f10 PO |
265 | } |
266 | ||
a0a29b62 DA |
267 | ucode_ptr += offset; |
268 | leftover = size - offset; | |
269 | ||
270 | while (leftover) { | |
2f9284e4 | 271 | unsigned int uninitialized_var(mc_size); |
a0a29b62 DA |
272 | struct microcode_header_amd *mc_header; |
273 | ||
0657d9eb | 274 | mc = get_next_ucode(ucode_ptr, leftover, &mc_size); |
a0a29b62 | 275 | if (!mc) |
80cc9f10 | 276 | break; |
a0a29b62 DA |
277 | |
278 | mc_header = (struct microcode_header_amd *)mc; | |
279 | if (get_matching_microcode(cpu, mc, new_rev)) { | |
aeef50bc | 280 | vfree(new_mc); |
a0a29b62 DA |
281 | new_rev = mc_header->patch_id; |
282 | new_mc = mc; | |
be957763 | 283 | } else |
a0a29b62 DA |
284 | vfree(mc); |
285 | ||
286 | ucode_ptr += mc_size; | |
287 | leftover -= mc_size; | |
80cc9f10 | 288 | } |
a0a29b62 DA |
289 | |
290 | if (new_mc) { | |
291 | if (!leftover) { | |
aeef50bc | 292 | vfree(uci->mc); |
18dbc916 | 293 | uci->mc = new_mc; |
be957763 AH |
294 | pr_debug("microcode: CPU%d found a matching microcode " |
295 | "update with version 0x%x (current=0x%x)\n", | |
296 | cpu, new_rev, uci->cpu_sig.rev); | |
871b72dd | 297 | } else { |
a0a29b62 | 298 | vfree(new_mc); |
871b72dd DA |
299 | state = UCODE_ERROR; |
300 | } | |
301 | } else | |
302 | state = UCODE_NFOUND; | |
a0a29b62 DA |
303 | |
304 | free_equiv_cpu_table(); | |
305 | ||
871b72dd | 306 | return state; |
a0a29b62 DA |
307 | } |
308 | ||
871b72dd | 309 | static enum ucode_state request_microcode_fw(int cpu, struct device *device) |
a0a29b62 DA |
310 | { |
311 | const char *fw_name = "amd-ucode/microcode_amd.bin"; | |
312 | const struct firmware *firmware; | |
871b72dd | 313 | enum ucode_state ret; |
a0a29b62 | 314 | |
871b72dd | 315 | if (request_firmware(&firmware, fw_name, device)) { |
df23cab5 | 316 | printk(KERN_ERR "microcode: failed to load file %s\n", fw_name); |
871b72dd | 317 | return UCODE_NFOUND; |
a0a29b62 DA |
318 | } |
319 | ||
0657d9eb | 320 | ret = generic_load_microcode(cpu, firmware->data, firmware->size); |
a0a29b62 | 321 | |
80cc9f10 PO |
322 | release_firmware(firmware); |
323 | ||
a0a29b62 DA |
324 | return ret; |
325 | } | |
326 | ||
871b72dd DA |
327 | static enum ucode_state |
328 | request_microcode_user(int cpu, const void __user *buf, size_t size) | |
a0a29b62 | 329 | { |
df23cab5 AH |
330 | printk(KERN_INFO "microcode: AMD microcode update via " |
331 | "/dev/cpu/microcode not supported\n"); | |
871b72dd | 332 | return UCODE_ERROR; |
80cc9f10 PO |
333 | } |
334 | ||
80cc9f10 PO |
335 | static void microcode_fini_cpu_amd(int cpu) |
336 | { | |
337 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; | |
338 | ||
18dbc916 DA |
339 | vfree(uci->mc); |
340 | uci->mc = NULL; | |
80cc9f10 PO |
341 | } |
342 | ||
343 | static struct microcode_ops microcode_amd_ops = { | |
a0a29b62 DA |
344 | .request_microcode_user = request_microcode_user, |
345 | .request_microcode_fw = request_microcode_fw, | |
80cc9f10 PO |
346 | .collect_cpu_info = collect_cpu_info_amd, |
347 | .apply_microcode = apply_microcode_amd, | |
348 | .microcode_fini_cpu = microcode_fini_cpu_amd, | |
349 | }; | |
350 | ||
18dbc916 | 351 | struct microcode_ops * __init init_amd_microcode(void) |
80cc9f10 | 352 | { |
18dbc916 | 353 | return µcode_amd_ops; |
80cc9f10 | 354 | } |