Commit | Line | Data |
---|---|---|
80cc9f10 PO |
1 | /* |
2 | * AMD CPU Microcode Update Driver for Linux | |
3 | * Copyright (C) 2008 Advanced Micro Devices Inc. | |
4 | * | |
5 | * Author: Peter Oruba <peter.oruba@amd.com> | |
6 | * | |
7 | * Based on work by: | |
8 | * Tigran Aivazian <tigran@aivazian.fsnet.co.uk> | |
9 | * | |
10 | * This driver allows to upgrade microcode on AMD | |
11 | * family 0x10 and 0x11 processors. | |
12 | * | |
2a3282a7 | 13 | * Licensed under the terms of the GNU General Public |
80cc9f10 | 14 | * License version 2. See file COPYING for details. |
4bae1967 | 15 | */ |
f58e1f53 JP |
16 | |
17 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
18 | ||
4bae1967 | 19 | #include <linux/firmware.h> |
4bae1967 IM |
20 | #include <linux/pci_ids.h> |
21 | #include <linux/uaccess.h> | |
22 | #include <linux/vmalloc.h> | |
23 | #include <linux/kernel.h> | |
24 | #include <linux/module.h> | |
80cc9f10 | 25 | #include <linux/pci.h> |
80cc9f10 | 26 | |
80cc9f10 | 27 | #include <asm/microcode.h> |
4bae1967 IM |
28 | #include <asm/processor.h> |
29 | #include <asm/msr.h> | |
80cc9f10 PO |
30 | |
31 | MODULE_DESCRIPTION("AMD Microcode Update Driver"); | |
3c52204b | 32 | MODULE_AUTHOR("Peter Oruba"); |
5d7b6052 | 33 | MODULE_LICENSE("GPL v2"); |
80cc9f10 PO |
34 | |
35 | #define UCODE_MAGIC 0x00414d44 | |
36 | #define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000 | |
37 | #define UCODE_UCODE_TYPE 0x00000001 | |
38 | ||
18dbc916 | 39 | struct equiv_cpu_entry { |
5549b94b AH |
40 | u32 installed_cpu; |
41 | u32 fixed_errata_mask; | |
42 | u32 fixed_errata_compare; | |
43 | u16 equiv_cpu; | |
44 | u16 res; | |
45 | } __attribute__((packed)); | |
18dbc916 DA |
46 | |
47 | struct microcode_header_amd { | |
5549b94b AH |
48 | u32 data_code; |
49 | u32 patch_id; | |
50 | u16 mc_patch_data_id; | |
51 | u8 mc_patch_data_len; | |
52 | u8 init_flag; | |
53 | u32 mc_patch_data_checksum; | |
54 | u32 nb_dev_id; | |
55 | u32 sb_dev_id; | |
56 | u16 processor_rev_id; | |
57 | u8 nb_rev_id; | |
58 | u8 sb_rev_id; | |
59 | u8 bios_api_rev; | |
60 | u8 reserved1[3]; | |
61 | u32 match_reg[8]; | |
62 | } __attribute__((packed)); | |
18dbc916 DA |
63 | |
64 | struct microcode_amd { | |
4bae1967 IM |
65 | struct microcode_header_amd hdr; |
66 | unsigned int mpb[0]; | |
18dbc916 DA |
67 | }; |
68 | ||
6cc9b6d9 AH |
69 | #define UCODE_CONTAINER_SECTION_HDR 8 |
70 | #define UCODE_CONTAINER_HEADER_SIZE 12 | |
80cc9f10 | 71 | |
a0a29b62 | 72 | static struct equiv_cpu_entry *equiv_cpu_table; |
80cc9f10 | 73 | |
d45de409 | 74 | static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig) |
80cc9f10 | 75 | { |
3b2e3d85 | 76 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
29d0887f | 77 | u32 dummy; |
80cc9f10 | 78 | |
3b2e3d85 | 79 | if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) { |
258721ef | 80 | pr_warning("CPU%d: family %d not supported\n", cpu, c->x86); |
3b2e3d85 AH |
81 | return -1; |
82 | } | |
258721ef | 83 | |
29d0887f | 84 | rdmsr(MSR_AMD64_PATCH_LEVEL, csig->rev, dummy); |
258721ef BP |
85 | pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev); |
86 | ||
d45de409 | 87 | return 0; |
80cc9f10 PO |
88 | } |
89 | ||
7cc27349 BP |
90 | static int get_matching_microcode(int cpu, struct microcode_header_amd *mc_hdr, |
91 | int rev) | |
80cc9f10 | 92 | { |
80cc9f10 | 93 | unsigned int current_cpu_id; |
5549b94b | 94 | u16 equiv_cpu_id = 0; |
80cc9f10 PO |
95 | unsigned int i = 0; |
96 | ||
a0a29b62 | 97 | BUG_ON(equiv_cpu_table == NULL); |
80cc9f10 PO |
98 | current_cpu_id = cpuid_eax(0x00000001); |
99 | ||
100 | while (equiv_cpu_table[i].installed_cpu != 0) { | |
101 | if (current_cpu_id == equiv_cpu_table[i].installed_cpu) { | |
5549b94b | 102 | equiv_cpu_id = equiv_cpu_table[i].equiv_cpu; |
80cc9f10 PO |
103 | break; |
104 | } | |
105 | i++; | |
106 | } | |
107 | ||
14c56942 | 108 | if (!equiv_cpu_id) |
80cc9f10 | 109 | return 0; |
80cc9f10 | 110 | |
7cc27349 | 111 | if (mc_hdr->processor_rev_id != equiv_cpu_id) |
80cc9f10 | 112 | return 0; |
80cc9f10 | 113 | |
98415301 | 114 | /* ucode might be chipset specific -- currently we don't support this */ |
7cc27349 | 115 | if (mc_hdr->nb_dev_id || mc_hdr->sb_dev_id) { |
258721ef | 116 | pr_err("CPU%d: chipset specific code not yet supported\n", |
f58e1f53 | 117 | cpu); |
98415301 | 118 | return 0; |
80cc9f10 PO |
119 | } |
120 | ||
7cc27349 | 121 | if (mc_hdr->patch_id <= rev) |
80cc9f10 PO |
122 | return 0; |
123 | ||
80cc9f10 PO |
124 | return 1; |
125 | } | |
126 | ||
871b72dd | 127 | static int apply_microcode_amd(int cpu) |
80cc9f10 | 128 | { |
29d0887f | 129 | u32 rev, dummy; |
80cc9f10 PO |
130 | int cpu_num = raw_smp_processor_id(); |
131 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu_num; | |
18dbc916 | 132 | struct microcode_amd *mc_amd = uci->mc; |
80cc9f10 PO |
133 | |
134 | /* We should bind the task to the CPU */ | |
135 | BUG_ON(cpu_num != cpu); | |
136 | ||
18dbc916 | 137 | if (mc_amd == NULL) |
871b72dd | 138 | return 0; |
80cc9f10 | 139 | |
f34a10bd | 140 | wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code); |
80cc9f10 | 141 | /* get patch id after patching */ |
29d0887f | 142 | rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); |
80cc9f10 PO |
143 | |
144 | /* check current patch id and patch's id for match */ | |
18dbc916 | 145 | if (rev != mc_amd->hdr.patch_id) { |
258721ef | 146 | pr_err("CPU%d: update failed for patch_level=0x%08x\n", |
f58e1f53 | 147 | cpu, mc_amd->hdr.patch_id); |
871b72dd | 148 | return -1; |
80cc9f10 PO |
149 | } |
150 | ||
258721ef | 151 | pr_info("CPU%d: new patch_level=0x%08x\n", cpu, rev); |
d45de409 | 152 | uci->cpu_sig.rev = rev; |
871b72dd DA |
153 | |
154 | return 0; | |
80cc9f10 PO |
155 | } |
156 | ||
44d60c0f BP |
157 | static unsigned int verify_ucode_size(int cpu, const u8 *buf, unsigned int size) |
158 | { | |
159 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
86b44567 | 160 | u32 max_size, actual_size; |
44d60c0f BP |
161 | |
162 | #define F1XH_MPB_MAX_SIZE 2048 | |
163 | #define F14H_MPB_MAX_SIZE 1824 | |
164 | #define F15H_MPB_MAX_SIZE 4096 | |
165 | ||
166 | switch (c->x86) { | |
167 | case 0x14: | |
168 | max_size = F14H_MPB_MAX_SIZE; | |
169 | break; | |
170 | case 0x15: | |
171 | max_size = F15H_MPB_MAX_SIZE; | |
172 | break; | |
173 | default: | |
174 | max_size = F1XH_MPB_MAX_SIZE; | |
175 | break; | |
176 | } | |
177 | ||
86b44567 | 178 | actual_size = *(u32 *)(buf + 4); |
44d60c0f BP |
179 | |
180 | if (actual_size > size || actual_size > max_size) { | |
181 | pr_err("section size mismatch\n"); | |
182 | return 0; | |
183 | } | |
184 | ||
185 | return actual_size; | |
186 | } | |
187 | ||
7cc27349 | 188 | static struct microcode_header_amd * |
44d60c0f | 189 | get_next_ucode(int cpu, const u8 *buf, unsigned int size, unsigned int *mc_size) |
80cc9f10 | 190 | { |
44d60c0f BP |
191 | struct microcode_header_amd *mc = NULL; |
192 | unsigned int actual_size = 0; | |
80cc9f10 | 193 | |
86b44567 | 194 | if (*(u32 *)buf != UCODE_UCODE_TYPE) { |
258721ef | 195 | pr_err("invalid type field in container file section header\n"); |
44d60c0f | 196 | goto out; |
80cc9f10 PO |
197 | } |
198 | ||
44d60c0f BP |
199 | actual_size = verify_ucode_size(cpu, buf, size); |
200 | if (!actual_size) | |
201 | goto out; | |
80cc9f10 | 202 | |
44d60c0f | 203 | mc = vzalloc(actual_size); |
1ea6be21 | 204 | if (!mc) |
44d60c0f | 205 | goto out; |
1ea6be21 | 206 | |
44d60c0f BP |
207 | get_ucode_data(mc, buf + UCODE_CONTAINER_SECTION_HDR, actual_size); |
208 | *mc_size = actual_size + UCODE_CONTAINER_SECTION_HDR; | |
1ea6be21 | 209 | |
44d60c0f | 210 | out: |
a0a29b62 | 211 | return mc; |
80cc9f10 PO |
212 | } |
213 | ||
0657d9eb | 214 | static int install_equiv_cpu_table(const u8 *buf) |
80cc9f10 | 215 | { |
10de52d6 BP |
216 | unsigned int *ibuf = (unsigned int *)buf; |
217 | unsigned int type = ibuf[1]; | |
218 | unsigned int size = ibuf[2]; | |
80cc9f10 | 219 | |
10de52d6 | 220 | if (type != UCODE_EQUIV_CPU_TABLE_TYPE || !size) { |
258721ef BP |
221 | pr_err("empty section/" |
222 | "invalid type field in container file section header\n"); | |
10de52d6 | 223 | return -EINVAL; |
80cc9f10 PO |
224 | } |
225 | ||
8e5e9521 | 226 | equiv_cpu_table = vmalloc(size); |
80cc9f10 | 227 | if (!equiv_cpu_table) { |
f58e1f53 | 228 | pr_err("failed to allocate equivalent CPU table\n"); |
10de52d6 | 229 | return -ENOMEM; |
80cc9f10 PO |
230 | } |
231 | ||
10de52d6 | 232 | get_ucode_data(equiv_cpu_table, buf + UCODE_CONTAINER_HEADER_SIZE, size); |
80cc9f10 | 233 | |
b6cffde1 | 234 | return size + UCODE_CONTAINER_HEADER_SIZE; /* add header length */ |
80cc9f10 PO |
235 | } |
236 | ||
a0a29b62 | 237 | static void free_equiv_cpu_table(void) |
80cc9f10 | 238 | { |
aeef50bc F |
239 | vfree(equiv_cpu_table); |
240 | equiv_cpu_table = NULL; | |
a0a29b62 | 241 | } |
80cc9f10 | 242 | |
871b72dd DA |
243 | static enum ucode_state |
244 | generic_load_microcode(int cpu, const u8 *data, size_t size) | |
a0a29b62 DA |
245 | { |
246 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; | |
7cc27349 BP |
247 | struct microcode_header_amd *mc_hdr = NULL; |
248 | unsigned int mc_size, leftover; | |
1396fa9c | 249 | int offset; |
8c135206 AH |
250 | const u8 *ucode_ptr = data; |
251 | void *new_mc = NULL; | |
258721ef | 252 | unsigned int new_rev = uci->cpu_sig.rev; |
871b72dd | 253 | enum ucode_state state = UCODE_OK; |
80cc9f10 | 254 | |
0657d9eb | 255 | offset = install_equiv_cpu_table(ucode_ptr); |
10de52d6 | 256 | if (offset < 0) { |
f58e1f53 | 257 | pr_err("failed to create equivalent cpu table\n"); |
871b72dd | 258 | return UCODE_ERROR; |
80cc9f10 PO |
259 | } |
260 | ||
a0a29b62 DA |
261 | ucode_ptr += offset; |
262 | leftover = size - offset; | |
263 | ||
264 | while (leftover) { | |
44d60c0f | 265 | mc_hdr = get_next_ucode(cpu, ucode_ptr, leftover, &mc_size); |
7cc27349 | 266 | if (!mc_hdr) |
80cc9f10 | 267 | break; |
a0a29b62 | 268 | |
7cc27349 | 269 | if (get_matching_microcode(cpu, mc_hdr, new_rev)) { |
aeef50bc | 270 | vfree(new_mc); |
7cc27349 BP |
271 | new_rev = mc_hdr->patch_id; |
272 | new_mc = mc_hdr; | |
be957763 | 273 | } else |
7cc27349 | 274 | vfree(mc_hdr); |
a0a29b62 DA |
275 | |
276 | ucode_ptr += mc_size; | |
277 | leftover -= mc_size; | |
80cc9f10 | 278 | } |
a0a29b62 | 279 | |
7cc27349 | 280 | if (!new_mc) { |
871b72dd | 281 | state = UCODE_NFOUND; |
7cc27349 BP |
282 | goto free_table; |
283 | } | |
284 | ||
285 | if (!leftover) { | |
286 | vfree(uci->mc); | |
287 | uci->mc = new_mc; | |
258721ef BP |
288 | pr_debug("CPU%d update ucode (0x%08x -> 0x%08x)\n", |
289 | cpu, uci->cpu_sig.rev, new_rev); | |
7cc27349 BP |
290 | } else { |
291 | vfree(new_mc); | |
292 | state = UCODE_ERROR; | |
293 | } | |
a0a29b62 | 294 | |
7cc27349 | 295 | free_table: |
a0a29b62 DA |
296 | free_equiv_cpu_table(); |
297 | ||
871b72dd | 298 | return state; |
a0a29b62 DA |
299 | } |
300 | ||
ffc7e8ac | 301 | static enum ucode_state request_microcode_amd(int cpu, struct device *device) |
a0a29b62 | 302 | { |
3b2e3d85 | 303 | const char *fw_name = "amd-ucode/microcode_amd.bin"; |
ffc7e8ac BP |
304 | const struct firmware *fw; |
305 | enum ucode_state ret = UCODE_NFOUND; | |
a0a29b62 | 306 | |
ffc7e8ac | 307 | if (request_firmware(&fw, fw_name, device)) { |
258721ef | 308 | pr_err("failed to load file %s\n", fw_name); |
ffc7e8ac | 309 | goto out; |
3b2e3d85 | 310 | } |
a0a29b62 | 311 | |
ffc7e8ac BP |
312 | ret = UCODE_ERROR; |
313 | if (*(u32 *)fw->data != UCODE_MAGIC) { | |
258721ef | 314 | pr_err("invalid magic value (0x%08x)\n", *(u32 *)fw->data); |
ffc7e8ac | 315 | goto fw_release; |
506f90ee BP |
316 | } |
317 | ||
ffc7e8ac | 318 | ret = generic_load_microcode(cpu, fw->data, fw->size); |
a0a29b62 | 319 | |
ffc7e8ac BP |
320 | fw_release: |
321 | release_firmware(fw); | |
3b2e3d85 | 322 | |
ffc7e8ac | 323 | out: |
a0a29b62 DA |
324 | return ret; |
325 | } | |
326 | ||
871b72dd DA |
327 | static enum ucode_state |
328 | request_microcode_user(int cpu, const void __user *buf, size_t size) | |
a0a29b62 | 329 | { |
f58e1f53 | 330 | pr_info("AMD microcode update via /dev/cpu/microcode not supported\n"); |
871b72dd | 331 | return UCODE_ERROR; |
80cc9f10 PO |
332 | } |
333 | ||
80cc9f10 PO |
334 | static void microcode_fini_cpu_amd(int cpu) |
335 | { | |
336 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; | |
337 | ||
18dbc916 DA |
338 | vfree(uci->mc); |
339 | uci->mc = NULL; | |
80cc9f10 PO |
340 | } |
341 | ||
342 | static struct microcode_ops microcode_amd_ops = { | |
a0a29b62 | 343 | .request_microcode_user = request_microcode_user, |
ffc7e8ac | 344 | .request_microcode_fw = request_microcode_amd, |
80cc9f10 PO |
345 | .collect_cpu_info = collect_cpu_info_amd, |
346 | .apply_microcode = apply_microcode_amd, | |
347 | .microcode_fini_cpu = microcode_fini_cpu_amd, | |
348 | }; | |
349 | ||
18dbc916 | 350 | struct microcode_ops * __init init_amd_microcode(void) |
80cc9f10 | 351 | { |
18dbc916 | 352 | return µcode_amd_ops; |
80cc9f10 | 353 | } |