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arch/x86/kernel/apm_32.c: use time_before, time_before_eq,
[linux-block.git] / arch / x86 / kernel / io_apic_32.c
CommitLineData
1da177e4
LT		 1/*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23#include <linux/mm.h>
1da177e4
LT		 24#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
1da177e4
LT		 28#include <linux/mc146818rtc.h>
29#include <linux/compiler.h>
30#include <linux/acpi.h>
129f6946 31#include <linux/module.h>
1da177e4 32#include <linux/sysdev.h>
2d3fcc1c 33#include <linux/pci.h>
3b7d1921 34#include <linux/msi.h>
95d77884 35#include <linux/htirq.h>
7dfb7103 36#include <linux/freezer.h>
f26d6a2b 37#include <linux/kthread.h>
54d5d424 38
1da177e4
LT		 39#include <asm/io.h>
40#include <asm/smp.h>
41#include <asm/desc.h>
42#include <asm/timer.h>
306e440d 43#include <asm/i8259.h>
3e4ff115 44#include <asm/nmi.h>
2d3fcc1c 45#include <asm/msidef.h>
8b955b0d 46#include <asm/hypertransport.h>
1da177e4
LT		 47
48#include <mach_apic.h>
874c4fe3 49#include <mach_apicdef.h>
1da177e4 50
1da177e4
LT		 51int (*ioapic_renumber_irq)(int ioapic, int irq);
52atomic_t irq_mis_count;
53
fcfd636a
EB		 54/* Where if anywhere is the i8259 connect in external int mode */
55static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
56
1da177e4 57static DEFINE_SPINLOCK(ioapic_lock);
0a1ad60d 58static DEFINE_SPINLOCK(vector_lock);
1da177e4 59
f9262c12
AK		 60int timer_over_8254 __initdata = 1;
61
1da177e4
LT		 62/*
63 * Is the SiS APIC rmw bug present ?
64 * -1 = don't know, 0 = no, 1 = yes
65 */
66int sis_apic_bug = -1;
67
68/*
69 * # of IRQ routing registers
70 */
71int nr_ioapic_registers[MAX_IO_APICS];
72
1a3f239d 73static int disable_timer_pin_1 __initdata;
66759a01 74
1da177e4
LT		 75/*
76 * Rough estimation of how many shared IRQs there are, can
77 * be changed anytime.
78 */
79#define MAX_PLUS_SHARED_IRQS NR_IRQS
80#define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
81
82/*
83 * This is performance-critical, we want to do it O(1)
84 *
85 * the indexing order of this array favors 1:1 mappings
86 * between pins and IRQs.
87 */
88
89static struct irq_pin_list {
90 int apic, pin, next;
91} irq_2_pin[PIN_MAP_SIZE];
92
130fe05d
LT		 93struct io_apic {
94 unsigned int index;
95 unsigned int unused[3];
96 unsigned int data;
97};
98
99static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
100{
101 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
102 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
103}
104
105static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
106{
107 struct io_apic __iomem *io_apic = io_apic_base(apic);
108 writel(reg, &io_apic->index);
109 return readl(&io_apic->data);
110}
111
112static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
113{
114 struct io_apic __iomem *io_apic = io_apic_base(apic);
115 writel(reg, &io_apic->index);
116 writel(value, &io_apic->data);
117}
118
119/*
120 * Re-write a value: to be used for read-modify-write
121 * cycles where the read already set up the index register.
122 *
123 * Older SiS APIC requires we rewrite the index register
124 */
125static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
126{
cb468984 127 volatile struct io_apic __iomem *io_apic = io_apic_base(apic);
130fe05d
LT		 128 if (sis_apic_bug)
129 writel(reg, &io_apic->index);
130 writel(value, &io_apic->data);
131}
132
cf4c6a2f
AK		 133union entry_union {
134 struct { u32 w1, w2; };
135 struct IO_APIC_route_entry entry;
136};
137
138static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
139{
140 union entry_union eu;
141 unsigned long flags;
142 spin_lock_irqsave(&ioapic_lock, flags);
143 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
144 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
145 spin_unlock_irqrestore(&ioapic_lock, flags);
146 return eu.entry;
147}
148
f9dadfa7
LT		 149/*
150 * When we write a new IO APIC routing entry, we need to write the high
151 * word first! If the mask bit in the low word is clear, we will enable
152 * the interrupt, and we need to make sure the entry is fully populated
153 * before that happens.
154 */
d15512f4
AK		 155static void
156__ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
cf4c6a2f 157{
cf4c6a2f
AK		 158 union entry_union eu;
159 eu.entry = e;
f9dadfa7
LT		 160 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
161 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
d15512f4
AK		 162}
163
164static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
165{
166 unsigned long flags;
167 spin_lock_irqsave(&ioapic_lock, flags);
168 __ioapic_write_entry(apic, pin, e);
f9dadfa7
LT		 169 spin_unlock_irqrestore(&ioapic_lock, flags);
170}
171
172/*
173 * When we mask an IO APIC routing entry, we need to write the low
174 * word first, in order to set the mask bit before we change the
175 * high bits!
176 */
177static void ioapic_mask_entry(int apic, int pin)
178{
179 unsigned long flags;
180 union entry_union eu = { .entry.mask = 1 };
181
cf4c6a2f
AK		 182 spin_lock_irqsave(&ioapic_lock, flags);
183 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
184 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
185 spin_unlock_irqrestore(&ioapic_lock, flags);
186}
187
1da177e4
LT		 188/*
189 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
190 * shared ISA-space IRQs, so we have to support them. We are super
191 * fast in the common case, and fast for shared ISA-space IRQs.
192 */
193static void add_pin_to_irq(unsigned int irq, int apic, int pin)
194{
195 static int first_free_entry = NR_IRQS;
196 struct irq_pin_list *entry = irq_2_pin + irq;
197
198 while (entry->next)
199 entry = irq_2_pin + entry->next;
200
201 if (entry->pin != -1) {
202 entry->next = first_free_entry;
203 entry = irq_2_pin + entry->next;
204 if (++first_free_entry >= PIN_MAP_SIZE)
205 panic("io_apic.c: whoops");
206 }
207 entry->apic = apic;
208 entry->pin = pin;
209}
210
211/*
212 * Reroute an IRQ to a different pin.
213 */
214static void __init replace_pin_at_irq(unsigned int irq,
215 int oldapic, int oldpin,
216 int newapic, int newpin)
217{
218 struct irq_pin_list *entry = irq_2_pin + irq;
219
220 while (1) {
221 if (entry->apic == oldapic && entry->pin == oldpin) {
222 entry->apic = newapic;
223 entry->pin = newpin;
224 }
225 if (!entry->next)
226 break;
227 entry = irq_2_pin + entry->next;
228 }
229}
230
231static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
232{
233 struct irq_pin_list *entry = irq_2_pin + irq;
234 unsigned int pin, reg;
235
236 for (;;) {
237 pin = entry->pin;
238 if (pin == -1)
239 break;
240 reg = io_apic_read(entry->apic, 0x10 + pin*2);
241 reg &= ~disable;
242 reg |= enable;
243 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
244 if (!entry->next)
245 break;
246 entry = irq_2_pin + entry->next;
247 }
248}
249
250/* mask = 1 */
251static void __mask_IO_APIC_irq (unsigned int irq)
252{
253 __modify_IO_APIC_irq(irq, 0x00010000, 0);
254}
255
256/* mask = 0 */
257static void __unmask_IO_APIC_irq (unsigned int irq)
258{
259 __modify_IO_APIC_irq(irq, 0, 0x00010000);
260}
261
262/* mask = 1, trigger = 0 */
263static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
264{
265 __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
266}
267
268/* mask = 0, trigger = 1 */
269static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
270{
271 __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
272}
273
274static void mask_IO_APIC_irq (unsigned int irq)
275{
276 unsigned long flags;
277
278 spin_lock_irqsave(&ioapic_lock, flags);
279 __mask_IO_APIC_irq(irq);
280 spin_unlock_irqrestore(&ioapic_lock, flags);
281}
282
283static void unmask_IO_APIC_irq (unsigned int irq)
284{
285 unsigned long flags;
286
287 spin_lock_irqsave(&ioapic_lock, flags);
288 __unmask_IO_APIC_irq(irq);
289 spin_unlock_irqrestore(&ioapic_lock, flags);
290}
291
292static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
293{
294 struct IO_APIC_route_entry entry;
1da177e4
LT		 295
296 /* Check delivery_mode to be sure we're not clearing an SMI pin */
cf4c6a2f 297 entry = ioapic_read_entry(apic, pin);
1da177e4
LT		 298 if (entry.delivery_mode == dest_SMI)
299 return;
300
301 /*
302 * Disable it in the IO-APIC irq-routing table:
303 */
f9dadfa7 304 ioapic_mask_entry(apic, pin);
1da177e4
LT		 305}
306
307static void clear_IO_APIC (void)
308{
309 int apic, pin;
310
311 for (apic = 0; apic < nr_ioapics; apic++)
312 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
313 clear_IO_APIC_pin(apic, pin);
314}
315
54d5d424 316#ifdef CONFIG_SMP
1da177e4
LT		 317static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
318{
319 unsigned long flags;
320 int pin;
321 struct irq_pin_list *entry = irq_2_pin + irq;
322 unsigned int apicid_value;
54d5d424 323 cpumask_t tmp;
1da177e4 324
54d5d424
AR		 325 cpus_and(tmp, cpumask, cpu_online_map);
326 if (cpus_empty(tmp))
327 tmp = TARGET_CPUS;
328
329 cpus_and(cpumask, tmp, CPU_MASK_ALL);
330
1da177e4
LT		 331 apicid_value = cpu_mask_to_apicid(cpumask);
332 /* Prepare to do the io_apic_write */
333 apicid_value = apicid_value << 24;
334 spin_lock_irqsave(&ioapic_lock, flags);
335 for (;;) {
336 pin = entry->pin;
337 if (pin == -1)
338 break;
339 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
340 if (!entry->next)
341 break;
342 entry = irq_2_pin + entry->next;
343 }
9f0a5ba5 344 irq_desc[irq].affinity = cpumask;
1da177e4
LT		 345 spin_unlock_irqrestore(&ioapic_lock, flags);
346}
347
348#if defined(CONFIG_IRQBALANCE)
349# include <asm/processor.h> /* kernel_thread() */
350# include <linux/kernel_stat.h> /* kstat */
351# include <linux/slab.h> /* kmalloc() */
352# include <linux/timer.h> /* time_after() */
353
1da177e4 354#define IRQBALANCE_CHECK_ARCH -999
1b61b910
ZY		 355#define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
356#define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
357#define BALANCED_IRQ_MORE_DELTA (HZ/10)
358#define BALANCED_IRQ_LESS_DELTA (HZ)
359
360static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
361static int physical_balance __read_mostly;
362static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
1da177e4
LT		 363
364static struct irq_cpu_info {
365 unsigned long * last_irq;
366 unsigned long * irq_delta;
367 unsigned long irq;
368} irq_cpu_data[NR_CPUS];
369
370#define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
371#define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
372#define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
373
374#define IDLE_ENOUGH(cpu,now) \
375 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
376
377#define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
378
d5a7430d 379#define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i)))
1da177e4 380
1b61b910
ZY		 381static cpumask_t balance_irq_affinity[NR_IRQS] = {
382 [0 ... NR_IRQS-1] = CPU_MASK_ALL
383};
1da177e4 384
1b61b910
ZY		 385void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
386{
387 balance_irq_affinity[irq] = mask;
388}
1da177e4
LT		 389
390static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
391 unsigned long now, int direction)
392{
393 int search_idle = 1;
394 int cpu = curr_cpu;
395
396 goto inside;
397
398 do {
399 if (unlikely(cpu == curr_cpu))
400 search_idle = 0;
401inside:
402 if (direction == 1) {
403 cpu++;
404 if (cpu >= NR_CPUS)
405 cpu = 0;
406 } else {
407 cpu--;
408 if (cpu == -1)
409 cpu = NR_CPUS-1;
410 }
411 } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
412 (search_idle && !IDLE_ENOUGH(cpu,now)));
413
414 return cpu;
415}
416
417static inline void balance_irq(int cpu, int irq)
418{
419 unsigned long now = jiffies;
420 cpumask_t allowed_mask;
421 unsigned int new_cpu;
422
423 if (irqbalance_disabled)
424 return;
425
1b61b910 426 cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
1da177e4
LT		 427 new_cpu = move(cpu, allowed_mask, now, 1);
428 if (cpu != new_cpu) {
54d5d424 429 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
1da177e4
LT		 430 }
431}
432
433static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
434{
435 int i, j;
edc2cbf4 436
394e3902
AM		 437 for_each_online_cpu(i) {
438 for (j = 0; j < NR_IRQS; j++) {
1da177e4
LT		 439 if (!irq_desc[j].action)
440 continue;
441 /* Is it a significant load ? */
442 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
443 useful_load_threshold)
444 continue;
445 balance_irq(i, j);
446 }
447 }
448 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
449 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
450 return;
451}
452
453static void do_irq_balance(void)
454{
455 int i, j;
456 unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
457 unsigned long move_this_load = 0;
458 int max_loaded = 0, min_loaded = 0;
459 int load;
460 unsigned long useful_load_threshold = balanced_irq_interval + 10;
461 int selected_irq;
462 int tmp_loaded, first_attempt = 1;
463 unsigned long tmp_cpu_irq;
464 unsigned long imbalance = 0;
465 cpumask_t allowed_mask, target_cpu_mask, tmp;
466
c8912599 467 for_each_possible_cpu(i) {
1da177e4
LT		 468 int package_index;
469 CPU_IRQ(i) = 0;
470 if (!cpu_online(i))
471 continue;
472 package_index = CPU_TO_PACKAGEINDEX(i);
473 for (j = 0; j < NR_IRQS; j++) {
474 unsigned long value_now, delta;
950f4427
TG		 475 /* Is this an active IRQ or balancing disabled ? */
476 if (!irq_desc[j].action || irq_balancing_disabled(j))
1da177e4
LT		 477 continue;
478 if ( package_index == i )
479 IRQ_DELTA(package_index,j) = 0;
480 /* Determine the total count per processor per IRQ */
481 value_now = (unsigned long) kstat_cpu(i).irqs[j];
482
483 /* Determine the activity per processor per IRQ */
484 delta = value_now - LAST_CPU_IRQ(i,j);
485
486 /* Update last_cpu_irq[][] for the next time */
487 LAST_CPU_IRQ(i,j) = value_now;
488
489 /* Ignore IRQs whose rate is less than the clock */
490 if (delta < useful_load_threshold)
491 continue;
492 /* update the load for the processor or package total */
493 IRQ_DELTA(package_index,j) += delta;
494
495 /* Keep track of the higher numbered sibling as well */
496 if (i != package_index)
497 CPU_IRQ(i) += delta;
498 /*
499 * We have sibling A and sibling B in the package
500 *
501 * cpu_irq[A] = load for cpu A + load for cpu B
502 * cpu_irq[B] = load for cpu B
503 */
504 CPU_IRQ(package_index) += delta;
505 }
506 }
507 /* Find the least loaded processor package */
394e3902 508 for_each_online_cpu(i) {
1da177e4
LT		 509 if (i != CPU_TO_PACKAGEINDEX(i))
510 continue;
511 if (min_cpu_irq > CPU_IRQ(i)) {
512 min_cpu_irq = CPU_IRQ(i);
513 min_loaded = i;
514 }
515 }
516 max_cpu_irq = ULONG_MAX;
517
518tryanothercpu:
519 /* Look for heaviest loaded processor.
520 * We may come back to get the next heaviest loaded processor.
521 * Skip processors with trivial loads.
522 */
523 tmp_cpu_irq = 0;
524 tmp_loaded = -1;
394e3902 525 for_each_online_cpu(i) {
1da177e4
LT		 526 if (i != CPU_TO_PACKAGEINDEX(i))
527 continue;
528 if (max_cpu_irq <= CPU_IRQ(i))
529 continue;
530 if (tmp_cpu_irq < CPU_IRQ(i)) {
531 tmp_cpu_irq = CPU_IRQ(i);
532 tmp_loaded = i;
533 }
534 }
535
536 if (tmp_loaded == -1) {
537 /* In the case of small number of heavy interrupt sources,
538 * loading some of the cpus too much. We use Ingo's original
539 * approach to rotate them around.
540 */
541 if (!first_attempt && imbalance >= useful_load_threshold) {
542 rotate_irqs_among_cpus(useful_load_threshold);
543 return;
544 }
545 goto not_worth_the_effort;
546 }
547
548 first_attempt = 0; /* heaviest search */
549 max_cpu_irq = tmp_cpu_irq; /* load */
550 max_loaded = tmp_loaded; /* processor */
551 imbalance = (max_cpu_irq - min_cpu_irq) / 2;
552
1da177e4
LT		 553 /* if imbalance is less than approx 10% of max load, then
554 * observe diminishing returns action. - quit
555 */
edc2cbf4 556 if (imbalance < (max_cpu_irq >> 3))
1da177e4 557 goto not_worth_the_effort;
1da177e4
LT		 558
559tryanotherirq:
560 /* if we select an IRQ to move that can't go where we want, then
561 * see if there is another one to try.
562 */
563 move_this_load = 0;
564 selected_irq = -1;
565 for (j = 0; j < NR_IRQS; j++) {
566 /* Is this an active IRQ? */
567 if (!irq_desc[j].action)
568 continue;
569 if (imbalance <= IRQ_DELTA(max_loaded,j))
570 continue;
571 /* Try to find the IRQ that is closest to the imbalance
572 * without going over.
573 */
574 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
575 move_this_load = IRQ_DELTA(max_loaded,j);
576 selected_irq = j;
577 }
578 }
579 if (selected_irq == -1) {
580 goto tryanothercpu;
581 }
582
583 imbalance = move_this_load;
584
27b46d76 585 /* For physical_balance case, we accumulated both load
1da177e4
LT		 586 * values in the one of the siblings cpu_irq[],
587 * to use the same code for physical and logical processors
588 * as much as possible.
589 *
590 * NOTE: the cpu_irq[] array holds the sum of the load for
591 * sibling A and sibling B in the slot for the lowest numbered
592 * sibling (A), _AND_ the load for sibling B in the slot for
593 * the higher numbered sibling.
594 *
595 * We seek the least loaded sibling by making the comparison
596 * (A+B)/2 vs B
597 */
598 load = CPU_IRQ(min_loaded) >> 1;
d5a7430d 599 for_each_cpu_mask(j, per_cpu(cpu_sibling_map, min_loaded)) {
1da177e4
LT		 600 if (load > CPU_IRQ(j)) {
601 /* This won't change cpu_sibling_map[min_loaded] */
602 load = CPU_IRQ(j);
603 min_loaded = j;
604 }
605 }
606
1b61b910
ZY		 607 cpus_and(allowed_mask,
608 cpu_online_map,
609 balance_irq_affinity[selected_irq]);
1da177e4
LT		 610 target_cpu_mask = cpumask_of_cpu(min_loaded);
611 cpus_and(tmp, target_cpu_mask, allowed_mask);
612
613 if (!cpus_empty(tmp)) {
1da177e4 614 /* mark for change destination */
54d5d424
AR		 615 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
616
1da177e4
LT		 617 /* Since we made a change, come back sooner to
618 * check for more variation.
619 */
620 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
621 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
622 return;
623 }
624 goto tryanotherirq;
625
626not_worth_the_effort:
627 /*
628 * if we did not find an IRQ to move, then adjust the time interval
629 * upward
630 */
631 balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
632 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
1da177e4
LT		 633 return;
634}
635
636static int balanced_irq(void *unused)
637{
638 int i;
639 unsigned long prev_balance_time = jiffies;
640 long time_remaining = balanced_irq_interval;
641
1da177e4
LT		 642 /* push everything to CPU 0 to give us a starting point. */
643 for (i = 0 ; i < NR_IRQS ; i++) {
cd916d31 644 irq_desc[i].pending_mask = cpumask_of_cpu(0);
54d5d424 645 set_pending_irq(i, cpumask_of_cpu(0));
1da177e4
LT		 646 }
647
83144186 648 set_freezable();
1da177e4 649 for ( ; ; ) {
52e6e630 650 time_remaining = schedule_timeout_interruptible(time_remaining);
3e1d1d28 651 try_to_freeze();
1da177e4
LT		 652 if (time_after(jiffies,
653 prev_balance_time+balanced_irq_interval)) {
f3705136 654 preempt_disable();
1da177e4
LT		 655 do_irq_balance();
656 prev_balance_time = jiffies;
657 time_remaining = balanced_irq_interval;
f3705136 658 preempt_enable();
1da177e4
LT		 659 }
660 }
661 return 0;
662}
663
664static int __init balanced_irq_init(void)
665{
666 int i;
667 struct cpuinfo_x86 *c;
668 cpumask_t tmp;
669
670 cpus_shift_right(tmp, cpu_online_map, 2);
671 c = &boot_cpu_data;
672 /* When not overwritten by the command line ask subarchitecture. */
673 if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
674 irqbalance_disabled = NO_BALANCE_IRQ;
675 if (irqbalance_disabled)
676 return 0;
677
678 /* disable irqbalance completely if there is only one processor online */
679 if (num_online_cpus() < 2) {
680 irqbalance_disabled = 1;
681 return 0;
682 }
683 /*
684 * Enable physical balance only if more than 1 physical processor
685 * is present
686 */
687 if (smp_num_siblings > 1 && !cpus_empty(tmp))
688 physical_balance = 1;
689
394e3902 690 for_each_online_cpu(i) {
1da177e4
LT		 691 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
692 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
693 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
694 printk(KERN_ERR "balanced_irq_init: out of memory");
695 goto failed;
696 }
697 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
698 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
699 }
700
701 printk(KERN_INFO "Starting balanced_irq\n");
f26d6a2b 702 if (!IS_ERR(kthread_run(balanced_irq, NULL, "kirqd")))
1da177e4 703 return 0;
f26d6a2b 704 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
1da177e4 705failed:
c8912599 706 for_each_possible_cpu(i) {
4ae6673e 707 kfree(irq_cpu_data[i].irq_delta);
394e3902 708 irq_cpu_data[i].irq_delta = NULL;
4ae6673e 709 kfree(irq_cpu_data[i].last_irq);
394e3902 710 irq_cpu_data[i].last_irq = NULL;
1da177e4
LT		 711 }
712 return 0;
713}
714
c2481cc4 715int __devinit irqbalance_disable(char *str)
1da177e4
LT		 716{
717 irqbalance_disabled = 1;
9b41046c 718 return 1;
1da177e4
LT		 719}
720
721__setup("noirqbalance", irqbalance_disable);
722
1da177e4 723late_initcall(balanced_irq_init);
1da177e4 724#endif /* CONFIG_IRQBALANCE */
54d5d424 725#endif /* CONFIG_SMP */
1da177e4
LT		 726
727#ifndef CONFIG_SMP
75604d7f 728void send_IPI_self(int vector)
1da177e4
LT		 729{
730 unsigned int cfg;
731
732 /*
733 * Wait for idle.
734 */
735 apic_wait_icr_idle();
736 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
737 /*
738 * Send the IPI. The write to APIC_ICR fires this off.
739 */
740 apic_write_around(APIC_ICR, cfg);
741}
742#endif /* !CONFIG_SMP */
743
744
745/*
746 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
747 * specific CPU-side IRQs.
748 */
749
750#define MAX_PIRQS 8
751static int pirq_entries [MAX_PIRQS];
752static int pirqs_enabled;
753int skip_ioapic_setup;
754
1da177e4
LT		 755static int __init ioapic_pirq_setup(char *str)
756{
757 int i, max;
758 int ints[MAX_PIRQS+1];
759
760 get_options(str, ARRAY_SIZE(ints), ints);
761
762 for (i = 0; i < MAX_PIRQS; i++)
763 pirq_entries[i] = -1;
764
765 pirqs_enabled = 1;
766 apic_printk(APIC_VERBOSE, KERN_INFO
767 "PIRQ redirection, working around broken MP-BIOS.\n");
768 max = MAX_PIRQS;
769 if (ints[0] < MAX_PIRQS)
770 max = ints[0];
771
772 for (i = 0; i < max; i++) {
773 apic_printk(APIC_VERBOSE, KERN_DEBUG
774 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
775 /*
776 * PIRQs are mapped upside down, usually.
777 */
778 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
779 }
780 return 1;
781}
782
783__setup("pirq=", ioapic_pirq_setup);
784
785/*
786 * Find the IRQ entry number of a certain pin.
787 */
788static int find_irq_entry(int apic, int pin, int type)
789{
790 int i;
791
792 for (i = 0; i < mp_irq_entries; i++)
793 if (mp_irqs[i].mpc_irqtype == type &&
794 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
795 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
796 mp_irqs[i].mpc_dstirq == pin)
797 return i;
798
799 return -1;
800}
801
802/*
803 * Find the pin to which IRQ[irq] (ISA) is connected
804 */
fcfd636a 805static int __init find_isa_irq_pin(int irq, int type)
1da177e4
LT		 806{
807 int i;
808
809 for (i = 0; i < mp_irq_entries; i++) {
810 int lbus = mp_irqs[i].mpc_srcbus;
811
812 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
813 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
d7fb0271 814 mp_bus_id_to_type[lbus] == MP_BUS_MCA
1da177e4
LT		 815 ) &&
816 (mp_irqs[i].mpc_irqtype == type) &&
817 (mp_irqs[i].mpc_srcbusirq == irq))
818
819 return mp_irqs[i].mpc_dstirq;
820 }
821 return -1;
822}
823
fcfd636a
EB		 824static int __init find_isa_irq_apic(int irq, int type)
825{
826 int i;
827
828 for (i = 0; i < mp_irq_entries; i++) {
829 int lbus = mp_irqs[i].mpc_srcbus;
830
831 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
832 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
d7fb0271 833 mp_bus_id_to_type[lbus] == MP_BUS_MCA
fcfd636a
EB		 834 ) &&
835 (mp_irqs[i].mpc_irqtype == type) &&
836 (mp_irqs[i].mpc_srcbusirq == irq))
837 break;
838 }
839 if (i < mp_irq_entries) {
840 int apic;
841 for(apic = 0; apic < nr_ioapics; apic++) {
842 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
843 return apic;
844 }
845 }
846
847 return -1;
848}
849
1da177e4
LT		 850/*
851 * Find a specific PCI IRQ entry.
852 * Not an __init, possibly needed by modules
853 */
854static int pin_2_irq(int idx, int apic, int pin);
855
856int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
857{
858 int apic, i, best_guess = -1;
859
860 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
861 "slot:%d, pin:%d.\n", bus, slot, pin);
862 if (mp_bus_id_to_pci_bus[bus] == -1) {
863 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
864 return -1;
865 }
866 for (i = 0; i < mp_irq_entries; i++) {
867 int lbus = mp_irqs[i].mpc_srcbus;
868
869 for (apic = 0; apic < nr_ioapics; apic++)
870 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
871 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
872 break;
873
874 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
875 !mp_irqs[i].mpc_irqtype &&
876 (bus == lbus) &&
877 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
878 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
879
880 if (!(apic || IO_APIC_IRQ(irq)))
881 continue;
882
883 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
884 return irq;
885 /*
886 * Use the first all-but-pin matching entry as a
887 * best-guess fuzzy result for broken mptables.
888 */
889 if (best_guess < 0)
890 best_guess = irq;
891 }
892 }
893 return best_guess;
894}
129f6946 895EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1da177e4
LT		 896
897/*
898 * This function currently is only a helper for the i386 smp boot process where
899 * we need to reprogram the ioredtbls to cater for the cpus which have come online
900 * so mask in all cases should simply be TARGET_CPUS
901 */
54d5d424 902#ifdef CONFIG_SMP
1da177e4
LT		 903void __init setup_ioapic_dest(void)
904{
905 int pin, ioapic, irq, irq_entry;
906
907 if (skip_ioapic_setup == 1)
908 return;
909
910 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
911 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
912 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
913 if (irq_entry == -1)
914 continue;
915 irq = pin_2_irq(irq_entry, ioapic, pin);
916 set_ioapic_affinity_irq(irq, TARGET_CPUS);
917 }
918
919 }
920}
54d5d424 921#endif
1da177e4
LT		 922
923/*
924 * EISA Edge/Level control register, ELCR
925 */
926static int EISA_ELCR(unsigned int irq)
927{
928 if (irq < 16) {
929 unsigned int port = 0x4d0 + (irq >> 3);
930 return (inb(port) >> (irq & 7)) & 1;
931 }
932 apic_printk(APIC_VERBOSE, KERN_INFO
933 "Broken MPtable reports ISA irq %d\n", irq);
934 return 0;
935}
936
937/* EISA interrupts are always polarity zero and can be edge or level
938 * trigger depending on the ELCR value. If an interrupt is listed as
939 * EISA conforming in the MP table, that means its trigger type must
940 * be read in from the ELCR */
941
942#define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
943#define default_EISA_polarity(idx) (0)
944
945/* ISA interrupts are always polarity zero edge triggered,
946 * when listed as conforming in the MP table. */
947
948#define default_ISA_trigger(idx) (0)
949#define default_ISA_polarity(idx) (0)
950
951/* PCI interrupts are always polarity one level triggered,
952 * when listed as conforming in the MP table. */
953
954#define default_PCI_trigger(idx) (1)
955#define default_PCI_polarity(idx) (1)
956
957/* MCA interrupts are always polarity zero level triggered,
958 * when listed as conforming in the MP table. */
959
960#define default_MCA_trigger(idx) (1)
961#define default_MCA_polarity(idx) (0)
962
61fd47e0 963static int MPBIOS_polarity(int idx)
1da177e4
LT		 964{
965 int bus = mp_irqs[idx].mpc_srcbus;
966 int polarity;
967
968 /*
969 * Determine IRQ line polarity (high active or low active):
970 */
971 switch (mp_irqs[idx].mpc_irqflag & 3)
972 {
973 case 0: /* conforms, ie. bus-type dependent polarity */
974 {
975 switch (mp_bus_id_to_type[bus])
976 {
977 case MP_BUS_ISA: /* ISA pin */
978 {
979 polarity = default_ISA_polarity(idx);
980 break;
981 }
982 case MP_BUS_EISA: /* EISA pin */
983 {
984 polarity = default_EISA_polarity(idx);
985 break;
986 }
987 case MP_BUS_PCI: /* PCI pin */
988 {
989 polarity = default_PCI_polarity(idx);
990 break;
991 }
992 case MP_BUS_MCA: /* MCA pin */
993 {
994 polarity = default_MCA_polarity(idx);
995 break;
996 }
1da177e4
LT		 997 default:
998 {
999 printk(KERN_WARNING "broken BIOS!!\n");
1000 polarity = 1;
1001 break;
1002 }
1003 }
1004 break;
1005 }
1006 case 1: /* high active */
1007 {
1008 polarity = 0;
1009 break;
1010 }
1011 case 2: /* reserved */
1012 {
1013 printk(KERN_WARNING "broken BIOS!!\n");
1014 polarity = 1;
1015 break;
1016 }
1017 case 3: /* low active */
1018 {
1019 polarity = 1;
1020 break;
1021 }
1022 default: /* invalid */
1023 {
1024 printk(KERN_WARNING "broken BIOS!!\n");
1025 polarity = 1;
1026 break;
1027 }
1028 }
1029 return polarity;
1030}
1031
1032static int MPBIOS_trigger(int idx)
1033{
1034 int bus = mp_irqs[idx].mpc_srcbus;
1035 int trigger;
1036
1037 /*
1038 * Determine IRQ trigger mode (edge or level sensitive):
1039 */
1040 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1041 {
1042 case 0: /* conforms, ie. bus-type dependent */
1043 {
1044 switch (mp_bus_id_to_type[bus])
1045 {
1046 case MP_BUS_ISA: /* ISA pin */
1047 {
1048 trigger = default_ISA_trigger(idx);
1049 break;
1050 }
1051 case MP_BUS_EISA: /* EISA pin */
1052 {
1053 trigger = default_EISA_trigger(idx);
1054 break;
1055 }
1056 case MP_BUS_PCI: /* PCI pin */
1057 {
1058 trigger = default_PCI_trigger(idx);
1059 break;
1060 }
1061 case MP_BUS_MCA: /* MCA pin */
1062 {
1063 trigger = default_MCA_trigger(idx);
1064 break;
1065 }
1da177e4
LT		 1066 default:
1067 {
1068 printk(KERN_WARNING "broken BIOS!!\n");
1069 trigger = 1;
1070 break;
1071 }
1072 }
1073 break;
1074 }
1075 case 1: /* edge */
1076 {
1077 trigger = 0;
1078 break;
1079 }
1080 case 2: /* reserved */
1081 {
1082 printk(KERN_WARNING "broken BIOS!!\n");
1083 trigger = 1;
1084 break;
1085 }
1086 case 3: /* level */
1087 {
1088 trigger = 1;
1089 break;
1090 }
1091 default: /* invalid */
1092 {
1093 printk(KERN_WARNING "broken BIOS!!\n");
1094 trigger = 0;
1095 break;
1096 }
1097 }
1098 return trigger;
1099}
1100
1101static inline int irq_polarity(int idx)
1102{
1103 return MPBIOS_polarity(idx);
1104}
1105
1106static inline int irq_trigger(int idx)
1107{
1108 return MPBIOS_trigger(idx);
1109}
1110
1111static int pin_2_irq(int idx, int apic, int pin)
1112{
1113 int irq, i;
1114 int bus = mp_irqs[idx].mpc_srcbus;
1115
1116 /*
1117 * Debugging check, we are in big trouble if this message pops up!
1118 */
1119 if (mp_irqs[idx].mpc_dstirq != pin)
1120 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1121
1122 switch (mp_bus_id_to_type[bus])
1123 {
1124 case MP_BUS_ISA: /* ISA pin */
1125 case MP_BUS_EISA:
1126 case MP_BUS_MCA:
1da177e4
LT		 1127 {
1128 irq = mp_irqs[idx].mpc_srcbusirq;
1129 break;
1130 }
1131 case MP_BUS_PCI: /* PCI pin */
1132 {
1133 /*
1134 * PCI IRQs are mapped in order
1135 */
1136 i = irq = 0;
1137 while (i < apic)
1138 irq += nr_ioapic_registers[i++];
1139 irq += pin;
1140
1141 /*
1142 * For MPS mode, so far only needed by ES7000 platform
1143 */
1144 if (ioapic_renumber_irq)
1145 irq = ioapic_renumber_irq(apic, irq);
1146
1147 break;
1148 }
1149 default:
1150 {
1151 printk(KERN_ERR "unknown bus type %d.\n",bus);
1152 irq = 0;
1153 break;
1154 }
1155 }
1156
1157 /*
1158 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1159 */
1160 if ((pin >= 16) && (pin <= 23)) {
1161 if (pirq_entries[pin-16] != -1) {
1162 if (!pirq_entries[pin-16]) {
1163 apic_printk(APIC_VERBOSE, KERN_DEBUG
1164 "disabling PIRQ%d\n", pin-16);
1165 } else {
1166 irq = pirq_entries[pin-16];
1167 apic_printk(APIC_VERBOSE, KERN_DEBUG
1168 "using PIRQ%d -> IRQ %d\n",
1169 pin-16, irq);
1170 }
1171 }
1172 }
1173 return irq;
1174}
1175
1176static inline int IO_APIC_irq_trigger(int irq)
1177{
1178 int apic, idx, pin;
1179
1180 for (apic = 0; apic < nr_ioapics; apic++) {
1181 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1182 idx = find_irq_entry(apic,pin,mp_INT);
1183 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1184 return irq_trigger(idx);
1185 }
1186 }
1187 /*
1188 * nonexistent IRQs are edge default
1189 */
1190 return 0;
1191}
1192
1193/* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
7e95b593 1194static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1da177e4 1195
ace80ab7 1196static int __assign_irq_vector(int irq)
1da177e4 1197{
8339f000 1198 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
dbeb2be2 1199 int vector, offset;
1da177e4 1200
ace80ab7 1201 BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
0a1ad60d 1202
b940d22d
EB		 1203 if (irq_vector[irq] > 0)
1204 return irq_vector[irq];
ace80ab7 1205
0a1ad60d 1206 vector = current_vector;
8339f000
EB		 1207 offset = current_offset;
1208next:
1209 vector += 8;
1210 if (vector >= FIRST_SYSTEM_VECTOR) {
1211 offset = (offset + 1) % 8;
1212 vector = FIRST_DEVICE_VECTOR + offset;
1213 }
1214 if (vector == current_vector)
1215 return -ENOSPC;
dbeb2be2 1216 if (test_and_set_bit(vector, used_vectors))
8339f000 1217 goto next;
8339f000
EB		 1218
1219 current_vector = vector;
1220 current_offset = offset;
b940d22d 1221 irq_vector[irq] = vector;
ace80ab7
EB		 1222
1223 return vector;
1224}
0a1ad60d 1225
ace80ab7
EB		 1226static int assign_irq_vector(int irq)
1227{
1228 unsigned long flags;
1229 int vector;
1230
1231 spin_lock_irqsave(&vector_lock, flags);
1232 vector = __assign_irq_vector(irq);
26a3c49c 1233 spin_unlock_irqrestore(&vector_lock, flags);
1da177e4 1234
0a1ad60d 1235 return vector;
1da177e4 1236}
f5b9ed7a 1237static struct irq_chip ioapic_chip;
1da177e4
LT		 1238
1239#define IOAPIC_AUTO -1
1240#define IOAPIC_EDGE 0
1241#define IOAPIC_LEVEL 1
1242
d1bef4ed 1243static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1da177e4 1244{
6ebcc00e 1245 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
cc75b92d
TG		 1246 trigger == IOAPIC_LEVEL) {
1247 irq_desc[irq].status |= IRQ_LEVEL;
a460e745
IM		 1248 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1249 handle_fasteoi_irq, "fasteoi");
cc75b92d
TG		 1250 } else {
1251 irq_desc[irq].status &= ~IRQ_LEVEL;
a460e745
IM		 1252 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1253 handle_edge_irq, "edge");
cc75b92d 1254 }
ace80ab7 1255 set_intr_gate(vector, interrupt[irq]);
1da177e4
LT		 1256}
1257
1258static void __init setup_IO_APIC_irqs(void)
1259{
1260 struct IO_APIC_route_entry entry;
1261 int apic, pin, idx, irq, first_notcon = 1, vector;
1262 unsigned long flags;
1263
1264 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1265
1266 for (apic = 0; apic < nr_ioapics; apic++) {
1267 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1268
1269 /*
1270 * add it to the IO-APIC irq-routing table:
1271 */
1272 memset(&entry,0,sizeof(entry));
1273
1274 entry.delivery_mode = INT_DELIVERY_MODE;
1275 entry.dest_mode = INT_DEST_MODE;
1276 entry.mask = 0; /* enable IRQ */
1277 entry.dest.logical.logical_dest =
1278 cpu_mask_to_apicid(TARGET_CPUS);
1279
1280 idx = find_irq_entry(apic,pin,mp_INT);
1281 if (idx == -1) {
1282 if (first_notcon) {
1283 apic_printk(APIC_VERBOSE, KERN_DEBUG
1284 " IO-APIC (apicid-pin) %d-%d",
1285 mp_ioapics[apic].mpc_apicid,
1286 pin);
1287 first_notcon = 0;
1288 } else
1289 apic_printk(APIC_VERBOSE, ", %d-%d",
1290 mp_ioapics[apic].mpc_apicid, pin);
1291 continue;
1292 }
1293
20d225b9
YL		 1294 if (!first_notcon) {
1295 apic_printk(APIC_VERBOSE, " not connected.\n");
1296 first_notcon = 1;
1297 }
1298
1da177e4
LT		 1299 entry.trigger = irq_trigger(idx);
1300 entry.polarity = irq_polarity(idx);
1301
1302 if (irq_trigger(idx)) {
1303 entry.trigger = 1;
1304 entry.mask = 1;
1305 }
1306
1307 irq = pin_2_irq(idx, apic, pin);
1308 /*
1309 * skip adding the timer int on secondary nodes, which causes
1310 * a small but painful rift in the time-space continuum
1311 */
1312 if (multi_timer_check(apic, irq))
1313 continue;
1314 else
1315 add_pin_to_irq(irq, apic, pin);
1316
1317 if (!apic && !IO_APIC_IRQ(irq))
1318 continue;
1319
1320 if (IO_APIC_IRQ(irq)) {
1321 vector = assign_irq_vector(irq);
1322 entry.vector = vector;
1323 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1324
1325 if (!apic && (irq < 16))
1326 disable_8259A_irq(irq);
1327 }
1328 spin_lock_irqsave(&ioapic_lock, flags);
d15512f4 1329 __ioapic_write_entry(apic, pin, entry);
1da177e4
LT		 1330 spin_unlock_irqrestore(&ioapic_lock, flags);
1331 }
1332 }
1333
1334 if (!first_notcon)
1335 apic_printk(APIC_VERBOSE, " not connected.\n");
1336}
1337
1338/*
1339 * Set up the 8259A-master output pin:
1340 */
fcfd636a 1341static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1da177e4
LT		 1342{
1343 struct IO_APIC_route_entry entry;
1da177e4
LT		 1344
1345 memset(&entry,0,sizeof(entry));
1346
1347 disable_8259A_irq(0);
1348
1349 /* mask LVT0 */
1350 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1351
1352 /*
1353 * We use logical delivery to get the timer IRQ
1354 * to the first CPU.
1355 */
1356 entry.dest_mode = INT_DEST_MODE;
1357 entry.mask = 0; /* unmask IRQ now */
1358 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1359 entry.delivery_mode = INT_DELIVERY_MODE;
1360 entry.polarity = 0;
1361 entry.trigger = 0;
1362 entry.vector = vector;
1363
1364 /*
1365 * The timer IRQ doesn't have to know that behind the
1366 * scene we have a 8259A-master in AEOI mode ...
1367 */
f5b9ed7a
IM		 1368 irq_desc[0].chip = &ioapic_chip;
1369 set_irq_handler(0, handle_edge_irq);
1da177e4
LT		 1370
1371 /*
1372 * Add it to the IO-APIC irq-routing table:
1373 */
cf4c6a2f 1374 ioapic_write_entry(apic, pin, entry);
1da177e4
LT		 1375
1376 enable_8259A_irq(0);
1377}
1378
1da177e4
LT		 1379void __init print_IO_APIC(void)
1380{
1381 int apic, i;
1382 union IO_APIC_reg_00 reg_00;
1383 union IO_APIC_reg_01 reg_01;
1384 union IO_APIC_reg_02 reg_02;
1385 union IO_APIC_reg_03 reg_03;
1386 unsigned long flags;
1387
1388 if (apic_verbosity == APIC_QUIET)
1389 return;
1390
1391 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1392 for (i = 0; i < nr_ioapics; i++)
1393 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1394 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1395
1396 /*
1397 * We are a bit conservative about what we expect. We have to
1398 * know about every hardware change ASAP.
1399 */
1400 printk(KERN_INFO "testing the IO APIC.......................\n");
1401
1402 for (apic = 0; apic < nr_ioapics; apic++) {
1403
1404 spin_lock_irqsave(&ioapic_lock, flags);
1405 reg_00.raw = io_apic_read(apic, 0);
1406 reg_01.raw = io_apic_read(apic, 1);
1407 if (reg_01.bits.version >= 0x10)
1408 reg_02.raw = io_apic_read(apic, 2);
1409 if (reg_01.bits.version >= 0x20)
1410 reg_03.raw = io_apic_read(apic, 3);
1411 spin_unlock_irqrestore(&ioapic_lock, flags);
1412
1413 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1414 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1415 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1416 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1417 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1da177e4
LT		 1418
1419 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1420 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1da177e4
LT		 1421
1422 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1423 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1da177e4
LT		 1424
1425 /*
1426 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1427 * but the value of reg_02 is read as the previous read register
1428 * value, so ignore it if reg_02 == reg_01.
1429 */
1430 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1431 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1432 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1da177e4
LT		 1433 }
1434
1435 /*
1436 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1437 * or reg_03, but the value of reg_0[23] is read as the previous read
1438 * register value, so ignore it if reg_03 == reg_0[12].
1439 */
1440 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1441 reg_03.raw != reg_01.raw) {
1442 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1443 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1da177e4
LT		 1444 }
1445
1446 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1447
1448 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1449 " Stat Dest Deli Vect: \n");
1450
1451 for (i = 0; i <= reg_01.bits.entries; i++) {
1452 struct IO_APIC_route_entry entry;
1453
cf4c6a2f 1454 entry = ioapic_read_entry(apic, i);
1da177e4
LT		 1455
1456 printk(KERN_DEBUG " %02x %03X %02X ",
1457 i,
1458 entry.dest.logical.logical_dest,
1459 entry.dest.physical.physical_dest
1460 );
1461
1462 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1463 entry.mask,
1464 entry.trigger,
1465 entry.irr,
1466 entry.polarity,
1467 entry.delivery_status,
1468 entry.dest_mode,
1469 entry.delivery_mode,
1470 entry.vector
1471 );
1472 }
1473 }
1da177e4
LT		 1474 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1475 for (i = 0; i < NR_IRQS; i++) {
1476 struct irq_pin_list *entry = irq_2_pin + i;
1477 if (entry->pin < 0)
1478 continue;
ace80ab7 1479 printk(KERN_DEBUG "IRQ%d ", i);
1da177e4
LT		 1480 for (;;) {
1481 printk("-> %d:%d", entry->apic, entry->pin);
1482 if (!entry->next)
1483 break;
1484 entry = irq_2_pin + entry->next;
1485 }
1486 printk("\n");
1487 }
1488
1489 printk(KERN_INFO ".................................... done.\n");
1490
1491 return;
1492}
1493
1494#if 0
1495
1496static void print_APIC_bitfield (int base)
1497{
1498 unsigned int v;
1499 int i, j;
1500
1501 if (apic_verbosity == APIC_QUIET)
1502 return;
1503
1504 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1505 for (i = 0; i < 8; i++) {
1506 v = apic_read(base + i*0x10);
1507 for (j = 0; j < 32; j++) {
1508 if (v & (1<<j))
1509 printk("1");
1510 else
1511 printk("0");
1512 }
1513 printk("\n");
1514 }
1515}
1516
1517void /*__init*/ print_local_APIC(void * dummy)
1518{
1519 unsigned int v, ver, maxlvt;
1520
1521 if (apic_verbosity == APIC_QUIET)
1522 return;
1523
1524 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1525 smp_processor_id(), hard_smp_processor_id());
1526 v = apic_read(APIC_ID);
1527 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1528 v = apic_read(APIC_LVR);
1529 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1530 ver = GET_APIC_VERSION(v);
e05d723f 1531 maxlvt = lapic_get_maxlvt();
1da177e4
LT		 1532
1533 v = apic_read(APIC_TASKPRI);
1534 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1535
1536 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1537 v = apic_read(APIC_ARBPRI);
1538 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1539 v & APIC_ARBPRI_MASK);
1540 v = apic_read(APIC_PROCPRI);
1541 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1542 }
1543
1544 v = apic_read(APIC_EOI);
1545 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1546 v = apic_read(APIC_RRR);
1547 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1548 v = apic_read(APIC_LDR);
1549 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1550 v = apic_read(APIC_DFR);
1551 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1552 v = apic_read(APIC_SPIV);
1553 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1554
1555 printk(KERN_DEBUG "... APIC ISR field:\n");
1556 print_APIC_bitfield(APIC_ISR);
1557 printk(KERN_DEBUG "... APIC TMR field:\n");
1558 print_APIC_bitfield(APIC_TMR);
1559 printk(KERN_DEBUG "... APIC IRR field:\n");
1560 print_APIC_bitfield(APIC_IRR);
1561
1562 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1563 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1564 apic_write(APIC_ESR, 0);
1565 v = apic_read(APIC_ESR);
1566 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1567 }
1568
1569 v = apic_read(APIC_ICR);
1570 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1571 v = apic_read(APIC_ICR2);
1572 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1573
1574 v = apic_read(APIC_LVTT);
1575 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1576
1577 if (maxlvt > 3) { /* PC is LVT#4. */
1578 v = apic_read(APIC_LVTPC);
1579 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1580 }
1581 v = apic_read(APIC_LVT0);
1582 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1583 v = apic_read(APIC_LVT1);
1584 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1585
1586 if (maxlvt > 2) { /* ERR is LVT#3. */
1587 v = apic_read(APIC_LVTERR);
1588 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1589 }
1590
1591 v = apic_read(APIC_TMICT);
1592 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1593 v = apic_read(APIC_TMCCT);
1594 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1595 v = apic_read(APIC_TDCR);
1596 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1597 printk("\n");
1598}
1599
1600void print_all_local_APICs (void)
1601{
1602 on_each_cpu(print_local_APIC, NULL, 1, 1);
1603}
1604
1605void /*__init*/ print_PIC(void)
1606{
1da177e4
LT		 1607 unsigned int v;
1608 unsigned long flags;
1609
1610 if (apic_verbosity == APIC_QUIET)
1611 return;
1612
1613 printk(KERN_DEBUG "\nprinting PIC contents\n");
1614
1615 spin_lock_irqsave(&i8259A_lock, flags);
1616
1617 v = inb(0xa1) << 8 | inb(0x21);
1618 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1619
1620 v = inb(0xa0) << 8 | inb(0x20);
1621 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1622
1623 outb(0x0b,0xa0);
1624 outb(0x0b,0x20);
1625 v = inb(0xa0) << 8 | inb(0x20);
1626 outb(0x0a,0xa0);
1627 outb(0x0a,0x20);
1628
1629 spin_unlock_irqrestore(&i8259A_lock, flags);
1630
1631 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1632
1633 v = inb(0x4d1) << 8 | inb(0x4d0);
1634 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1635}
1636
1637#endif /* 0 */
1638
1639static void __init enable_IO_APIC(void)
1640{
1641 union IO_APIC_reg_01 reg_01;
fcfd636a
EB		 1642 int i8259_apic, i8259_pin;
1643 int i, apic;
1da177e4
LT		 1644 unsigned long flags;
1645
1646 for (i = 0; i < PIN_MAP_SIZE; i++) {
1647 irq_2_pin[i].pin = -1;
1648 irq_2_pin[i].next = 0;
1649 }
1650 if (!pirqs_enabled)
1651 for (i = 0; i < MAX_PIRQS; i++)
1652 pirq_entries[i] = -1;
1653
1654 /*
1655 * The number of IO-APIC IRQ registers (== #pins):
1656 */
fcfd636a 1657 for (apic = 0; apic < nr_ioapics; apic++) {
1da177e4 1658 spin_lock_irqsave(&ioapic_lock, flags);
fcfd636a 1659 reg_01.raw = io_apic_read(apic, 1);
1da177e4 1660 spin_unlock_irqrestore(&ioapic_lock, flags);
fcfd636a
EB		 1661 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1662 }
1663 for(apic = 0; apic < nr_ioapics; apic++) {
1664 int pin;
1665 /* See if any of the pins is in ExtINT mode */
1008fddc 1666 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
fcfd636a 1667 struct IO_APIC_route_entry entry;
cf4c6a2f 1668 entry = ioapic_read_entry(apic, pin);
fcfd636a
EB		 1669
1670
1671 /* If the interrupt line is enabled and in ExtInt mode
1672 * I have found the pin where the i8259 is connected.
1673 */
1674 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1675 ioapic_i8259.apic = apic;
1676 ioapic_i8259.pin = pin;
1677 goto found_i8259;
1678 }
1679 }
1680 }
1681 found_i8259:
1682 /* Look to see what if the MP table has reported the ExtINT */
1683 /* If we could not find the appropriate pin by looking at the ioapic
1684 * the i8259 probably is not connected the ioapic but give the
1685 * mptable a chance anyway.
1686 */
1687 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1688 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1689 /* Trust the MP table if nothing is setup in the hardware */
1690 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1691 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1692 ioapic_i8259.pin = i8259_pin;
1693 ioapic_i8259.apic = i8259_apic;
1694 }
1695 /* Complain if the MP table and the hardware disagree */
1696 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1697 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1698 {
1699 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1da177e4
LT		 1700 }
1701
1702 /*
1703 * Do not trust the IO-APIC being empty at bootup
1704 */
1705 clear_IO_APIC();
1706}
1707
1708/*
1709 * Not an __init, needed by the reboot code
1710 */
1711void disable_IO_APIC(void)
1712{
1713 /*
1714 * Clear the IO-APIC before rebooting:
1715 */
1716 clear_IO_APIC();
1717
650927ef 1718 /*
0b968d23 1719 * If the i8259 is routed through an IOAPIC
650927ef 1720 * Put that IOAPIC in virtual wire mode
0b968d23 1721 * so legacy interrupts can be delivered.
650927ef 1722 */
fcfd636a 1723 if (ioapic_i8259.pin != -1) {
650927ef 1724 struct IO_APIC_route_entry entry;
650927ef
EB		 1725
1726 memset(&entry, 0, sizeof(entry));
1727 entry.mask = 0; /* Enabled */
1728 entry.trigger = 0; /* Edge */
1729 entry.irr = 0;
1730 entry.polarity = 0; /* High */
1731 entry.delivery_status = 0;
1732 entry.dest_mode = 0; /* Physical */
fcfd636a 1733 entry.delivery_mode = dest_ExtINT; /* ExtInt */
650927ef 1734 entry.vector = 0;
76865c3f
VG		 1735 entry.dest.physical.physical_dest =
1736 GET_APIC_ID(apic_read(APIC_ID));
650927ef
EB		 1737
1738 /*
1739 * Add it to the IO-APIC irq-routing table:
1740 */
cf4c6a2f 1741 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
650927ef 1742 }
fcfd636a 1743 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1da177e4
LT		 1744}
1745
1746/*
1747 * function to set the IO-APIC physical IDs based on the
1748 * values stored in the MPC table.
1749 *
1750 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1751 */
1752
1753#ifndef CONFIG_X86_NUMAQ
1754static void __init setup_ioapic_ids_from_mpc(void)
1755{
1756 union IO_APIC_reg_00 reg_00;
1757 physid_mask_t phys_id_present_map;
1758 int apic;
1759 int i;
1760 unsigned char old_id;
1761 unsigned long flags;
1762
ca05fea6
NP		 1763 /*
1764 * Don't check I/O APIC IDs for xAPIC systems. They have
1765 * no meaning without the serial APIC bus.
1766 */
7c5c1e42
SL		 1767 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1768 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
ca05fea6 1769 return;
1da177e4
LT		 1770 /*
1771 * This is broken; anything with a real cpu count has to
1772 * circumvent this idiocy regardless.
1773 */
1774 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1775
1776 /*
1777 * Set the IOAPIC ID to the value stored in the MPC table.
1778 */
1779 for (apic = 0; apic < nr_ioapics; apic++) {
1780
1781 /* Read the register 0 value */
1782 spin_lock_irqsave(&ioapic_lock, flags);
1783 reg_00.raw = io_apic_read(apic, 0);
1784 spin_unlock_irqrestore(&ioapic_lock, flags);
1785
1786 old_id = mp_ioapics[apic].mpc_apicid;
1787
1788 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1789 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1790 apic, mp_ioapics[apic].mpc_apicid);
1791 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1792 reg_00.bits.ID);
1793 mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1794 }
1795
1da177e4
LT		 1796 /*
1797 * Sanity check, is the ID really free? Every APIC in a
1798 * system must have a unique ID or we get lots of nice
1799 * 'stuck on smp_invalidate_needed IPI wait' messages.
1800 */
1801 if (check_apicid_used(phys_id_present_map,
1802 mp_ioapics[apic].mpc_apicid)) {
1803 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1804 apic, mp_ioapics[apic].mpc_apicid);
1805 for (i = 0; i < get_physical_broadcast(); i++)
1806 if (!physid_isset(i, phys_id_present_map))
1807 break;
1808 if (i >= get_physical_broadcast())
1809 panic("Max APIC ID exceeded!\n");
1810 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1811 i);
1812 physid_set(i, phys_id_present_map);
1813 mp_ioapics[apic].mpc_apicid = i;
1814 } else {
1815 physid_mask_t tmp;
1816 tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1817 apic_printk(APIC_VERBOSE, "Setting %d in the "
1818 "phys_id_present_map\n",
1819 mp_ioapics[apic].mpc_apicid);
1820 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1821 }
1822
1823
1824 /*
1825 * We need to adjust the IRQ routing table
1826 * if the ID changed.
1827 */
1828 if (old_id != mp_ioapics[apic].mpc_apicid)
1829 for (i = 0; i < mp_irq_entries; i++)
1830 if (mp_irqs[i].mpc_dstapic == old_id)
1831 mp_irqs[i].mpc_dstapic
1832 = mp_ioapics[apic].mpc_apicid;
1833
1834 /*
1835 * Read the right value from the MPC table and
1836 * write it into the ID register.
1837 */
1838 apic_printk(APIC_VERBOSE, KERN_INFO
1839 "...changing IO-APIC physical APIC ID to %d ...",
1840 mp_ioapics[apic].mpc_apicid);
1841
1842 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1843 spin_lock_irqsave(&ioapic_lock, flags);
1844 io_apic_write(apic, 0, reg_00.raw);
1845 spin_unlock_irqrestore(&ioapic_lock, flags);
1846
1847 /*
1848 * Sanity check
1849 */
1850 spin_lock_irqsave(&ioapic_lock, flags);
1851 reg_00.raw = io_apic_read(apic, 0);
1852 spin_unlock_irqrestore(&ioapic_lock, flags);
1853 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1854 printk("could not set ID!\n");
1855 else
1856 apic_printk(APIC_VERBOSE, " ok.\n");
1857 }
1858}
1859#else
1860static void __init setup_ioapic_ids_from_mpc(void) { }
1861#endif
1862
7ce0bcfd 1863int no_timer_check __initdata;
8542b200
ZA		 1864
1865static int __init notimercheck(char *s)
1866{
1867 no_timer_check = 1;
1868 return 1;
1869}
1870__setup("no_timer_check", notimercheck);
1871
1da177e4
LT		 1872/*
1873 * There is a nasty bug in some older SMP boards, their mptable lies
1874 * about the timer IRQ. We do the following to work around the situation:
1875 *
1876 * - timer IRQ defaults to IO-APIC IRQ
1877 * - if this function detects that timer IRQs are defunct, then we fall
1878 * back to ISA timer IRQs
1879 */
f0a7a5c9 1880static int __init timer_irq_works(void)
1da177e4
LT		 1881{
1882 unsigned long t1 = jiffies;
4aae0702 1883 unsigned long flags;
1da177e4 1884
8542b200
ZA		 1885 if (no_timer_check)
1886 return 1;
1887
4aae0702 1888 local_save_flags(flags);
1da177e4
LT		 1889 local_irq_enable();
1890 /* Let ten ticks pass... */
1891 mdelay((10 * 1000) / HZ);
4aae0702 1892 local_irq_restore(flags);
1da177e4
LT		 1893
1894 /*
1895 * Expect a few ticks at least, to be sure some possible
1896 * glue logic does not lock up after one or two first
1897 * ticks in a non-ExtINT mode. Also the local APIC
1898 * might have cached one ExtINT interrupt. Finally, at
1899 * least one tick may be lost due to delays.
1900 */
1901 if (jiffies - t1 > 4)
1902 return 1;
1903
1904 return 0;
1905}
1906
1907/*
1908 * In the SMP+IOAPIC case it might happen that there are an unspecified
1909 * number of pending IRQ events unhandled. These cases are very rare,
1910 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1911 * better to do it this way as thus we do not have to be aware of
1912 * 'pending' interrupts in the IRQ path, except at this point.
1913 */
1914/*
1915 * Edge triggered needs to resend any interrupt
1916 * that was delayed but this is now handled in the device
1917 * independent code.
1918 */
1919
1920/*
f5b9ed7a
IM		 1921 * Startup quirk:
1922 *
1da177e4
LT		 1923 * Starting up a edge-triggered IO-APIC interrupt is
1924 * nasty - we need to make sure that we get the edge.
1925 * If it is already asserted for some reason, we need
1926 * return 1 to indicate that is was pending.
1927 *
1928 * This is not complete - we should be able to fake
1929 * an edge even if it isn't on the 8259A...
f5b9ed7a
IM		 1930 *
1931 * (We do this for level-triggered IRQs too - it cannot hurt.)
1da177e4 1932 */
f5b9ed7a 1933static unsigned int startup_ioapic_irq(unsigned int irq)
1da177e4
LT		 1934{
1935 int was_pending = 0;
1936 unsigned long flags;
1937
1938 spin_lock_irqsave(&ioapic_lock, flags);
1939 if (irq < 16) {
1940 disable_8259A_irq(irq);
1941 if (i8259A_irq_pending(irq))
1942 was_pending = 1;
1943 }
1944 __unmask_IO_APIC_irq(irq);
1945 spin_unlock_irqrestore(&ioapic_lock, flags);
1946
1947 return was_pending;
1948}
1949
f5b9ed7a 1950static void ack_ioapic_irq(unsigned int irq)
1da177e4 1951{
ace80ab7 1952 move_native_irq(irq);
1da177e4
LT		 1953 ack_APIC_irq();
1954}
1955
f5b9ed7a 1956static void ack_ioapic_quirk_irq(unsigned int irq)
1da177e4
LT		 1957{
1958 unsigned long v;
1959 int i;
1960
ace80ab7 1961 move_native_irq(irq);
1da177e4
LT		 1962/*
1963 * It appears there is an erratum which affects at least version 0x11
1964 * of I/O APIC (that's the 82093AA and cores integrated into various
1965 * chipsets). Under certain conditions a level-triggered interrupt is
1966 * erroneously delivered as edge-triggered one but the respective IRR
1967 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1968 * message but it will never arrive and further interrupts are blocked
1969 * from the source. The exact reason is so far unknown, but the
1970 * phenomenon was observed when two consecutive interrupt requests
1971 * from a given source get delivered to the same CPU and the source is
1972 * temporarily disabled in between.
1973 *
1974 * A workaround is to simulate an EOI message manually. We achieve it
1975 * by setting the trigger mode to edge and then to level when the edge
1976 * trigger mode gets detected in the TMR of a local APIC for a
1977 * level-triggered interrupt. We mask the source for the time of the
1978 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1979 * The idea is from Manfred Spraul. --macro
1980 */
b940d22d 1981 i = irq_vector[irq];
1da177e4
LT		 1982
1983 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1984
1985 ack_APIC_irq();
1986
1987 if (!(v & (1 << (i & 0x1f)))) {
1988 atomic_inc(&irq_mis_count);
1989 spin_lock(&ioapic_lock);
1990 __mask_and_edge_IO_APIC_irq(irq);
1991 __unmask_and_level_IO_APIC_irq(irq);
1992 spin_unlock(&ioapic_lock);
1993 }
1994}
1995
ace80ab7 1996static int ioapic_retrigger_irq(unsigned int irq)
1da177e4 1997{
b940d22d 1998 send_IPI_self(irq_vector[irq]);
c0ad90a3
IM		 1999
2000 return 1;
2001}
2002
f5b9ed7a
IM		 2003static struct irq_chip ioapic_chip __read_mostly = {
2004 .name = "IO-APIC",
ace80ab7
EB		 2005 .startup = startup_ioapic_irq,
2006 .mask = mask_IO_APIC_irq,
2007 .unmask = unmask_IO_APIC_irq,
2008 .ack = ack_ioapic_irq,
2009 .eoi = ack_ioapic_quirk_irq,
54d5d424 2010#ifdef CONFIG_SMP
ace80ab7 2011 .set_affinity = set_ioapic_affinity_irq,
54d5d424 2012#endif
ace80ab7 2013 .retrigger = ioapic_retrigger_irq,
1da177e4
LT		 2014};
2015
1da177e4
LT		 2016
2017static inline void init_IO_APIC_traps(void)
2018{
2019 int irq;
2020
2021 /*
2022 * NOTE! The local APIC isn't very good at handling
2023 * multiple interrupts at the same interrupt level.
2024 * As the interrupt level is determined by taking the
2025 * vector number and shifting that right by 4, we
2026 * want to spread these out a bit so that they don't
2027 * all fall in the same interrupt level.
2028 *
2029 * Also, we've got to be careful not to trash gate
2030 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2031 */
2032 for (irq = 0; irq < NR_IRQS ; irq++) {
2033 int tmp = irq;
b940d22d 2034 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
1da177e4
LT		 2035 /*
2036 * Hmm.. We don't have an entry for this,
2037 * so default to an old-fashioned 8259
2038 * interrupt if we can..
2039 */
2040 if (irq < 16)
2041 make_8259A_irq(irq);
2042 else
2043 /* Strange. Oh, well.. */
f5b9ed7a 2044 irq_desc[irq].chip = &no_irq_chip;
1da177e4
LT		 2045 }
2046 }
2047}
2048
f5b9ed7a
IM		 2049/*
2050 * The local APIC irq-chip implementation:
2051 */
1da177e4 2052
f5b9ed7a
IM		 2053static void ack_apic(unsigned int irq)
2054{
2055 ack_APIC_irq();
1da177e4
LT		 2056}
2057
f5b9ed7a 2058static void mask_lapic_irq (unsigned int irq)
1da177e4
LT		 2059{
2060 unsigned long v;
2061
2062 v = apic_read(APIC_LVT0);
2063 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2064}
2065
f5b9ed7a 2066static void unmask_lapic_irq (unsigned int irq)
1da177e4 2067{
f5b9ed7a 2068 unsigned long v;
1da177e4 2069
f5b9ed7a
IM		 2070 v = apic_read(APIC_LVT0);
2071 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2072}
1da177e4 2073
f5b9ed7a
IM		 2074static struct irq_chip lapic_chip __read_mostly = {
2075 .name = "local-APIC-edge",
2076 .mask = mask_lapic_irq,
2077 .unmask = unmask_lapic_irq,
2078 .eoi = ack_apic,
1da177e4
LT		 2079};
2080
e9427101 2081static void __init setup_nmi(void)
1da177e4
LT		 2082{
2083 /*
2084 * Dirty trick to enable the NMI watchdog ...
2085 * We put the 8259A master into AEOI mode and
2086 * unmask on all local APICs LVT0 as NMI.
2087 *
2088 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2089 * is from Maciej W. Rozycki - so we do not have to EOI from
2090 * the NMI handler or the timer interrupt.
2091 */
2092 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2093
e9427101 2094 enable_NMI_through_LVT0();
1da177e4
LT		 2095
2096 apic_printk(APIC_VERBOSE, " done.\n");
2097}
2098
2099/*
2100 * This looks a bit hackish but it's about the only one way of sending
2101 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2102 * not support the ExtINT mode, unfortunately. We need to send these
2103 * cycles as some i82489DX-based boards have glue logic that keeps the
2104 * 8259A interrupt line asserted until INTA. --macro
2105 */
2106static inline void unlock_ExtINT_logic(void)
2107{
fcfd636a 2108 int apic, pin, i;
1da177e4
LT		 2109 struct IO_APIC_route_entry entry0, entry1;
2110 unsigned char save_control, save_freq_select;
1da177e4 2111
fcfd636a 2112 pin = find_isa_irq_pin(8, mp_INT);
956fb531
AB		 2113 if (pin == -1) {
2114 WARN_ON_ONCE(1);
2115 return;
2116 }
fcfd636a 2117 apic = find_isa_irq_apic(8, mp_INT);
956fb531
AB		 2118 if (apic == -1) {
2119 WARN_ON_ONCE(1);
1da177e4 2120 return;
956fb531 2121 }
1da177e4 2122
cf4c6a2f 2123 entry0 = ioapic_read_entry(apic, pin);
fcfd636a 2124 clear_IO_APIC_pin(apic, pin);
1da177e4
LT		 2125
2126 memset(&entry1, 0, sizeof(entry1));
2127
2128 entry1.dest_mode = 0; /* physical delivery */
2129 entry1.mask = 0; /* unmask IRQ now */
2130 entry1.dest.physical.physical_dest = hard_smp_processor_id();
2131 entry1.delivery_mode = dest_ExtINT;
2132 entry1.polarity = entry0.polarity;
2133 entry1.trigger = 0;
2134 entry1.vector = 0;
2135
cf4c6a2f 2136 ioapic_write_entry(apic, pin, entry1);
1da177e4
LT		 2137
2138 save_control = CMOS_READ(RTC_CONTROL);
2139 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2140 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2141 RTC_FREQ_SELECT);
2142 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2143
2144 i = 100;
2145 while (i-- > 0) {
2146 mdelay(10);
2147 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2148 i -= 10;
2149 }
2150
2151 CMOS_WRITE(save_control, RTC_CONTROL);
2152 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
fcfd636a 2153 clear_IO_APIC_pin(apic, pin);
1da177e4 2154
cf4c6a2f 2155 ioapic_write_entry(apic, pin, entry0);
1da177e4
LT		 2156}
2157
e0c1e9bf
KM		 2158int timer_uses_ioapic_pin_0;
2159
1da177e4
LT		 2160/*
2161 * This code may look a bit paranoid, but it's supposed to cooperate with
2162 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2163 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2164 * fanatically on his truly buggy board.
2165 */
8542b200 2166static inline void __init check_timer(void)
1da177e4 2167{
fcfd636a 2168 int apic1, pin1, apic2, pin2;
1da177e4 2169 int vector;
4aae0702
IM		 2170 unsigned long flags;
2171
2172 local_irq_save(flags);
d4d25dec 2173
1da177e4
LT		 2174 /*
2175 * get/set the timer IRQ vector:
2176 */
2177 disable_8259A_irq(0);
2178 vector = assign_irq_vector(0);
2179 set_intr_gate(vector, interrupt[0]);
2180
2181 /*
2182 * Subtle, code in do_timer_interrupt() expects an AEOI
2183 * mode for the 8259A whenever interrupts are routed
2184 * through I/O APICs. Also IRQ0 has to be enabled in
2185 * the 8259A which implies the virtual wire has to be
4960c9df 2186 * disabled in the local APIC.
1da177e4
LT		 2187 */
2188 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2189 init_8259A(1);
4960c9df 2190 timer_ack = 1;
f9262c12
AK		 2191 if (timer_over_8254 > 0)
2192 enable_8259A_irq(0);
1da177e4 2193
fcfd636a
EB		 2194 pin1 = find_isa_irq_pin(0, mp_INT);
2195 apic1 = find_isa_irq_apic(0, mp_INT);
2196 pin2 = ioapic_i8259.pin;
2197 apic2 = ioapic_i8259.apic;
1da177e4 2198
e0c1e9bf
KM		 2199 if (pin1 == 0)
2200 timer_uses_ioapic_pin_0 = 1;
2201
fcfd636a
EB		 2202 printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2203 vector, apic1, pin1, apic2, pin2);
1da177e4
LT		 2204
2205 if (pin1 != -1) {
2206 /*
2207 * Ok, does IRQ0 through the IOAPIC work?
2208 */
2209 unmask_IO_APIC_irq(0);
2210 if (timer_irq_works()) {
2211 if (nmi_watchdog == NMI_IO_APIC) {
2212 disable_8259A_irq(0);
2213 setup_nmi();
2214 enable_8259A_irq(0);
1da177e4 2215 }
66759a01
CE		 2216 if (disable_timer_pin_1 > 0)
2217 clear_IO_APIC_pin(0, pin1);
4aae0702 2218 goto out;
1da177e4 2219 }
fcfd636a
EB		 2220 clear_IO_APIC_pin(apic1, pin1);
2221 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2222 "IO-APIC\n");
1da177e4
LT		 2223 }
2224
2225 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2226 if (pin2 != -1) {
2227 printk("\n..... (found pin %d) ...", pin2);
2228 /*
2229 * legacy devices should be connected to IO APIC #0
2230 */
fcfd636a 2231 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1da177e4
LT		 2232 if (timer_irq_works()) {
2233 printk("works.\n");
2234 if (pin1 != -1)
fcfd636a 2235 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
1da177e4 2236 else
fcfd636a 2237 add_pin_to_irq(0, apic2, pin2);
1da177e4
LT		 2238 if (nmi_watchdog == NMI_IO_APIC) {
2239 setup_nmi();
1da177e4 2240 }
4aae0702 2241 goto out;
1da177e4
LT		 2242 }
2243 /*
2244 * Cleanup, just in case ...
2245 */
fcfd636a 2246 clear_IO_APIC_pin(apic2, pin2);
1da177e4
LT		 2247 }
2248 printk(" failed.\n");
2249
2250 if (nmi_watchdog == NMI_IO_APIC) {
2251 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2252 nmi_watchdog = 0;
2253 }
2254
2255 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2256
2257 disable_8259A_irq(0);
a460e745 2258 set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq,
2e188938 2259 "fasteoi");
1da177e4
LT		 2260 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
2261 enable_8259A_irq(0);
2262
2263 if (timer_irq_works()) {
2264 printk(" works.\n");
4aae0702 2265 goto out;
1da177e4
LT		 2266 }
2267 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2268 printk(" failed.\n");
2269
2270 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2271
2272 timer_ack = 0;
2273 init_8259A(0);
2274 make_8259A_irq(0);
2275 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2276
2277 unlock_ExtINT_logic();
2278
2279 if (timer_irq_works()) {
2280 printk(" works.\n");
4aae0702 2281 goto out;
1da177e4
LT		 2282 }
2283 printk(" failed :(.\n");
2284 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2285 "report. Then try booting with the 'noapic' option");
4aae0702
IM		 2286out:
2287 local_irq_restore(flags);
1da177e4
LT		 2288}
2289
2290/*
2291 *
2292 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2293 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2294 * Linux doesn't really care, as it's not actually used
2295 * for any interrupt handling anyway.
2296 */
2297#define PIC_IRQS (1 << PIC_CASCADE_IR)
2298
2299void __init setup_IO_APIC(void)
2300{
dbeb2be2
RR		 2301 int i;
2302
2303 /* Reserve all the system vectors. */
2304 for (i = FIRST_SYSTEM_VECTOR; i < NR_VECTORS; i++)
2305 set_bit(i, used_vectors);
2306
1da177e4
LT		 2307 enable_IO_APIC();
2308
2309 if (acpi_ioapic)
2310 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
2311 else
2312 io_apic_irqs = ~PIC_IRQS;
2313
2314 printk("ENABLING IO-APIC IRQs\n");
2315
2316 /*
2317 * Set up IO-APIC IRQ routing.
2318 */
2319 if (!acpi_ioapic)
2320 setup_ioapic_ids_from_mpc();
2321 sync_Arb_IDs();
2322 setup_IO_APIC_irqs();
2323 init_IO_APIC_traps();
1e4c85f9 2324 check_timer();
1da177e4
LT		 2325 if (!acpi_ioapic)
2326 print_IO_APIC();
2327}
2328
f9262c12
AK		 2329static int __init setup_disable_8254_timer(char *s)
2330{
2331 timer_over_8254 = -1;
2332 return 1;
2333}
2334static int __init setup_enable_8254_timer(char *s)
2335{
2336 timer_over_8254 = 2;
2337 return 1;
2338}
2339
2340__setup("disable_8254_timer", setup_disable_8254_timer);
2341__setup("enable_8254_timer", setup_enable_8254_timer);
2342
1da177e4
LT		 2343/*
2344 * Called after all the initialization is done. If we didnt find any
2345 * APIC bugs then we can allow the modify fast path
2346 */
2347
2348static int __init io_apic_bug_finalize(void)
2349{
2350 if(sis_apic_bug == -1)
2351 sis_apic_bug = 0;
2352 return 0;
2353}
2354
2355late_initcall(io_apic_bug_finalize);
2356
2357struct sysfs_ioapic_data {
2358 struct sys_device dev;
2359 struct IO_APIC_route_entry entry[0];
2360};
2361static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2362
438510f6 2363static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1da177e4
LT		 2364{
2365 struct IO_APIC_route_entry *entry;
2366 struct sysfs_ioapic_data *data;
1da177e4
LT		 2367 int i;
2368
2369 data = container_of(dev, struct sysfs_ioapic_data, dev);
2370 entry = data->entry;
cf4c6a2f
AK		 2371 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2372 entry[i] = ioapic_read_entry(dev->id, i);
1da177e4
LT		 2373
2374 return 0;
2375}
2376
2377static int ioapic_resume(struct sys_device *dev)
2378{
2379 struct IO_APIC_route_entry *entry;
2380 struct sysfs_ioapic_data *data;
2381 unsigned long flags;
2382 union IO_APIC_reg_00 reg_00;
2383 int i;
2384
2385 data = container_of(dev, struct sysfs_ioapic_data, dev);
2386 entry = data->entry;
2387
2388 spin_lock_irqsave(&ioapic_lock, flags);
2389 reg_00.raw = io_apic_read(dev->id, 0);
2390 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2391 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2392 io_apic_write(dev->id, 0, reg_00.raw);
2393 }
1da177e4 2394 spin_unlock_irqrestore(&ioapic_lock, flags);
cf4c6a2f
AK		 2395 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2396 ioapic_write_entry(dev->id, i, entry[i]);
1da177e4
LT		 2397
2398 return 0;
2399}
2400
2401static struct sysdev_class ioapic_sysdev_class = {
af5ca3f4 2402 .name = "ioapic",
1da177e4
LT		 2403 .suspend = ioapic_suspend,
2404 .resume = ioapic_resume,
2405};
2406
2407static int __init ioapic_init_sysfs(void)
2408{
2409 struct sys_device * dev;
2410 int i, size, error = 0;
2411
2412 error = sysdev_class_register(&ioapic_sysdev_class);
2413 if (error)
2414 return error;
2415
2416 for (i = 0; i < nr_ioapics; i++ ) {
2417 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2418 * sizeof(struct IO_APIC_route_entry);
2419 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2420 if (!mp_ioapic_data[i]) {
2421 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2422 continue;
2423 }
2424 memset(mp_ioapic_data[i], 0, size);
2425 dev = &mp_ioapic_data[i]->dev;
2426 dev->id = i;
2427 dev->cls = &ioapic_sysdev_class;
2428 error = sysdev_register(dev);
2429 if (error) {
2430 kfree(mp_ioapic_data[i]);
2431 mp_ioapic_data[i] = NULL;
2432 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2433 continue;
2434 }
2435 }
2436
2437 return 0;
2438}
2439
2440device_initcall(ioapic_init_sysfs);
2441
3fc471ed 2442/*
95d77884 2443 * Dynamic irq allocate and deallocation
3fc471ed
EB		 2444 */
2445int create_irq(void)
2446{
ace80ab7 2447 /* Allocate an unused irq */
306a22c2 2448 int irq, new, vector = 0;
3fc471ed 2449 unsigned long flags;
3fc471ed 2450
ace80ab7
EB		 2451 irq = -ENOSPC;
2452 spin_lock_irqsave(&vector_lock, flags);
2453 for (new = (NR_IRQS - 1); new >= 0; new--) {
2454 if (platform_legacy_irq(new))
2455 continue;
2456 if (irq_vector[new] != 0)
2457 continue;
2458 vector = __assign_irq_vector(new);
2459 if (likely(vector > 0))
2460 irq = new;
2461 break;
2462 }
2463 spin_unlock_irqrestore(&vector_lock, flags);
3fc471ed 2464
ace80ab7 2465 if (irq >= 0) {
3fc471ed 2466 set_intr_gate(vector, interrupt[irq]);
3fc471ed
EB		 2467 dynamic_irq_init(irq);
2468 }
2469 return irq;
2470}
2471
2472void destroy_irq(unsigned int irq)
2473{
2474 unsigned long flags;
3fc471ed
EB		 2475
2476 dynamic_irq_cleanup(irq);
2477
2478 spin_lock_irqsave(&vector_lock, flags);
3fc471ed
EB		 2479 irq_vector[irq] = 0;
2480 spin_unlock_irqrestore(&vector_lock, flags);
2481}
3fc471ed 2482
2d3fcc1c 2483/*
27b46d76 2484 * MSI message composition
2d3fcc1c
EB		 2485 */
2486#ifdef CONFIG_PCI_MSI
3b7d1921 2487static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2d3fcc1c 2488{
2d3fcc1c
EB		 2489 int vector;
2490 unsigned dest;
2491
2492 vector = assign_irq_vector(irq);
2493 if (vector >= 0) {
2494 dest = cpu_mask_to_apicid(TARGET_CPUS);
2495
2496 msg->address_hi = MSI_ADDR_BASE_HI;
2497 msg->address_lo =
2498 MSI_ADDR_BASE_LO |
2499 ((INT_DEST_MODE == 0) ?
2500 MSI_ADDR_DEST_MODE_PHYSICAL:
2501 MSI_ADDR_DEST_MODE_LOGICAL) |
2502 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2503 MSI_ADDR_REDIRECTION_CPU:
2504 MSI_ADDR_REDIRECTION_LOWPRI) |
2505 MSI_ADDR_DEST_ID(dest);
2506
2507 msg->data =
2508 MSI_DATA_TRIGGER_EDGE |
2509 MSI_DATA_LEVEL_ASSERT |
2510 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2511 MSI_DATA_DELIVERY_FIXED:
2512 MSI_DATA_DELIVERY_LOWPRI) |
2513 MSI_DATA_VECTOR(vector);
2514 }
2515 return vector;
2516}
2517
3b7d1921
EB		 2518#ifdef CONFIG_SMP
2519static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2d3fcc1c 2520{
3b7d1921
EB		 2521 struct msi_msg msg;
2522 unsigned int dest;
2523 cpumask_t tmp;
2d3fcc1c 2524 int vector;
3b7d1921
EB		 2525
2526 cpus_and(tmp, mask, cpu_online_map);
2527 if (cpus_empty(tmp))
2528 tmp = TARGET_CPUS;
2d3fcc1c
EB		 2529
2530 vector = assign_irq_vector(irq);
3b7d1921
EB		 2531 if (vector < 0)
2532 return;
2d3fcc1c 2533
3b7d1921
EB		 2534 dest = cpu_mask_to_apicid(mask);
2535
2536 read_msi_msg(irq, &msg);
2537
2538 msg.data &= ~MSI_DATA_VECTOR_MASK;
2539 msg.data |= MSI_DATA_VECTOR(vector);
2540 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2541 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2542
2543 write_msi_msg(irq, &msg);
9f0a5ba5 2544 irq_desc[irq].affinity = mask;
2d3fcc1c 2545}
3b7d1921 2546#endif /* CONFIG_SMP */
2d3fcc1c 2547
3b7d1921
EB		 2548/*
2549 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2550 * which implement the MSI or MSI-X Capability Structure.
2551 */
2552static struct irq_chip msi_chip = {
2553 .name = "PCI-MSI",
2554 .unmask = unmask_msi_irq,
2555 .mask = mask_msi_irq,
2556 .ack = ack_ioapic_irq,
2557#ifdef CONFIG_SMP
2558 .set_affinity = set_msi_irq_affinity,
2559#endif
2560 .retrigger = ioapic_retrigger_irq,
2d3fcc1c
EB		 2561};
2562
f7feaca7 2563int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
3b7d1921
EB		 2564{
2565 struct msi_msg msg;
f7feaca7
EB		 2566 int irq, ret;
2567 irq = create_irq();
2568 if (irq < 0)
2569 return irq;
2570
3b7d1921 2571 ret = msi_compose_msg(dev, irq, &msg);
f7feaca7
EB		 2572 if (ret < 0) {
2573 destroy_irq(irq);
3b7d1921 2574 return ret;
f7feaca7 2575 }
3b7d1921 2576
7fe3730d 2577 set_irq_msi(irq, desc);
3b7d1921
EB		 2578 write_msi_msg(irq, &msg);
2579
a460e745
IM		 2580 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq,
2581 "edge");
3b7d1921 2582
7fe3730d 2583 return 0;
3b7d1921
EB		 2584}
2585
2586void arch_teardown_msi_irq(unsigned int irq)
2587{
f7feaca7 2588 destroy_irq(irq);
3b7d1921
EB		 2589}
2590
2d3fcc1c
EB		 2591#endif /* CONFIG_PCI_MSI */
2592
8b955b0d
EB		 2593/*
2594 * Hypertransport interrupt support
2595 */
2596#ifdef CONFIG_HT_IRQ
2597
2598#ifdef CONFIG_SMP
2599
2600static void target_ht_irq(unsigned int irq, unsigned int dest)
2601{
ec68307c
EB		 2602 struct ht_irq_msg msg;
2603 fetch_ht_irq_msg(irq, &msg);
8b955b0d 2604
ec68307c
EB		 2605 msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK);
2606 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
8b955b0d 2607
ec68307c
EB		 2608 msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest);
2609 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
8b955b0d 2610
ec68307c 2611 write_ht_irq_msg(irq, &msg);
8b955b0d
EB		 2612}
2613
2614static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2615{
2616 unsigned int dest;
2617 cpumask_t tmp;
2618
2619 cpus_and(tmp, mask, cpu_online_map);
2620 if (cpus_empty(tmp))
2621 tmp = TARGET_CPUS;
2622
2623 cpus_and(mask, tmp, CPU_MASK_ALL);
2624
2625 dest = cpu_mask_to_apicid(mask);
2626
2627 target_ht_irq(irq, dest);
9f0a5ba5 2628 irq_desc[irq].affinity = mask;
8b955b0d
EB		 2629}
2630#endif
2631
c37e108d 2632static struct irq_chip ht_irq_chip = {
8b955b0d
EB		 2633 .name = "PCI-HT",
2634 .mask = mask_ht_irq,
2635 .unmask = unmask_ht_irq,
2636 .ack = ack_ioapic_irq,
2637#ifdef CONFIG_SMP
2638 .set_affinity = set_ht_irq_affinity,
2639#endif
2640 .retrigger = ioapic_retrigger_irq,
2641};
2642
2643int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2644{
2645 int vector;
2646
2647 vector = assign_irq_vector(irq);
2648 if (vector >= 0) {
ec68307c 2649 struct ht_irq_msg msg;
8b955b0d
EB		 2650 unsigned dest;
2651 cpumask_t tmp;
2652
2653 cpus_clear(tmp);
2654 cpu_set(vector >> 8, tmp);
2655 dest = cpu_mask_to_apicid(tmp);
2656
ec68307c 2657 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
8b955b0d 2658
ec68307c
EB		 2659 msg.address_lo =
2660 HT_IRQ_LOW_BASE |
8b955b0d
EB		 2661 HT_IRQ_LOW_DEST_ID(dest) |
2662 HT_IRQ_LOW_VECTOR(vector) |
2663 ((INT_DEST_MODE == 0) ?
2664 HT_IRQ_LOW_DM_PHYSICAL :
2665 HT_IRQ_LOW_DM_LOGICAL) |
2666 HT_IRQ_LOW_RQEOI_EDGE |
2667 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2668 HT_IRQ_LOW_MT_FIXED :
2669 HT_IRQ_LOW_MT_ARBITRATED) |
2670 HT_IRQ_LOW_IRQ_MASKED;
2671
ec68307c 2672 write_ht_irq_msg(irq, &msg);
8b955b0d 2673
a460e745
IM		 2674 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2675 handle_edge_irq, "edge");
8b955b0d
EB		 2676 }
2677 return vector;
2678}
2679#endif /* CONFIG_HT_IRQ */
2680
1da177e4
LT		 2681/* --------------------------------------------------------------------------
2682 ACPI-based IOAPIC Configuration
2683 -------------------------------------------------------------------------- */
2684
888ba6c6 2685#ifdef CONFIG_ACPI
1da177e4
LT		 2686
2687int __init io_apic_get_unique_id (int ioapic, int apic_id)
2688{
2689 union IO_APIC_reg_00 reg_00;
2690 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2691 physid_mask_t tmp;
2692 unsigned long flags;
2693 int i = 0;
2694
2695 /*
2696 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2697 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2698 * supports up to 16 on one shared APIC bus.
2699 *
2700 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2701 * advantage of new APIC bus architecture.
2702 */
2703
2704 if (physids_empty(apic_id_map))
2705 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2706
2707 spin_lock_irqsave(&ioapic_lock, flags);
2708 reg_00.raw = io_apic_read(ioapic, 0);
2709 spin_unlock_irqrestore(&ioapic_lock, flags);
2710
2711 if (apic_id >= get_physical_broadcast()) {
2712 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2713 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2714 apic_id = reg_00.bits.ID;
2715 }
2716
2717 /*
2718 * Every APIC in a system must have a unique ID or we get lots of nice
2719 * 'stuck on smp_invalidate_needed IPI wait' messages.
2720 */
2721 if (check_apicid_used(apic_id_map, apic_id)) {
2722
2723 for (i = 0; i < get_physical_broadcast(); i++) {
2724 if (!check_apicid_used(apic_id_map, i))
2725 break;
2726 }
2727
2728 if (i == get_physical_broadcast())
2729 panic("Max apic_id exceeded!\n");
2730
2731 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2732 "trying %d\n", ioapic, apic_id, i);
2733
2734 apic_id = i;
2735 }
2736
2737 tmp = apicid_to_cpu_present(apic_id);
2738 physids_or(apic_id_map, apic_id_map, tmp);
2739
2740 if (reg_00.bits.ID != apic_id) {
2741 reg_00.bits.ID = apic_id;
2742
2743 spin_lock_irqsave(&ioapic_lock, flags);
2744 io_apic_write(ioapic, 0, reg_00.raw);
2745 reg_00.raw = io_apic_read(ioapic, 0);
2746 spin_unlock_irqrestore(&ioapic_lock, flags);
2747
2748 /* Sanity check */
6070f9ec
AD		 2749 if (reg_00.bits.ID != apic_id) {
2750 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2751 return -1;
2752 }
1da177e4
LT		 2753 }
2754
2755 apic_printk(APIC_VERBOSE, KERN_INFO
2756 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2757
2758 return apic_id;
2759}
2760
2761
2762int __init io_apic_get_version (int ioapic)
2763{
2764 union IO_APIC_reg_01 reg_01;
2765 unsigned long flags;
2766
2767 spin_lock_irqsave(&ioapic_lock, flags);
2768 reg_01.raw = io_apic_read(ioapic, 1);
2769 spin_unlock_irqrestore(&ioapic_lock, flags);
2770
2771 return reg_01.bits.version;
2772}
2773
2774
2775int __init io_apic_get_redir_entries (int ioapic)
2776{
2777 union IO_APIC_reg_01 reg_01;
2778 unsigned long flags;
2779
2780 spin_lock_irqsave(&ioapic_lock, flags);
2781 reg_01.raw = io_apic_read(ioapic, 1);
2782 spin_unlock_irqrestore(&ioapic_lock, flags);
2783
2784 return reg_01.bits.entries;
2785}
2786
2787
2788int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2789{
2790 struct IO_APIC_route_entry entry;
2791 unsigned long flags;
2792
2793 if (!IO_APIC_IRQ(irq)) {
2794 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2795 ioapic);
2796 return -EINVAL;
2797 }
2798
2799 /*
2800 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2801 * Note that we mask (disable) IRQs now -- these get enabled when the
2802 * corresponding device driver registers for this IRQ.
2803 */
2804
2805 memset(&entry,0,sizeof(entry));
2806
2807 entry.delivery_mode = INT_DELIVERY_MODE;
2808 entry.dest_mode = INT_DEST_MODE;
2809 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2810 entry.trigger = edge_level;
2811 entry.polarity = active_high_low;
2812 entry.mask = 1;
2813
2814 /*
2815 * IRQs < 16 are already in the irq_2_pin[] map
2816 */
2817 if (irq >= 16)
2818 add_pin_to_irq(irq, ioapic, pin);
2819
2820 entry.vector = assign_irq_vector(irq);
2821
2822 apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2823 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2824 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2825 edge_level, active_high_low);
2826
2827 ioapic_register_intr(irq, entry.vector, edge_level);
2828
2829 if (!ioapic && (irq < 16))
2830 disable_8259A_irq(irq);
2831
2832 spin_lock_irqsave(&ioapic_lock, flags);
d15512f4 2833 __ioapic_write_entry(ioapic, pin, entry);
1da177e4
LT		 2834 spin_unlock_irqrestore(&ioapic_lock, flags);
2835
2836 return 0;
2837}
2838
61fd47e0
SL		 2839int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2840{
2841 int i;
2842
2843 if (skip_ioapic_setup)
2844 return -1;
2845
2846 for (i = 0; i < mp_irq_entries; i++)
2847 if (mp_irqs[i].mpc_irqtype == mp_INT &&
2848 mp_irqs[i].mpc_srcbusirq == bus_irq)
2849 break;
2850 if (i >= mp_irq_entries)
2851 return -1;
2852
2853 *trigger = irq_trigger(i);
2854 *polarity = irq_polarity(i);
2855 return 0;
2856}
2857
888ba6c6 2858#endif /* CONFIG_ACPI */
1a3f239d
RR		 2859
2860static int __init parse_disable_timer_pin_1(char *arg)
2861{
2862 disable_timer_pin_1 = 1;
2863 return 0;
2864}
2865early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2866
2867static int __init parse_enable_timer_pin_1(char *arg)
2868{
2869 disable_timer_pin_1 = -1;
2870 return 0;
2871}
2872early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2873
2874static int __init parse_noapic(char *arg)
2875{
2876 /* disable IO-APIC */
2877 disable_ioapic_setup();
2878 return 0;
2879}
2880early_param("noapic", parse_noapic);
Linux 6.x block layer and io_uring tree(s)