Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo | |
5 | * | |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
f3294a33 | 28 | #include <linux/bootmem.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
2d3fcc1c | 34 | #include <linux/pci.h> |
3b7d1921 | 35 | #include <linux/msi.h> |
95d77884 | 36 | #include <linux/htirq.h> |
7dfb7103 | 37 | #include <linux/freezer.h> |
f26d6a2b | 38 | #include <linux/kthread.h> |
1d16b53e | 39 | #include <linux/jiffies.h> /* time_after() */ |
54d5d424 | 40 | |
1da177e4 LT |
41 | #include <asm/io.h> |
42 | #include <asm/smp.h> | |
43 | #include <asm/desc.h> | |
44 | #include <asm/timer.h> | |
306e440d | 45 | #include <asm/i8259.h> |
3e4ff115 | 46 | #include <asm/nmi.h> |
2d3fcc1c | 47 | #include <asm/msidef.h> |
8b955b0d | 48 | #include <asm/hypertransport.h> |
a4dbc34d | 49 | #include <asm/setup.h> |
1da177e4 LT |
50 | |
51 | #include <mach_apic.h> | |
874c4fe3 | 52 | #include <mach_apicdef.h> |
1da177e4 | 53 | |
32f71aff MR |
54 | #define __apicdebuginit(type) static type __init |
55 | ||
1da177e4 LT |
56 | int (*ioapic_renumber_irq)(int ioapic, int irq); |
57 | atomic_t irq_mis_count; | |
58 | ||
fcfd636a EB |
59 | /* Where if anywhere is the i8259 connect in external int mode */ |
60 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
61 | ||
1da177e4 | 62 | static DEFINE_SPINLOCK(ioapic_lock); |
d388e5fd | 63 | DEFINE_SPINLOCK(vector_lock); |
1da177e4 | 64 | |
35542c5e | 65 | int timer_through_8259 __initdata; |
f9262c12 | 66 | |
1da177e4 LT |
67 | /* |
68 | * Is the SiS APIC rmw bug present ? | |
69 | * -1 = don't know, 0 = no, 1 = yes | |
70 | */ | |
71 | int sis_apic_bug = -1; | |
72 | ||
301e6190 | 73 | int first_free_entry; |
1da177e4 LT |
74 | /* |
75 | * # of IRQ routing registers | |
76 | */ | |
77 | int nr_ioapic_registers[MAX_IO_APICS]; | |
78 | ||
9f640ccb | 79 | /* I/O APIC entries */ |
ec2cd0a2 | 80 | struct mp_config_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
81 | int nr_ioapics; |
82 | ||
584f734d | 83 | /* MP IRQ source entries */ |
2fddb6e2 | 84 | struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
85 | |
86 | /* # of MP IRQ source entries */ | |
87 | int mp_irq_entries; | |
88 | ||
8732fc4b AS |
89 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
90 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
91 | #endif | |
92 | ||
93 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
94 | ||
1a3f239d | 95 | static int disable_timer_pin_1 __initdata; |
66759a01 | 96 | |
1da177e4 LT |
97 | /* |
98 | * Rough estimation of how many shared IRQs there are, can | |
99 | * be changed anytime. | |
100 | */ | |
301e6190 | 101 | int pin_map_size; |
0799e432 | 102 | |
1da177e4 LT |
103 | /* |
104 | * This is performance-critical, we want to do it O(1) | |
105 | * | |
106 | * the indexing order of this array favors 1:1 mappings | |
107 | * between pins and IRQs. | |
108 | */ | |
109 | ||
110 | static struct irq_pin_list { | |
111 | int apic, pin, next; | |
301e6190 YL |
112 | } *irq_2_pin; |
113 | ||
114 | DEFINE_DYN_ARRAY(irq_2_pin, sizeof(struct irq_pin_list), pin_map_size, 16, NULL); | |
1da177e4 | 115 | |
130fe05d LT |
116 | struct io_apic { |
117 | unsigned int index; | |
118 | unsigned int unused[3]; | |
119 | unsigned int data; | |
120 | }; | |
121 | ||
122 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
123 | { | |
124 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
ec2cd0a2 | 125 | + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK); |
130fe05d LT |
126 | } |
127 | ||
128 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) | |
129 | { | |
130 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
131 | writel(reg, &io_apic->index); | |
132 | return readl(&io_apic->data); | |
133 | } | |
134 | ||
135 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
136 | { | |
137 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
138 | writel(reg, &io_apic->index); | |
139 | writel(value, &io_apic->data); | |
140 | } | |
141 | ||
142 | /* | |
143 | * Re-write a value: to be used for read-modify-write | |
144 | * cycles where the read already set up the index register. | |
145 | * | |
146 | * Older SiS APIC requires we rewrite the index register | |
147 | */ | |
148 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
149 | { | |
cb468984 | 150 | volatile struct io_apic __iomem *io_apic = io_apic_base(apic); |
130fe05d LT |
151 | if (sis_apic_bug) |
152 | writel(reg, &io_apic->index); | |
153 | writel(value, &io_apic->data); | |
154 | } | |
155 | ||
cf4c6a2f AK |
156 | union entry_union { |
157 | struct { u32 w1, w2; }; | |
158 | struct IO_APIC_route_entry entry; | |
159 | }; | |
160 | ||
161 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
162 | { | |
163 | union entry_union eu; | |
164 | unsigned long flags; | |
165 | spin_lock_irqsave(&ioapic_lock, flags); | |
166 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
167 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
168 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
169 | return eu.entry; | |
170 | } | |
171 | ||
f9dadfa7 LT |
172 | /* |
173 | * When we write a new IO APIC routing entry, we need to write the high | |
174 | * word first! If the mask bit in the low word is clear, we will enable | |
175 | * the interrupt, and we need to make sure the entry is fully populated | |
176 | * before that happens. | |
177 | */ | |
d15512f4 AK |
178 | static void |
179 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 180 | { |
cf4c6a2f AK |
181 | union entry_union eu; |
182 | eu.entry = e; | |
f9dadfa7 LT |
183 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
184 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
185 | } |
186 | ||
187 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
188 | { | |
189 | unsigned long flags; | |
190 | spin_lock_irqsave(&ioapic_lock, flags); | |
191 | __ioapic_write_entry(apic, pin, e); | |
f9dadfa7 LT |
192 | spin_unlock_irqrestore(&ioapic_lock, flags); |
193 | } | |
194 | ||
195 | /* | |
196 | * When we mask an IO APIC routing entry, we need to write the low | |
197 | * word first, in order to set the mask bit before we change the | |
198 | * high bits! | |
199 | */ | |
200 | static void ioapic_mask_entry(int apic, int pin) | |
201 | { | |
202 | unsigned long flags; | |
203 | union entry_union eu = { .entry.mask = 1 }; | |
204 | ||
cf4c6a2f AK |
205 | spin_lock_irqsave(&ioapic_lock, flags); |
206 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
207 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
208 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
209 | } | |
210 | ||
1da177e4 LT |
211 | /* |
212 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
213 | * shared ISA-space IRQs, so we have to support them. We are super | |
214 | * fast in the common case, and fast for shared ISA-space IRQs. | |
215 | */ | |
216 | static void add_pin_to_irq(unsigned int irq, int apic, int pin) | |
217 | { | |
1da177e4 LT |
218 | struct irq_pin_list *entry = irq_2_pin + irq; |
219 | ||
220 | while (entry->next) | |
221 | entry = irq_2_pin + entry->next; | |
222 | ||
223 | if (entry->pin != -1) { | |
224 | entry->next = first_free_entry; | |
225 | entry = irq_2_pin + entry->next; | |
0799e432 | 226 | if (++first_free_entry >= pin_map_size) |
1da177e4 LT |
227 | panic("io_apic.c: whoops"); |
228 | } | |
229 | entry->apic = apic; | |
230 | entry->pin = pin; | |
231 | } | |
232 | ||
233 | /* | |
234 | * Reroute an IRQ to a different pin. | |
235 | */ | |
236 | static void __init replace_pin_at_irq(unsigned int irq, | |
237 | int oldapic, int oldpin, | |
238 | int newapic, int newpin) | |
239 | { | |
240 | struct irq_pin_list *entry = irq_2_pin + irq; | |
241 | ||
242 | while (1) { | |
243 | if (entry->apic == oldapic && entry->pin == oldpin) { | |
244 | entry->apic = newapic; | |
245 | entry->pin = newpin; | |
246 | } | |
247 | if (!entry->next) | |
248 | break; | |
249 | entry = irq_2_pin + entry->next; | |
250 | } | |
251 | } | |
252 | ||
36062448 | 253 | static void __modify_IO_APIC_irq(unsigned int irq, unsigned long enable, unsigned long disable) |
1da177e4 LT |
254 | { |
255 | struct irq_pin_list *entry = irq_2_pin + irq; | |
256 | unsigned int pin, reg; | |
257 | ||
258 | for (;;) { | |
259 | pin = entry->pin; | |
260 | if (pin == -1) | |
261 | break; | |
262 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
263 | reg &= ~disable; | |
264 | reg |= enable; | |
265 | io_apic_modify(entry->apic, 0x10 + pin*2, reg); | |
266 | if (!entry->next) | |
267 | break; | |
268 | entry = irq_2_pin + entry->next; | |
269 | } | |
270 | } | |
271 | ||
272 | /* mask = 1 */ | |
36062448 | 273 | static void __mask_IO_APIC_irq(unsigned int irq) |
1da177e4 | 274 | { |
46b3b4ef | 275 | __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED, 0); |
1da177e4 LT |
276 | } |
277 | ||
278 | /* mask = 0 */ | |
36062448 | 279 | static void __unmask_IO_APIC_irq(unsigned int irq) |
1da177e4 | 280 | { |
46b3b4ef | 281 | __modify_IO_APIC_irq(irq, 0, IO_APIC_REDIR_MASKED); |
1da177e4 LT |
282 | } |
283 | ||
284 | /* mask = 1, trigger = 0 */ | |
36062448 | 285 | static void __mask_and_edge_IO_APIC_irq(unsigned int irq) |
1da177e4 | 286 | { |
46b3b4ef CG |
287 | __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED, |
288 | IO_APIC_REDIR_LEVEL_TRIGGER); | |
1da177e4 LT |
289 | } |
290 | ||
291 | /* mask = 0, trigger = 1 */ | |
36062448 | 292 | static void __unmask_and_level_IO_APIC_irq(unsigned int irq) |
1da177e4 | 293 | { |
46b3b4ef CG |
294 | __modify_IO_APIC_irq(irq, IO_APIC_REDIR_LEVEL_TRIGGER, |
295 | IO_APIC_REDIR_MASKED); | |
1da177e4 LT |
296 | } |
297 | ||
36062448 | 298 | static void mask_IO_APIC_irq(unsigned int irq) |
1da177e4 LT |
299 | { |
300 | unsigned long flags; | |
301 | ||
302 | spin_lock_irqsave(&ioapic_lock, flags); | |
303 | __mask_IO_APIC_irq(irq); | |
304 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
305 | } | |
306 | ||
36062448 | 307 | static void unmask_IO_APIC_irq(unsigned int irq) |
1da177e4 LT |
308 | { |
309 | unsigned long flags; | |
310 | ||
311 | spin_lock_irqsave(&ioapic_lock, flags); | |
312 | __unmask_IO_APIC_irq(irq); | |
313 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
314 | } | |
315 | ||
316 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) | |
317 | { | |
318 | struct IO_APIC_route_entry entry; | |
36062448 | 319 | |
1da177e4 | 320 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 321 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
322 | if (entry.delivery_mode == dest_SMI) |
323 | return; | |
324 | ||
325 | /* | |
326 | * Disable it in the IO-APIC irq-routing table: | |
327 | */ | |
f9dadfa7 | 328 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
329 | } |
330 | ||
36062448 | 331 | static void clear_IO_APIC(void) |
1da177e4 LT |
332 | { |
333 | int apic, pin; | |
334 | ||
335 | for (apic = 0; apic < nr_ioapics; apic++) | |
336 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
337 | clear_IO_APIC_pin(apic, pin); | |
338 | } | |
339 | ||
54d5d424 | 340 | #ifdef CONFIG_SMP |
1da177e4 LT |
341 | static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask) |
342 | { | |
343 | unsigned long flags; | |
344 | int pin; | |
345 | struct irq_pin_list *entry = irq_2_pin + irq; | |
346 | unsigned int apicid_value; | |
54d5d424 | 347 | cpumask_t tmp; |
08678b08 | 348 | struct irq_desc *desc; |
36062448 | 349 | |
54d5d424 AR |
350 | cpus_and(tmp, cpumask, cpu_online_map); |
351 | if (cpus_empty(tmp)) | |
352 | tmp = TARGET_CPUS; | |
353 | ||
354 | cpus_and(cpumask, tmp, CPU_MASK_ALL); | |
355 | ||
1da177e4 LT |
356 | apicid_value = cpu_mask_to_apicid(cpumask); |
357 | /* Prepare to do the io_apic_write */ | |
358 | apicid_value = apicid_value << 24; | |
359 | spin_lock_irqsave(&ioapic_lock, flags); | |
360 | for (;;) { | |
361 | pin = entry->pin; | |
362 | if (pin == -1) | |
363 | break; | |
364 | io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value); | |
365 | if (!entry->next) | |
366 | break; | |
367 | entry = irq_2_pin + entry->next; | |
368 | } | |
08678b08 YL |
369 | desc = irq_to_desc(irq); |
370 | desc->affinity = cpumask; | |
1da177e4 LT |
371 | spin_unlock_irqrestore(&ioapic_lock, flags); |
372 | } | |
373 | ||
374 | #if defined(CONFIG_IRQBALANCE) | |
375 | # include <asm/processor.h> /* kernel_thread() */ | |
376 | # include <linux/kernel_stat.h> /* kstat */ | |
377 | # include <linux/slab.h> /* kmalloc() */ | |
1d16b53e | 378 | # include <linux/timer.h> |
36062448 | 379 | |
1da177e4 | 380 | #define IRQBALANCE_CHECK_ARCH -999 |
1b61b910 ZY |
381 | #define MAX_BALANCED_IRQ_INTERVAL (5*HZ) |
382 | #define MIN_BALANCED_IRQ_INTERVAL (HZ/2) | |
383 | #define BALANCED_IRQ_MORE_DELTA (HZ/10) | |
384 | #define BALANCED_IRQ_LESS_DELTA (HZ) | |
385 | ||
386 | static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH; | |
387 | static int physical_balance __read_mostly; | |
388 | static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL; | |
1da177e4 LT |
389 | |
390 | static struct irq_cpu_info { | |
36062448 PC |
391 | unsigned long *last_irq; |
392 | unsigned long *irq_delta; | |
1da177e4 LT |
393 | unsigned long irq; |
394 | } irq_cpu_data[NR_CPUS]; | |
395 | ||
396 | #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq) | |
36062448 PC |
397 | #define LAST_CPU_IRQ(cpu, irq) (irq_cpu_data[cpu].last_irq[irq]) |
398 | #define IRQ_DELTA(cpu, irq) (irq_cpu_data[cpu].irq_delta[irq]) | |
1da177e4 LT |
399 | |
400 | #define IDLE_ENOUGH(cpu,now) \ | |
401 | (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1)) | |
402 | ||
403 | #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask) | |
404 | ||
d5a7430d | 405 | #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i))) |
1da177e4 | 406 | |
301e6190 YL |
407 | static cpumask_t balance_irq_affinity_init __initdata = CPU_MASK_ALL; |
408 | ||
409 | static cpumask_t *balance_irq_affinity; | |
410 | ||
411 | ||
412 | static void __init irq_affinity_init_work(void *data) | |
413 | { | |
414 | struct dyn_array *da = data; | |
415 | ||
416 | int i; | |
417 | struct balance_irq_affinity *affinity; | |
418 | ||
419 | affinity = *da->name; | |
420 | ||
421 | for (i = 0; i < *da->nr; i++) | |
422 | memcpy(&affinity[i], &balance_irq_affinity_init, | |
423 | sizeof(struct balance_irq_affinity)); | |
424 | ||
425 | } | |
426 | ||
427 | DEFINE_DYN_ARRAY(balance_irq_affinity, sizeof(struct balance_irq_affinity), nr_irqs, PAGE_SIZE, irq_affinity_init_work); | |
428 | ||
1da177e4 | 429 | |
1b61b910 ZY |
430 | void set_balance_irq_affinity(unsigned int irq, cpumask_t mask) |
431 | { | |
432 | balance_irq_affinity[irq] = mask; | |
433 | } | |
1da177e4 LT |
434 | |
435 | static unsigned long move(int curr_cpu, cpumask_t allowed_mask, | |
436 | unsigned long now, int direction) | |
437 | { | |
438 | int search_idle = 1; | |
439 | int cpu = curr_cpu; | |
440 | ||
441 | goto inside; | |
442 | ||
443 | do { | |
444 | if (unlikely(cpu == curr_cpu)) | |
445 | search_idle = 0; | |
446 | inside: | |
447 | if (direction == 1) { | |
448 | cpu++; | |
449 | if (cpu >= NR_CPUS) | |
450 | cpu = 0; | |
451 | } else { | |
452 | cpu--; | |
453 | if (cpu == -1) | |
454 | cpu = NR_CPUS-1; | |
455 | } | |
36062448 PC |
456 | } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu, allowed_mask) || |
457 | (search_idle && !IDLE_ENOUGH(cpu, now))); | |
1da177e4 LT |
458 | |
459 | return cpu; | |
460 | } | |
461 | ||
462 | static inline void balance_irq(int cpu, int irq) | |
463 | { | |
464 | unsigned long now = jiffies; | |
465 | cpumask_t allowed_mask; | |
466 | unsigned int new_cpu; | |
36062448 | 467 | |
1da177e4 | 468 | if (irqbalance_disabled) |
36062448 | 469 | return; |
1da177e4 | 470 | |
1b61b910 | 471 | cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]); |
1da177e4 | 472 | new_cpu = move(cpu, allowed_mask, now, 1); |
36062448 | 473 | if (cpu != new_cpu) |
54d5d424 | 474 | set_pending_irq(irq, cpumask_of_cpu(new_cpu)); |
1da177e4 LT |
475 | } |
476 | ||
477 | static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold) | |
478 | { | |
479 | int i, j; | |
08678b08 | 480 | struct irq_desc *desc; |
edc2cbf4 | 481 | |
394e3902 | 482 | for_each_online_cpu(i) { |
0799e432 | 483 | for (j = 0; j < nr_irqs; j++) { |
08678b08 YL |
484 | desc = irq_to_desc(j); |
485 | if (!desc->action) | |
1da177e4 LT |
486 | continue; |
487 | /* Is it a significant load ? */ | |
36062448 | 488 | if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i), j) < |
1da177e4 LT |
489 | useful_load_threshold) |
490 | continue; | |
491 | balance_irq(i, j); | |
492 | } | |
493 | } | |
494 | balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL, | |
36062448 | 495 | balanced_irq_interval - BALANCED_IRQ_LESS_DELTA); |
1da177e4 LT |
496 | return; |
497 | } | |
498 | ||
499 | static void do_irq_balance(void) | |
500 | { | |
501 | int i, j; | |
502 | unsigned long max_cpu_irq = 0, min_cpu_irq = (~0); | |
503 | unsigned long move_this_load = 0; | |
504 | int max_loaded = 0, min_loaded = 0; | |
505 | int load; | |
506 | unsigned long useful_load_threshold = balanced_irq_interval + 10; | |
507 | int selected_irq; | |
508 | int tmp_loaded, first_attempt = 1; | |
509 | unsigned long tmp_cpu_irq; | |
510 | unsigned long imbalance = 0; | |
511 | cpumask_t allowed_mask, target_cpu_mask, tmp; | |
08678b08 | 512 | struct irq_desc *desc; |
1da177e4 | 513 | |
c8912599 | 514 | for_each_possible_cpu(i) { |
1da177e4 LT |
515 | int package_index; |
516 | CPU_IRQ(i) = 0; | |
517 | if (!cpu_online(i)) | |
518 | continue; | |
519 | package_index = CPU_TO_PACKAGEINDEX(i); | |
0799e432 | 520 | for (j = 0; j < nr_irqs; j++) { |
1da177e4 | 521 | unsigned long value_now, delta; |
950f4427 | 522 | /* Is this an active IRQ or balancing disabled ? */ |
08678b08 YL |
523 | desc = irq_to_desc(j); |
524 | if (!desc->action || irq_balancing_disabled(j)) | |
1da177e4 | 525 | continue; |
36062448 PC |
526 | if (package_index == i) |
527 | IRQ_DELTA(package_index, j) = 0; | |
1da177e4 LT |
528 | /* Determine the total count per processor per IRQ */ |
529 | value_now = (unsigned long) kstat_cpu(i).irqs[j]; | |
530 | ||
531 | /* Determine the activity per processor per IRQ */ | |
36062448 | 532 | delta = value_now - LAST_CPU_IRQ(i, j); |
1da177e4 LT |
533 | |
534 | /* Update last_cpu_irq[][] for the next time */ | |
36062448 | 535 | LAST_CPU_IRQ(i, j) = value_now; |
1da177e4 LT |
536 | |
537 | /* Ignore IRQs whose rate is less than the clock */ | |
538 | if (delta < useful_load_threshold) | |
539 | continue; | |
540 | /* update the load for the processor or package total */ | |
36062448 | 541 | IRQ_DELTA(package_index, j) += delta; |
1da177e4 LT |
542 | |
543 | /* Keep track of the higher numbered sibling as well */ | |
544 | if (i != package_index) | |
545 | CPU_IRQ(i) += delta; | |
546 | /* | |
547 | * We have sibling A and sibling B in the package | |
548 | * | |
549 | * cpu_irq[A] = load for cpu A + load for cpu B | |
550 | * cpu_irq[B] = load for cpu B | |
551 | */ | |
552 | CPU_IRQ(package_index) += delta; | |
553 | } | |
554 | } | |
555 | /* Find the least loaded processor package */ | |
394e3902 | 556 | for_each_online_cpu(i) { |
1da177e4 LT |
557 | if (i != CPU_TO_PACKAGEINDEX(i)) |
558 | continue; | |
559 | if (min_cpu_irq > CPU_IRQ(i)) { | |
560 | min_cpu_irq = CPU_IRQ(i); | |
561 | min_loaded = i; | |
562 | } | |
563 | } | |
564 | max_cpu_irq = ULONG_MAX; | |
565 | ||
566 | tryanothercpu: | |
36062448 PC |
567 | /* |
568 | * Look for heaviest loaded processor. | |
1da177e4 LT |
569 | * We may come back to get the next heaviest loaded processor. |
570 | * Skip processors with trivial loads. | |
571 | */ | |
572 | tmp_cpu_irq = 0; | |
573 | tmp_loaded = -1; | |
394e3902 | 574 | for_each_online_cpu(i) { |
1da177e4 LT |
575 | if (i != CPU_TO_PACKAGEINDEX(i)) |
576 | continue; | |
36062448 | 577 | if (max_cpu_irq <= CPU_IRQ(i)) |
1da177e4 LT |
578 | continue; |
579 | if (tmp_cpu_irq < CPU_IRQ(i)) { | |
580 | tmp_cpu_irq = CPU_IRQ(i); | |
581 | tmp_loaded = i; | |
582 | } | |
583 | } | |
584 | ||
585 | if (tmp_loaded == -1) { | |
36062448 PC |
586 | /* |
587 | * In the case of small number of heavy interrupt sources, | |
588 | * loading some of the cpus too much. We use Ingo's original | |
1da177e4 LT |
589 | * approach to rotate them around. |
590 | */ | |
591 | if (!first_attempt && imbalance >= useful_load_threshold) { | |
592 | rotate_irqs_among_cpus(useful_load_threshold); | |
593 | return; | |
594 | } | |
595 | goto not_worth_the_effort; | |
596 | } | |
36062448 | 597 | |
1da177e4 LT |
598 | first_attempt = 0; /* heaviest search */ |
599 | max_cpu_irq = tmp_cpu_irq; /* load */ | |
600 | max_loaded = tmp_loaded; /* processor */ | |
601 | imbalance = (max_cpu_irq - min_cpu_irq) / 2; | |
36062448 PC |
602 | |
603 | /* | |
604 | * if imbalance is less than approx 10% of max load, then | |
1da177e4 LT |
605 | * observe diminishing returns action. - quit |
606 | */ | |
edc2cbf4 | 607 | if (imbalance < (max_cpu_irq >> 3)) |
1da177e4 | 608 | goto not_worth_the_effort; |
1da177e4 LT |
609 | |
610 | tryanotherirq: | |
611 | /* if we select an IRQ to move that can't go where we want, then | |
612 | * see if there is another one to try. | |
613 | */ | |
614 | move_this_load = 0; | |
615 | selected_irq = -1; | |
0799e432 | 616 | for (j = 0; j < nr_irqs; j++) { |
1da177e4 | 617 | /* Is this an active IRQ? */ |
08678b08 YL |
618 | desc = irq_to_desc(j); |
619 | if (!desc->action) | |
1da177e4 | 620 | continue; |
36062448 | 621 | if (imbalance <= IRQ_DELTA(max_loaded, j)) |
1da177e4 LT |
622 | continue; |
623 | /* Try to find the IRQ that is closest to the imbalance | |
624 | * without going over. | |
625 | */ | |
36062448 PC |
626 | if (move_this_load < IRQ_DELTA(max_loaded, j)) { |
627 | move_this_load = IRQ_DELTA(max_loaded, j); | |
1da177e4 LT |
628 | selected_irq = j; |
629 | } | |
630 | } | |
36062448 | 631 | if (selected_irq == -1) |
1da177e4 | 632 | goto tryanothercpu; |
1da177e4 LT |
633 | |
634 | imbalance = move_this_load; | |
36062448 | 635 | |
27b46d76 | 636 | /* For physical_balance case, we accumulated both load |
1da177e4 LT |
637 | * values in the one of the siblings cpu_irq[], |
638 | * to use the same code for physical and logical processors | |
36062448 | 639 | * as much as possible. |
1da177e4 LT |
640 | * |
641 | * NOTE: the cpu_irq[] array holds the sum of the load for | |
642 | * sibling A and sibling B in the slot for the lowest numbered | |
643 | * sibling (A), _AND_ the load for sibling B in the slot for | |
644 | * the higher numbered sibling. | |
645 | * | |
646 | * We seek the least loaded sibling by making the comparison | |
647 | * (A+B)/2 vs B | |
648 | */ | |
649 | load = CPU_IRQ(min_loaded) >> 1; | |
d5a7430d | 650 | for_each_cpu_mask(j, per_cpu(cpu_sibling_map, min_loaded)) { |
1da177e4 LT |
651 | if (load > CPU_IRQ(j)) { |
652 | /* This won't change cpu_sibling_map[min_loaded] */ | |
653 | load = CPU_IRQ(j); | |
654 | min_loaded = j; | |
655 | } | |
656 | } | |
657 | ||
1b61b910 ZY |
658 | cpus_and(allowed_mask, |
659 | cpu_online_map, | |
660 | balance_irq_affinity[selected_irq]); | |
1da177e4 LT |
661 | target_cpu_mask = cpumask_of_cpu(min_loaded); |
662 | cpus_and(tmp, target_cpu_mask, allowed_mask); | |
663 | ||
664 | if (!cpus_empty(tmp)) { | |
1da177e4 | 665 | /* mark for change destination */ |
54d5d424 AR |
666 | set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded)); |
667 | ||
36062448 | 668 | /* Since we made a change, come back sooner to |
1da177e4 LT |
669 | * check for more variation. |
670 | */ | |
671 | balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL, | |
36062448 | 672 | balanced_irq_interval - BALANCED_IRQ_LESS_DELTA); |
1da177e4 LT |
673 | return; |
674 | } | |
675 | goto tryanotherirq; | |
676 | ||
677 | not_worth_the_effort: | |
678 | /* | |
679 | * if we did not find an IRQ to move, then adjust the time interval | |
680 | * upward | |
681 | */ | |
682 | balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL, | |
36062448 | 683 | balanced_irq_interval + BALANCED_IRQ_MORE_DELTA); |
1da177e4 LT |
684 | return; |
685 | } | |
686 | ||
687 | static int balanced_irq(void *unused) | |
688 | { | |
689 | int i; | |
690 | unsigned long prev_balance_time = jiffies; | |
691 | long time_remaining = balanced_irq_interval; | |
08678b08 | 692 | struct irq_desc *desc; |
1da177e4 | 693 | |
1da177e4 | 694 | /* push everything to CPU 0 to give us a starting point. */ |
0799e432 | 695 | for (i = 0 ; i < nr_irqs ; i++) { |
08678b08 YL |
696 | desc = irq_to_desc(i); |
697 | desc->pending_mask = cpumask_of_cpu(0); | |
54d5d424 | 698 | set_pending_irq(i, cpumask_of_cpu(0)); |
1da177e4 LT |
699 | } |
700 | ||
83144186 | 701 | set_freezable(); |
1da177e4 | 702 | for ( ; ; ) { |
52e6e630 | 703 | time_remaining = schedule_timeout_interruptible(time_remaining); |
3e1d1d28 | 704 | try_to_freeze(); |
1da177e4 LT |
705 | if (time_after(jiffies, |
706 | prev_balance_time+balanced_irq_interval)) { | |
f3705136 | 707 | preempt_disable(); |
1da177e4 LT |
708 | do_irq_balance(); |
709 | prev_balance_time = jiffies; | |
710 | time_remaining = balanced_irq_interval; | |
f3705136 | 711 | preempt_enable(); |
1da177e4 LT |
712 | } |
713 | } | |
714 | return 0; | |
715 | } | |
716 | ||
717 | static int __init balanced_irq_init(void) | |
718 | { | |
719 | int i; | |
720 | struct cpuinfo_x86 *c; | |
721 | cpumask_t tmp; | |
722 | ||
723 | cpus_shift_right(tmp, cpu_online_map, 2); | |
36062448 | 724 | c = &boot_cpu_data; |
1da177e4 LT |
725 | /* When not overwritten by the command line ask subarchitecture. */ |
726 | if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH) | |
727 | irqbalance_disabled = NO_BALANCE_IRQ; | |
728 | if (irqbalance_disabled) | |
729 | return 0; | |
36062448 | 730 | |
1da177e4 LT |
731 | /* disable irqbalance completely if there is only one processor online */ |
732 | if (num_online_cpus() < 2) { | |
733 | irqbalance_disabled = 1; | |
734 | return 0; | |
735 | } | |
736 | /* | |
737 | * Enable physical balance only if more than 1 physical processor | |
738 | * is present | |
739 | */ | |
740 | if (smp_num_siblings > 1 && !cpus_empty(tmp)) | |
741 | physical_balance = 1; | |
742 | ||
394e3902 | 743 | for_each_online_cpu(i) { |
0799e432 YL |
744 | irq_cpu_data[i].irq_delta = kzalloc(sizeof(unsigned long) * nr_irqs, GFP_KERNEL); |
745 | irq_cpu_data[i].last_irq = kzalloc(sizeof(unsigned long) * nr_irqs, GFP_KERNEL); | |
1da177e4 LT |
746 | if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) { |
747 | printk(KERN_ERR "balanced_irq_init: out of memory"); | |
748 | goto failed; | |
749 | } | |
1da177e4 | 750 | } |
36062448 | 751 | |
1da177e4 | 752 | printk(KERN_INFO "Starting balanced_irq\n"); |
f26d6a2b | 753 | if (!IS_ERR(kthread_run(balanced_irq, NULL, "kirqd"))) |
1da177e4 | 754 | return 0; |
f26d6a2b | 755 | printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq"); |
1da177e4 | 756 | failed: |
c8912599 | 757 | for_each_possible_cpu(i) { |
4ae6673e | 758 | kfree(irq_cpu_data[i].irq_delta); |
394e3902 | 759 | irq_cpu_data[i].irq_delta = NULL; |
4ae6673e | 760 | kfree(irq_cpu_data[i].last_irq); |
394e3902 | 761 | irq_cpu_data[i].last_irq = NULL; |
1da177e4 LT |
762 | } |
763 | return 0; | |
764 | } | |
765 | ||
c2481cc4 | 766 | int __devinit irqbalance_disable(char *str) |
1da177e4 LT |
767 | { |
768 | irqbalance_disabled = 1; | |
9b41046c | 769 | return 1; |
1da177e4 LT |
770 | } |
771 | ||
772 | __setup("noirqbalance", irqbalance_disable); | |
773 | ||
1da177e4 | 774 | late_initcall(balanced_irq_init); |
1da177e4 | 775 | #endif /* CONFIG_IRQBALANCE */ |
54d5d424 | 776 | #endif /* CONFIG_SMP */ |
1da177e4 LT |
777 | |
778 | #ifndef CONFIG_SMP | |
75604d7f | 779 | void send_IPI_self(int vector) |
1da177e4 LT |
780 | { |
781 | unsigned int cfg; | |
782 | ||
783 | /* | |
784 | * Wait for idle. | |
785 | */ | |
786 | apic_wait_icr_idle(); | |
787 | cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL; | |
788 | /* | |
789 | * Send the IPI. The write to APIC_ICR fires this off. | |
790 | */ | |
593f4a78 | 791 | apic_write(APIC_ICR, cfg); |
1da177e4 LT |
792 | } |
793 | #endif /* !CONFIG_SMP */ | |
794 | ||
795 | ||
796 | /* | |
797 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
798 | * specific CPU-side IRQs. | |
799 | */ | |
800 | ||
801 | #define MAX_PIRQS 8 | |
802 | static int pirq_entries [MAX_PIRQS]; | |
803 | static int pirqs_enabled; | |
804 | int skip_ioapic_setup; | |
805 | ||
1da177e4 LT |
806 | static int __init ioapic_pirq_setup(char *str) |
807 | { | |
808 | int i, max; | |
809 | int ints[MAX_PIRQS+1]; | |
810 | ||
811 | get_options(str, ARRAY_SIZE(ints), ints); | |
812 | ||
813 | for (i = 0; i < MAX_PIRQS; i++) | |
814 | pirq_entries[i] = -1; | |
815 | ||
816 | pirqs_enabled = 1; | |
817 | apic_printk(APIC_VERBOSE, KERN_INFO | |
818 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
819 | max = MAX_PIRQS; | |
820 | if (ints[0] < MAX_PIRQS) | |
821 | max = ints[0]; | |
822 | ||
823 | for (i = 0; i < max; i++) { | |
824 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
825 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
826 | /* | |
827 | * PIRQs are mapped upside down, usually. | |
828 | */ | |
829 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
830 | } | |
831 | return 1; | |
832 | } | |
833 | ||
834 | __setup("pirq=", ioapic_pirq_setup); | |
835 | ||
836 | /* | |
837 | * Find the IRQ entry number of a certain pin. | |
838 | */ | |
839 | static int find_irq_entry(int apic, int pin, int type) | |
840 | { | |
841 | int i; | |
842 | ||
843 | for (i = 0; i < mp_irq_entries; i++) | |
2fddb6e2 AS |
844 | if (mp_irqs[i].mp_irqtype == type && |
845 | (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid || | |
846 | mp_irqs[i].mp_dstapic == MP_APIC_ALL) && | |
847 | mp_irqs[i].mp_dstirq == pin) | |
1da177e4 LT |
848 | return i; |
849 | ||
850 | return -1; | |
851 | } | |
852 | ||
853 | /* | |
854 | * Find the pin to which IRQ[irq] (ISA) is connected | |
855 | */ | |
fcfd636a | 856 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
857 | { |
858 | int i; | |
859 | ||
860 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 861 | int lbus = mp_irqs[i].mp_srcbus; |
1da177e4 | 862 | |
d27e2b8e | 863 | if (test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 AS |
864 | (mp_irqs[i].mp_irqtype == type) && |
865 | (mp_irqs[i].mp_srcbusirq == irq)) | |
1da177e4 | 866 | |
2fddb6e2 | 867 | return mp_irqs[i].mp_dstirq; |
1da177e4 LT |
868 | } |
869 | return -1; | |
870 | } | |
871 | ||
fcfd636a EB |
872 | static int __init find_isa_irq_apic(int irq, int type) |
873 | { | |
874 | int i; | |
875 | ||
876 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 877 | int lbus = mp_irqs[i].mp_srcbus; |
fcfd636a | 878 | |
73b2961b | 879 | if (test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 AS |
880 | (mp_irqs[i].mp_irqtype == type) && |
881 | (mp_irqs[i].mp_srcbusirq == irq)) | |
fcfd636a EB |
882 | break; |
883 | } | |
884 | if (i < mp_irq_entries) { | |
885 | int apic; | |
36062448 | 886 | for (apic = 0; apic < nr_ioapics; apic++) { |
2fddb6e2 | 887 | if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic) |
fcfd636a EB |
888 | return apic; |
889 | } | |
890 | } | |
891 | ||
892 | return -1; | |
893 | } | |
894 | ||
1da177e4 LT |
895 | /* |
896 | * Find a specific PCI IRQ entry. | |
897 | * Not an __init, possibly needed by modules | |
898 | */ | |
899 | static int pin_2_irq(int idx, int apic, int pin); | |
900 | ||
901 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) | |
902 | { | |
903 | int apic, i, best_guess = -1; | |
904 | ||
905 | apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, " | |
906 | "slot:%d, pin:%d.\n", bus, slot, pin); | |
ce6444d3 | 907 | if (test_bit(bus, mp_bus_not_pci)) { |
1da177e4 LT |
908 | printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus); |
909 | return -1; | |
910 | } | |
911 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 912 | int lbus = mp_irqs[i].mp_srcbus; |
1da177e4 LT |
913 | |
914 | for (apic = 0; apic < nr_ioapics; apic++) | |
2fddb6e2 AS |
915 | if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic || |
916 | mp_irqs[i].mp_dstapic == MP_APIC_ALL) | |
1da177e4 LT |
917 | break; |
918 | ||
47cab822 | 919 | if (!test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 | 920 | !mp_irqs[i].mp_irqtype && |
1da177e4 | 921 | (bus == lbus) && |
2fddb6e2 | 922 | (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) { |
3de352bb | 923 | int irq = pin_2_irq(i, apic, mp_irqs[i].mp_dstirq); |
1da177e4 LT |
924 | |
925 | if (!(apic || IO_APIC_IRQ(irq))) | |
926 | continue; | |
927 | ||
2fddb6e2 | 928 | if (pin == (mp_irqs[i].mp_srcbusirq & 3)) |
1da177e4 LT |
929 | return irq; |
930 | /* | |
931 | * Use the first all-but-pin matching entry as a | |
932 | * best-guess fuzzy result for broken mptables. | |
933 | */ | |
934 | if (best_guess < 0) | |
935 | best_guess = irq; | |
936 | } | |
937 | } | |
938 | return best_guess; | |
939 | } | |
129f6946 | 940 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); |
1da177e4 LT |
941 | |
942 | /* | |
36062448 | 943 | * This function currently is only a helper for the i386 smp boot process where |
1da177e4 LT |
944 | * we need to reprogram the ioredtbls to cater for the cpus which have come online |
945 | * so mask in all cases should simply be TARGET_CPUS | |
946 | */ | |
54d5d424 | 947 | #ifdef CONFIG_SMP |
1da177e4 LT |
948 | void __init setup_ioapic_dest(void) |
949 | { | |
950 | int pin, ioapic, irq, irq_entry; | |
951 | ||
952 | if (skip_ioapic_setup == 1) | |
953 | return; | |
954 | ||
955 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) { | |
956 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { | |
957 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
958 | if (irq_entry == -1) | |
959 | continue; | |
960 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
961 | set_ioapic_affinity_irq(irq, TARGET_CPUS); | |
962 | } | |
963 | ||
964 | } | |
965 | } | |
54d5d424 | 966 | #endif |
1da177e4 | 967 | |
c0a282c2 | 968 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
969 | /* |
970 | * EISA Edge/Level control register, ELCR | |
971 | */ | |
972 | static int EISA_ELCR(unsigned int irq) | |
973 | { | |
974 | if (irq < 16) { | |
975 | unsigned int port = 0x4d0 + (irq >> 3); | |
976 | return (inb(port) >> (irq & 7)) & 1; | |
977 | } | |
978 | apic_printk(APIC_VERBOSE, KERN_INFO | |
979 | "Broken MPtable reports ISA irq %d\n", irq); | |
980 | return 0; | |
981 | } | |
c0a282c2 | 982 | #endif |
1da177e4 | 983 | |
6728801d AS |
984 | /* ISA interrupts are always polarity zero edge triggered, |
985 | * when listed as conforming in the MP table. */ | |
986 | ||
987 | #define default_ISA_trigger(idx) (0) | |
988 | #define default_ISA_polarity(idx) (0) | |
989 | ||
1da177e4 LT |
990 | /* EISA interrupts are always polarity zero and can be edge or level |
991 | * trigger depending on the ELCR value. If an interrupt is listed as | |
992 | * EISA conforming in the MP table, that means its trigger type must | |
993 | * be read in from the ELCR */ | |
994 | ||
2fddb6e2 | 995 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq)) |
6728801d | 996 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
997 | |
998 | /* PCI interrupts are always polarity one level triggered, | |
999 | * when listed as conforming in the MP table. */ | |
1000 | ||
1001 | #define default_PCI_trigger(idx) (1) | |
1002 | #define default_PCI_polarity(idx) (1) | |
1003 | ||
1004 | /* MCA interrupts are always polarity zero level triggered, | |
1005 | * when listed as conforming in the MP table. */ | |
1006 | ||
1007 | #define default_MCA_trigger(idx) (1) | |
6728801d | 1008 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 1009 | |
61fd47e0 | 1010 | static int MPBIOS_polarity(int idx) |
1da177e4 | 1011 | { |
2fddb6e2 | 1012 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
1013 | int polarity; |
1014 | ||
1015 | /* | |
1016 | * Determine IRQ line polarity (high active or low active): | |
1017 | */ | |
3de352bb | 1018 | switch (mp_irqs[idx].mp_irqflag & 3) { |
36062448 | 1019 | case 0: /* conforms, ie. bus-type dependent polarity */ |
1da177e4 | 1020 | { |
36062448 PC |
1021 | polarity = test_bit(bus, mp_bus_not_pci)? |
1022 | default_ISA_polarity(idx): | |
1023 | default_PCI_polarity(idx); | |
1024 | break; | |
1025 | } | |
1026 | case 1: /* high active */ | |
1027 | { | |
1028 | polarity = 0; | |
1029 | break; | |
1030 | } | |
1031 | case 2: /* reserved */ | |
1032 | { | |
1033 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1034 | polarity = 1; | |
1035 | break; | |
1036 | } | |
1037 | case 3: /* low active */ | |
1038 | { | |
1039 | polarity = 1; | |
1040 | break; | |
1041 | } | |
1042 | default: /* invalid */ | |
1043 | { | |
1044 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1045 | polarity = 1; | |
1046 | break; | |
1047 | } | |
1da177e4 LT |
1048 | } |
1049 | return polarity; | |
1050 | } | |
1051 | ||
1052 | static int MPBIOS_trigger(int idx) | |
1053 | { | |
2fddb6e2 | 1054 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
1055 | int trigger; |
1056 | ||
1057 | /* | |
1058 | * Determine IRQ trigger mode (edge or level sensitive): | |
1059 | */ | |
3de352bb | 1060 | switch ((mp_irqs[idx].mp_irqflag>>2) & 3) { |
36062448 | 1061 | case 0: /* conforms, ie. bus-type dependent */ |
1da177e4 | 1062 | { |
36062448 PC |
1063 | trigger = test_bit(bus, mp_bus_not_pci)? |
1064 | default_ISA_trigger(idx): | |
1065 | default_PCI_trigger(idx); | |
c0a282c2 | 1066 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
36062448 PC |
1067 | switch (mp_bus_id_to_type[bus]) { |
1068 | case MP_BUS_ISA: /* ISA pin */ | |
1069 | { | |
1070 | /* set before the switch */ | |
1da177e4 LT |
1071 | break; |
1072 | } | |
36062448 | 1073 | case MP_BUS_EISA: /* EISA pin */ |
1da177e4 | 1074 | { |
36062448 | 1075 | trigger = default_EISA_trigger(idx); |
1da177e4 LT |
1076 | break; |
1077 | } | |
36062448 | 1078 | case MP_BUS_PCI: /* PCI pin */ |
1da177e4 | 1079 | { |
36062448 | 1080 | /* set before the switch */ |
1da177e4 LT |
1081 | break; |
1082 | } | |
36062448 | 1083 | case MP_BUS_MCA: /* MCA pin */ |
1da177e4 | 1084 | { |
36062448 | 1085 | trigger = default_MCA_trigger(idx); |
1da177e4 LT |
1086 | break; |
1087 | } | |
36062448 | 1088 | default: |
1da177e4 LT |
1089 | { |
1090 | printk(KERN_WARNING "broken BIOS!!\n"); | |
36062448 | 1091 | trigger = 1; |
1da177e4 LT |
1092 | break; |
1093 | } | |
1094 | } | |
36062448 PC |
1095 | #endif |
1096 | break; | |
1097 | } | |
1098 | case 1: /* edge */ | |
1099 | { | |
1100 | trigger = 0; | |
1101 | break; | |
1102 | } | |
1103 | case 2: /* reserved */ | |
1104 | { | |
1105 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1106 | trigger = 1; | |
1107 | break; | |
1108 | } | |
1109 | case 3: /* level */ | |
1110 | { | |
1111 | trigger = 1; | |
1112 | break; | |
1113 | } | |
1114 | default: /* invalid */ | |
1115 | { | |
1116 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1117 | trigger = 0; | |
1118 | break; | |
1119 | } | |
1120 | } | |
1da177e4 LT |
1121 | return trigger; |
1122 | } | |
1123 | ||
1124 | static inline int irq_polarity(int idx) | |
1125 | { | |
1126 | return MPBIOS_polarity(idx); | |
1127 | } | |
1128 | ||
1129 | static inline int irq_trigger(int idx) | |
1130 | { | |
1131 | return MPBIOS_trigger(idx); | |
1132 | } | |
1133 | ||
1134 | static int pin_2_irq(int idx, int apic, int pin) | |
1135 | { | |
1136 | int irq, i; | |
2fddb6e2 | 1137 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
1138 | |
1139 | /* | |
1140 | * Debugging check, we are in big trouble if this message pops up! | |
1141 | */ | |
2fddb6e2 | 1142 | if (mp_irqs[idx].mp_dstirq != pin) |
1da177e4 LT |
1143 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
1144 | ||
643befed | 1145 | if (test_bit(bus, mp_bus_not_pci)) |
2fddb6e2 | 1146 | irq = mp_irqs[idx].mp_srcbusirq; |
643befed AS |
1147 | else { |
1148 | /* | |
1149 | * PCI IRQs are mapped in order | |
1150 | */ | |
1151 | i = irq = 0; | |
1152 | while (i < apic) | |
1153 | irq += nr_ioapic_registers[i++]; | |
1154 | irq += pin; | |
1da177e4 | 1155 | |
643befed AS |
1156 | /* |
1157 | * For MPS mode, so far only needed by ES7000 platform | |
1158 | */ | |
1159 | if (ioapic_renumber_irq) | |
1160 | irq = ioapic_renumber_irq(apic, irq); | |
1da177e4 LT |
1161 | } |
1162 | ||
1163 | /* | |
1164 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1165 | */ | |
1166 | if ((pin >= 16) && (pin <= 23)) { | |
1167 | if (pirq_entries[pin-16] != -1) { | |
1168 | if (!pirq_entries[pin-16]) { | |
1169 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1170 | "disabling PIRQ%d\n", pin-16); | |
1171 | } else { | |
1172 | irq = pirq_entries[pin-16]; | |
1173 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1174 | "using PIRQ%d -> IRQ %d\n", | |
1175 | pin-16, irq); | |
1176 | } | |
1177 | } | |
1178 | } | |
1179 | return irq; | |
1180 | } | |
1181 | ||
1182 | static inline int IO_APIC_irq_trigger(int irq) | |
1183 | { | |
1184 | int apic, idx, pin; | |
1185 | ||
1186 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1187 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
36062448 PC |
1188 | idx = find_irq_entry(apic, pin, mp_INT); |
1189 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1da177e4 LT |
1190 | return irq_trigger(idx); |
1191 | } | |
1192 | } | |
1193 | /* | |
1194 | * nonexistent IRQs are edge default | |
1195 | */ | |
1196 | return 0; | |
1197 | } | |
1198 | ||
1199 | /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */ | |
301e6190 YL |
1200 | static u8 irq_vector_init_first __initdata = FIRST_DEVICE_VECTOR; |
1201 | static u8 *irq_vector; | |
1202 | ||
1203 | static void __init irq_vector_init_work(void *data) | |
1204 | { | |
1205 | struct dyn_array *da = data; | |
1206 | ||
1207 | u8 *irq_vec; | |
1208 | ||
1209 | irq_vec = *da->name; | |
1210 | ||
1211 | irq_vec[0] = irq_vector_init_first; | |
1212 | } | |
1213 | ||
1214 | DEFINE_DYN_ARRAY(irq_vector, sizeof(u8), nr_irqs, PAGE_SIZE, irq_vector_init_work); | |
1da177e4 | 1215 | |
ace80ab7 | 1216 | static int __assign_irq_vector(int irq) |
1da177e4 | 1217 | { |
36062448 | 1218 | static int current_vector = FIRST_DEVICE_VECTOR, current_offset; |
dbeb2be2 | 1219 | int vector, offset; |
1da177e4 | 1220 | |
301e6190 | 1221 | BUG_ON((unsigned)irq >= nr_irqs); |
0a1ad60d | 1222 | |
b940d22d EB |
1223 | if (irq_vector[irq] > 0) |
1224 | return irq_vector[irq]; | |
ace80ab7 | 1225 | |
0a1ad60d | 1226 | vector = current_vector; |
8339f000 EB |
1227 | offset = current_offset; |
1228 | next: | |
1229 | vector += 8; | |
305b92a2 | 1230 | if (vector >= first_system_vector) { |
8339f000 EB |
1231 | offset = (offset + 1) % 8; |
1232 | vector = FIRST_DEVICE_VECTOR + offset; | |
1233 | } | |
1234 | if (vector == current_vector) | |
1235 | return -ENOSPC; | |
dbeb2be2 | 1236 | if (test_and_set_bit(vector, used_vectors)) |
8339f000 | 1237 | goto next; |
8339f000 EB |
1238 | |
1239 | current_vector = vector; | |
1240 | current_offset = offset; | |
b940d22d | 1241 | irq_vector[irq] = vector; |
ace80ab7 EB |
1242 | |
1243 | return vector; | |
1244 | } | |
0a1ad60d | 1245 | |
ace80ab7 EB |
1246 | static int assign_irq_vector(int irq) |
1247 | { | |
1248 | unsigned long flags; | |
1249 | int vector; | |
1250 | ||
1251 | spin_lock_irqsave(&vector_lock, flags); | |
1252 | vector = __assign_irq_vector(irq); | |
26a3c49c | 1253 | spin_unlock_irqrestore(&vector_lock, flags); |
1da177e4 | 1254 | |
0a1ad60d | 1255 | return vector; |
1da177e4 | 1256 | } |
3fde6900 | 1257 | |
f5b9ed7a | 1258 | static struct irq_chip ioapic_chip; |
1da177e4 LT |
1259 | |
1260 | #define IOAPIC_AUTO -1 | |
1261 | #define IOAPIC_EDGE 0 | |
1262 | #define IOAPIC_LEVEL 1 | |
1263 | ||
d1bef4ed | 1264 | static void ioapic_register_intr(int irq, int vector, unsigned long trigger) |
1da177e4 | 1265 | { |
08678b08 YL |
1266 | struct irq_desc *desc; |
1267 | ||
1268 | desc = irq_to_desc(irq); | |
6ebcc00e | 1269 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
cc75b92d | 1270 | trigger == IOAPIC_LEVEL) { |
08678b08 | 1271 | desc->status |= IRQ_LEVEL; |
a460e745 IM |
1272 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
1273 | handle_fasteoi_irq, "fasteoi"); | |
cc75b92d | 1274 | } else { |
08678b08 | 1275 | desc->status &= ~IRQ_LEVEL; |
a460e745 IM |
1276 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
1277 | handle_edge_irq, "edge"); | |
cc75b92d | 1278 | } |
ace80ab7 | 1279 | set_intr_gate(vector, interrupt[irq]); |
1da177e4 LT |
1280 | } |
1281 | ||
1282 | static void __init setup_IO_APIC_irqs(void) | |
1283 | { | |
1284 | struct IO_APIC_route_entry entry; | |
1285 | int apic, pin, idx, irq, first_notcon = 1, vector; | |
1da177e4 LT |
1286 | |
1287 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1288 | ||
1289 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1290 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1291 | ||
1292 | /* | |
1293 | * add it to the IO-APIC irq-routing table: | |
1294 | */ | |
36062448 | 1295 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1296 | |
1297 | entry.delivery_mode = INT_DELIVERY_MODE; | |
1298 | entry.dest_mode = INT_DEST_MODE; | |
1299 | entry.mask = 0; /* enable IRQ */ | |
36062448 | 1300 | entry.dest.logical.logical_dest = |
1da177e4 LT |
1301 | cpu_mask_to_apicid(TARGET_CPUS); |
1302 | ||
36062448 | 1303 | idx = find_irq_entry(apic, pin, mp_INT); |
1da177e4 LT |
1304 | if (idx == -1) { |
1305 | if (first_notcon) { | |
1306 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1307 | " IO-APIC (apicid-pin) %d-%d", | |
ec2cd0a2 | 1308 | mp_ioapics[apic].mp_apicid, |
1da177e4 LT |
1309 | pin); |
1310 | first_notcon = 0; | |
1311 | } else | |
1312 | apic_printk(APIC_VERBOSE, ", %d-%d", | |
ec2cd0a2 | 1313 | mp_ioapics[apic].mp_apicid, pin); |
1da177e4 LT |
1314 | continue; |
1315 | } | |
1316 | ||
20d225b9 YL |
1317 | if (!first_notcon) { |
1318 | apic_printk(APIC_VERBOSE, " not connected.\n"); | |
1319 | first_notcon = 1; | |
1320 | } | |
1321 | ||
1da177e4 LT |
1322 | entry.trigger = irq_trigger(idx); |
1323 | entry.polarity = irq_polarity(idx); | |
1324 | ||
1325 | if (irq_trigger(idx)) { | |
1326 | entry.trigger = 1; | |
1327 | entry.mask = 1; | |
1328 | } | |
1329 | ||
1330 | irq = pin_2_irq(idx, apic, pin); | |
1331 | /* | |
1332 | * skip adding the timer int on secondary nodes, which causes | |
1333 | * a small but painful rift in the time-space continuum | |
1334 | */ | |
1335 | if (multi_timer_check(apic, irq)) | |
1336 | continue; | |
1337 | else | |
1338 | add_pin_to_irq(irq, apic, pin); | |
1339 | ||
1340 | if (!apic && !IO_APIC_IRQ(irq)) | |
1341 | continue; | |
1342 | ||
1343 | if (IO_APIC_IRQ(irq)) { | |
1344 | vector = assign_irq_vector(irq); | |
1345 | entry.vector = vector; | |
1346 | ioapic_register_intr(irq, vector, IOAPIC_AUTO); | |
36062448 | 1347 | |
1da177e4 LT |
1348 | if (!apic && (irq < 16)) |
1349 | disable_8259A_irq(irq); | |
1350 | } | |
a2249cba | 1351 | ioapic_write_entry(apic, pin, entry); |
1da177e4 LT |
1352 | } |
1353 | } | |
1354 | ||
1355 | if (!first_notcon) | |
1356 | apic_printk(APIC_VERBOSE, " not connected.\n"); | |
1357 | } | |
1358 | ||
1359 | /* | |
f7633ce5 | 1360 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1361 | */ |
f7633ce5 MR |
1362 | static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin, |
1363 | int vector) | |
1da177e4 LT |
1364 | { |
1365 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1366 | |
36062448 | 1367 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1368 | |
1369 | /* | |
1370 | * We use logical delivery to get the timer IRQ | |
1371 | * to the first CPU. | |
1372 | */ | |
1373 | entry.dest_mode = INT_DEST_MODE; | |
03be7505 | 1374 | entry.mask = 1; /* mask IRQ now */ |
1da177e4 LT |
1375 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); |
1376 | entry.delivery_mode = INT_DELIVERY_MODE; | |
1377 | entry.polarity = 0; | |
1378 | entry.trigger = 0; | |
1379 | entry.vector = vector; | |
1380 | ||
1381 | /* | |
1382 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1383 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1384 | */ |
f0825262 | 1385 | ioapic_register_intr(0, vector, IOAPIC_EDGE); |
1da177e4 LT |
1386 | |
1387 | /* | |
1388 | * Add it to the IO-APIC irq-routing table: | |
1389 | */ | |
cf4c6a2f | 1390 | ioapic_write_entry(apic, pin, entry); |
1da177e4 LT |
1391 | } |
1392 | ||
32f71aff MR |
1393 | |
1394 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1395 | { |
1396 | int apic, i; | |
1397 | union IO_APIC_reg_00 reg_00; | |
1398 | union IO_APIC_reg_01 reg_01; | |
1399 | union IO_APIC_reg_02 reg_02; | |
1400 | union IO_APIC_reg_03 reg_03; | |
1401 | unsigned long flags; | |
1402 | ||
1403 | if (apic_verbosity == APIC_QUIET) | |
1404 | return; | |
1405 | ||
36062448 | 1406 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1407 | for (i = 0; i < nr_ioapics; i++) |
1408 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
ec2cd0a2 | 1409 | mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1410 | |
1411 | /* | |
1412 | * We are a bit conservative about what we expect. We have to | |
1413 | * know about every hardware change ASAP. | |
1414 | */ | |
1415 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1416 | ||
1417 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1418 | ||
1419 | spin_lock_irqsave(&ioapic_lock, flags); | |
1420 | reg_00.raw = io_apic_read(apic, 0); | |
1421 | reg_01.raw = io_apic_read(apic, 1); | |
1422 | if (reg_01.bits.version >= 0x10) | |
1423 | reg_02.raw = io_apic_read(apic, 2); | |
1424 | if (reg_01.bits.version >= 0x20) | |
1425 | reg_03.raw = io_apic_read(apic, 3); | |
1426 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1427 | ||
ec2cd0a2 | 1428 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1429 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1430 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1431 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1432 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 LT |
1433 | |
1434 | printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw); | |
1435 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); | |
1da177e4 LT |
1436 | |
1437 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1438 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1439 | |
1440 | /* | |
1441 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1442 | * but the value of reg_02 is read as the previous read register | |
1443 | * value, so ignore it if reg_02 == reg_01. | |
1444 | */ | |
1445 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1446 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1447 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1448 | } |
1449 | ||
1450 | /* | |
1451 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1452 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1453 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1454 | */ | |
1455 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1456 | reg_03.raw != reg_01.raw) { | |
1457 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1458 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1459 | } |
1460 | ||
1461 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1462 | ||
1463 | printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol" | |
1464 | " Stat Dest Deli Vect: \n"); | |
1465 | ||
1466 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1467 | struct IO_APIC_route_entry entry; | |
1468 | ||
cf4c6a2f | 1469 | entry = ioapic_read_entry(apic, i); |
1da177e4 LT |
1470 | |
1471 | printk(KERN_DEBUG " %02x %03X %02X ", | |
1472 | i, | |
1473 | entry.dest.logical.logical_dest, | |
1474 | entry.dest.physical.physical_dest | |
1475 | ); | |
1476 | ||
1477 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1478 | entry.mask, | |
1479 | entry.trigger, | |
1480 | entry.irr, | |
1481 | entry.polarity, | |
1482 | entry.delivery_status, | |
1483 | entry.dest_mode, | |
1484 | entry.delivery_mode, | |
1485 | entry.vector | |
1486 | ); | |
1487 | } | |
1488 | } | |
1da177e4 | 1489 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
0799e432 | 1490 | for (i = 0; i < nr_irqs; i++) { |
1da177e4 LT |
1491 | struct irq_pin_list *entry = irq_2_pin + i; |
1492 | if (entry->pin < 0) | |
1493 | continue; | |
ace80ab7 | 1494 | printk(KERN_DEBUG "IRQ%d ", i); |
1da177e4 LT |
1495 | for (;;) { |
1496 | printk("-> %d:%d", entry->apic, entry->pin); | |
1497 | if (!entry->next) | |
1498 | break; | |
1499 | entry = irq_2_pin + entry->next; | |
1500 | } | |
1501 | printk("\n"); | |
1502 | } | |
1503 | ||
1504 | printk(KERN_INFO ".................................... done.\n"); | |
1505 | ||
1506 | return; | |
1507 | } | |
1508 | ||
32f71aff | 1509 | __apicdebuginit(void) print_APIC_bitfield(int base) |
1da177e4 LT |
1510 | { |
1511 | unsigned int v; | |
1512 | int i, j; | |
1513 | ||
1514 | if (apic_verbosity == APIC_QUIET) | |
1515 | return; | |
1516 | ||
1517 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); | |
1518 | for (i = 0; i < 8; i++) { | |
1519 | v = apic_read(base + i*0x10); | |
1520 | for (j = 0; j < 32; j++) { | |
1521 | if (v & (1<<j)) | |
1522 | printk("1"); | |
1523 | else | |
1524 | printk("0"); | |
1525 | } | |
1526 | printk("\n"); | |
1527 | } | |
1528 | } | |
1529 | ||
32f71aff | 1530 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 LT |
1531 | { |
1532 | unsigned int v, ver, maxlvt; | |
7ab6af7a | 1533 | u64 icr; |
1da177e4 LT |
1534 | |
1535 | if (apic_verbosity == APIC_QUIET) | |
1536 | return; | |
1537 | ||
1538 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", | |
1539 | smp_processor_id(), hard_smp_processor_id()); | |
66823114 | 1540 | v = apic_read(APIC_ID); |
05f2d12c | 1541 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, |
4c9961d5 | 1542 | GET_APIC_ID(v)); |
1da177e4 LT |
1543 | v = apic_read(APIC_LVR); |
1544 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1545 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1546 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1547 | |
1548 | v = apic_read(APIC_TASKPRI); | |
1549 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1550 | ||
1551 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ | |
1552 | v = apic_read(APIC_ARBPRI); | |
1553 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1554 | v & APIC_ARBPRI_MASK); | |
1555 | v = apic_read(APIC_PROCPRI); | |
1556 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1557 | } | |
1558 | ||
1559 | v = apic_read(APIC_EOI); | |
1560 | printk(KERN_DEBUG "... APIC EOI: %08x\n", v); | |
1561 | v = apic_read(APIC_RRR); | |
1562 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1563 | v = apic_read(APIC_LDR); | |
1564 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
1565 | v = apic_read(APIC_DFR); | |
1566 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1567 | v = apic_read(APIC_SPIV); | |
1568 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1569 | ||
1570 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
1571 | print_APIC_bitfield(APIC_ISR); | |
1572 | printk(KERN_DEBUG "... APIC TMR field:\n"); | |
1573 | print_APIC_bitfield(APIC_TMR); | |
1574 | printk(KERN_DEBUG "... APIC IRR field:\n"); | |
1575 | print_APIC_bitfield(APIC_IRR); | |
1576 | ||
1577 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ | |
1578 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1579 | apic_write(APIC_ESR, 0); | |
1580 | v = apic_read(APIC_ESR); | |
1581 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1582 | } | |
1583 | ||
7ab6af7a HS |
1584 | icr = apic_icr_read(); |
1585 | printk(KERN_DEBUG "... APIC ICR: %08x\n", icr); | |
1586 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", icr >> 32); | |
1da177e4 LT |
1587 | |
1588 | v = apic_read(APIC_LVTT); | |
1589 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1590 | ||
1591 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1592 | v = apic_read(APIC_LVTPC); | |
1593 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1594 | } | |
1595 | v = apic_read(APIC_LVT0); | |
1596 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1597 | v = apic_read(APIC_LVT1); | |
1598 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1599 | ||
1600 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1601 | v = apic_read(APIC_LVTERR); | |
1602 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1603 | } | |
1604 | ||
1605 | v = apic_read(APIC_TMICT); | |
1606 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1607 | v = apic_read(APIC_TMCCT); | |
1608 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1609 | v = apic_read(APIC_TDCR); | |
1610 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
1611 | printk("\n"); | |
1612 | } | |
1613 | ||
32f71aff | 1614 | __apicdebuginit(void) print_all_local_APICs(void) |
1da177e4 | 1615 | { |
15c8b6c1 | 1616 | on_each_cpu(print_local_APIC, NULL, 1); |
1da177e4 LT |
1617 | } |
1618 | ||
32f71aff | 1619 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1620 | { |
1da177e4 LT |
1621 | unsigned int v; |
1622 | unsigned long flags; | |
1623 | ||
1624 | if (apic_verbosity == APIC_QUIET) | |
1625 | return; | |
1626 | ||
1627 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1628 | ||
1629 | spin_lock_irqsave(&i8259A_lock, flags); | |
1630 | ||
1631 | v = inb(0xa1) << 8 | inb(0x21); | |
1632 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1633 | ||
1634 | v = inb(0xa0) << 8 | inb(0x20); | |
1635 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1636 | ||
36062448 PC |
1637 | outb(0x0b, 0xa0); |
1638 | outb(0x0b, 0x20); | |
1da177e4 | 1639 | v = inb(0xa0) << 8 | inb(0x20); |
36062448 PC |
1640 | outb(0x0a, 0xa0); |
1641 | outb(0x0a, 0x20); | |
1da177e4 LT |
1642 | |
1643 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1644 | ||
1645 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1646 | ||
1647 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1648 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1649 | } | |
1650 | ||
32f71aff MR |
1651 | __apicdebuginit(int) print_all_ICs(void) |
1652 | { | |
1653 | print_PIC(); | |
1654 | print_all_local_APICs(); | |
1655 | print_IO_APIC(); | |
1656 | ||
1657 | return 0; | |
1658 | } | |
1659 | ||
1660 | fs_initcall(print_all_ICs); | |
1661 | ||
1da177e4 LT |
1662 | |
1663 | static void __init enable_IO_APIC(void) | |
1664 | { | |
1665 | union IO_APIC_reg_01 reg_01; | |
fcfd636a EB |
1666 | int i8259_apic, i8259_pin; |
1667 | int i, apic; | |
1da177e4 LT |
1668 | unsigned long flags; |
1669 | ||
0799e432 | 1670 | for (i = 0; i < pin_map_size; i++) { |
1da177e4 LT |
1671 | irq_2_pin[i].pin = -1; |
1672 | irq_2_pin[i].next = 0; | |
1673 | } | |
1674 | if (!pirqs_enabled) | |
1675 | for (i = 0; i < MAX_PIRQS; i++) | |
1676 | pirq_entries[i] = -1; | |
1677 | ||
1678 | /* | |
1679 | * The number of IO-APIC IRQ registers (== #pins): | |
1680 | */ | |
fcfd636a | 1681 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 1682 | spin_lock_irqsave(&ioapic_lock, flags); |
fcfd636a | 1683 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 1684 | spin_unlock_irqrestore(&ioapic_lock, flags); |
fcfd636a EB |
1685 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
1686 | } | |
36062448 | 1687 | for (apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1688 | int pin; |
1689 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1690 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1691 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1692 | entry = ioapic_read_entry(apic, pin); |
fcfd636a EB |
1693 | |
1694 | ||
1695 | /* If the interrupt line is enabled and in ExtInt mode | |
1696 | * I have found the pin where the i8259 is connected. | |
1697 | */ | |
1698 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1699 | ioapic_i8259.apic = apic; | |
1700 | ioapic_i8259.pin = pin; | |
1701 | goto found_i8259; | |
1702 | } | |
1703 | } | |
1704 | } | |
1705 | found_i8259: | |
1706 | /* Look to see what if the MP table has reported the ExtINT */ | |
1707 | /* If we could not find the appropriate pin by looking at the ioapic | |
1708 | * the i8259 probably is not connected the ioapic but give the | |
1709 | * mptable a chance anyway. | |
1710 | */ | |
1711 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1712 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1713 | /* Trust the MP table if nothing is setup in the hardware */ | |
1714 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1715 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1716 | ioapic_i8259.pin = i8259_pin; | |
1717 | ioapic_i8259.apic = i8259_apic; | |
1718 | } | |
1719 | /* Complain if the MP table and the hardware disagree */ | |
1720 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1721 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1722 | { | |
1723 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1724 | } |
1725 | ||
1726 | /* | |
1727 | * Do not trust the IO-APIC being empty at bootup | |
1728 | */ | |
1729 | clear_IO_APIC(); | |
1730 | } | |
1731 | ||
1732 | /* | |
1733 | * Not an __init, needed by the reboot code | |
1734 | */ | |
1735 | void disable_IO_APIC(void) | |
1736 | { | |
1737 | /* | |
1738 | * Clear the IO-APIC before rebooting: | |
1739 | */ | |
1740 | clear_IO_APIC(); | |
1741 | ||
650927ef | 1742 | /* |
0b968d23 | 1743 | * If the i8259 is routed through an IOAPIC |
650927ef | 1744 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1745 | * so legacy interrupts can be delivered. |
650927ef | 1746 | */ |
fcfd636a | 1747 | if (ioapic_i8259.pin != -1) { |
650927ef | 1748 | struct IO_APIC_route_entry entry; |
650927ef EB |
1749 | |
1750 | memset(&entry, 0, sizeof(entry)); | |
1751 | entry.mask = 0; /* Enabled */ | |
1752 | entry.trigger = 0; /* Edge */ | |
1753 | entry.irr = 0; | |
1754 | entry.polarity = 0; /* High */ | |
1755 | entry.delivery_status = 0; | |
1756 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1757 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1758 | entry.vector = 0; |
4c9961d5 | 1759 | entry.dest.physical.physical_dest = read_apic_id(); |
650927ef EB |
1760 | |
1761 | /* | |
1762 | * Add it to the IO-APIC irq-routing table: | |
1763 | */ | |
cf4c6a2f | 1764 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1765 | } |
fcfd636a | 1766 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); |
1da177e4 LT |
1767 | } |
1768 | ||
1769 | /* | |
1770 | * function to set the IO-APIC physical IDs based on the | |
1771 | * values stored in the MPC table. | |
1772 | * | |
1773 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
1774 | */ | |
1775 | ||
1da177e4 LT |
1776 | static void __init setup_ioapic_ids_from_mpc(void) |
1777 | { | |
1778 | union IO_APIC_reg_00 reg_00; | |
1779 | physid_mask_t phys_id_present_map; | |
1780 | int apic; | |
1781 | int i; | |
1782 | unsigned char old_id; | |
1783 | unsigned long flags; | |
1784 | ||
a4dbc34d | 1785 | if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids()) |
d49c4288 | 1786 | return; |
d49c4288 | 1787 | |
ca05fea6 NP |
1788 | /* |
1789 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
1790 | * no meaning without the serial APIC bus. | |
1791 | */ | |
7c5c1e42 SL |
1792 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
1793 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 1794 | return; |
1da177e4 LT |
1795 | /* |
1796 | * This is broken; anything with a real cpu count has to | |
1797 | * circumvent this idiocy regardless. | |
1798 | */ | |
1799 | phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map); | |
1800 | ||
1801 | /* | |
1802 | * Set the IOAPIC ID to the value stored in the MPC table. | |
1803 | */ | |
1804 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1805 | ||
1806 | /* Read the register 0 value */ | |
1807 | spin_lock_irqsave(&ioapic_lock, flags); | |
1808 | reg_00.raw = io_apic_read(apic, 0); | |
1809 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
36062448 | 1810 | |
ec2cd0a2 | 1811 | old_id = mp_ioapics[apic].mp_apicid; |
1da177e4 | 1812 | |
ec2cd0a2 | 1813 | if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) { |
1da177e4 | 1814 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
ec2cd0a2 | 1815 | apic, mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1816 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
1817 | reg_00.bits.ID); | |
ec2cd0a2 | 1818 | mp_ioapics[apic].mp_apicid = reg_00.bits.ID; |
1da177e4 LT |
1819 | } |
1820 | ||
1da177e4 LT |
1821 | /* |
1822 | * Sanity check, is the ID really free? Every APIC in a | |
1823 | * system must have a unique ID or we get lots of nice | |
1824 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
1825 | */ | |
1826 | if (check_apicid_used(phys_id_present_map, | |
ec2cd0a2 | 1827 | mp_ioapics[apic].mp_apicid)) { |
1da177e4 | 1828 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
ec2cd0a2 | 1829 | apic, mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1830 | for (i = 0; i < get_physical_broadcast(); i++) |
1831 | if (!physid_isset(i, phys_id_present_map)) | |
1832 | break; | |
1833 | if (i >= get_physical_broadcast()) | |
1834 | panic("Max APIC ID exceeded!\n"); | |
1835 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
1836 | i); | |
1837 | physid_set(i, phys_id_present_map); | |
ec2cd0a2 | 1838 | mp_ioapics[apic].mp_apicid = i; |
1da177e4 LT |
1839 | } else { |
1840 | physid_mask_t tmp; | |
ec2cd0a2 | 1841 | tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1842 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
1843 | "phys_id_present_map\n", | |
ec2cd0a2 | 1844 | mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1845 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
1846 | } | |
1847 | ||
1848 | ||
1849 | /* | |
1850 | * We need to adjust the IRQ routing table | |
1851 | * if the ID changed. | |
1852 | */ | |
ec2cd0a2 | 1853 | if (old_id != mp_ioapics[apic].mp_apicid) |
1da177e4 | 1854 | for (i = 0; i < mp_irq_entries; i++) |
2fddb6e2 AS |
1855 | if (mp_irqs[i].mp_dstapic == old_id) |
1856 | mp_irqs[i].mp_dstapic | |
ec2cd0a2 | 1857 | = mp_ioapics[apic].mp_apicid; |
1da177e4 LT |
1858 | |
1859 | /* | |
1860 | * Read the right value from the MPC table and | |
1861 | * write it into the ID register. | |
36062448 | 1862 | */ |
1da177e4 LT |
1863 | apic_printk(APIC_VERBOSE, KERN_INFO |
1864 | "...changing IO-APIC physical APIC ID to %d ...", | |
ec2cd0a2 | 1865 | mp_ioapics[apic].mp_apicid); |
1da177e4 | 1866 | |
ec2cd0a2 | 1867 | reg_00.bits.ID = mp_ioapics[apic].mp_apicid; |
1da177e4 LT |
1868 | spin_lock_irqsave(&ioapic_lock, flags); |
1869 | io_apic_write(apic, 0, reg_00.raw); | |
1870 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1871 | ||
1872 | /* | |
1873 | * Sanity check | |
1874 | */ | |
1875 | spin_lock_irqsave(&ioapic_lock, flags); | |
1876 | reg_00.raw = io_apic_read(apic, 0); | |
1877 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
ec2cd0a2 | 1878 | if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid) |
1da177e4 LT |
1879 | printk("could not set ID!\n"); |
1880 | else | |
1881 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
1882 | } | |
1883 | } | |
1da177e4 | 1884 | |
7ce0bcfd | 1885 | int no_timer_check __initdata; |
8542b200 ZA |
1886 | |
1887 | static int __init notimercheck(char *s) | |
1888 | { | |
1889 | no_timer_check = 1; | |
1890 | return 1; | |
1891 | } | |
1892 | __setup("no_timer_check", notimercheck); | |
1893 | ||
1da177e4 LT |
1894 | /* |
1895 | * There is a nasty bug in some older SMP boards, their mptable lies | |
1896 | * about the timer IRQ. We do the following to work around the situation: | |
1897 | * | |
1898 | * - timer IRQ defaults to IO-APIC IRQ | |
1899 | * - if this function detects that timer IRQs are defunct, then we fall | |
1900 | * back to ISA timer IRQs | |
1901 | */ | |
f0a7a5c9 | 1902 | static int __init timer_irq_works(void) |
1da177e4 LT |
1903 | { |
1904 | unsigned long t1 = jiffies; | |
4aae0702 | 1905 | unsigned long flags; |
1da177e4 | 1906 | |
8542b200 ZA |
1907 | if (no_timer_check) |
1908 | return 1; | |
1909 | ||
4aae0702 | 1910 | local_save_flags(flags); |
1da177e4 LT |
1911 | local_irq_enable(); |
1912 | /* Let ten ticks pass... */ | |
1913 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 1914 | local_irq_restore(flags); |
1da177e4 LT |
1915 | |
1916 | /* | |
1917 | * Expect a few ticks at least, to be sure some possible | |
1918 | * glue logic does not lock up after one or two first | |
1919 | * ticks in a non-ExtINT mode. Also the local APIC | |
1920 | * might have cached one ExtINT interrupt. Finally, at | |
1921 | * least one tick may be lost due to delays. | |
1922 | */ | |
1d16b53e | 1923 | if (time_after(jiffies, t1 + 4)) |
1da177e4 LT |
1924 | return 1; |
1925 | ||
1926 | return 0; | |
1927 | } | |
1928 | ||
1929 | /* | |
1930 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
1931 | * number of pending IRQ events unhandled. These cases are very rare, | |
1932 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
1933 | * better to do it this way as thus we do not have to be aware of | |
1934 | * 'pending' interrupts in the IRQ path, except at this point. | |
1935 | */ | |
1936 | /* | |
1937 | * Edge triggered needs to resend any interrupt | |
1938 | * that was delayed but this is now handled in the device | |
1939 | * independent code. | |
1940 | */ | |
1941 | ||
1942 | /* | |
f5b9ed7a IM |
1943 | * Startup quirk: |
1944 | * | |
1da177e4 LT |
1945 | * Starting up a edge-triggered IO-APIC interrupt is |
1946 | * nasty - we need to make sure that we get the edge. | |
1947 | * If it is already asserted for some reason, we need | |
1948 | * return 1 to indicate that is was pending. | |
1949 | * | |
1950 | * This is not complete - we should be able to fake | |
1951 | * an edge even if it isn't on the 8259A... | |
f5b9ed7a IM |
1952 | * |
1953 | * (We do this for level-triggered IRQs too - it cannot hurt.) | |
1da177e4 | 1954 | */ |
f5b9ed7a | 1955 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
1956 | { |
1957 | int was_pending = 0; | |
1958 | unsigned long flags; | |
1959 | ||
1960 | spin_lock_irqsave(&ioapic_lock, flags); | |
1961 | if (irq < 16) { | |
1962 | disable_8259A_irq(irq); | |
1963 | if (i8259A_irq_pending(irq)) | |
1964 | was_pending = 1; | |
1965 | } | |
1966 | __unmask_IO_APIC_irq(irq); | |
1967 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1968 | ||
1969 | return was_pending; | |
1970 | } | |
1971 | ||
f5b9ed7a | 1972 | static void ack_ioapic_irq(unsigned int irq) |
1da177e4 | 1973 | { |
ace80ab7 | 1974 | move_native_irq(irq); |
1da177e4 LT |
1975 | ack_APIC_irq(); |
1976 | } | |
1977 | ||
f5b9ed7a | 1978 | static void ack_ioapic_quirk_irq(unsigned int irq) |
1da177e4 LT |
1979 | { |
1980 | unsigned long v; | |
1981 | int i; | |
1982 | ||
ace80ab7 | 1983 | move_native_irq(irq); |
1da177e4 LT |
1984 | /* |
1985 | * It appears there is an erratum which affects at least version 0x11 | |
1986 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
1987 | * chipsets). Under certain conditions a level-triggered interrupt is | |
1988 | * erroneously delivered as edge-triggered one but the respective IRR | |
1989 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
1990 | * message but it will never arrive and further interrupts are blocked | |
1991 | * from the source. The exact reason is so far unknown, but the | |
1992 | * phenomenon was observed when two consecutive interrupt requests | |
1993 | * from a given source get delivered to the same CPU and the source is | |
1994 | * temporarily disabled in between. | |
1995 | * | |
1996 | * A workaround is to simulate an EOI message manually. We achieve it | |
1997 | * by setting the trigger mode to edge and then to level when the edge | |
1998 | * trigger mode gets detected in the TMR of a local APIC for a | |
1999 | * level-triggered interrupt. We mask the source for the time of the | |
2000 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2001 | * The idea is from Manfred Spraul. --macro | |
2002 | */ | |
b940d22d | 2003 | i = irq_vector[irq]; |
1da177e4 LT |
2004 | |
2005 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); | |
2006 | ||
2007 | ack_APIC_irq(); | |
2008 | ||
2009 | if (!(v & (1 << (i & 0x1f)))) { | |
2010 | atomic_inc(&irq_mis_count); | |
2011 | spin_lock(&ioapic_lock); | |
2012 | __mask_and_edge_IO_APIC_irq(irq); | |
2013 | __unmask_and_level_IO_APIC_irq(irq); | |
2014 | spin_unlock(&ioapic_lock); | |
2015 | } | |
2016 | } | |
2017 | ||
ace80ab7 | 2018 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 2019 | { |
b940d22d | 2020 | send_IPI_self(irq_vector[irq]); |
c0ad90a3 IM |
2021 | |
2022 | return 1; | |
2023 | } | |
2024 | ||
f5b9ed7a IM |
2025 | static struct irq_chip ioapic_chip __read_mostly = { |
2026 | .name = "IO-APIC", | |
ace80ab7 EB |
2027 | .startup = startup_ioapic_irq, |
2028 | .mask = mask_IO_APIC_irq, | |
2029 | .unmask = unmask_IO_APIC_irq, | |
2030 | .ack = ack_ioapic_irq, | |
2031 | .eoi = ack_ioapic_quirk_irq, | |
54d5d424 | 2032 | #ifdef CONFIG_SMP |
ace80ab7 | 2033 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2034 | #endif |
ace80ab7 | 2035 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2036 | }; |
2037 | ||
1da177e4 LT |
2038 | |
2039 | static inline void init_IO_APIC_traps(void) | |
2040 | { | |
2041 | int irq; | |
08678b08 | 2042 | struct irq_desc *desc; |
1da177e4 LT |
2043 | |
2044 | /* | |
2045 | * NOTE! The local APIC isn't very good at handling | |
2046 | * multiple interrupts at the same interrupt level. | |
2047 | * As the interrupt level is determined by taking the | |
2048 | * vector number and shifting that right by 4, we | |
2049 | * want to spread these out a bit so that they don't | |
2050 | * all fall in the same interrupt level. | |
2051 | * | |
2052 | * Also, we've got to be careful not to trash gate | |
2053 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2054 | */ | |
0799e432 | 2055 | for (irq = 0; irq < nr_irqs ; irq++) { |
addfc66b | 2056 | if (IO_APIC_IRQ(irq) && !irq_vector[irq]) { |
1da177e4 LT |
2057 | /* |
2058 | * Hmm.. We don't have an entry for this, | |
2059 | * so default to an old-fashioned 8259 | |
2060 | * interrupt if we can.. | |
2061 | */ | |
2062 | if (irq < 16) | |
2063 | make_8259A_irq(irq); | |
08678b08 YL |
2064 | else { |
2065 | desc = irq_to_desc(irq); | |
1da177e4 | 2066 | /* Strange. Oh, well.. */ |
08678b08 YL |
2067 | desc->chip = &no_irq_chip; |
2068 | } | |
1da177e4 LT |
2069 | } |
2070 | } | |
2071 | } | |
2072 | ||
f5b9ed7a IM |
2073 | /* |
2074 | * The local APIC irq-chip implementation: | |
2075 | */ | |
1da177e4 | 2076 | |
c88ac1df | 2077 | static void ack_lapic_irq(unsigned int irq) |
f5b9ed7a IM |
2078 | { |
2079 | ack_APIC_irq(); | |
1da177e4 LT |
2080 | } |
2081 | ||
36062448 | 2082 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
2083 | { |
2084 | unsigned long v; | |
2085 | ||
2086 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2087 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2088 | } |
2089 | ||
36062448 | 2090 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 | 2091 | { |
f5b9ed7a | 2092 | unsigned long v; |
1da177e4 | 2093 | |
f5b9ed7a | 2094 | v = apic_read(APIC_LVT0); |
593f4a78 | 2095 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2096 | } |
1da177e4 | 2097 | |
f5b9ed7a | 2098 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2099 | .name = "local-APIC", |
f5b9ed7a IM |
2100 | .mask = mask_lapic_irq, |
2101 | .unmask = unmask_lapic_irq, | |
c88ac1df | 2102 | .ack = ack_lapic_irq, |
1da177e4 LT |
2103 | }; |
2104 | ||
c88ac1df MR |
2105 | static void lapic_register_intr(int irq, int vector) |
2106 | { | |
08678b08 YL |
2107 | struct irq_desc *desc; |
2108 | ||
2109 | desc = irq_to_desc(irq); | |
2110 | desc->status &= ~IRQ_LEVEL; | |
c88ac1df MR |
2111 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
2112 | "edge"); | |
2113 | set_intr_gate(vector, interrupt[irq]); | |
2114 | } | |
2115 | ||
e9427101 | 2116 | static void __init setup_nmi(void) |
1da177e4 LT |
2117 | { |
2118 | /* | |
36062448 | 2119 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
2120 | * We put the 8259A master into AEOI mode and |
2121 | * unmask on all local APICs LVT0 as NMI. | |
2122 | * | |
2123 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2124 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2125 | * the NMI handler or the timer interrupt. | |
36062448 | 2126 | */ |
1da177e4 LT |
2127 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
2128 | ||
e9427101 | 2129 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2130 | |
2131 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2132 | } | |
2133 | ||
2134 | /* | |
2135 | * This looks a bit hackish but it's about the only one way of sending | |
2136 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2137 | * not support the ExtINT mode, unfortunately. We need to send these | |
2138 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2139 | * 8259A interrupt line asserted until INTA. --macro | |
2140 | */ | |
28acf285 | 2141 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2142 | { |
fcfd636a | 2143 | int apic, pin, i; |
1da177e4 LT |
2144 | struct IO_APIC_route_entry entry0, entry1; |
2145 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2146 | |
fcfd636a | 2147 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2148 | if (pin == -1) { |
2149 | WARN_ON_ONCE(1); | |
2150 | return; | |
2151 | } | |
fcfd636a | 2152 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2153 | if (apic == -1) { |
2154 | WARN_ON_ONCE(1); | |
1da177e4 | 2155 | return; |
956fb531 | 2156 | } |
1da177e4 | 2157 | |
cf4c6a2f | 2158 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2159 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2160 | |
2161 | memset(&entry1, 0, sizeof(entry1)); | |
2162 | ||
2163 | entry1.dest_mode = 0; /* physical delivery */ | |
2164 | entry1.mask = 0; /* unmask IRQ now */ | |
2165 | entry1.dest.physical.physical_dest = hard_smp_processor_id(); | |
2166 | entry1.delivery_mode = dest_ExtINT; | |
2167 | entry1.polarity = entry0.polarity; | |
2168 | entry1.trigger = 0; | |
2169 | entry1.vector = 0; | |
2170 | ||
cf4c6a2f | 2171 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2172 | |
2173 | save_control = CMOS_READ(RTC_CONTROL); | |
2174 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2175 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2176 | RTC_FREQ_SELECT); | |
2177 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2178 | ||
2179 | i = 100; | |
2180 | while (i-- > 0) { | |
2181 | mdelay(10); | |
2182 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2183 | i -= 10; | |
2184 | } | |
2185 | ||
2186 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2187 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2188 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2189 | |
cf4c6a2f | 2190 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2191 | } |
2192 | ||
2193 | /* | |
2194 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2195 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2196 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2197 | * fanatically on his truly buggy board. | |
2198 | */ | |
8542b200 | 2199 | static inline void __init check_timer(void) |
1da177e4 | 2200 | { |
fcfd636a | 2201 | int apic1, pin1, apic2, pin2; |
691874fa | 2202 | int no_pin1 = 0; |
1da177e4 | 2203 | int vector; |
6e908947 | 2204 | unsigned int ver; |
4aae0702 IM |
2205 | unsigned long flags; |
2206 | ||
2207 | local_irq_save(flags); | |
d4d25dec | 2208 | |
6e908947 IM |
2209 | ver = apic_read(APIC_LVR); |
2210 | ver = GET_APIC_VERSION(ver); | |
2211 | ||
1da177e4 LT |
2212 | /* |
2213 | * get/set the timer IRQ vector: | |
2214 | */ | |
2215 | disable_8259A_irq(0); | |
2216 | vector = assign_irq_vector(0); | |
2217 | set_intr_gate(vector, interrupt[0]); | |
2218 | ||
2219 | /* | |
d11d5794 MR |
2220 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2221 | * wire has to be disabled in the local APIC. Also | |
2222 | * timer interrupts need to be acknowledged manually in | |
2223 | * the 8259A for the i82489DX when using the NMI | |
2224 | * watchdog as that APIC treats NMIs as level-triggered. | |
2225 | * The AEOI mode will finish them in the 8259A | |
2226 | * automatically. | |
1da177e4 | 2227 | */ |
593f4a78 | 2228 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
1da177e4 | 2229 | init_8259A(1); |
d11d5794 | 2230 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); |
1da177e4 | 2231 | |
fcfd636a EB |
2232 | pin1 = find_isa_irq_pin(0, mp_INT); |
2233 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2234 | pin2 = ioapic_i8259.pin; | |
2235 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2236 | |
49a66a0b MR |
2237 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2238 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
2239 | vector, apic1, pin1, apic2, pin2); | |
1da177e4 | 2240 | |
691874fa MR |
2241 | /* |
2242 | * Some BIOS writers are clueless and report the ExtINTA | |
2243 | * I/O APIC input from the cascaded 8259A as the timer | |
2244 | * interrupt input. So just in case, if only one pin | |
2245 | * was found above, try it both directly and through the | |
2246 | * 8259A. | |
2247 | */ | |
2248 | if (pin1 == -1) { | |
2249 | pin1 = pin2; | |
2250 | apic1 = apic2; | |
2251 | no_pin1 = 1; | |
2252 | } else if (pin2 == -1) { | |
2253 | pin2 = pin1; | |
2254 | apic2 = apic1; | |
2255 | } | |
2256 | ||
1da177e4 LT |
2257 | if (pin1 != -1) { |
2258 | /* | |
2259 | * Ok, does IRQ0 through the IOAPIC work? | |
2260 | */ | |
691874fa MR |
2261 | if (no_pin1) { |
2262 | add_pin_to_irq(0, apic1, pin1); | |
2263 | setup_timer_IRQ0_pin(apic1, pin1, vector); | |
2264 | } | |
1da177e4 LT |
2265 | unmask_IO_APIC_irq(0); |
2266 | if (timer_irq_works()) { | |
2267 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 LT |
2268 | setup_nmi(); |
2269 | enable_8259A_irq(0); | |
1da177e4 | 2270 | } |
66759a01 CE |
2271 | if (disable_timer_pin_1 > 0) |
2272 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2273 | goto out; |
1da177e4 | 2274 | } |
fcfd636a | 2275 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2276 | if (!no_pin1) |
49a66a0b MR |
2277 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2278 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2279 | |
49a66a0b MR |
2280 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2281 | "(IRQ0) through the 8259A ...\n"); | |
2282 | apic_printk(APIC_QUIET, KERN_INFO | |
2283 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2284 | /* |
2285 | * legacy devices should be connected to IO APIC #0 | |
2286 | */ | |
691874fa | 2287 | replace_pin_at_irq(0, apic1, pin1, apic2, pin2); |
f7633ce5 | 2288 | setup_timer_IRQ0_pin(apic2, pin2, vector); |
24742ece | 2289 | unmask_IO_APIC_irq(0); |
ecd29476 | 2290 | enable_8259A_irq(0); |
1da177e4 | 2291 | if (timer_irq_works()) { |
49a66a0b | 2292 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 2293 | timer_through_8259 = 1; |
1da177e4 | 2294 | if (nmi_watchdog == NMI_IO_APIC) { |
60134ebe | 2295 | disable_8259A_irq(0); |
1da177e4 | 2296 | setup_nmi(); |
60134ebe | 2297 | enable_8259A_irq(0); |
1da177e4 | 2298 | } |
4aae0702 | 2299 | goto out; |
1da177e4 LT |
2300 | } |
2301 | /* | |
2302 | * Cleanup, just in case ... | |
2303 | */ | |
ecd29476 | 2304 | disable_8259A_irq(0); |
fcfd636a | 2305 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2306 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2307 | } |
1da177e4 LT |
2308 | |
2309 | if (nmi_watchdog == NMI_IO_APIC) { | |
49a66a0b MR |
2310 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
2311 | "through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 2312 | nmi_watchdog = NMI_NONE; |
1da177e4 | 2313 | } |
d11d5794 | 2314 | timer_ack = 0; |
1da177e4 | 2315 | |
49a66a0b MR |
2316 | apic_printk(APIC_QUIET, KERN_INFO |
2317 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2318 | |
c88ac1df | 2319 | lapic_register_intr(0, vector); |
593f4a78 | 2320 | apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */ |
1da177e4 LT |
2321 | enable_8259A_irq(0); |
2322 | ||
2323 | if (timer_irq_works()) { | |
49a66a0b | 2324 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2325 | goto out; |
1da177e4 | 2326 | } |
e67465f1 | 2327 | disable_8259A_irq(0); |
593f4a78 | 2328 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector); |
49a66a0b | 2329 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 2330 | |
49a66a0b MR |
2331 | apic_printk(APIC_QUIET, KERN_INFO |
2332 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 2333 | |
1da177e4 LT |
2334 | init_8259A(0); |
2335 | make_8259A_irq(0); | |
593f4a78 | 2336 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
2337 | |
2338 | unlock_ExtINT_logic(); | |
2339 | ||
2340 | if (timer_irq_works()) { | |
49a66a0b | 2341 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2342 | goto out; |
1da177e4 | 2343 | } |
49a66a0b | 2344 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 2345 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 2346 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
2347 | out: |
2348 | local_irq_restore(flags); | |
1da177e4 LT |
2349 | } |
2350 | ||
2351 | /* | |
af174783 MR |
2352 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
2353 | * to devices. However there may be an I/O APIC pin available for | |
2354 | * this interrupt regardless. The pin may be left unconnected, but | |
2355 | * typically it will be reused as an ExtINT cascade interrupt for | |
2356 | * the master 8259A. In the MPS case such a pin will normally be | |
2357 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
2358 | * there is no provision for ExtINT interrupts, and in the absence | |
2359 | * of an override it would be treated as an ordinary ISA I/O APIC | |
2360 | * interrupt, that is edge-triggered and unmasked by default. We | |
2361 | * used to do this, but it caused problems on some systems because | |
2362 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
2363 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
2364 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
2365 | * the I/O APIC in all cases now. No actual device should request | |
2366 | * it anyway. --macro | |
1da177e4 LT |
2367 | */ |
2368 | #define PIC_IRQS (1 << PIC_CASCADE_IR) | |
2369 | ||
2370 | void __init setup_IO_APIC(void) | |
2371 | { | |
dbeb2be2 RR |
2372 | int i; |
2373 | ||
2374 | /* Reserve all the system vectors. */ | |
305b92a2 | 2375 | for (i = first_system_vector; i < NR_VECTORS; i++) |
dbeb2be2 RR |
2376 | set_bit(i, used_vectors); |
2377 | ||
1da177e4 LT |
2378 | enable_IO_APIC(); |
2379 | ||
af174783 | 2380 | io_apic_irqs = ~PIC_IRQS; |
1da177e4 LT |
2381 | |
2382 | printk("ENABLING IO-APIC IRQs\n"); | |
2383 | ||
2384 | /* | |
2385 | * Set up IO-APIC IRQ routing. | |
2386 | */ | |
2387 | if (!acpi_ioapic) | |
2388 | setup_ioapic_ids_from_mpc(); | |
2389 | sync_Arb_IDs(); | |
2390 | setup_IO_APIC_irqs(); | |
2391 | init_IO_APIC_traps(); | |
1e4c85f9 | 2392 | check_timer(); |
1da177e4 LT |
2393 | } |
2394 | ||
2395 | /* | |
2396 | * Called after all the initialization is done. If we didnt find any | |
2397 | * APIC bugs then we can allow the modify fast path | |
2398 | */ | |
36062448 | 2399 | |
1da177e4 LT |
2400 | static int __init io_apic_bug_finalize(void) |
2401 | { | |
36062448 | 2402 | if (sis_apic_bug == -1) |
1da177e4 LT |
2403 | sis_apic_bug = 0; |
2404 | return 0; | |
2405 | } | |
2406 | ||
2407 | late_initcall(io_apic_bug_finalize); | |
2408 | ||
2409 | struct sysfs_ioapic_data { | |
2410 | struct sys_device dev; | |
2411 | struct IO_APIC_route_entry entry[0]; | |
2412 | }; | |
36062448 | 2413 | static struct sysfs_ioapic_data *mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 2414 | |
438510f6 | 2415 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
2416 | { |
2417 | struct IO_APIC_route_entry *entry; | |
2418 | struct sysfs_ioapic_data *data; | |
1da177e4 | 2419 | int i; |
36062448 | 2420 | |
1da177e4 LT |
2421 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
2422 | entry = data->entry; | |
36062448 | 2423 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 2424 | entry[i] = ioapic_read_entry(dev->id, i); |
1da177e4 LT |
2425 | |
2426 | return 0; | |
2427 | } | |
2428 | ||
2429 | static int ioapic_resume(struct sys_device *dev) | |
2430 | { | |
2431 | struct IO_APIC_route_entry *entry; | |
2432 | struct sysfs_ioapic_data *data; | |
2433 | unsigned long flags; | |
2434 | union IO_APIC_reg_00 reg_00; | |
2435 | int i; | |
36062448 | 2436 | |
1da177e4 LT |
2437 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
2438 | entry = data->entry; | |
2439 | ||
2440 | spin_lock_irqsave(&ioapic_lock, flags); | |
2441 | reg_00.raw = io_apic_read(dev->id, 0); | |
ec2cd0a2 AS |
2442 | if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) { |
2443 | reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid; | |
1da177e4 LT |
2444 | io_apic_write(dev->id, 0, reg_00.raw); |
2445 | } | |
1da177e4 | 2446 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 2447 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 2448 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
2449 | |
2450 | return 0; | |
2451 | } | |
2452 | ||
2453 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 2454 | .name = "ioapic", |
1da177e4 LT |
2455 | .suspend = ioapic_suspend, |
2456 | .resume = ioapic_resume, | |
2457 | }; | |
2458 | ||
2459 | static int __init ioapic_init_sysfs(void) | |
2460 | { | |
36062448 | 2461 | struct sys_device *dev; |
1da177e4 LT |
2462 | int i, size, error = 0; |
2463 | ||
2464 | error = sysdev_class_register(&ioapic_sysdev_class); | |
2465 | if (error) | |
2466 | return error; | |
2467 | ||
36062448 PC |
2468 | for (i = 0; i < nr_ioapics; i++) { |
2469 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] | |
1da177e4 | 2470 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 2471 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
2472 | if (!mp_ioapic_data[i]) { |
2473 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
2474 | continue; | |
2475 | } | |
1da177e4 | 2476 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 2477 | dev->id = i; |
1da177e4 LT |
2478 | dev->cls = &ioapic_sysdev_class; |
2479 | error = sysdev_register(dev); | |
2480 | if (error) { | |
2481 | kfree(mp_ioapic_data[i]); | |
2482 | mp_ioapic_data[i] = NULL; | |
2483 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
2484 | continue; | |
2485 | } | |
2486 | } | |
2487 | ||
2488 | return 0; | |
2489 | } | |
2490 | ||
2491 | device_initcall(ioapic_init_sysfs); | |
2492 | ||
3fc471ed | 2493 | /* |
95d77884 | 2494 | * Dynamic irq allocate and deallocation |
3fc471ed EB |
2495 | */ |
2496 | int create_irq(void) | |
2497 | { | |
ace80ab7 | 2498 | /* Allocate an unused irq */ |
306a22c2 | 2499 | int irq, new, vector = 0; |
3fc471ed | 2500 | unsigned long flags; |
3fc471ed | 2501 | |
ace80ab7 EB |
2502 | irq = -ENOSPC; |
2503 | spin_lock_irqsave(&vector_lock, flags); | |
0799e432 | 2504 | for (new = (nr_irqs - 1); new >= 0; new--) { |
ace80ab7 EB |
2505 | if (platform_legacy_irq(new)) |
2506 | continue; | |
2507 | if (irq_vector[new] != 0) | |
2508 | continue; | |
2509 | vector = __assign_irq_vector(new); | |
2510 | if (likely(vector > 0)) | |
2511 | irq = new; | |
2512 | break; | |
2513 | } | |
2514 | spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 2515 | |
ace80ab7 | 2516 | if (irq >= 0) { |
3fc471ed | 2517 | set_intr_gate(vector, interrupt[irq]); |
3fc471ed EB |
2518 | dynamic_irq_init(irq); |
2519 | } | |
2520 | return irq; | |
2521 | } | |
2522 | ||
2523 | void destroy_irq(unsigned int irq) | |
2524 | { | |
2525 | unsigned long flags; | |
3fc471ed EB |
2526 | |
2527 | dynamic_irq_cleanup(irq); | |
2528 | ||
2529 | spin_lock_irqsave(&vector_lock, flags); | |
9d9ad4b5 | 2530 | clear_bit(irq_vector[irq], used_vectors); |
3fc471ed EB |
2531 | irq_vector[irq] = 0; |
2532 | spin_unlock_irqrestore(&vector_lock, flags); | |
2533 | } | |
3fc471ed | 2534 | |
2d3fcc1c | 2535 | /* |
27b46d76 | 2536 | * MSI message composition |
2d3fcc1c EB |
2537 | */ |
2538 | #ifdef CONFIG_PCI_MSI | |
3b7d1921 | 2539 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
2d3fcc1c | 2540 | { |
2d3fcc1c EB |
2541 | int vector; |
2542 | unsigned dest; | |
2543 | ||
2544 | vector = assign_irq_vector(irq); | |
2545 | if (vector >= 0) { | |
2546 | dest = cpu_mask_to_apicid(TARGET_CPUS); | |
2547 | ||
2548 | msg->address_hi = MSI_ADDR_BASE_HI; | |
2549 | msg->address_lo = | |
2550 | MSI_ADDR_BASE_LO | | |
2551 | ((INT_DEST_MODE == 0) ? | |
36062448 | 2552 | MSI_ADDR_DEST_MODE_PHYSICAL: |
2d3fcc1c EB |
2553 | MSI_ADDR_DEST_MODE_LOGICAL) | |
2554 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
2555 | MSI_ADDR_REDIRECTION_CPU: | |
2556 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
2557 | MSI_ADDR_DEST_ID(dest); | |
2558 | ||
2559 | msg->data = | |
2560 | MSI_DATA_TRIGGER_EDGE | | |
2561 | MSI_DATA_LEVEL_ASSERT | | |
2562 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
36062448 | 2563 | MSI_DATA_DELIVERY_FIXED: |
2d3fcc1c EB |
2564 | MSI_DATA_DELIVERY_LOWPRI) | |
2565 | MSI_DATA_VECTOR(vector); | |
2566 | } | |
2567 | return vector; | |
2568 | } | |
2569 | ||
3b7d1921 EB |
2570 | #ifdef CONFIG_SMP |
2571 | static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask) | |
2d3fcc1c | 2572 | { |
3b7d1921 EB |
2573 | struct msi_msg msg; |
2574 | unsigned int dest; | |
2575 | cpumask_t tmp; | |
2d3fcc1c | 2576 | int vector; |
08678b08 | 2577 | struct irq_desc *desc; |
3b7d1921 EB |
2578 | |
2579 | cpus_and(tmp, mask, cpu_online_map); | |
2580 | if (cpus_empty(tmp)) | |
2581 | tmp = TARGET_CPUS; | |
2d3fcc1c EB |
2582 | |
2583 | vector = assign_irq_vector(irq); | |
3b7d1921 EB |
2584 | if (vector < 0) |
2585 | return; | |
2d3fcc1c | 2586 | |
3b7d1921 EB |
2587 | dest = cpu_mask_to_apicid(mask); |
2588 | ||
2589 | read_msi_msg(irq, &msg); | |
2590 | ||
2591 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
2592 | msg.data |= MSI_DATA_VECTOR(vector); | |
2593 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
2594 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
2595 | ||
2596 | write_msi_msg(irq, &msg); | |
08678b08 YL |
2597 | desc = irq_to_desc(irq); |
2598 | desc->affinity = mask; | |
2d3fcc1c | 2599 | } |
3b7d1921 | 2600 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 2601 | |
3b7d1921 EB |
2602 | /* |
2603 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
2604 | * which implement the MSI or MSI-X Capability Structure. | |
2605 | */ | |
2606 | static struct irq_chip msi_chip = { | |
2607 | .name = "PCI-MSI", | |
2608 | .unmask = unmask_msi_irq, | |
2609 | .mask = mask_msi_irq, | |
2610 | .ack = ack_ioapic_irq, | |
2611 | #ifdef CONFIG_SMP | |
2612 | .set_affinity = set_msi_irq_affinity, | |
2613 | #endif | |
2614 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
2615 | }; |
2616 | ||
f7feaca7 | 2617 | int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
3b7d1921 EB |
2618 | { |
2619 | struct msi_msg msg; | |
f7feaca7 EB |
2620 | int irq, ret; |
2621 | irq = create_irq(); | |
2622 | if (irq < 0) | |
2623 | return irq; | |
2624 | ||
3b7d1921 | 2625 | ret = msi_compose_msg(dev, irq, &msg); |
f7feaca7 EB |
2626 | if (ret < 0) { |
2627 | destroy_irq(irq); | |
3b7d1921 | 2628 | return ret; |
f7feaca7 | 2629 | } |
3b7d1921 | 2630 | |
7fe3730d | 2631 | set_irq_msi(irq, desc); |
3b7d1921 EB |
2632 | write_msi_msg(irq, &msg); |
2633 | ||
a460e745 IM |
2634 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, |
2635 | "edge"); | |
3b7d1921 | 2636 | |
7fe3730d | 2637 | return 0; |
3b7d1921 EB |
2638 | } |
2639 | ||
2640 | void arch_teardown_msi_irq(unsigned int irq) | |
2641 | { | |
f7feaca7 | 2642 | destroy_irq(irq); |
3b7d1921 EB |
2643 | } |
2644 | ||
2d3fcc1c EB |
2645 | #endif /* CONFIG_PCI_MSI */ |
2646 | ||
8b955b0d EB |
2647 | /* |
2648 | * Hypertransport interrupt support | |
2649 | */ | |
2650 | #ifdef CONFIG_HT_IRQ | |
2651 | ||
2652 | #ifdef CONFIG_SMP | |
2653 | ||
2654 | static void target_ht_irq(unsigned int irq, unsigned int dest) | |
2655 | { | |
ec68307c EB |
2656 | struct ht_irq_msg msg; |
2657 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 2658 | |
ec68307c EB |
2659 | msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK); |
2660 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); | |
8b955b0d | 2661 | |
ec68307c EB |
2662 | msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest); |
2663 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); | |
8b955b0d | 2664 | |
ec68307c | 2665 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
2666 | } |
2667 | ||
2668 | static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask) | |
2669 | { | |
2670 | unsigned int dest; | |
2671 | cpumask_t tmp; | |
08678b08 | 2672 | struct irq_desc *desc; |
8b955b0d EB |
2673 | |
2674 | cpus_and(tmp, mask, cpu_online_map); | |
2675 | if (cpus_empty(tmp)) | |
2676 | tmp = TARGET_CPUS; | |
2677 | ||
2678 | cpus_and(mask, tmp, CPU_MASK_ALL); | |
2679 | ||
2680 | dest = cpu_mask_to_apicid(mask); | |
2681 | ||
2682 | target_ht_irq(irq, dest); | |
08678b08 YL |
2683 | desc = irq_to_desc(irq); |
2684 | desc->affinity = mask; | |
8b955b0d EB |
2685 | } |
2686 | #endif | |
2687 | ||
c37e108d | 2688 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
2689 | .name = "PCI-HT", |
2690 | .mask = mask_ht_irq, | |
2691 | .unmask = unmask_ht_irq, | |
2692 | .ack = ack_ioapic_irq, | |
2693 | #ifdef CONFIG_SMP | |
2694 | .set_affinity = set_ht_irq_affinity, | |
2695 | #endif | |
2696 | .retrigger = ioapic_retrigger_irq, | |
2697 | }; | |
2698 | ||
2699 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
2700 | { | |
2701 | int vector; | |
2702 | ||
2703 | vector = assign_irq_vector(irq); | |
2704 | if (vector >= 0) { | |
ec68307c | 2705 | struct ht_irq_msg msg; |
8b955b0d EB |
2706 | unsigned dest; |
2707 | cpumask_t tmp; | |
2708 | ||
2709 | cpus_clear(tmp); | |
2710 | cpu_set(vector >> 8, tmp); | |
2711 | dest = cpu_mask_to_apicid(tmp); | |
2712 | ||
ec68307c | 2713 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 2714 | |
ec68307c EB |
2715 | msg.address_lo = |
2716 | HT_IRQ_LOW_BASE | | |
8b955b0d EB |
2717 | HT_IRQ_LOW_DEST_ID(dest) | |
2718 | HT_IRQ_LOW_VECTOR(vector) | | |
2719 | ((INT_DEST_MODE == 0) ? | |
2720 | HT_IRQ_LOW_DM_PHYSICAL : | |
2721 | HT_IRQ_LOW_DM_LOGICAL) | | |
2722 | HT_IRQ_LOW_RQEOI_EDGE | | |
2723 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
2724 | HT_IRQ_LOW_MT_FIXED : | |
2725 | HT_IRQ_LOW_MT_ARBITRATED) | | |
2726 | HT_IRQ_LOW_IRQ_MASKED; | |
2727 | ||
ec68307c | 2728 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 2729 | |
a460e745 IM |
2730 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
2731 | handle_edge_irq, "edge"); | |
8b955b0d EB |
2732 | } |
2733 | return vector; | |
2734 | } | |
2735 | #endif /* CONFIG_HT_IRQ */ | |
2736 | ||
1da177e4 | 2737 | /* -------------------------------------------------------------------------- |
36062448 | 2738 | ACPI-based IOAPIC Configuration |
1da177e4 LT |
2739 | -------------------------------------------------------------------------- */ |
2740 | ||
888ba6c6 | 2741 | #ifdef CONFIG_ACPI |
1da177e4 | 2742 | |
36062448 | 2743 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
2744 | { |
2745 | union IO_APIC_reg_00 reg_00; | |
2746 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
2747 | physid_mask_t tmp; | |
2748 | unsigned long flags; | |
2749 | int i = 0; | |
2750 | ||
2751 | /* | |
36062448 PC |
2752 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
2753 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 2754 | * supports up to 16 on one shared APIC bus. |
36062448 | 2755 | * |
1da177e4 LT |
2756 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
2757 | * advantage of new APIC bus architecture. | |
2758 | */ | |
2759 | ||
2760 | if (physids_empty(apic_id_map)) | |
2761 | apic_id_map = ioapic_phys_id_map(phys_cpu_present_map); | |
2762 | ||
2763 | spin_lock_irqsave(&ioapic_lock, flags); | |
2764 | reg_00.raw = io_apic_read(ioapic, 0); | |
2765 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2766 | ||
2767 | if (apic_id >= get_physical_broadcast()) { | |
2768 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
2769 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
2770 | apic_id = reg_00.bits.ID; | |
2771 | } | |
2772 | ||
2773 | /* | |
36062448 | 2774 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
2775 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
2776 | */ | |
2777 | if (check_apicid_used(apic_id_map, apic_id)) { | |
2778 | ||
2779 | for (i = 0; i < get_physical_broadcast(); i++) { | |
2780 | if (!check_apicid_used(apic_id_map, i)) | |
2781 | break; | |
2782 | } | |
2783 | ||
2784 | if (i == get_physical_broadcast()) | |
2785 | panic("Max apic_id exceeded!\n"); | |
2786 | ||
2787 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
2788 | "trying %d\n", ioapic, apic_id, i); | |
2789 | ||
2790 | apic_id = i; | |
36062448 | 2791 | } |
1da177e4 LT |
2792 | |
2793 | tmp = apicid_to_cpu_present(apic_id); | |
2794 | physids_or(apic_id_map, apic_id_map, tmp); | |
2795 | ||
2796 | if (reg_00.bits.ID != apic_id) { | |
2797 | reg_00.bits.ID = apic_id; | |
2798 | ||
2799 | spin_lock_irqsave(&ioapic_lock, flags); | |
2800 | io_apic_write(ioapic, 0, reg_00.raw); | |
2801 | reg_00.raw = io_apic_read(ioapic, 0); | |
2802 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2803 | ||
2804 | /* Sanity check */ | |
6070f9ec AD |
2805 | if (reg_00.bits.ID != apic_id) { |
2806 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
2807 | return -1; | |
2808 | } | |
1da177e4 LT |
2809 | } |
2810 | ||
2811 | apic_printk(APIC_VERBOSE, KERN_INFO | |
2812 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
2813 | ||
2814 | return apic_id; | |
2815 | } | |
2816 | ||
2817 | ||
36062448 | 2818 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
2819 | { |
2820 | union IO_APIC_reg_01 reg_01; | |
2821 | unsigned long flags; | |
2822 | ||
2823 | spin_lock_irqsave(&ioapic_lock, flags); | |
2824 | reg_01.raw = io_apic_read(ioapic, 1); | |
2825 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2826 | ||
2827 | return reg_01.bits.version; | |
2828 | } | |
2829 | ||
2830 | ||
36062448 | 2831 | int __init io_apic_get_redir_entries(int ioapic) |
1da177e4 LT |
2832 | { |
2833 | union IO_APIC_reg_01 reg_01; | |
2834 | unsigned long flags; | |
2835 | ||
2836 | spin_lock_irqsave(&ioapic_lock, flags); | |
2837 | reg_01.raw = io_apic_read(ioapic, 1); | |
2838 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2839 | ||
2840 | return reg_01.bits.entries; | |
2841 | } | |
2842 | ||
2843 | ||
36062448 | 2844 | int io_apic_set_pci_routing(int ioapic, int pin, int irq, int edge_level, int active_high_low) |
1da177e4 LT |
2845 | { |
2846 | struct IO_APIC_route_entry entry; | |
1da177e4 LT |
2847 | |
2848 | if (!IO_APIC_IRQ(irq)) { | |
2849 | printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
2850 | ioapic); | |
2851 | return -EINVAL; | |
2852 | } | |
2853 | ||
2854 | /* | |
2855 | * Generate a PCI IRQ routing entry and program the IOAPIC accordingly. | |
2856 | * Note that we mask (disable) IRQs now -- these get enabled when the | |
2857 | * corresponding device driver registers for this IRQ. | |
2858 | */ | |
2859 | ||
36062448 | 2860 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
2861 | |
2862 | entry.delivery_mode = INT_DELIVERY_MODE; | |
2863 | entry.dest_mode = INT_DEST_MODE; | |
2864 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); | |
2865 | entry.trigger = edge_level; | |
2866 | entry.polarity = active_high_low; | |
2867 | entry.mask = 1; | |
2868 | ||
2869 | /* | |
2870 | * IRQs < 16 are already in the irq_2_pin[] map | |
2871 | */ | |
2872 | if (irq >= 16) | |
2873 | add_pin_to_irq(irq, ioapic, pin); | |
2874 | ||
2875 | entry.vector = assign_irq_vector(irq); | |
2876 | ||
2877 | apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry " | |
2878 | "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic, | |
ec2cd0a2 | 2879 | mp_ioapics[ioapic].mp_apicid, pin, entry.vector, irq, |
1da177e4 LT |
2880 | edge_level, active_high_low); |
2881 | ||
2882 | ioapic_register_intr(irq, entry.vector, edge_level); | |
2883 | ||
2884 | if (!ioapic && (irq < 16)) | |
2885 | disable_8259A_irq(irq); | |
2886 | ||
a2249cba | 2887 | ioapic_write_entry(ioapic, pin, entry); |
1da177e4 LT |
2888 | |
2889 | return 0; | |
2890 | } | |
2891 | ||
61fd47e0 SL |
2892 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
2893 | { | |
2894 | int i; | |
2895 | ||
2896 | if (skip_ioapic_setup) | |
2897 | return -1; | |
2898 | ||
2899 | for (i = 0; i < mp_irq_entries; i++) | |
2fddb6e2 AS |
2900 | if (mp_irqs[i].mp_irqtype == mp_INT && |
2901 | mp_irqs[i].mp_srcbusirq == bus_irq) | |
61fd47e0 SL |
2902 | break; |
2903 | if (i >= mp_irq_entries) | |
2904 | return -1; | |
2905 | ||
2906 | *trigger = irq_trigger(i); | |
2907 | *polarity = irq_polarity(i); | |
2908 | return 0; | |
2909 | } | |
2910 | ||
888ba6c6 | 2911 | #endif /* CONFIG_ACPI */ |
1a3f239d RR |
2912 | |
2913 | static int __init parse_disable_timer_pin_1(char *arg) | |
2914 | { | |
2915 | disable_timer_pin_1 = 1; | |
2916 | return 0; | |
2917 | } | |
2918 | early_param("disable_timer_pin_1", parse_disable_timer_pin_1); | |
2919 | ||
2920 | static int __init parse_enable_timer_pin_1(char *arg) | |
2921 | { | |
2922 | disable_timer_pin_1 = -1; | |
2923 | return 0; | |
2924 | } | |
2925 | early_param("enable_timer_pin_1", parse_enable_timer_pin_1); | |
2926 | ||
2927 | static int __init parse_noapic(char *arg) | |
2928 | { | |
2929 | /* disable IO-APIC */ | |
2930 | disable_ioapic_setup(); | |
2931 | return 0; | |
2932 | } | |
2933 | early_param("noapic", parse_noapic); | |
f3294a33 YL |
2934 | |
2935 | void __init ioapic_init_mappings(void) | |
2936 | { | |
2937 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
2938 | int i; | |
2939 | ||
2940 | for (i = 0; i < nr_ioapics; i++) { | |
2941 | if (smp_found_config) { | |
2942 | ioapic_phys = mp_ioapics[i].mp_apicaddr; | |
2943 | if (!ioapic_phys) { | |
2944 | printk(KERN_ERR | |
2945 | "WARNING: bogus zero IO-APIC " | |
2946 | "address found in MPTABLE, " | |
2947 | "disabling IO/APIC support!\n"); | |
2948 | smp_found_config = 0; | |
2949 | skip_ioapic_setup = 1; | |
2950 | goto fake_ioapic_page; | |
2951 | } | |
2952 | } else { | |
2953 | fake_ioapic_page: | |
2954 | ioapic_phys = (unsigned long) | |
2955 | alloc_bootmem_pages(PAGE_SIZE); | |
2956 | ioapic_phys = __pa(ioapic_phys); | |
2957 | } | |
2958 | set_fixmap_nocache(idx, ioapic_phys); | |
2959 | printk(KERN_DEBUG "mapped IOAPIC to %08lx (%08lx)\n", | |
2960 | __fix_to_virt(idx), ioapic_phys); | |
2961 | idx++; | |
2962 | } | |
2963 | } | |
2964 |