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sparseirq: export nr_irqs on m68k/sparc/s390
[linux-2.6-block.git] / arch / x86 / kernel / io_apic.c
CommitLineData
1da177e4
LT		 1/*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23#include <linux/mm.h>
1da177e4
LT		 24#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
d4057bdb 28#include <linux/pci.h>
1da177e4
LT		 29#include <linux/mc146818rtc.h>
30#include <linux/compiler.h>
31#include <linux/acpi.h>
129f6946 32#include <linux/module.h>
1da177e4 33#include <linux/sysdev.h>
3b7d1921 34#include <linux/msi.h>
95d77884 35#include <linux/htirq.h>
7dfb7103 36#include <linux/freezer.h>
f26d6a2b 37#include <linux/kthread.h>
54168ed7 38#include <linux/jiffies.h> /* time_after() */
d4057bdb
YL		 39#ifdef CONFIG_ACPI
40#include <acpi/acpi_bus.h>
41#endif
42#include <linux/bootmem.h>
43#include <linux/dmar.h>
54d5d424 44
d4057bdb 45#include <asm/idle.h>
1da177e4
LT		 46#include <asm/io.h>
47#include <asm/smp.h>
48#include <asm/desc.h>
d4057bdb
YL		 49#include <asm/proto.h>
50#include <asm/acpi.h>
51#include <asm/dma.h>
1da177e4 52#include <asm/timer.h>
306e440d 53#include <asm/i8259.h>
3e4ff115 54#include <asm/nmi.h>
2d3fcc1c 55#include <asm/msidef.h>
8b955b0d 56#include <asm/hypertransport.h>
a4dbc34d 57#include <asm/setup.h>
d4057bdb 58#include <asm/irq_remapping.h>
1da177e4 59
497c9a19 60#include <mach_ipi.h>
1da177e4 61#include <mach_apic.h>
874c4fe3 62#include <mach_apicdef.h>
1da177e4 63
32f71aff
MR		 64#define __apicdebuginit(type) static type __init
65
1da177e4 66/*
54168ed7
IM		 67 * Is the SiS APIC rmw bug present ?
68 * -1 = don't know, 0 = no, 1 = yes
1da177e4
LT		 69 */
70int sis_apic_bug = -1;
71
efa2559f
YL		 72static DEFINE_SPINLOCK(ioapic_lock);
73static DEFINE_SPINLOCK(vector_lock);
74
1da177e4
LT		 75/*
76 * # of IRQ routing registers
77 */
78int nr_ioapic_registers[MAX_IO_APICS];
79
9f640ccb 80/* I/O APIC entries */
ec2cd0a2 81struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
9f640ccb
AS		 82int nr_ioapics;
83
584f734d 84/* MP IRQ source entries */
2fddb6e2 85struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
584f734d
AS		 86
87/* # of MP IRQ source entries */
88int mp_irq_entries;
89
8732fc4b
AS		 90#if defined (CONFIG_MCA) || defined (CONFIG_EISA)
91int mp_bus_id_to_type[MAX_MP_BUSSES];
92#endif
93
94DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
95
efa2559f
YL		 96int skip_ioapic_setup;
97
54168ed7 98static int __init parse_noapic(char *str)
efa2559f
YL		 99{
100 /* disable IO-APIC */
101 disable_ioapic_setup();
102 return 0;
103}
104early_param("noapic", parse_noapic);
66759a01 105
da51a821 106struct irq_cfg;
0f978f45 107struct irq_pin_list;
a1420f39 108struct irq_cfg {
da51a821 109 unsigned int irq;
8f09cd20 110#ifdef CONFIG_HAVE_SPARSE_IRQ
da51a821 111 struct irq_cfg *next;
8f09cd20 112#endif
0f978f45 113 struct irq_pin_list *irq_2_pin;
497c9a19
YL		 114 cpumask_t domain;
115 cpumask_t old_domain;
116 unsigned move_cleanup_count;
a1420f39 117 u8 vector;
497c9a19 118 u8 move_in_progress : 1;
a1420f39
YL		 119};
120
a1420f39
YL		 121/* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
122static struct irq_cfg irq_cfg_legacy[] __initdata = {
497c9a19
YL		 123 [0] = { .irq = 0, .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
124 [1] = { .irq = 1, .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
125 [2] = { .irq = 2, .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
126 [3] = { .irq = 3, .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
127 [4] = { .irq = 4, .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
128 [5] = { .irq = 5, .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
129 [6] = { .irq = 6, .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
130 [7] = { .irq = 7, .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
131 [8] = { .irq = 8, .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
132 [9] = { .irq = 9, .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
133 [10] = { .irq = 10, .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
134 [11] = { .irq = 11, .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
135 [12] = { .irq = 12, .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
136 [13] = { .irq = 13, .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
137 [14] = { .irq = 14, .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
138 [15] = { .irq = 15, .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
a1420f39
YL		 139};
140
da51a821 141static struct irq_cfg irq_cfg_init = { .irq = -1U, };
da51a821
YL		 142
143static void init_one_irq_cfg(struct irq_cfg *cfg)
144{
145 memcpy(cfg, &irq_cfg_init, sizeof(struct irq_cfg));
146}
147
148static struct irq_cfg *irq_cfgx;
e89eb438
YL		 149
150/*
151 * Protect the irq_cfgx_free freelist:
152 */
153static DEFINE_SPINLOCK(irq_cfg_lock);
154
8f09cd20 155#ifdef CONFIG_HAVE_SPARSE_IRQ
da51a821 156static struct irq_cfg *irq_cfgx_free;
8f09cd20 157#endif
a1420f39
YL		 158static void __init init_work(void *data)
159{
da51a821
YL		 160 struct dyn_array *da = data;
161 struct irq_cfg *cfg;
162 int legacy_count;
163 int i;
164
165 cfg = *da->name;
a1420f39 166
da51a821 167 memcpy(cfg, irq_cfg_legacy, sizeof(irq_cfg_legacy));
a1420f39 168
da51a821
YL		 169 legacy_count = sizeof(irq_cfg_legacy)/sizeof(irq_cfg_legacy[0]);
170 for (i = legacy_count; i < *da->nr; i++)
171 init_one_irq_cfg(&cfg[i]);
a1420f39 172
8f09cd20 173#ifdef CONFIG_HAVE_SPARSE_IRQ
da51a821
YL		 174 for (i = 1; i < *da->nr; i++)
175 cfg[i-1].next = &cfg[i];
a1420f39 176
da51a821
YL		 177 irq_cfgx_free = &irq_cfgx[legacy_count];
178 irq_cfgx[legacy_count - 1].next = NULL;
8f09cd20
YL		 179#endif
180}
181
182#ifdef CONFIG_HAVE_SPARSE_IRQ
183/* need to be biger than size of irq_cfg_legacy */
184static int nr_irq_cfg = 32;
185
186static int __init parse_nr_irq_cfg(char *arg)
187{
188 if (arg) {
189 nr_irq_cfg = simple_strtoul(arg, NULL, 0);
190 if (nr_irq_cfg < 32)
191 nr_irq_cfg = 32;
192 }
193 return 0;
a1420f39
YL		 194}
195
8f09cd20
YL		 196early_param("nr_irq_cfg", parse_nr_irq_cfg);
197
198#define for_each_irq_cfg(irqX, cfg) \
199 for (cfg = irq_cfgx, irqX = cfg->irq; cfg; cfg = cfg->next, irqX = cfg ? cfg->irq : -1U)
200
da51a821
YL		 201
202DEFINE_DYN_ARRAY(irq_cfgx, sizeof(struct irq_cfg), nr_irq_cfg, PAGE_SIZE, init_work);
a1420f39
YL		 203
204static struct irq_cfg *irq_cfg(unsigned int irq)
205{
da51a821
YL		 206 struct irq_cfg *cfg;
207
208 cfg = irq_cfgx;
209 while (cfg) {
210 if (cfg->irq == irq)
211 return cfg;
212
213 cfg = cfg->next;
214 }
215
216 return NULL;
217}
218
219static struct irq_cfg *irq_cfg_alloc(unsigned int irq)
220{
221 struct irq_cfg *cfg, *cfg_pri;
e89eb438 222 unsigned long flags;
da51a821 223 int count = 0;
e89eb438 224 int i;
da51a821
YL		 225
226 cfg_pri = cfg = irq_cfgx;
227 while (cfg) {
228 if (cfg->irq == irq)
229 return cfg;
230
231 cfg_pri = cfg;
232 cfg = cfg->next;
233 count++;
234 }
235
e89eb438 236 spin_lock_irqsave(&irq_cfg_lock, flags);
da51a821
YL		 237 if (!irq_cfgx_free) {
238 unsigned long phys;
239 unsigned long total_bytes;
240 /*
241 * we run out of pre-allocate ones, allocate more
242 */
243 printk(KERN_DEBUG "try to get more irq_cfg %d\n", nr_irq_cfg);
244
245 total_bytes = sizeof(struct irq_cfg) * nr_irq_cfg;
246 if (after_bootmem)
247 cfg = kzalloc(total_bytes, GFP_ATOMIC);
248 else
249 cfg = __alloc_bootmem_nopanic(total_bytes, PAGE_SIZE, 0);
a1420f39 250
da51a821
YL		 251 if (!cfg)
252 panic("please boot with nr_irq_cfg= %d\n", count * 2);
253
254 phys = __pa(cfg);
255 printk(KERN_DEBUG "irq_irq ==> [%#lx - %#lx]\n", phys, phys + total_bytes);
256
257 for (i = 0; i < nr_irq_cfg; i++)
258 init_one_irq_cfg(&cfg[i]);
259
260 for (i = 1; i < nr_irq_cfg; i++)
261 cfg[i-1].next = &cfg[i];
262
263 irq_cfgx_free = cfg;
264 }
265
266 cfg = irq_cfgx_free;
267 irq_cfgx_free = irq_cfgx_free->next;
268 cfg->next = NULL;
269 if (cfg_pri)
270 cfg_pri->next = cfg;
271 else
272 irq_cfgx = cfg;
273 cfg->irq = irq;
e89eb438
YL		 274
275 spin_unlock_irqrestore(&irq_cfg_lock, flags);
276
da51a821 277 printk(KERN_DEBUG "found new irq_cfg for irq %d\n", cfg->irq);
da51a821
YL		 278#ifdef CONFIG_HAVE_SPARSE_IRQ_DEBUG
279 {
280 /* dump the results */
281 struct irq_cfg *cfg;
282 unsigned long phys;
283 unsigned long bytes = sizeof(struct irq_cfg);
284
285 printk(KERN_DEBUG "=========================== %d\n", irq);
286 printk(KERN_DEBUG "irq_cfg dump after get that for %d\n", irq);
287 for_each_irq_cfg(cfg) {
288 phys = __pa(cfg);
289 printk(KERN_DEBUG "irq_cfg %d ==> [%#lx - %#lx]\n", cfg->irq, phys, phys + bytes);
290 }
291 printk(KERN_DEBUG "===========================\n");
292 }
293#endif
294 return cfg;
a1420f39 295}
8f09cd20
YL		 296#else
297
298#define for_each_irq_cfg(irq, cfg) \
299 for (irq = 0, cfg = &irq_cfgx[irq]; irq < nr_irqs; irq++, cfg = &irq_cfgx[irq])
300
301DEFINE_DYN_ARRAY(irq_cfgx, sizeof(struct irq_cfg), nr_irqs, PAGE_SIZE, init_work);
a1420f39 302
8f09cd20
YL		 303struct irq_cfg *irq_cfg(unsigned int irq)
304{
305 if (irq < nr_irqs)
306 return &irq_cfgx[irq];
307
308 return NULL;
309}
310struct irq_cfg *irq_cfg_alloc(unsigned int irq)
311{
312 return irq_cfg(irq);
313}
314
315#endif
1da177e4
LT		 316/*
317 * This is performance-critical, we want to do it O(1)
318 *
319 * the indexing order of this array favors 1:1 mappings
320 * between pins and IRQs.
321 */
322
0f978f45
YL		 323struct irq_pin_list {
324 int apic, pin;
325 struct irq_pin_list *next;
326};
327
328static struct irq_pin_list *irq_2_pin_head;
329/* fill one page ? */
330static int nr_irq_2_pin = 0x100;
331static struct irq_pin_list *irq_2_pin_ptr;
332static void __init irq_2_pin_init_work(void *data)
333{
334 struct dyn_array *da = data;
335 struct irq_pin_list *pin;
336 int i;
337
338 pin = *da->name;
339
340 for (i = 1; i < *da->nr; i++)
341 pin[i-1].next = &pin[i];
342
343 irq_2_pin_ptr = &pin[0];
344}
345DEFINE_DYN_ARRAY(irq_2_pin_head, sizeof(struct irq_pin_list), nr_irq_2_pin, PAGE_SIZE, irq_2_pin_init_work);
346
347static struct irq_pin_list *get_one_free_irq_2_pin(void)
348{
349 struct irq_pin_list *pin;
350 int i;
351
352 pin = irq_2_pin_ptr;
353
354 if (pin) {
355 irq_2_pin_ptr = pin->next;
356 pin->next = NULL;
357 return pin;
358 }
359
360 /*
361 * we run out of pre-allocate ones, allocate more
362 */
363 printk(KERN_DEBUG "try to get more irq_2_pin %d\n", nr_irq_2_pin);
364
365 if (after_bootmem)
366 pin = kzalloc(sizeof(struct irq_pin_list)*nr_irq_2_pin,
367 GFP_ATOMIC);
368 else
369 pin = __alloc_bootmem_nopanic(sizeof(struct irq_pin_list) *
370 nr_irq_2_pin, PAGE_SIZE, 0);
371
372 if (!pin)
373 panic("can not get more irq_2_pin\n");
301e6190 374
0f978f45
YL		 375 for (i = 1; i < nr_irq_2_pin; i++)
376 pin[i-1].next = &pin[i];
377
378 irq_2_pin_ptr = pin->next;
379 pin->next = NULL;
380
381 return pin;
382}
1da177e4 383
130fe05d
LT		 384struct io_apic {
385 unsigned int index;
386 unsigned int unused[3];
387 unsigned int data;
388};
389
390static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
391{
392 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
ec2cd0a2 393 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
130fe05d
LT		 394}
395
396static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
397{
398 struct io_apic __iomem *io_apic = io_apic_base(apic);
399 writel(reg, &io_apic->index);
400 return readl(&io_apic->data);
401}
402
403static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
404{
405 struct io_apic __iomem *io_apic = io_apic_base(apic);
406 writel(reg, &io_apic->index);
407 writel(value, &io_apic->data);
408}
409
410/*
411 * Re-write a value: to be used for read-modify-write
412 * cycles where the read already set up the index register.
413 *
414 * Older SiS APIC requires we rewrite the index register
415 */
416static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
417{
54168ed7
IM		 418 struct io_apic __iomem *io_apic = io_apic_base(apic);
419 if (sis_apic_bug)
420 writel(reg, &io_apic->index);
130fe05d
LT		 421 writel(value, &io_apic->data);
422}
423
047c8fdb
YL		 424static bool io_apic_level_ack_pending(unsigned int irq)
425{
426 struct irq_pin_list *entry;
427 unsigned long flags;
428 struct irq_cfg *cfg = irq_cfg(irq);
429
430 spin_lock_irqsave(&ioapic_lock, flags);
431 entry = cfg->irq_2_pin;
432 for (;;) {
433 unsigned int reg;
434 int pin;
435
436 if (!entry)
437 break;
438 pin = entry->pin;
439 reg = io_apic_read(entry->apic, 0x10 + pin*2);
440 /* Is the remote IRR bit set? */
441 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
442 spin_unlock_irqrestore(&ioapic_lock, flags);
443 return true;
444 }
445 if (!entry->next)
446 break;
447 entry = entry->next;
448 }
449 spin_unlock_irqrestore(&ioapic_lock, flags);
450
451 return false;
452}
047c8fdb 453
cf4c6a2f
AK		 454union entry_union {
455 struct { u32 w1, w2; };
456 struct IO_APIC_route_entry entry;
457};
458
459static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
460{
461 union entry_union eu;
462 unsigned long flags;
463 spin_lock_irqsave(&ioapic_lock, flags);
464 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
465 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
466 spin_unlock_irqrestore(&ioapic_lock, flags);
467 return eu.entry;
468}
469
f9dadfa7
LT		 470/*
471 * When we write a new IO APIC routing entry, we need to write the high
472 * word first! If the mask bit in the low word is clear, we will enable
473 * the interrupt, and we need to make sure the entry is fully populated
474 * before that happens.
475 */
d15512f4
AK		 476static void
477__ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
cf4c6a2f 478{
cf4c6a2f
AK		 479 union entry_union eu;
480 eu.entry = e;
f9dadfa7
LT		 481 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
482 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
d15512f4
AK		 483}
484
485static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
486{
487 unsigned long flags;
488 spin_lock_irqsave(&ioapic_lock, flags);
489 __ioapic_write_entry(apic, pin, e);
f9dadfa7
LT		 490 spin_unlock_irqrestore(&ioapic_lock, flags);
491}
492
493/*
494 * When we mask an IO APIC routing entry, we need to write the low
495 * word first, in order to set the mask bit before we change the
496 * high bits!
497 */
498static void ioapic_mask_entry(int apic, int pin)
499{
500 unsigned long flags;
501 union entry_union eu = { .entry.mask = 1 };
502
cf4c6a2f
AK		 503 spin_lock_irqsave(&ioapic_lock, flags);
504 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
505 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
506 spin_unlock_irqrestore(&ioapic_lock, flags);
507}
508
497c9a19
YL		 509#ifdef CONFIG_SMP
510static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
511{
512 int apic, pin;
513 struct irq_cfg *cfg;
514 struct irq_pin_list *entry;
515
516 cfg = irq_cfg(irq);
517 entry = cfg->irq_2_pin;
518 for (;;) {
519 unsigned int reg;
520
521 if (!entry)
522 break;
523
524 apic = entry->apic;
525 pin = entry->pin;
54168ed7
IM		 526#ifdef CONFIG_INTR_REMAP
527 /*
528 * With interrupt-remapping, destination information comes
529 * from interrupt-remapping table entry.
530 */
531 if (!irq_remapped(irq))
532 io_apic_write(apic, 0x11 + pin*2, dest);
533#else
497c9a19 534 io_apic_write(apic, 0x11 + pin*2, dest);
54168ed7 535#endif
497c9a19
YL		 536 reg = io_apic_read(apic, 0x10 + pin*2);
537 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
538 reg |= vector;
54168ed7 539 io_apic_modify(apic, 0x10 + pin*2, reg);
497c9a19
YL		 540 if (!entry->next)
541 break;
542 entry = entry->next;
543 }
544}
efa2559f
YL		 545
546static int assign_irq_vector(int irq, cpumask_t mask);
547
497c9a19
YL		 548static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
549{
550 struct irq_cfg *cfg;
551 unsigned long flags;
552 unsigned int dest;
553 cpumask_t tmp;
54168ed7 554 struct irq_desc *desc;
497c9a19 555
497c9a19
YL		 556 cpus_and(tmp, mask, cpu_online_map);
557 if (cpus_empty(tmp))
558 return;
559
047c8fdb 560 cfg = irq_cfg(irq);
497c9a19
YL		 561 if (assign_irq_vector(irq, mask))
562 return;
563
564 cpus_and(tmp, cfg->domain, mask);
497c9a19
YL		 565 dest = cpu_mask_to_apicid(tmp);
566 /*
567 * Only the high 8 bits are valid.
568 */
569 dest = SET_APIC_LOGICAL_ID(dest);
570
54168ed7 571 desc = irq_to_desc(irq);
497c9a19
YL		 572 spin_lock_irqsave(&ioapic_lock, flags);
573 __target_IO_APIC_irq(irq, dest, cfg->vector);
54168ed7 574 desc->affinity = mask;
497c9a19
YL		 575 spin_unlock_irqrestore(&ioapic_lock, flags);
576}
497c9a19
YL		 577#endif /* CONFIG_SMP */
578
1da177e4
LT		 579/*
580 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
581 * shared ISA-space IRQs, so we have to support them. We are super
582 * fast in the common case, and fast for shared ISA-space IRQs.
583 */
584static void add_pin_to_irq(unsigned int irq, int apic, int pin)
585{
0f978f45
YL		 586 struct irq_cfg *cfg;
587 struct irq_pin_list *entry;
588
589 /* first time to refer irq_cfg, so with new */
590 cfg = irq_cfg_alloc(irq);
591 entry = cfg->irq_2_pin;
592 if (!entry) {
593 entry = get_one_free_irq_2_pin();
594 cfg->irq_2_pin = entry;
595 entry->apic = apic;
596 entry->pin = pin;
597 printk(KERN_DEBUG " 0 add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin);
598 return;
599 }
1da177e4 600
0f978f45
YL		 601 while (entry->next) {
602 /* not again, please */
603 if (entry->apic == apic && entry->pin == pin)
604 return;
1da177e4 605
0f978f45 606 entry = entry->next;
1da177e4 607 }
0f978f45
YL		 608
609 entry->next = get_one_free_irq_2_pin();
610 entry = entry->next;
1da177e4
LT		 611 entry->apic = apic;
612 entry->pin = pin;
0f978f45 613 printk(KERN_DEBUG " x add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin);
1da177e4
LT		 614}
615
616/*
617 * Reroute an IRQ to a different pin.
618 */
619static void __init replace_pin_at_irq(unsigned int irq,
620 int oldapic, int oldpin,
621 int newapic, int newpin)
622{
0f978f45
YL		 623 struct irq_cfg *cfg = irq_cfg(irq);
624 struct irq_pin_list *entry = cfg->irq_2_pin;
625 int replaced = 0;
1da177e4 626
0f978f45 627 while (entry) {
1da177e4
LT		 628 if (entry->apic == oldapic && entry->pin == oldpin) {
629 entry->apic = newapic;
630 entry->pin = newpin;
0f978f45
YL		 631 replaced = 1;
632 /* every one is different, right? */
1da177e4 633 break;
0f978f45
YL		 634 }
635 entry = entry->next;
1da177e4 636 }
0f978f45
YL		 637
638 /* why? call replace before add? */
639 if (!replaced)
640 add_pin_to_irq(irq, newapic, newpin);
1da177e4
LT		 641}
642
4e738e2f 643#define __DO_ACTION(R, ACTION_ENABLE, ACTION_DISABLE, FINAL) \
047c8fdb
YL		 644 \
645{ \
646 int pin; \
647 struct irq_cfg *cfg; \
648 struct irq_pin_list *entry; \
649 \
650 cfg = irq_cfg(irq); \
651 entry = cfg->irq_2_pin; \
652 for (;;) { \
653 unsigned int reg; \
654 if (!entry) \
655 break; \
656 pin = entry->pin; \
657 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
4e738e2f
YL		 658 reg ACTION_DISABLE; \
659 reg ACTION_ENABLE; \
047c8fdb
YL		 660 io_apic_modify(entry->apic, 0x10 + R + pin*2, reg); \
661 FINAL; \
662 if (!entry->next) \
663 break; \
664 entry = entry->next; \
665 } \
666}
667
4e738e2f 668#define DO_ACTION(name,R, ACTION_ENABLE, ACTION_DISABLE, FINAL) \
047c8fdb
YL		 669 \
670 static void name##_IO_APIC_irq (unsigned int irq) \
4e738e2f 671 __DO_ACTION(R, ACTION_ENABLE, ACTION_DISABLE, FINAL)
047c8fdb
YL		 672
673/* mask = 0 */
4e738e2f 674DO_ACTION(__unmask, 0, |= 0, &= ~IO_APIC_REDIR_MASKED, )
047c8fdb 675
4e738e2f
YL		 676#ifdef CONFIG_X86_64
677/*
678 * Synchronize the IO-APIC and the CPU by doing
679 * a dummy read from the IO-APIC
680 */
681static inline void io_apic_sync(unsigned int apic)
1da177e4 682{
4e738e2f
YL		 683 struct io_apic __iomem *io_apic = io_apic_base(apic);
684 readl(&io_apic->data);
1da177e4
LT		 685}
686
687/* mask = 1 */
4e738e2f 688DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, &= ~0, io_apic_sync(entry->apic))
1da177e4 689
4e738e2f
YL		 690#else
691
692/* mask = 1 */
693DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, &= ~0, )
1da177e4
LT		 694
695/* mask = 1, trigger = 0 */
4e738e2f 696DO_ACTION(__mask_and_edge, 0, |= IO_APIC_REDIR_MASKED, &= ~IO_APIC_REDIR_LEVEL_TRIGGER, )
1da177e4
LT		 697
698/* mask = 0, trigger = 1 */
4e738e2f 699DO_ACTION(__unmask_and_level, 0, |= IO_APIC_REDIR_LEVEL_TRIGGER, &= ~IO_APIC_REDIR_MASKED, )
1da177e4 700
047c8fdb
YL		 701#endif
702
54168ed7 703static void mask_IO_APIC_irq (unsigned int irq)
1da177e4
LT		 704{
705 unsigned long flags;
706
707 spin_lock_irqsave(&ioapic_lock, flags);
708 __mask_IO_APIC_irq(irq);
709 spin_unlock_irqrestore(&ioapic_lock, flags);
710}
711
54168ed7 712static void unmask_IO_APIC_irq (unsigned int irq)
1da177e4
LT		 713{
714 unsigned long flags;
715
716 spin_lock_irqsave(&ioapic_lock, flags);
717 __unmask_IO_APIC_irq(irq);
718 spin_unlock_irqrestore(&ioapic_lock, flags);
719}
720
721static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
722{
723 struct IO_APIC_route_entry entry;
36062448 724
1da177e4 725 /* Check delivery_mode to be sure we're not clearing an SMI pin */
cf4c6a2f 726 entry = ioapic_read_entry(apic, pin);
1da177e4
LT		 727 if (entry.delivery_mode == dest_SMI)
728 return;
1da177e4
LT		 729 /*
730 * Disable it in the IO-APIC irq-routing table:
731 */
f9dadfa7 732 ioapic_mask_entry(apic, pin);
1da177e4
LT		 733}
734
54168ed7 735static void clear_IO_APIC (void)
1da177e4
LT		 736{
737 int apic, pin;
738
739 for (apic = 0; apic < nr_ioapics; apic++)
740 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
741 clear_IO_APIC_pin(apic, pin);
742}
743
54168ed7 744#if !defined(CONFIG_SMP) && defined(CONFIG_X86_32)
75604d7f 745void send_IPI_self(int vector)
1da177e4
LT		 746{
747 unsigned int cfg;
748
749 /*
750 * Wait for idle.
751 */
752 apic_wait_icr_idle();
753 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
754 /*
755 * Send the IPI. The write to APIC_ICR fires this off.
756 */
593f4a78 757 apic_write(APIC_ICR, cfg);
1da177e4 758}
54168ed7 759#endif /* !CONFIG_SMP && CONFIG_X86_32*/
1da177e4 760
54168ed7 761#ifdef CONFIG_X86_32
1da177e4
LT		 762/*
763 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
764 * specific CPU-side IRQs.
765 */
766
767#define MAX_PIRQS 8
768static int pirq_entries [MAX_PIRQS];
769static int pirqs_enabled;
1da177e4 770
1da177e4
LT		 771static int __init ioapic_pirq_setup(char *str)
772{
773 int i, max;
774 int ints[MAX_PIRQS+1];
775
776 get_options(str, ARRAY_SIZE(ints), ints);
777
778 for (i = 0; i < MAX_PIRQS; i++)
779 pirq_entries[i] = -1;
780
781 pirqs_enabled = 1;
782 apic_printk(APIC_VERBOSE, KERN_INFO
783 "PIRQ redirection, working around broken MP-BIOS.\n");
784 max = MAX_PIRQS;
785 if (ints[0] < MAX_PIRQS)
786 max = ints[0];
787
788 for (i = 0; i < max; i++) {
789 apic_printk(APIC_VERBOSE, KERN_DEBUG
790 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
791 /*
792 * PIRQs are mapped upside down, usually.
793 */
794 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
795 }
796 return 1;
797}
798
799__setup("pirq=", ioapic_pirq_setup);
54168ed7
IM		 800#endif /* CONFIG_X86_32 */
801
802#ifdef CONFIG_INTR_REMAP
803/* I/O APIC RTE contents at the OS boot up */
804static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
805
806/*
807 * Saves and masks all the unmasked IO-APIC RTE's
808 */
809int save_mask_IO_APIC_setup(void)
810{
811 union IO_APIC_reg_01 reg_01;
812 unsigned long flags;
813 int apic, pin;
814
815 /*
816 * The number of IO-APIC IRQ registers (== #pins):
817 */
818 for (apic = 0; apic < nr_ioapics; apic++) {
819 spin_lock_irqsave(&ioapic_lock, flags);
820 reg_01.raw = io_apic_read(apic, 1);
821 spin_unlock_irqrestore(&ioapic_lock, flags);
822 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
823 }
824
825 for (apic = 0; apic < nr_ioapics; apic++) {
826 early_ioapic_entries[apic] =
827 kzalloc(sizeof(struct IO_APIC_route_entry) *
828 nr_ioapic_registers[apic], GFP_KERNEL);
829 if (!early_ioapic_entries[apic])
830 return -ENOMEM;
831 }
832
833 for (apic = 0; apic < nr_ioapics; apic++)
834 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
835 struct IO_APIC_route_entry entry;
836
837 entry = early_ioapic_entries[apic][pin] =
838 ioapic_read_entry(apic, pin);
839 if (!entry.mask) {
840 entry.mask = 1;
841 ioapic_write_entry(apic, pin, entry);
842 }
843 }
844 return 0;
845}
846
847void restore_IO_APIC_setup(void)
848{
849 int apic, pin;
850
851 for (apic = 0; apic < nr_ioapics; apic++)
852 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
853 ioapic_write_entry(apic, pin,
854 early_ioapic_entries[apic][pin]);
855}
856
857void reinit_intr_remapped_IO_APIC(int intr_remapping)
858{
859 /*
860 * for now plain restore of previous settings.
861 * TBD: In the case of OS enabling interrupt-remapping,
862 * IO-APIC RTE's need to be setup to point to interrupt-remapping
863 * table entries. for now, do a plain restore, and wait for
864 * the setup_IO_APIC_irqs() to do proper initialization.
865 */
866 restore_IO_APIC_setup();
867}
868#endif
1da177e4
LT		 869
870/*
871 * Find the IRQ entry number of a certain pin.
872 */
873static int find_irq_entry(int apic, int pin, int type)
874{
875 int i;
876
877 for (i = 0; i < mp_irq_entries; i++)
2fddb6e2
AS		 878 if (mp_irqs[i].mp_irqtype == type &&
879 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
880 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
881 mp_irqs[i].mp_dstirq == pin)
1da177e4
LT		 882 return i;
883
884 return -1;
885}
886
887/*
888 * Find the pin to which IRQ[irq] (ISA) is connected
889 */
fcfd636a 890static int __init find_isa_irq_pin(int irq, int type)
1da177e4
LT		 891{
892 int i;
893
894 for (i = 0; i < mp_irq_entries; i++) {
2fddb6e2 895 int lbus = mp_irqs[i].mp_srcbus;
1da177e4 896
d27e2b8e 897 if (test_bit(lbus, mp_bus_not_pci) &&
2fddb6e2
AS		 898 (mp_irqs[i].mp_irqtype == type) &&
899 (mp_irqs[i].mp_srcbusirq == irq))
1da177e4 900
2fddb6e2 901 return mp_irqs[i].mp_dstirq;
1da177e4
LT		 902 }
903 return -1;
904}
905
fcfd636a
EB		 906static int __init find_isa_irq_apic(int irq, int type)
907{
908 int i;
909
910 for (i = 0; i < mp_irq_entries; i++) {
2fddb6e2 911 int lbus = mp_irqs[i].mp_srcbus;
fcfd636a 912
73b2961b 913 if (test_bit(lbus, mp_bus_not_pci) &&
2fddb6e2
AS		 914 (mp_irqs[i].mp_irqtype == type) &&
915 (mp_irqs[i].mp_srcbusirq == irq))
fcfd636a
EB		 916 break;
917 }
918 if (i < mp_irq_entries) {
919 int apic;
54168ed7 920 for(apic = 0; apic < nr_ioapics; apic++) {
2fddb6e2 921 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
fcfd636a
EB		 922 return apic;
923 }
924 }
925
926 return -1;
927}
928
1da177e4
LT		 929/*
930 * Find a specific PCI IRQ entry.
931 * Not an __init, possibly needed by modules
932 */
933static int pin_2_irq(int idx, int apic, int pin);
934
935int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
936{
937 int apic, i, best_guess = -1;
938
54168ed7
IM		 939 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
940 bus, slot, pin);
ce6444d3 941 if (test_bit(bus, mp_bus_not_pci)) {
54168ed7 942 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1da177e4
LT		 943 return -1;
944 }
945 for (i = 0; i < mp_irq_entries; i++) {
2fddb6e2 946 int lbus = mp_irqs[i].mp_srcbus;
1da177e4
LT		 947
948 for (apic = 0; apic < nr_ioapics; apic++)
2fddb6e2
AS		 949 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
950 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
1da177e4
LT		 951 break;
952
47cab822 953 if (!test_bit(lbus, mp_bus_not_pci) &&
2fddb6e2 954 !mp_irqs[i].mp_irqtype &&
1da177e4 955 (bus == lbus) &&
2fddb6e2 956 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
54168ed7 957 int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq);
1da177e4
LT		 958
959 if (!(apic || IO_APIC_IRQ(irq)))
960 continue;
961
2fddb6e2 962 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
1da177e4
LT		 963 return irq;
964 /*
965 * Use the first all-but-pin matching entry as a
966 * best-guess fuzzy result for broken mptables.
967 */
968 if (best_guess < 0)
969 best_guess = irq;
970 }
971 }
972 return best_guess;
973}
54168ed7 974
129f6946 975EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1da177e4 976
c0a282c2 977#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1da177e4
LT		 978/*
979 * EISA Edge/Level control register, ELCR
980 */
981static int EISA_ELCR(unsigned int irq)
982{
983 if (irq < 16) {
984 unsigned int port = 0x4d0 + (irq >> 3);
985 return (inb(port) >> (irq & 7)) & 1;
986 }
987 apic_printk(APIC_VERBOSE, KERN_INFO
988 "Broken MPtable reports ISA irq %d\n", irq);
989 return 0;
990}
54168ed7 991
c0a282c2 992#endif
1da177e4 993
6728801d
AS		 994/* ISA interrupts are always polarity zero edge triggered,
995 * when listed as conforming in the MP table. */
996
997#define default_ISA_trigger(idx) (0)
998#define default_ISA_polarity(idx) (0)
999
1da177e4
LT		 1000/* EISA interrupts are always polarity zero and can be edge or level
1001 * trigger depending on the ELCR value. If an interrupt is listed as
1002 * EISA conforming in the MP table, that means its trigger type must
1003 * be read in from the ELCR */
1004
2fddb6e2 1005#define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
6728801d 1006#define default_EISA_polarity(idx) default_ISA_polarity(idx)
1da177e4
LT		 1007
1008/* PCI interrupts are always polarity one level triggered,
1009 * when listed as conforming in the MP table. */
1010
1011#define default_PCI_trigger(idx) (1)
1012#define default_PCI_polarity(idx) (1)
1013
1014/* MCA interrupts are always polarity zero level triggered,
1015 * when listed as conforming in the MP table. */
1016
1017#define default_MCA_trigger(idx) (1)
6728801d 1018#define default_MCA_polarity(idx) default_ISA_polarity(idx)
1da177e4 1019
61fd47e0 1020static int MPBIOS_polarity(int idx)
1da177e4 1021{
2fddb6e2 1022 int bus = mp_irqs[idx].mp_srcbus;
1da177e4
LT		 1023 int polarity;
1024
1025 /*
1026 * Determine IRQ line polarity (high active or low active):
1027 */
54168ed7 1028 switch (mp_irqs[idx].mp_irqflag & 3)
36062448 1029 {
54168ed7
IM		 1030 case 0: /* conforms, ie. bus-type dependent polarity */
1031 if (test_bit(bus, mp_bus_not_pci))
1032 polarity = default_ISA_polarity(idx);
1033 else
1034 polarity = default_PCI_polarity(idx);
1035 break;
1036 case 1: /* high active */
1037 {
1038 polarity = 0;
1039 break;
1040 }
1041 case 2: /* reserved */
1042 {
1043 printk(KERN_WARNING "broken BIOS!!\n");
1044 polarity = 1;
1045 break;
1046 }
1047 case 3: /* low active */
1048 {
1049 polarity = 1;
1050 break;
1051 }
1052 default: /* invalid */
1053 {
1054 printk(KERN_WARNING "broken BIOS!!\n");
1055 polarity = 1;
1056 break;
1057 }
1da177e4
LT		 1058 }
1059 return polarity;
1060}
1061
1062static int MPBIOS_trigger(int idx)
1063{
2fddb6e2 1064 int bus = mp_irqs[idx].mp_srcbus;
1da177e4
LT		 1065 int trigger;
1066
1067 /*
1068 * Determine IRQ trigger mode (edge or level sensitive):
1069 */
54168ed7 1070 switch ((mp_irqs[idx].mp_irqflag>>2) & 3)
1da177e4 1071 {
54168ed7
IM		 1072 case 0: /* conforms, ie. bus-type dependent */
1073 if (test_bit(bus, mp_bus_not_pci))
1074 trigger = default_ISA_trigger(idx);
1075 else
1076 trigger = default_PCI_trigger(idx);
c0a282c2 1077#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
54168ed7
IM		 1078 switch (mp_bus_id_to_type[bus]) {
1079 case MP_BUS_ISA: /* ISA pin */
1080 {
1081 /* set before the switch */
1082 break;
1083 }
1084 case MP_BUS_EISA: /* EISA pin */
1085 {
1086 trigger = default_EISA_trigger(idx);
1087 break;
1088 }
1089 case MP_BUS_PCI: /* PCI pin */
1090 {
1091 /* set before the switch */
1092 break;
1093 }
1094 case MP_BUS_MCA: /* MCA pin */
1095 {
1096 trigger = default_MCA_trigger(idx);
1097 break;
1098 }
1099 default:
1100 {
1101 printk(KERN_WARNING "broken BIOS!!\n");
1102 trigger = 1;
1103 break;
1104 }
1105 }
1106#endif
1da177e4 1107 break;
54168ed7 1108 case 1: /* edge */
1da177e4 1109 {
54168ed7 1110 trigger = 0;
1da177e4
LT		 1111 break;
1112 }
54168ed7 1113 case 2: /* reserved */
1da177e4 1114 {
54168ed7
IM		 1115 printk(KERN_WARNING "broken BIOS!!\n");
1116 trigger = 1;
1da177e4
LT		 1117 break;
1118 }
54168ed7 1119 case 3: /* level */
1da177e4 1120 {
54168ed7 1121 trigger = 1;
1da177e4
LT		 1122 break;
1123 }
54168ed7 1124 default: /* invalid */
1da177e4
LT		 1125 {
1126 printk(KERN_WARNING "broken BIOS!!\n");
54168ed7 1127 trigger = 0;
1da177e4
LT		 1128 break;
1129 }
1130 }
1131 return trigger;
1132}
1133
1134static inline int irq_polarity(int idx)
1135{
1136 return MPBIOS_polarity(idx);
1137}
1138
1139static inline int irq_trigger(int idx)
1140{
1141 return MPBIOS_trigger(idx);
1142}
1143
efa2559f 1144int (*ioapic_renumber_irq)(int ioapic, int irq);
1da177e4
LT		 1145static int pin_2_irq(int idx, int apic, int pin)
1146{
1147 int irq, i;
2fddb6e2 1148 int bus = mp_irqs[idx].mp_srcbus;
1da177e4
LT		 1149
1150 /*
1151 * Debugging check, we are in big trouble if this message pops up!
1152 */
2fddb6e2 1153 if (mp_irqs[idx].mp_dstirq != pin)
1da177e4
LT		 1154 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1155
54168ed7 1156 if (test_bit(bus, mp_bus_not_pci)) {
2fddb6e2 1157 irq = mp_irqs[idx].mp_srcbusirq;
54168ed7 1158 } else {
643befed
AS		 1159 /*
1160 * PCI IRQs are mapped in order
1161 */
1162 i = irq = 0;
1163 while (i < apic)
1164 irq += nr_ioapic_registers[i++];
1165 irq += pin;
54168ed7
IM		 1166 /*
1167 * For MPS mode, so far only needed by ES7000 platform
1168 */
1169 if (ioapic_renumber_irq)
1170 irq = ioapic_renumber_irq(apic, irq);
1da177e4
LT		 1171 }
1172
54168ed7 1173#ifdef CONFIG_X86_32
1da177e4
LT		 1174 /*
1175 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1176 */
1177 if ((pin >= 16) && (pin <= 23)) {
1178 if (pirq_entries[pin-16] != -1) {
1179 if (!pirq_entries[pin-16]) {
1180 apic_printk(APIC_VERBOSE, KERN_DEBUG
1181 "disabling PIRQ%d\n", pin-16);
1182 } else {
1183 irq = pirq_entries[pin-16];
1184 apic_printk(APIC_VERBOSE, KERN_DEBUG
1185 "using PIRQ%d -> IRQ %d\n",
1186 pin-16, irq);
1187 }
1188 }
1189 }
54168ed7
IM		 1190#endif
1191
1da177e4
LT		 1192 return irq;
1193}
1194
497c9a19
YL		 1195void lock_vector_lock(void)
1196{
1197 /* Used to the online set of cpus does not change
1198 * during assign_irq_vector.
1199 */
1200 spin_lock(&vector_lock);
1201}
1da177e4 1202
497c9a19 1203void unlock_vector_lock(void)
1da177e4 1204{
497c9a19
YL		 1205 spin_unlock(&vector_lock);
1206}
1da177e4 1207
497c9a19
YL		 1208static int __assign_irq_vector(int irq, cpumask_t mask)
1209{
047c8fdb
YL		 1210 /*
1211 * NOTE! The local APIC isn't very good at handling
1212 * multiple interrupts at the same interrupt level.
1213 * As the interrupt level is determined by taking the
1214 * vector number and shifting that right by 4, we
1215 * want to spread these out a bit so that they don't
1216 * all fall in the same interrupt level.
1217 *
1218 * Also, we've got to be careful not to trash gate
1219 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1220 */
54168ed7
IM		 1221 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1222 unsigned int old_vector;
1223 int cpu;
1224 struct irq_cfg *cfg;
ace80ab7 1225
54168ed7 1226 cfg = irq_cfg(irq);
8339f000 1227
54168ed7
IM		 1228 /* Only try and allocate irqs on cpus that are present */
1229 cpus_and(mask, mask, cpu_online_map);
ace80ab7 1230
54168ed7
IM		 1231 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1232 return -EBUSY;
0a1ad60d 1233
54168ed7
IM		 1234 old_vector = cfg->vector;
1235 if (old_vector) {
1236 cpumask_t tmp;
1237 cpus_and(tmp, cfg->domain, mask);
1238 if (!cpus_empty(tmp))
1239 return 0;
1240 }
497c9a19 1241
54168ed7
IM		 1242 for_each_cpu_mask_nr(cpu, mask) {
1243 cpumask_t domain, new_mask;
1244 int new_cpu;
1245 int vector, offset;
497c9a19 1246
54168ed7
IM		 1247 domain = vector_allocation_domain(cpu);
1248 cpus_and(new_mask, domain, cpu_online_map);
497c9a19 1249
54168ed7
IM		 1250 vector = current_vector;
1251 offset = current_offset;
497c9a19 1252next:
54168ed7
IM		 1253 vector += 8;
1254 if (vector >= first_system_vector) {
1255 /* If we run out of vectors on large boxen, must share them. */
1256 offset = (offset + 1) % 8;
1257 vector = FIRST_DEVICE_VECTOR + offset;
1258 }
1259 if (unlikely(current_vector == vector))
1260 continue;
047c8fdb 1261#ifdef CONFIG_X86_64
54168ed7
IM		 1262 if (vector == IA32_SYSCALL_VECTOR)
1263 goto next;
047c8fdb 1264#else
54168ed7
IM		 1265 if (vector == SYSCALL_VECTOR)
1266 goto next;
047c8fdb 1267#endif
54168ed7
IM		 1268 for_each_cpu_mask_nr(new_cpu, new_mask)
1269 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1270 goto next;
1271 /* Found one! */
1272 current_vector = vector;
1273 current_offset = offset;
1274 if (old_vector) {
1275 cfg->move_in_progress = 1;
1276 cfg->old_domain = cfg->domain;
7a959cff 1277 }
54168ed7
IM		 1278 for_each_cpu_mask_nr(new_cpu, new_mask)
1279 per_cpu(vector_irq, new_cpu)[vector] = irq;
1280 cfg->vector = vector;
1281 cfg->domain = domain;
1282 return 0;
1283 }
1284 return -ENOSPC;
497c9a19
YL		 1285}
1286
1287static int assign_irq_vector(int irq, cpumask_t mask)
1288{
1289 int err;
ace80ab7 1290 unsigned long flags;
ace80ab7
EB		 1291
1292 spin_lock_irqsave(&vector_lock, flags);
497c9a19 1293 err = __assign_irq_vector(irq, mask);
26a3c49c 1294 spin_unlock_irqrestore(&vector_lock, flags);
497c9a19
YL		 1295 return err;
1296}
1297
1298static void __clear_irq_vector(int irq)
1299{
1300 struct irq_cfg *cfg;
1301 cpumask_t mask;
1302 int cpu, vector;
1303
1304 cfg = irq_cfg(irq);
1305 BUG_ON(!cfg->vector);
1306
1307 vector = cfg->vector;
1308 cpus_and(mask, cfg->domain, cpu_online_map);
1309 for_each_cpu_mask_nr(cpu, mask)
1310 per_cpu(vector_irq, cpu)[vector] = -1;
1311
1312 cfg->vector = 0;
1313 cpus_clear(cfg->domain);
1314}
1315
1316void __setup_vector_irq(int cpu)
1317{
1318 /* Initialize vector_irq on a new cpu */
1319 /* This function must be called with vector_lock held */
1320 int irq, vector;
1321 struct irq_cfg *cfg;
1322
1323 /* Mark the inuse vectors */
8f09cd20 1324 for_each_irq_cfg(irq, cfg) {
497c9a19
YL		 1325 if (!cpu_isset(cpu, cfg->domain))
1326 continue;
1327 vector = cfg->vector;
497c9a19
YL		 1328 per_cpu(vector_irq, cpu)[vector] = irq;
1329 }
1330 /* Mark the free vectors */
1331 for (vector = 0; vector < NR_VECTORS; ++vector) {
1332 irq = per_cpu(vector_irq, cpu)[vector];
1333 if (irq < 0)
1334 continue;
1335
1336 cfg = irq_cfg(irq);
1337 if (!cpu_isset(cpu, cfg->domain))
1338 per_cpu(vector_irq, cpu)[vector] = -1;
54168ed7 1339 }
1da177e4 1340}
3fde6900 1341
f5b9ed7a 1342static struct irq_chip ioapic_chip;
54168ed7
IM		 1343#ifdef CONFIG_INTR_REMAP
1344static struct irq_chip ir_ioapic_chip;
1345#endif
1da177e4 1346
54168ed7
IM		 1347#define IOAPIC_AUTO -1
1348#define IOAPIC_EDGE 0
1349#define IOAPIC_LEVEL 1
1da177e4 1350
047c8fdb 1351#ifdef CONFIG_X86_32
1d025192
YL		 1352static inline int IO_APIC_irq_trigger(int irq)
1353{
54168ed7 1354 int apic, idx, pin;
1d025192 1355
54168ed7
IM		 1356 for (apic = 0; apic < nr_ioapics; apic++) {
1357 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1358 idx = find_irq_entry(apic, pin, mp_INT);
1359 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1360 return irq_trigger(idx);
1361 }
1362 }
1363 /*
1364 * nonexistent IRQs are edge default
1365 */
1366 return 0;
1d025192 1367}
047c8fdb
YL		 1368#else
1369static inline int IO_APIC_irq_trigger(int irq)
1370{
54168ed7 1371 return 1;
047c8fdb
YL		 1372}
1373#endif
1d025192 1374
497c9a19 1375static void ioapic_register_intr(int irq, unsigned long trigger)
1da177e4 1376{
08678b08
YL		 1377 struct irq_desc *desc;
1378
199751d7
YL		 1379 /* first time to use this irq_desc */
1380 if (irq < 16)
1381 desc = irq_to_desc(irq);
1382 else
1383 desc = irq_to_desc_alloc(irq);
1384
6ebcc00e 1385 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
047c8fdb 1386 trigger == IOAPIC_LEVEL)
08678b08 1387 desc->status |= IRQ_LEVEL;
047c8fdb
YL		 1388 else
1389 desc->status &= ~IRQ_LEVEL;
1390
54168ed7
IM		 1391#ifdef CONFIG_INTR_REMAP
1392 if (irq_remapped(irq)) {
1393 desc->status |= IRQ_MOVE_PCNTXT;
1394 if (trigger)
1395 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1396 handle_fasteoi_irq,
1397 "fasteoi");
1398 else
1399 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1400 handle_edge_irq, "edge");
1401 return;
1402 }
1403#endif
047c8fdb
YL		 1404 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1405 trigger == IOAPIC_LEVEL)
a460e745 1406 set_irq_chip_and_handler_name(irq, &ioapic_chip,
54168ed7
IM		 1407 handle_fasteoi_irq,
1408 "fasteoi");
047c8fdb 1409 else
a460e745 1410 set_irq_chip_and_handler_name(irq, &ioapic_chip,
54168ed7 1411 handle_edge_irq, "edge");
1da177e4
LT		 1412}
1413
497c9a19
YL		 1414static int setup_ioapic_entry(int apic, int irq,
1415 struct IO_APIC_route_entry *entry,
1416 unsigned int destination, int trigger,
1417 int polarity, int vector)
1da177e4 1418{
497c9a19
YL		 1419 /*
1420 * add it to the IO-APIC irq-routing table:
1421 */
1422 memset(entry,0,sizeof(*entry));
1423
54168ed7
IM		 1424#ifdef CONFIG_INTR_REMAP
1425 if (intr_remapping_enabled) {
1426 struct intel_iommu *iommu = map_ioapic_to_ir(apic);
1427 struct irte irte;
1428 struct IR_IO_APIC_route_entry *ir_entry =
1429 (struct IR_IO_APIC_route_entry *) entry;
1430 int index;
1431
1432 if (!iommu)
1433 panic("No mapping iommu for ioapic %d\n", apic);
1434
1435 index = alloc_irte(iommu, irq, 1);
1436 if (index < 0)
1437 panic("Failed to allocate IRTE for ioapic %d\n", apic);
1438
1439 memset(&irte, 0, sizeof(irte));
1440
1441 irte.present = 1;
1442 irte.dst_mode = INT_DEST_MODE;
1443 irte.trigger_mode = trigger;
1444 irte.dlvry_mode = INT_DELIVERY_MODE;
1445 irte.vector = vector;
1446 irte.dest_id = IRTE_DEST(destination);
1447
1448 modify_irte(irq, &irte);
1449
1450 ir_entry->index2 = (index >> 15) & 0x1;
1451 ir_entry->zero = 0;
1452 ir_entry->format = 1;
1453 ir_entry->index = (index & 0x7fff);
1454 } else
1455#endif
1456 {
1457 entry->delivery_mode = INT_DELIVERY_MODE;
1458 entry->dest_mode = INT_DEST_MODE;
1459 entry->dest = destination;
1460 }
497c9a19 1461
54168ed7 1462 entry->mask = 0; /* enable IRQ */
497c9a19
YL		 1463 entry->trigger = trigger;
1464 entry->polarity = polarity;
1465 entry->vector = vector;
1466
1467 /* Mask level triggered irqs.
1468 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1469 */
1470 if (trigger)
1471 entry->mask = 1;
497c9a19
YL		 1472 return 0;
1473}
1474
1475static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
54168ed7 1476 int trigger, int polarity)
497c9a19
YL		 1477{
1478 struct irq_cfg *cfg;
1da177e4 1479 struct IO_APIC_route_entry entry;
497c9a19
YL		 1480 cpumask_t mask;
1481
1482 if (!IO_APIC_IRQ(irq))
1483 return;
1484
1485 cfg = irq_cfg(irq);
1486
1487 mask = TARGET_CPUS;
1488 if (assign_irq_vector(irq, mask))
1489 return;
1490
1491 cpus_and(mask, cfg->domain, mask);
1492
1493 apic_printk(APIC_VERBOSE,KERN_DEBUG
1494 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1495 "IRQ %d Mode:%i Active:%i)\n",
1496 apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
1497 irq, trigger, polarity);
1498
1499
1500 if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry,
1501 cpu_mask_to_apicid(mask), trigger, polarity,
1502 cfg->vector)) {
1503 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1504 mp_ioapics[apic].mp_apicid, pin);
1505 __clear_irq_vector(irq);
1506 return;
1507 }
1508
1509 ioapic_register_intr(irq, trigger);
1510 if (irq < 16)
1511 disable_8259A_irq(irq);
1512
1513 ioapic_write_entry(apic, pin, entry);
1514}
1515
1516static void __init setup_IO_APIC_irqs(void)
1517{
1518 int apic, pin, idx, irq, first_notcon = 1;
1da177e4
LT		 1519
1520 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1521
1522 for (apic = 0; apic < nr_ioapics; apic++) {
1523 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1524
497c9a19 1525 idx = find_irq_entry(apic,pin,mp_INT);
1da177e4
LT		 1526 if (idx == -1) {
1527 if (first_notcon) {
497c9a19 1528 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mp_apicid, pin);
1da177e4
LT		 1529 first_notcon = 0;
1530 } else
497c9a19 1531 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mp_apicid, pin);
1da177e4
LT		 1532 continue;
1533 }
20d225b9
YL		 1534 if (!first_notcon) {
1535 apic_printk(APIC_VERBOSE, " not connected.\n");
1536 first_notcon = 1;
1537 }
1538
1da177e4 1539 irq = pin_2_irq(idx, apic, pin);
54168ed7 1540#ifdef CONFIG_X86_32
497c9a19
YL		 1541 if (multi_timer_check(apic, irq))
1542 continue;
54168ed7 1543#endif
497c9a19 1544 add_pin_to_irq(irq, apic, pin);
36062448 1545
497c9a19
YL		 1546 setup_IO_APIC_irq(apic, pin, irq,
1547 irq_trigger(idx), irq_polarity(idx));
1da177e4
LT		 1548 }
1549 }
1550
1551 if (!first_notcon)
1552 apic_printk(APIC_VERBOSE, " not connected.\n");
1553}
1554
1555/*
f7633ce5 1556 * Set up the timer pin, possibly with the 8259A-master behind.
1da177e4 1557 */
f7633ce5
MR		 1558static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1559 int vector)
1da177e4
LT		 1560{
1561 struct IO_APIC_route_entry entry;
1da177e4 1562
54168ed7
IM		 1563#ifdef CONFIG_INTR_REMAP
1564 if (intr_remapping_enabled)
1565 return;
1566#endif
1567
36062448 1568 memset(&entry, 0, sizeof(entry));
1da177e4
LT		 1569
1570 /*
1571 * We use logical delivery to get the timer IRQ
1572 * to the first CPU.
1573 */
1574 entry.dest_mode = INT_DEST_MODE;
03be7505 1575 entry.mask = 1; /* mask IRQ now */
d83e94ac 1576 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
1da177e4
LT		 1577 entry.delivery_mode = INT_DELIVERY_MODE;
1578 entry.polarity = 0;
1579 entry.trigger = 0;
1580 entry.vector = vector;
1581
1582 /*
1583 * The timer IRQ doesn't have to know that behind the
f7633ce5 1584 * scene we may have a 8259A-master in AEOI mode ...
1da177e4 1585 */
54168ed7 1586 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1da177e4
LT		 1587
1588 /*
1589 * Add it to the IO-APIC irq-routing table:
1590 */
cf4c6a2f 1591 ioapic_write_entry(apic, pin, entry);
1da177e4
LT		 1592}
1593
32f71aff
MR		 1594
1595__apicdebuginit(void) print_IO_APIC(void)
1da177e4
LT		 1596{
1597 int apic, i;
1598 union IO_APIC_reg_00 reg_00;
1599 union IO_APIC_reg_01 reg_01;
1600 union IO_APIC_reg_02 reg_02;
1601 union IO_APIC_reg_03 reg_03;
1602 unsigned long flags;
0f978f45 1603 struct irq_cfg *cfg;
8f09cd20 1604 unsigned int irq;
1da177e4
LT		 1605
1606 if (apic_verbosity == APIC_QUIET)
1607 return;
1608
36062448 1609 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1da177e4
LT		 1610 for (i = 0; i < nr_ioapics; i++)
1611 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
ec2cd0a2 1612 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1da177e4
LT		 1613
1614 /*
1615 * We are a bit conservative about what we expect. We have to
1616 * know about every hardware change ASAP.
1617 */
1618 printk(KERN_INFO "testing the IO APIC.......................\n");
1619
1620 for (apic = 0; apic < nr_ioapics; apic++) {
1621
1622 spin_lock_irqsave(&ioapic_lock, flags);
1623 reg_00.raw = io_apic_read(apic, 0);
1624 reg_01.raw = io_apic_read(apic, 1);
1625 if (reg_01.bits.version >= 0x10)
1626 reg_02.raw = io_apic_read(apic, 2);
54168ed7
IM		 1627 if (reg_01.bits.version >= 0x20)
1628 reg_03.raw = io_apic_read(apic, 3);
1da177e4
LT		 1629 spin_unlock_irqrestore(&ioapic_lock, flags);
1630
54168ed7 1631 printk("\n");
ec2cd0a2 1632 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1da177e4
LT		 1633 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1634 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1635 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1636 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1da177e4 1637
54168ed7 1638 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1da177e4 1639 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1da177e4
LT		 1640
1641 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1642 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1da177e4
LT		 1643
1644 /*
1645 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1646 * but the value of reg_02 is read as the previous read register
1647 * value, so ignore it if reg_02 == reg_01.
1648 */
1649 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1650 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1651 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1da177e4
LT		 1652 }
1653
1654 /*
1655 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1656 * or reg_03, but the value of reg_0[23] is read as the previous read
1657 * register value, so ignore it if reg_03 == reg_0[12].
1658 */
1659 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1660 reg_03.raw != reg_01.raw) {
1661 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1662 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1da177e4
LT		 1663 }
1664
1665 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1666
d83e94ac
YL		 1667 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1668 " Stat Dmod Deli Vect: \n");
1da177e4
LT		 1669
1670 for (i = 0; i <= reg_01.bits.entries; i++) {
1671 struct IO_APIC_route_entry entry;
1672
cf4c6a2f 1673 entry = ioapic_read_entry(apic, i);
1da177e4 1674
54168ed7
IM		 1675 printk(KERN_DEBUG " %02x %03X ",
1676 i,
1677 entry.dest
1678 );
1da177e4
LT		 1679
1680 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1681 entry.mask,
1682 entry.trigger,
1683 entry.irr,
1684 entry.polarity,
1685 entry.delivery_status,
1686 entry.dest_mode,
1687 entry.delivery_mode,
1688 entry.vector
1689 );
1690 }
1691 }
1da177e4 1692 printk(KERN_DEBUG "IRQ to pin mappings:\n");
8f09cd20 1693 for_each_irq_cfg(irq, cfg) {
0f978f45
YL		 1694 struct irq_pin_list *entry = cfg->irq_2_pin;
1695 if (!entry)
1da177e4 1696 continue;
8f09cd20 1697 printk(KERN_DEBUG "IRQ%d ", irq);
1da177e4
LT		 1698 for (;;) {
1699 printk("-> %d:%d", entry->apic, entry->pin);
1700 if (!entry->next)
1701 break;
0f978f45 1702 entry = entry->next;
1da177e4
LT		 1703 }
1704 printk("\n");
1705 }
1706
1707 printk(KERN_INFO ".................................... done.\n");
1708
1709 return;
1710}
1711
32f71aff 1712__apicdebuginit(void) print_APIC_bitfield(int base)
1da177e4
LT		 1713{
1714 unsigned int v;
1715 int i, j;
1716
1717 if (apic_verbosity == APIC_QUIET)
1718 return;
1719
1720 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1721 for (i = 0; i < 8; i++) {
1722 v = apic_read(base + i*0x10);
1723 for (j = 0; j < 32; j++) {
1724 if (v & (1<<j))
1725 printk("1");
1726 else
1727 printk("0");
1728 }
1729 printk("\n");
1730 }
1731}
1732
32f71aff 1733__apicdebuginit(void) print_local_APIC(void *dummy)
1da177e4
LT		 1734{
1735 unsigned int v, ver, maxlvt;
7ab6af7a 1736 u64 icr;
1da177e4
LT		 1737
1738 if (apic_verbosity == APIC_QUIET)
1739 return;
1740
1741 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1742 smp_processor_id(), hard_smp_processor_id());
66823114 1743 v = apic_read(APIC_ID);
54168ed7 1744 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1da177e4
LT		 1745 v = apic_read(APIC_LVR);
1746 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1747 ver = GET_APIC_VERSION(v);
e05d723f 1748 maxlvt = lapic_get_maxlvt();
1da177e4
LT		 1749
1750 v = apic_read(APIC_TASKPRI);
1751 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1752
54168ed7 1753 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1da177e4
LT		 1754 v = apic_read(APIC_ARBPRI);
1755 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1756 v & APIC_ARBPRI_MASK);
1757 v = apic_read(APIC_PROCPRI);
1758 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1759 }
1760
1761 v = apic_read(APIC_EOI);
1762 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1763 v = apic_read(APIC_RRR);
1764 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1765 v = apic_read(APIC_LDR);
1766 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1767 v = apic_read(APIC_DFR);
1768 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1769 v = apic_read(APIC_SPIV);
1770 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1771
1772 printk(KERN_DEBUG "... APIC ISR field:\n");
1773 print_APIC_bitfield(APIC_ISR);
1774 printk(KERN_DEBUG "... APIC TMR field:\n");
1775 print_APIC_bitfield(APIC_TMR);
1776 printk(KERN_DEBUG "... APIC IRR field:\n");
1777 print_APIC_bitfield(APIC_IRR);
1778
54168ed7
IM		 1779 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1780 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1da177e4 1781 apic_write(APIC_ESR, 0);
54168ed7 1782
1da177e4
LT		 1783 v = apic_read(APIC_ESR);
1784 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1785 }
1786
7ab6af7a 1787 icr = apic_icr_read();
0c425cec
IM		 1788 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1789 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1da177e4
LT		 1790
1791 v = apic_read(APIC_LVTT);
1792 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1793
1794 if (maxlvt > 3) { /* PC is LVT#4. */
1795 v = apic_read(APIC_LVTPC);
1796 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1797 }
1798 v = apic_read(APIC_LVT0);
1799 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1800 v = apic_read(APIC_LVT1);
1801 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1802
1803 if (maxlvt > 2) { /* ERR is LVT#3. */
1804 v = apic_read(APIC_LVTERR);
1805 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1806 }
1807
1808 v = apic_read(APIC_TMICT);
1809 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1810 v = apic_read(APIC_TMCCT);
1811 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1812 v = apic_read(APIC_TDCR);
1813 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1814 printk("\n");
1815}
1816
32f71aff 1817__apicdebuginit(void) print_all_local_APICs(void)
1da177e4 1818{
ffd5aae7
YL		 1819 int cpu;
1820
1821 preempt_disable();
1822 for_each_online_cpu(cpu)
1823 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1824 preempt_enable();
1da177e4
LT		 1825}
1826
32f71aff 1827__apicdebuginit(void) print_PIC(void)
1da177e4 1828{
1da177e4
LT		 1829 unsigned int v;
1830 unsigned long flags;
1831
1832 if (apic_verbosity == APIC_QUIET)
1833 return;
1834
1835 printk(KERN_DEBUG "\nprinting PIC contents\n");
1836
1837 spin_lock_irqsave(&i8259A_lock, flags);
1838
1839 v = inb(0xa1) << 8 | inb(0x21);
1840 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1841
1842 v = inb(0xa0) << 8 | inb(0x20);
1843 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1844
54168ed7
IM		 1845 outb(0x0b,0xa0);
1846 outb(0x0b,0x20);
1da177e4 1847 v = inb(0xa0) << 8 | inb(0x20);
54168ed7
IM		 1848 outb(0x0a,0xa0);
1849 outb(0x0a,0x20);
1da177e4
LT		 1850
1851 spin_unlock_irqrestore(&i8259A_lock, flags);
1852
1853 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1854
1855 v = inb(0x4d1) << 8 | inb(0x4d0);
1856 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1857}
1858
32f71aff
MR		 1859__apicdebuginit(int) print_all_ICs(void)
1860{
1861 print_PIC();
1862 print_all_local_APICs();
1863 print_IO_APIC();
1864
1865 return 0;
1866}
1867
1868fs_initcall(print_all_ICs);
1869
1da177e4 1870
efa2559f
YL		 1871/* Where if anywhere is the i8259 connect in external int mode */
1872static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1873
54168ed7 1874void __init enable_IO_APIC(void)
1da177e4
LT		 1875{
1876 union IO_APIC_reg_01 reg_01;
fcfd636a 1877 int i8259_apic, i8259_pin;
54168ed7 1878 int apic;
1da177e4
LT		 1879 unsigned long flags;
1880
54168ed7
IM		 1881#ifdef CONFIG_X86_32
1882 int i;
1da177e4
LT		 1883 if (!pirqs_enabled)
1884 for (i = 0; i < MAX_PIRQS; i++)
1885 pirq_entries[i] = -1;
54168ed7 1886#endif
1da177e4
LT		 1887
1888 /*
1889 * The number of IO-APIC IRQ registers (== #pins):
1890 */
fcfd636a 1891 for (apic = 0; apic < nr_ioapics; apic++) {
1da177e4 1892 spin_lock_irqsave(&ioapic_lock, flags);
fcfd636a 1893 reg_01.raw = io_apic_read(apic, 1);
1da177e4 1894 spin_unlock_irqrestore(&ioapic_lock, flags);
fcfd636a
EB		 1895 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1896 }
54168ed7 1897 for(apic = 0; apic < nr_ioapics; apic++) {
fcfd636a
EB		 1898 int pin;
1899 /* See if any of the pins is in ExtINT mode */
1008fddc 1900 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
fcfd636a 1901 struct IO_APIC_route_entry entry;
cf4c6a2f 1902 entry = ioapic_read_entry(apic, pin);
fcfd636a 1903
fcfd636a
EB		 1904 /* If the interrupt line is enabled and in ExtInt mode
1905 * I have found the pin where the i8259 is connected.
1906 */
1907 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1908 ioapic_i8259.apic = apic;
1909 ioapic_i8259.pin = pin;
1910 goto found_i8259;
1911 }
1912 }
1913 }
1914 found_i8259:
1915 /* Look to see what if the MP table has reported the ExtINT */
1916 /* If we could not find the appropriate pin by looking at the ioapic
1917 * the i8259 probably is not connected the ioapic but give the
1918 * mptable a chance anyway.
1919 */
1920 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1921 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1922 /* Trust the MP table if nothing is setup in the hardware */
1923 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1924 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1925 ioapic_i8259.pin = i8259_pin;
1926 ioapic_i8259.apic = i8259_apic;
1927 }
1928 /* Complain if the MP table and the hardware disagree */
1929 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1930 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1931 {
1932 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1da177e4
LT		 1933 }
1934
1935 /*
1936 * Do not trust the IO-APIC being empty at bootup
1937 */
1938 clear_IO_APIC();
1939}
1940
1941/*
1942 * Not an __init, needed by the reboot code
1943 */
1944void disable_IO_APIC(void)
1945{
1946 /*
1947 * Clear the IO-APIC before rebooting:
1948 */
1949 clear_IO_APIC();
1950
650927ef 1951 /*
0b968d23 1952 * If the i8259 is routed through an IOAPIC
650927ef 1953 * Put that IOAPIC in virtual wire mode
0b968d23 1954 * so legacy interrupts can be delivered.
650927ef 1955 */
fcfd636a 1956 if (ioapic_i8259.pin != -1) {
650927ef 1957 struct IO_APIC_route_entry entry;
650927ef
EB		 1958
1959 memset(&entry, 0, sizeof(entry));
1960 entry.mask = 0; /* Enabled */
1961 entry.trigger = 0; /* Edge */
1962 entry.irr = 0;
1963 entry.polarity = 0; /* High */
1964 entry.delivery_status = 0;
1965 entry.dest_mode = 0; /* Physical */
fcfd636a 1966 entry.delivery_mode = dest_ExtINT; /* ExtInt */
650927ef 1967 entry.vector = 0;
54168ed7 1968 entry.dest = read_apic_id();
650927ef
EB		 1969
1970 /*
1971 * Add it to the IO-APIC irq-routing table:
1972 */
cf4c6a2f 1973 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
650927ef 1974 }
54168ed7 1975
fcfd636a 1976 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1da177e4
LT		 1977}
1978
54168ed7 1979#ifdef CONFIG_X86_32
1da177e4
LT		 1980/*
1981 * function to set the IO-APIC physical IDs based on the
1982 * values stored in the MPC table.
1983 *
1984 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1985 */
1986
1da177e4
LT		 1987static void __init setup_ioapic_ids_from_mpc(void)
1988{
1989 union IO_APIC_reg_00 reg_00;
1990 physid_mask_t phys_id_present_map;
1991 int apic;
1992 int i;
1993 unsigned char old_id;
1994 unsigned long flags;
1995
a4dbc34d 1996 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
d49c4288 1997 return;
d49c4288 1998
ca05fea6
NP		 1999 /*
2000 * Don't check I/O APIC IDs for xAPIC systems. They have
2001 * no meaning without the serial APIC bus.
2002 */
7c5c1e42
SL		 2003 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2004 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
ca05fea6 2005 return;
1da177e4
LT		 2006 /*
2007 * This is broken; anything with a real cpu count has to
2008 * circumvent this idiocy regardless.
2009 */
2010 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
2011
2012 /*
2013 * Set the IOAPIC ID to the value stored in the MPC table.
2014 */
2015 for (apic = 0; apic < nr_ioapics; apic++) {
2016
2017 /* Read the register 0 value */
2018 spin_lock_irqsave(&ioapic_lock, flags);
2019 reg_00.raw = io_apic_read(apic, 0);
2020 spin_unlock_irqrestore(&ioapic_lock, flags);
36062448 2021
ec2cd0a2 2022 old_id = mp_ioapics[apic].mp_apicid;
1da177e4 2023
ec2cd0a2 2024 if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) {
1da177e4 2025 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
ec2cd0a2 2026 apic, mp_ioapics[apic].mp_apicid);
1da177e4
LT		 2027 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2028 reg_00.bits.ID);
ec2cd0a2 2029 mp_ioapics[apic].mp_apicid = reg_00.bits.ID;
1da177e4
LT		 2030 }
2031
1da177e4
LT		 2032 /*
2033 * Sanity check, is the ID really free? Every APIC in a
2034 * system must have a unique ID or we get lots of nice
2035 * 'stuck on smp_invalidate_needed IPI wait' messages.
2036 */
2037 if (check_apicid_used(phys_id_present_map,
ec2cd0a2 2038 mp_ioapics[apic].mp_apicid)) {
1da177e4 2039 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
ec2cd0a2 2040 apic, mp_ioapics[apic].mp_apicid);
1da177e4
LT		 2041 for (i = 0; i < get_physical_broadcast(); i++)
2042 if (!physid_isset(i, phys_id_present_map))
2043 break;
2044 if (i >= get_physical_broadcast())
2045 panic("Max APIC ID exceeded!\n");
2046 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2047 i);
2048 physid_set(i, phys_id_present_map);
ec2cd0a2 2049 mp_ioapics[apic].mp_apicid = i;
1da177e4
LT		 2050 } else {
2051 physid_mask_t tmp;
ec2cd0a2 2052 tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid);
1da177e4
LT		 2053 apic_printk(APIC_VERBOSE, "Setting %d in the "
2054 "phys_id_present_map\n",
ec2cd0a2 2055 mp_ioapics[apic].mp_apicid);
1da177e4
LT		 2056 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2057 }
2058
2059
2060 /*
2061 * We need to adjust the IRQ routing table
2062 * if the ID changed.
2063 */
ec2cd0a2 2064 if (old_id != mp_ioapics[apic].mp_apicid)
1da177e4 2065 for (i = 0; i < mp_irq_entries; i++)
2fddb6e2
AS		 2066 if (mp_irqs[i].mp_dstapic == old_id)
2067 mp_irqs[i].mp_dstapic
ec2cd0a2 2068 = mp_ioapics[apic].mp_apicid;
1da177e4
LT		 2069
2070 /*
2071 * Read the right value from the MPC table and
2072 * write it into the ID register.
36062448 2073 */
1da177e4
LT		 2074 apic_printk(APIC_VERBOSE, KERN_INFO
2075 "...changing IO-APIC physical APIC ID to %d ...",
ec2cd0a2 2076 mp_ioapics[apic].mp_apicid);
1da177e4 2077
ec2cd0a2 2078 reg_00.bits.ID = mp_ioapics[apic].mp_apicid;
1da177e4 2079 spin_lock_irqsave(&ioapic_lock, flags);
a2d332fa
YL		 2080 io_apic_write(apic, 0, reg_00.raw);
2081 spin_unlock_irqrestore(&ioapic_lock, flags);
1da177e4
LT		 2082
2083 /*
2084 * Sanity check
2085 */
2086 spin_lock_irqsave(&ioapic_lock, flags);
2087 reg_00.raw = io_apic_read(apic, 0);
2088 spin_unlock_irqrestore(&ioapic_lock, flags);
ec2cd0a2 2089 if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid)
1da177e4
LT		 2090 printk("could not set ID!\n");
2091 else
2092 apic_printk(APIC_VERBOSE, " ok.\n");
2093 }
2094}
54168ed7 2095#endif
1da177e4 2096
7ce0bcfd 2097int no_timer_check __initdata;
8542b200
ZA		 2098
2099static int __init notimercheck(char *s)
2100{
2101 no_timer_check = 1;
2102 return 1;
2103}
2104__setup("no_timer_check", notimercheck);
2105
1da177e4
LT		 2106/*
2107 * There is a nasty bug in some older SMP boards, their mptable lies
2108 * about the timer IRQ. We do the following to work around the situation:
2109 *
2110 * - timer IRQ defaults to IO-APIC IRQ
2111 * - if this function detects that timer IRQs are defunct, then we fall
2112 * back to ISA timer IRQs
2113 */
f0a7a5c9 2114static int __init timer_irq_works(void)
1da177e4
LT		 2115{
2116 unsigned long t1 = jiffies;
4aae0702 2117 unsigned long flags;
1da177e4 2118
8542b200
ZA		 2119 if (no_timer_check)
2120 return 1;
2121
4aae0702 2122 local_save_flags(flags);
1da177e4
LT		 2123 local_irq_enable();
2124 /* Let ten ticks pass... */
2125 mdelay((10 * 1000) / HZ);
4aae0702 2126 local_irq_restore(flags);
1da177e4
LT		 2127
2128 /*
2129 * Expect a few ticks at least, to be sure some possible
2130 * glue logic does not lock up after one or two first
2131 * ticks in a non-ExtINT mode. Also the local APIC
2132 * might have cached one ExtINT interrupt. Finally, at
2133 * least one tick may be lost due to delays.
2134 */
54168ed7
IM		 2135
2136 /* jiffies wrap? */
1d16b53e 2137 if (time_after(jiffies, t1 + 4))
1da177e4 2138 return 1;
1da177e4
LT		 2139 return 0;
2140}
2141
2142/*
2143 * In the SMP+IOAPIC case it might happen that there are an unspecified
2144 * number of pending IRQ events unhandled. These cases are very rare,
2145 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2146 * better to do it this way as thus we do not have to be aware of
2147 * 'pending' interrupts in the IRQ path, except at this point.
2148 */
2149/*
2150 * Edge triggered needs to resend any interrupt
2151 * that was delayed but this is now handled in the device
2152 * independent code.
2153 */
2154
2155/*
2156 * Starting up a edge-triggered IO-APIC interrupt is
2157 * nasty - we need to make sure that we get the edge.
2158 * If it is already asserted for some reason, we need
2159 * return 1 to indicate that is was pending.
2160 *
2161 * This is not complete - we should be able to fake
2162 * an edge even if it isn't on the 8259A...
2163 */
54168ed7 2164
f5b9ed7a 2165static unsigned int startup_ioapic_irq(unsigned int irq)
1da177e4
LT		 2166{
2167 int was_pending = 0;
2168 unsigned long flags;
2169
2170 spin_lock_irqsave(&ioapic_lock, flags);
2171 if (irq < 16) {
2172 disable_8259A_irq(irq);
2173 if (i8259A_irq_pending(irq))
2174 was_pending = 1;
2175 }
2176 __unmask_IO_APIC_irq(irq);
2177 spin_unlock_irqrestore(&ioapic_lock, flags);
2178
2179 return was_pending;
2180}
2181
54168ed7 2182#ifdef CONFIG_X86_64
ace80ab7 2183static int ioapic_retrigger_irq(unsigned int irq)
1da177e4 2184{
54168ed7
IM		 2185
2186 struct irq_cfg *cfg = irq_cfg(irq);
2187 unsigned long flags;
2188
2189 spin_lock_irqsave(&vector_lock, flags);
2190 send_IPI_mask(cpumask_of_cpu(first_cpu(cfg->domain)), cfg->vector);
2191 spin_unlock_irqrestore(&vector_lock, flags);
c0ad90a3
IM		 2192
2193 return 1;
2194}
54168ed7
IM		 2195#else
2196static int ioapic_retrigger_irq(unsigned int irq)
497c9a19 2197{
54168ed7 2198 send_IPI_self(irq_cfg(irq)->vector);
497c9a19 2199
54168ed7
IM		 2200 return 1;
2201}
2202#endif
497c9a19 2203
54168ed7
IM		 2204/*
2205 * Level and edge triggered IO-APIC interrupts need different handling,
2206 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2207 * handled with the level-triggered descriptor, but that one has slightly
2208 * more overhead. Level-triggered interrupts cannot be handled with the
2209 * edge-triggered handler, without risking IRQ storms and other ugly
2210 * races.
2211 */
497c9a19 2212
54168ed7 2213#ifdef CONFIG_SMP
497c9a19 2214
54168ed7
IM		 2215#ifdef CONFIG_INTR_REMAP
2216static void ir_irq_migration(struct work_struct *work);
497c9a19 2217
54168ed7 2218static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration);
497c9a19 2219
54168ed7
IM		 2220/*
2221 * Migrate the IO-APIC irq in the presence of intr-remapping.
2222 *
2223 * For edge triggered, irq migration is a simple atomic update(of vector
2224 * and cpu destination) of IRTE and flush the hardware cache.
2225 *
2226 * For level triggered, we need to modify the io-apic RTE aswell with the update
2227 * vector information, along with modifying IRTE with vector and destination.
2228 * So irq migration for level triggered is little bit more complex compared to
2229 * edge triggered migration. But the good news is, we use the same algorithm
2230 * for level triggered migration as we have today, only difference being,
2231 * we now initiate the irq migration from process context instead of the
2232 * interrupt context.
2233 *
2234 * In future, when we do a directed EOI (combined with cpu EOI broadcast
2235 * suppression) to the IO-APIC, level triggered irq migration will also be
2236 * as simple as edge triggered migration and we can do the irq migration
2237 * with a simple atomic update to IO-APIC RTE.
2238 */
2239static void migrate_ioapic_irq(int irq, cpumask_t mask)
497c9a19 2240{
54168ed7
IM		 2241 struct irq_cfg *cfg;
2242 struct irq_desc *desc;
2243 cpumask_t tmp, cleanup_mask;
2244 struct irte irte;
2245 int modify_ioapic_rte;
2246 unsigned int dest;
2247 unsigned long flags;
497c9a19 2248
54168ed7
IM		 2249 cpus_and(tmp, mask, cpu_online_map);
2250 if (cpus_empty(tmp))
497c9a19
YL		 2251 return;
2252
54168ed7
IM		 2253 if (get_irte(irq, &irte))
2254 return;
497c9a19 2255
54168ed7
IM		 2256 if (assign_irq_vector(irq, mask))
2257 return;
2258
2259 cfg = irq_cfg(irq);
2260 cpus_and(tmp, cfg->domain, mask);
2261 dest = cpu_mask_to_apicid(tmp);
2262
2263 desc = irq_to_desc(irq);
2264 modify_ioapic_rte = desc->status & IRQ_LEVEL;
2265 if (modify_ioapic_rte) {
2266 spin_lock_irqsave(&ioapic_lock, flags);
2267 __target_IO_APIC_irq(irq, dest, cfg->vector);
2268 spin_unlock_irqrestore(&ioapic_lock, flags);
2269 }
2270
2271 irte.vector = cfg->vector;
2272 irte.dest_id = IRTE_DEST(dest);
2273
2274 /*
2275 * Modified the IRTE and flushes the Interrupt entry cache.
2276 */
2277 modify_irte(irq, &irte);
2278
2279 if (cfg->move_in_progress) {
2280 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2281 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2282 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2283 cfg->move_in_progress = 0;
2284 }
2285
2286 desc->affinity = mask;
2287}
2288
2289static int migrate_irq_remapped_level(int irq)
2290{
2291 int ret = -1;
2292 struct irq_desc *desc = irq_to_desc(irq);
2293
2294 mask_IO_APIC_irq(irq);
2295
2296 if (io_apic_level_ack_pending(irq)) {
2297 /*
2298 * Interrupt in progress. Migrating irq now will change the
2299 * vector information in the IO-APIC RTE and that will confuse
2300 * the EOI broadcast performed by cpu.
2301 * So, delay the irq migration to the next instance.
2302 */
2303 schedule_delayed_work(&ir_migration_work, 1);
2304 goto unmask;
2305 }
2306
2307 /* everthing is clear. we have right of way */
2308 migrate_ioapic_irq(irq, desc->pending_mask);
2309
2310 ret = 0;
2311 desc->status &= ~IRQ_MOVE_PENDING;
2312 cpus_clear(desc->pending_mask);
2313
2314unmask:
2315 unmask_IO_APIC_irq(irq);
2316 return ret;
2317}
2318
2319static void ir_irq_migration(struct work_struct *work)
2320{
2321 unsigned int irq;
2322 struct irq_desc *desc;
2323
2324 for_each_irq_desc(irq, desc) {
2325 if (desc->status & IRQ_MOVE_PENDING) {
2326 unsigned long flags;
2327
2328 spin_lock_irqsave(&desc->lock, flags);
2329 if (!desc->chip->set_affinity ||
2330 !(desc->status & IRQ_MOVE_PENDING)) {
2331 desc->status &= ~IRQ_MOVE_PENDING;
2332 spin_unlock_irqrestore(&desc->lock, flags);
2333 continue;
2334 }
2335
2336 desc->chip->set_affinity(irq, desc->pending_mask);
2337 spin_unlock_irqrestore(&desc->lock, flags);
2338 }
2339 }
2340}
2341
2342/*
2343 * Migrates the IRQ destination in the process context.
2344 */
2345static void set_ir_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
2346{
2347 struct irq_desc *desc = irq_to_desc(irq);
2348
2349 if (desc->status & IRQ_LEVEL) {
2350 desc->status |= IRQ_MOVE_PENDING;
2351 desc->pending_mask = mask;
2352 migrate_irq_remapped_level(irq);
2353 return;
2354 }
2355
2356 migrate_ioapic_irq(irq, mask);
2357}
2358#endif
2359
2360asmlinkage void smp_irq_move_cleanup_interrupt(void)
2361{
2362 unsigned vector, me;
2363 ack_APIC_irq();
2364#ifdef CONFIG_X86_64
2365 exit_idle();
2366#endif
2367 irq_enter();
2368
2369 me = smp_processor_id();
2370 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2371 unsigned int irq;
2372 struct irq_desc *desc;
2373 struct irq_cfg *cfg;
2374 irq = __get_cpu_var(vector_irq)[vector];
2375
2376 desc = irq_to_desc(irq);
2377 if (!desc)
2378 continue;
2379
2380 cfg = irq_cfg(irq);
2381 spin_lock(&desc->lock);
2382 if (!cfg->move_cleanup_count)
2383 goto unlock;
2384
2385 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
2386 goto unlock;
2387
2388 __get_cpu_var(vector_irq)[vector] = -1;
2389 cfg->move_cleanup_count--;
2390unlock:
2391 spin_unlock(&desc->lock);
2392 }
2393
2394 irq_exit();
2395}
2396
2397static void irq_complete_move(unsigned int irq)
2398{
2399 struct irq_cfg *cfg = irq_cfg(irq);
2400 unsigned vector, me;
2401
2402 if (likely(!cfg->move_in_progress))
2403 return;
2404
2405 vector = ~get_irq_regs()->orig_ax;
2406 me = smp_processor_id();
2407 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
2408 cpumask_t cleanup_mask;
2409
2410 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2411 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2412 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
497c9a19
YL		 2413 cfg->move_in_progress = 0;
2414 }
2415}
2416#else
2417static inline void irq_complete_move(unsigned int irq) {}
2418#endif
54168ed7
IM		 2419#ifdef CONFIG_INTR_REMAP
2420static void ack_x2apic_level(unsigned int irq)
2421{
2422 ack_x2APIC_irq();
2423}
2424
2425static void ack_x2apic_edge(unsigned int irq)
2426{
2427 ack_x2APIC_irq();
2428}
2429#endif
497c9a19 2430
1d025192
YL		 2431static void ack_apic_edge(unsigned int irq)
2432{
2433 irq_complete_move(irq);
2434 move_native_irq(irq);
2435 ack_APIC_irq();
2436}
2437
3eb2cce8
YL		 2438#ifdef CONFIG_X86_32
2439atomic_t irq_mis_count;
2440#endif
2441
047c8fdb
YL		 2442static void ack_apic_level(unsigned int irq)
2443{
3eb2cce8
YL		 2444#ifdef CONFIG_X86_32
2445 unsigned long v;
2446 int i;
2447#endif
54168ed7 2448 int do_unmask_irq = 0;
047c8fdb 2449
54168ed7 2450 irq_complete_move(irq);
047c8fdb 2451#ifdef CONFIG_GENERIC_PENDING_IRQ
54168ed7
IM		 2452 /* If we are moving the irq we need to mask it */
2453 if (unlikely(irq_to_desc(irq)->status & IRQ_MOVE_PENDING)) {
2454 do_unmask_irq = 1;
2455 mask_IO_APIC_irq(irq);
2456 }
047c8fdb
YL		 2457#endif
2458
3eb2cce8
YL		 2459#ifdef CONFIG_X86_32
2460 /*
2461 * It appears there is an erratum which affects at least version 0x11
2462 * of I/O APIC (that's the 82093AA and cores integrated into various
2463 * chipsets). Under certain conditions a level-triggered interrupt is
2464 * erroneously delivered as edge-triggered one but the respective IRR
2465 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2466 * message but it will never arrive and further interrupts are blocked
2467 * from the source. The exact reason is so far unknown, but the
2468 * phenomenon was observed when two consecutive interrupt requests
2469 * from a given source get delivered to the same CPU and the source is
2470 * temporarily disabled in between.
2471 *
2472 * A workaround is to simulate an EOI message manually. We achieve it
2473 * by setting the trigger mode to edge and then to level when the edge
2474 * trigger mode gets detected in the TMR of a local APIC for a
2475 * level-triggered interrupt. We mask the source for the time of the
2476 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2477 * The idea is from Manfred Spraul. --macro
2478 */
2479 i = irq_cfg(irq)->vector;
2480
2481 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2482#endif
2483
54168ed7
IM		 2484 /*
2485 * We must acknowledge the irq before we move it or the acknowledge will
2486 * not propagate properly.
2487 */
2488 ack_APIC_irq();
2489
2490 /* Now we can move and renable the irq */
2491 if (unlikely(do_unmask_irq)) {
2492 /* Only migrate the irq if the ack has been received.
2493 *
2494 * On rare occasions the broadcast level triggered ack gets
2495 * delayed going to ioapics, and if we reprogram the
2496 * vector while Remote IRR is still set the irq will never
2497 * fire again.
2498 *
2499 * To prevent this scenario we read the Remote IRR bit
2500 * of the ioapic. This has two effects.
2501 * - On any sane system the read of the ioapic will
2502 * flush writes (and acks) going to the ioapic from
2503 * this cpu.
2504 * - We get to see if the ACK has actually been delivered.
2505 *
2506 * Based on failed experiments of reprogramming the
2507 * ioapic entry from outside of irq context starting
2508 * with masking the ioapic entry and then polling until
2509 * Remote IRR was clear before reprogramming the
2510 * ioapic I don't trust the Remote IRR bit to be
2511 * completey accurate.
2512 *
2513 * However there appears to be no other way to plug
2514 * this race, so if the Remote IRR bit is not
2515 * accurate and is causing problems then it is a hardware bug
2516 * and you can go talk to the chipset vendor about it.
2517 */
2518 if (!io_apic_level_ack_pending(irq))
2519 move_masked_irq(irq);
2520 unmask_IO_APIC_irq(irq);
2521 }
1d025192 2522
3eb2cce8 2523#ifdef CONFIG_X86_32
1d025192
YL		 2524 if (!(v & (1 << (i & 0x1f)))) {
2525 atomic_inc(&irq_mis_count);
2526 spin_lock(&ioapic_lock);
2527 __mask_and_edge_IO_APIC_irq(irq);
2528 __unmask_and_level_IO_APIC_irq(irq);
2529 spin_unlock(&ioapic_lock);
2530 }
047c8fdb 2531#endif
3eb2cce8 2532}
1d025192 2533
f5b9ed7a
IM		 2534static struct irq_chip ioapic_chip __read_mostly = {
2535 .name = "IO-APIC",
ace80ab7
EB		 2536 .startup = startup_ioapic_irq,
2537 .mask = mask_IO_APIC_irq,
2538 .unmask = unmask_IO_APIC_irq,
1d025192
YL		 2539 .ack = ack_apic_edge,
2540 .eoi = ack_apic_level,
54d5d424 2541#ifdef CONFIG_SMP
ace80ab7 2542 .set_affinity = set_ioapic_affinity_irq,
54d5d424 2543#endif
ace80ab7 2544 .retrigger = ioapic_retrigger_irq,
1da177e4
LT		 2545};
2546
54168ed7
IM		 2547#ifdef CONFIG_INTR_REMAP
2548static struct irq_chip ir_ioapic_chip __read_mostly = {
2549 .name = "IR-IO-APIC",
2550 .startup = startup_ioapic_irq,
2551 .mask = mask_IO_APIC_irq,
2552 .unmask = unmask_IO_APIC_irq,
2553 .ack = ack_x2apic_edge,
2554 .eoi = ack_x2apic_level,
2555#ifdef CONFIG_SMP
2556 .set_affinity = set_ir_ioapic_affinity_irq,
2557#endif
2558 .retrigger = ioapic_retrigger_irq,
2559};
2560#endif
1da177e4
LT		 2561
2562static inline void init_IO_APIC_traps(void)
2563{
2564 int irq;
08678b08 2565 struct irq_desc *desc;
da51a821 2566 struct irq_cfg *cfg;
1da177e4
LT		 2567
2568 /*
2569 * NOTE! The local APIC isn't very good at handling
2570 * multiple interrupts at the same interrupt level.
2571 * As the interrupt level is determined by taking the
2572 * vector number and shifting that right by 4, we
2573 * want to spread these out a bit so that they don't
2574 * all fall in the same interrupt level.
2575 *
2576 * Also, we've got to be careful not to trash gate
2577 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2578 */
8f09cd20 2579 for_each_irq_cfg(irq, cfg) {
da51a821 2580 if (IO_APIC_IRQ(irq) && !cfg->vector) {
1da177e4
LT		 2581 /*
2582 * Hmm.. We don't have an entry for this,
2583 * so default to an old-fashioned 8259
2584 * interrupt if we can..
2585 */
2586 if (irq < 16)
2587 make_8259A_irq(irq);
08678b08
YL		 2588 else {
2589 desc = irq_to_desc(irq);
1da177e4 2590 /* Strange. Oh, well.. */
08678b08
YL		 2591 desc->chip = &no_irq_chip;
2592 }
1da177e4
LT		 2593 }
2594 }
2595}
2596
f5b9ed7a
IM		 2597/*
2598 * The local APIC irq-chip implementation:
2599 */
1da177e4 2600
36062448 2601static void mask_lapic_irq(unsigned int irq)
1da177e4
LT		 2602{
2603 unsigned long v;
2604
2605 v = apic_read(APIC_LVT0);
593f4a78 2606 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1da177e4
LT		 2607}
2608
36062448 2609static void unmask_lapic_irq(unsigned int irq)
1da177e4 2610{
f5b9ed7a 2611 unsigned long v;
1da177e4 2612
f5b9ed7a 2613 v = apic_read(APIC_LVT0);
593f4a78 2614 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
f5b9ed7a 2615}
1da177e4 2616
54168ed7 2617static void ack_lapic_irq (unsigned int irq)
1d025192
YL		 2618{
2619 ack_APIC_irq();
2620}
2621
f5b9ed7a 2622static struct irq_chip lapic_chip __read_mostly = {
9a1c6192 2623 .name = "local-APIC",
f5b9ed7a
IM		 2624 .mask = mask_lapic_irq,
2625 .unmask = unmask_lapic_irq,
c88ac1df 2626 .ack = ack_lapic_irq,
1da177e4
LT		 2627};
2628
497c9a19 2629static void lapic_register_intr(int irq)
c88ac1df 2630{
08678b08
YL		 2631 struct irq_desc *desc;
2632
2633 desc = irq_to_desc(irq);
2634 desc->status &= ~IRQ_LEVEL;
c88ac1df
MR		 2635 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2636 "edge");
c88ac1df
MR		 2637}
2638
e9427101 2639static void __init setup_nmi(void)
1da177e4
LT		 2640{
2641 /*
36062448 2642 * Dirty trick to enable the NMI watchdog ...
1da177e4
LT		 2643 * We put the 8259A master into AEOI mode and
2644 * unmask on all local APICs LVT0 as NMI.
2645 *
2646 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2647 * is from Maciej W. Rozycki - so we do not have to EOI from
2648 * the NMI handler or the timer interrupt.
36062448 2649 */
1da177e4
LT		 2650 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2651
e9427101 2652 enable_NMI_through_LVT0();
1da177e4
LT		 2653
2654 apic_printk(APIC_VERBOSE, " done.\n");
2655}
2656
2657/*
2658 * This looks a bit hackish but it's about the only one way of sending
2659 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2660 * not support the ExtINT mode, unfortunately. We need to send these
2661 * cycles as some i82489DX-based boards have glue logic that keeps the
2662 * 8259A interrupt line asserted until INTA. --macro
2663 */
28acf285 2664static inline void __init unlock_ExtINT_logic(void)
1da177e4 2665{
fcfd636a 2666 int apic, pin, i;
1da177e4
LT		 2667 struct IO_APIC_route_entry entry0, entry1;
2668 unsigned char save_control, save_freq_select;
1da177e4 2669
fcfd636a 2670 pin = find_isa_irq_pin(8, mp_INT);
956fb531
AB		 2671 if (pin == -1) {
2672 WARN_ON_ONCE(1);
2673 return;
2674 }
fcfd636a 2675 apic = find_isa_irq_apic(8, mp_INT);
956fb531
AB		 2676 if (apic == -1) {
2677 WARN_ON_ONCE(1);
1da177e4 2678 return;
956fb531 2679 }
1da177e4 2680
cf4c6a2f 2681 entry0 = ioapic_read_entry(apic, pin);
fcfd636a 2682 clear_IO_APIC_pin(apic, pin);
1da177e4
LT		 2683
2684 memset(&entry1, 0, sizeof(entry1));
2685
2686 entry1.dest_mode = 0; /* physical delivery */
2687 entry1.mask = 0; /* unmask IRQ now */
d83e94ac 2688 entry1.dest = hard_smp_processor_id();
1da177e4
LT		 2689 entry1.delivery_mode = dest_ExtINT;
2690 entry1.polarity = entry0.polarity;
2691 entry1.trigger = 0;
2692 entry1.vector = 0;
2693
cf4c6a2f 2694 ioapic_write_entry(apic, pin, entry1);
1da177e4
LT		 2695
2696 save_control = CMOS_READ(RTC_CONTROL);
2697 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2698 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2699 RTC_FREQ_SELECT);
2700 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2701
2702 i = 100;
2703 while (i-- > 0) {
2704 mdelay(10);
2705 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2706 i -= 10;
2707 }
2708
2709 CMOS_WRITE(save_control, RTC_CONTROL);
2710 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
fcfd636a 2711 clear_IO_APIC_pin(apic, pin);
1da177e4 2712
cf4c6a2f 2713 ioapic_write_entry(apic, pin, entry0);
1da177e4
LT		 2714}
2715
efa2559f 2716static int disable_timer_pin_1 __initdata;
047c8fdb 2717/* Actually the next is obsolete, but keep it for paranoid reasons -AK */
54168ed7 2718static int __init disable_timer_pin_setup(char *arg)
efa2559f
YL		 2719{
2720 disable_timer_pin_1 = 1;
2721 return 0;
2722}
54168ed7 2723early_param("disable_timer_pin_1", disable_timer_pin_setup);
efa2559f
YL		 2724
2725int timer_through_8259 __initdata;
2726
1da177e4
LT		 2727/*
2728 * This code may look a bit paranoid, but it's supposed to cooperate with
2729 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2730 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2731 * fanatically on his truly buggy board.
54168ed7
IM		 2732 *
2733 * FIXME: really need to revamp this for all platforms.
1da177e4 2734 */
8542b200 2735static inline void __init check_timer(void)
1da177e4 2736{
497c9a19 2737 struct irq_cfg *cfg = irq_cfg(0);
fcfd636a 2738 int apic1, pin1, apic2, pin2;
4aae0702 2739 unsigned long flags;
047c8fdb
YL		 2740 unsigned int ver;
2741 int no_pin1 = 0;
4aae0702
IM		 2742
2743 local_irq_save(flags);
d4d25dec 2744
54168ed7
IM		 2745 ver = apic_read(APIC_LVR);
2746 ver = GET_APIC_VERSION(ver);
6e908947 2747
1da177e4
LT		 2748 /*
2749 * get/set the timer IRQ vector:
2750 */
2751 disable_8259A_irq(0);
497c9a19 2752 assign_irq_vector(0, TARGET_CPUS);
1da177e4
LT		 2753
2754 /*
d11d5794
MR		 2755 * As IRQ0 is to be enabled in the 8259A, the virtual
2756 * wire has to be disabled in the local APIC. Also
2757 * timer interrupts need to be acknowledged manually in
2758 * the 8259A for the i82489DX when using the NMI
2759 * watchdog as that APIC treats NMIs as level-triggered.
2760 * The AEOI mode will finish them in the 8259A
2761 * automatically.
1da177e4 2762 */
593f4a78 2763 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1da177e4 2764 init_8259A(1);
54168ed7 2765#ifdef CONFIG_X86_32
d11d5794 2766 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
54168ed7 2767#endif
1da177e4 2768
fcfd636a
EB		 2769 pin1 = find_isa_irq_pin(0, mp_INT);
2770 apic1 = find_isa_irq_apic(0, mp_INT);
2771 pin2 = ioapic_i8259.pin;
2772 apic2 = ioapic_i8259.apic;
1da177e4 2773
49a66a0b
MR		 2774 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2775 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
497c9a19 2776 cfg->vector, apic1, pin1, apic2, pin2);
1da177e4 2777
691874fa
MR		 2778 /*
2779 * Some BIOS writers are clueless and report the ExtINTA
2780 * I/O APIC input from the cascaded 8259A as the timer
2781 * interrupt input. So just in case, if only one pin
2782 * was found above, try it both directly and through the
2783 * 8259A.
2784 */
2785 if (pin1 == -1) {
54168ed7
IM		 2786#ifdef CONFIG_INTR_REMAP
2787 if (intr_remapping_enabled)
2788 panic("BIOS bug: timer not connected to IO-APIC");
2789#endif
691874fa
MR		 2790 pin1 = pin2;
2791 apic1 = apic2;
2792 no_pin1 = 1;
2793 } else if (pin2 == -1) {
2794 pin2 = pin1;
2795 apic2 = apic1;
2796 }
2797
1da177e4
LT		 2798 if (pin1 != -1) {
2799 /*
2800 * Ok, does IRQ0 through the IOAPIC work?
2801 */
691874fa
MR		 2802 if (no_pin1) {
2803 add_pin_to_irq(0, apic1, pin1);
497c9a19 2804 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
691874fa 2805 }
1da177e4
LT		 2806 unmask_IO_APIC_irq(0);
2807 if (timer_irq_works()) {
2808 if (nmi_watchdog == NMI_IO_APIC) {
1da177e4
LT		 2809 setup_nmi();
2810 enable_8259A_irq(0);
1da177e4 2811 }
66759a01
CE		 2812 if (disable_timer_pin_1 > 0)
2813 clear_IO_APIC_pin(0, pin1);
4aae0702 2814 goto out;
1da177e4 2815 }
54168ed7
IM		 2816#ifdef CONFIG_INTR_REMAP
2817 if (intr_remapping_enabled)
2818 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2819#endif
fcfd636a 2820 clear_IO_APIC_pin(apic1, pin1);
691874fa 2821 if (!no_pin1)
49a66a0b
MR		 2822 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2823 "8254 timer not connected to IO-APIC\n");
1da177e4 2824
49a66a0b
MR		 2825 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2826 "(IRQ0) through the 8259A ...\n");
2827 apic_printk(APIC_QUIET, KERN_INFO
2828 "..... (found apic %d pin %d) ...\n", apic2, pin2);
1da177e4
LT		 2829 /*
2830 * legacy devices should be connected to IO APIC #0
2831 */
691874fa 2832 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
497c9a19 2833 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
24742ece 2834 unmask_IO_APIC_irq(0);
ecd29476 2835 enable_8259A_irq(0);
1da177e4 2836 if (timer_irq_works()) {
49a66a0b 2837 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
35542c5e 2838 timer_through_8259 = 1;
1da177e4 2839 if (nmi_watchdog == NMI_IO_APIC) {
60134ebe 2840 disable_8259A_irq(0);
1da177e4 2841 setup_nmi();
60134ebe 2842 enable_8259A_irq(0);
1da177e4 2843 }
4aae0702 2844 goto out;
1da177e4
LT		 2845 }
2846 /*
2847 * Cleanup, just in case ...
2848 */
ecd29476 2849 disable_8259A_irq(0);
fcfd636a 2850 clear_IO_APIC_pin(apic2, pin2);
49a66a0b 2851 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
1da177e4 2852 }
1da177e4
LT		 2853
2854 if (nmi_watchdog == NMI_IO_APIC) {
49a66a0b
MR		 2855 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2856 "through the IO-APIC - disabling NMI Watchdog!\n");
067fa0ff 2857 nmi_watchdog = NMI_NONE;
1da177e4 2858 }
54168ed7 2859#ifdef CONFIG_X86_32
d11d5794 2860 timer_ack = 0;
54168ed7 2861#endif
1da177e4 2862
49a66a0b
MR		 2863 apic_printk(APIC_QUIET, KERN_INFO
2864 "...trying to set up timer as Virtual Wire IRQ...\n");
1da177e4 2865
497c9a19
YL		 2866 lapic_register_intr(0);
2867 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
1da177e4
LT		 2868 enable_8259A_irq(0);
2869
2870 if (timer_irq_works()) {
49a66a0b 2871 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
4aae0702 2872 goto out;
1da177e4 2873 }
e67465f1 2874 disable_8259A_irq(0);
497c9a19 2875 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
49a66a0b 2876 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
1da177e4 2877
49a66a0b
MR		 2878 apic_printk(APIC_QUIET, KERN_INFO
2879 "...trying to set up timer as ExtINT IRQ...\n");
1da177e4 2880
1da177e4
LT		 2881 init_8259A(0);
2882 make_8259A_irq(0);
593f4a78 2883 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1da177e4
LT		 2884
2885 unlock_ExtINT_logic();
2886
2887 if (timer_irq_works()) {
49a66a0b 2888 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
4aae0702 2889 goto out;
1da177e4 2890 }
49a66a0b 2891 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
1da177e4 2892 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
49a66a0b 2893 "report. Then try booting with the 'noapic' option.\n");
4aae0702
IM		 2894out:
2895 local_irq_restore(flags);
1da177e4
LT		 2896}
2897
2898/*
af174783
MR		 2899 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2900 * to devices. However there may be an I/O APIC pin available for
2901 * this interrupt regardless. The pin may be left unconnected, but
2902 * typically it will be reused as an ExtINT cascade interrupt for
2903 * the master 8259A. In the MPS case such a pin will normally be
2904 * reported as an ExtINT interrupt in the MP table. With ACPI
2905 * there is no provision for ExtINT interrupts, and in the absence
2906 * of an override it would be treated as an ordinary ISA I/O APIC
2907 * interrupt, that is edge-triggered and unmasked by default. We
2908 * used to do this, but it caused problems on some systems because
2909 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2910 * the same ExtINT cascade interrupt to drive the local APIC of the
2911 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2912 * the I/O APIC in all cases now. No actual device should request
2913 * it anyway. --macro
1da177e4
LT		 2914 */
2915#define PIC_IRQS (1 << PIC_CASCADE_IR)
2916
2917void __init setup_IO_APIC(void)
2918{
54168ed7
IM		 2919
2920#ifdef CONFIG_X86_32
1da177e4 2921 enable_IO_APIC();
54168ed7
IM		 2922#else
2923 /*
2924 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2925 */
2926#endif
1da177e4 2927
af174783 2928 io_apic_irqs = ~PIC_IRQS;
1da177e4 2929
54168ed7
IM		 2930 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2931 /*
2932 * Set up IO-APIC IRQ routing.
2933 */
2934#ifdef CONFIG_X86_32
2935 if (!acpi_ioapic)
2936 setup_ioapic_ids_from_mpc();
2937#endif
1da177e4
LT		 2938 sync_Arb_IDs();
2939 setup_IO_APIC_irqs();
2940 init_IO_APIC_traps();
1e4c85f9 2941 check_timer();
1da177e4
LT		 2942}
2943
2944/*
54168ed7
IM		 2945 * Called after all the initialization is done. If we didnt find any
2946 * APIC bugs then we can allow the modify fast path
1da177e4 2947 */
36062448 2948
1da177e4
LT		 2949static int __init io_apic_bug_finalize(void)
2950{
54168ed7
IM		 2951 if (sis_apic_bug == -1)
2952 sis_apic_bug = 0;
2953 return 0;
1da177e4
LT		 2954}
2955
2956late_initcall(io_apic_bug_finalize);
2957
2958struct sysfs_ioapic_data {
2959 struct sys_device dev;
2960 struct IO_APIC_route_entry entry[0];
2961};
54168ed7 2962static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1da177e4 2963
438510f6 2964static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1da177e4
LT		 2965{
2966 struct IO_APIC_route_entry *entry;
2967 struct sysfs_ioapic_data *data;
1da177e4 2968 int i;
36062448 2969
1da177e4
LT		 2970 data = container_of(dev, struct sysfs_ioapic_data, dev);
2971 entry = data->entry;
54168ed7
IM		 2972 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
2973 *entry = ioapic_read_entry(dev->id, i);
1da177e4
LT		 2974
2975 return 0;
2976}
2977
2978static int ioapic_resume(struct sys_device *dev)
2979{
2980 struct IO_APIC_route_entry *entry;
2981 struct sysfs_ioapic_data *data;
2982 unsigned long flags;
2983 union IO_APIC_reg_00 reg_00;
2984 int i;
36062448 2985
1da177e4
LT		 2986 data = container_of(dev, struct sysfs_ioapic_data, dev);
2987 entry = data->entry;
2988
2989 spin_lock_irqsave(&ioapic_lock, flags);
2990 reg_00.raw = io_apic_read(dev->id, 0);
ec2cd0a2
AS		 2991 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
2992 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
1da177e4
LT		 2993 io_apic_write(dev->id, 0, reg_00.raw);
2994 }
1da177e4 2995 spin_unlock_irqrestore(&ioapic_lock, flags);
36062448 2996 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
cf4c6a2f 2997 ioapic_write_entry(dev->id, i, entry[i]);
1da177e4
LT		 2998
2999 return 0;
3000}
3001
3002static struct sysdev_class ioapic_sysdev_class = {
af5ca3f4 3003 .name = "ioapic",
1da177e4
LT		 3004 .suspend = ioapic_suspend,
3005 .resume = ioapic_resume,
3006};
3007
3008static int __init ioapic_init_sysfs(void)
3009{
54168ed7
IM		 3010 struct sys_device * dev;
3011 int i, size, error;
1da177e4
LT		 3012
3013 error = sysdev_class_register(&ioapic_sysdev_class);
3014 if (error)
3015 return error;
3016
54168ed7 3017 for (i = 0; i < nr_ioapics; i++ ) {
36062448 3018 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1da177e4 3019 * sizeof(struct IO_APIC_route_entry);
25556c16 3020 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
1da177e4
LT		 3021 if (!mp_ioapic_data[i]) {
3022 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3023 continue;
3024 }
1da177e4 3025 dev = &mp_ioapic_data[i]->dev;
36062448 3026 dev->id = i;
1da177e4
LT		 3027 dev->cls = &ioapic_sysdev_class;
3028 error = sysdev_register(dev);
3029 if (error) {
3030 kfree(mp_ioapic_data[i]);
3031 mp_ioapic_data[i] = NULL;
3032 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3033 continue;
3034 }
3035 }
3036
3037 return 0;
3038}
3039
3040device_initcall(ioapic_init_sysfs);
3041
3fc471ed 3042/*
95d77884 3043 * Dynamic irq allocate and deallocation
3fc471ed 3044 */
199751d7 3045unsigned int create_irq_nr(unsigned int irq_want)
3fc471ed 3046{
ace80ab7 3047 /* Allocate an unused irq */
54168ed7
IM		 3048 unsigned int irq;
3049 unsigned int new;
3fc471ed 3050 unsigned long flags;
da51a821 3051 struct irq_cfg *cfg_new;
3fc471ed 3052
497c9a19 3053#ifndef CONFIG_HAVE_SPARSE_IRQ
199751d7 3054 irq_want = nr_irqs - 1;
497c9a19 3055#endif
199751d7
YL		 3056
3057 irq = 0;
ace80ab7 3058 spin_lock_irqsave(&vector_lock, flags);
54168ed7 3059 for (new = irq_want; new > 0; new--) {
ace80ab7
EB		 3060 if (platform_legacy_irq(new))
3061 continue;
da51a821
YL		 3062 cfg_new = irq_cfg(new);
3063 if (cfg_new && cfg_new->vector != 0)
ace80ab7 3064 continue;
047c8fdb 3065 /* check if need to create one */
da51a821
YL		 3066 if (!cfg_new)
3067 cfg_new = irq_cfg_alloc(new);
497c9a19 3068 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
ace80ab7
EB		 3069 irq = new;
3070 break;
3071 }
3072 spin_unlock_irqrestore(&vector_lock, flags);
3fc471ed 3073
199751d7 3074 if (irq > 0) {
3fc471ed
EB		 3075 dynamic_irq_init(irq);
3076 }
3077 return irq;
3078}
3079
199751d7
YL		 3080int create_irq(void)
3081{
54168ed7
IM		 3082 int irq;
3083
3084 irq = create_irq_nr(nr_irqs - 1);
3085
3086 if (irq == 0)
3087 irq = -1;
3088
3089 return irq;
199751d7
YL		 3090}
3091
3fc471ed
EB		 3092void destroy_irq(unsigned int irq)
3093{
3094 unsigned long flags;
3fc471ed
EB		 3095
3096 dynamic_irq_cleanup(irq);
3097
54168ed7
IM		 3098#ifdef CONFIG_INTR_REMAP
3099 free_irte(irq);
3100#endif
3fc471ed 3101 spin_lock_irqsave(&vector_lock, flags);
497c9a19 3102 __clear_irq_vector(irq);
3fc471ed
EB		 3103 spin_unlock_irqrestore(&vector_lock, flags);
3104}
3fc471ed 3105
2d3fcc1c 3106/*
27b46d76 3107 * MSI message composition
2d3fcc1c
EB		 3108 */
3109#ifdef CONFIG_PCI_MSI
3b7d1921 3110static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2d3fcc1c 3111{
497c9a19
YL		 3112 struct irq_cfg *cfg;
3113 int err;
2d3fcc1c 3114 unsigned dest;
497c9a19 3115 cpumask_t tmp;
2d3fcc1c 3116
497c9a19
YL		 3117 tmp = TARGET_CPUS;
3118 err = assign_irq_vector(irq, tmp);
3119 if (err)
3120 return err;
2d3fcc1c 3121
497c9a19
YL		 3122 cfg = irq_cfg(irq);
3123 cpus_and(tmp, cfg->domain, tmp);
3124 dest = cpu_mask_to_apicid(tmp);
3125
54168ed7
IM		 3126#ifdef CONFIG_INTR_REMAP
3127 if (irq_remapped(irq)) {
3128 struct irte irte;
3129 int ir_index;
3130 u16 sub_handle;
3131
3132 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3133 BUG_ON(ir_index == -1);
3134
3135 memset (&irte, 0, sizeof(irte));
3136
3137 irte.present = 1;
3138 irte.dst_mode = INT_DEST_MODE;
3139 irte.trigger_mode = 0; /* edge */
3140 irte.dlvry_mode = INT_DELIVERY_MODE;
3141 irte.vector = cfg->vector;
3142 irte.dest_id = IRTE_DEST(dest);
3143
3144 modify_irte(irq, &irte);
3145
3146 msg->address_hi = MSI_ADDR_BASE_HI;
3147 msg->data = sub_handle;
3148 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3149 MSI_ADDR_IR_SHV |
3150 MSI_ADDR_IR_INDEX1(ir_index) |
3151 MSI_ADDR_IR_INDEX2(ir_index);
3152 } else
3153#endif
3154 {
3155 msg->address_hi = MSI_ADDR_BASE_HI;
3156 msg->address_lo =
3157 MSI_ADDR_BASE_LO |
3158 ((INT_DEST_MODE == 0) ?
3159 MSI_ADDR_DEST_MODE_PHYSICAL:
3160 MSI_ADDR_DEST_MODE_LOGICAL) |
3161 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3162 MSI_ADDR_REDIRECTION_CPU:
3163 MSI_ADDR_REDIRECTION_LOWPRI) |
3164 MSI_ADDR_DEST_ID(dest);
497c9a19 3165
54168ed7
IM		 3166 msg->data =
3167 MSI_DATA_TRIGGER_EDGE |
3168 MSI_DATA_LEVEL_ASSERT |
3169 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3170 MSI_DATA_DELIVERY_FIXED:
3171 MSI_DATA_DELIVERY_LOWPRI) |
3172 MSI_DATA_VECTOR(cfg->vector);
3173 }
497c9a19 3174 return err;
2d3fcc1c
EB		 3175}
3176
3b7d1921
EB		 3177#ifdef CONFIG_SMP
3178static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2d3fcc1c 3179{
497c9a19 3180 struct irq_cfg *cfg;
3b7d1921
EB		 3181 struct msi_msg msg;
3182 unsigned int dest;
3183 cpumask_t tmp;
54168ed7 3184 struct irq_desc *desc;
3b7d1921
EB		 3185
3186 cpus_and(tmp, mask, cpu_online_map);
3187 if (cpus_empty(tmp))
497c9a19 3188 return;
2d3fcc1c 3189
497c9a19 3190 if (assign_irq_vector(irq, mask))
3b7d1921 3191 return;
2d3fcc1c 3192
497c9a19
YL		 3193 cfg = irq_cfg(irq);
3194 cpus_and(tmp, cfg->domain, mask);
3195 dest = cpu_mask_to_apicid(tmp);
3b7d1921
EB		 3196
3197 read_msi_msg(irq, &msg);
3198
3199 msg.data &= ~MSI_DATA_VECTOR_MASK;
497c9a19 3200 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3b7d1921
EB		 3201 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3202 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3203
3204 write_msi_msg(irq, &msg);
54168ed7
IM		 3205 desc = irq_to_desc(irq);
3206 desc->affinity = mask;
2d3fcc1c 3207}
54168ed7
IM		 3208
3209#ifdef CONFIG_INTR_REMAP
3210/*
3211 * Migrate the MSI irq to another cpumask. This migration is
3212 * done in the process context using interrupt-remapping hardware.
3213 */
3214static void ir_set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
3215{
3216 struct irq_cfg *cfg;
3217 unsigned int dest;
3218 cpumask_t tmp, cleanup_mask;
3219 struct irte irte;
3220 struct irq_desc *desc;
3221
3222 cpus_and(tmp, mask, cpu_online_map);
3223 if (cpus_empty(tmp))
3224 return;
3225
3226 if (get_irte(irq, &irte))
3227 return;
3228
3229 if (assign_irq_vector(irq, mask))
3230 return;
3231
3232 cfg = irq_cfg(irq);
3233 cpus_and(tmp, cfg->domain, mask);
3234 dest = cpu_mask_to_apicid(tmp);
3235
3236 irte.vector = cfg->vector;
3237 irte.dest_id = IRTE_DEST(dest);
3238
3239 /*
3240 * atomically update the IRTE with the new destination and vector.
3241 */
3242 modify_irte(irq, &irte);
3243
3244 /*
3245 * After this point, all the interrupts will start arriving
3246 * at the new destination. So, time to cleanup the previous
3247 * vector allocation.
3248 */
3249 if (cfg->move_in_progress) {
3250 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
3251 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
3252 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
3253 cfg->move_in_progress = 0;
3254 }
3255
3256 desc = irq_to_desc(irq);
3257 desc->affinity = mask;
3258}
3259#endif
3b7d1921 3260#endif /* CONFIG_SMP */
2d3fcc1c 3261
3b7d1921
EB		 3262/*
3263 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3264 * which implement the MSI or MSI-X Capability Structure.
3265 */
3266static struct irq_chip msi_chip = {
3267 .name = "PCI-MSI",
3268 .unmask = unmask_msi_irq,
3269 .mask = mask_msi_irq,
1d025192 3270 .ack = ack_apic_edge,
3b7d1921
EB		 3271#ifdef CONFIG_SMP
3272 .set_affinity = set_msi_irq_affinity,
3273#endif
3274 .retrigger = ioapic_retrigger_irq,
2d3fcc1c
EB		 3275};
3276
54168ed7
IM		 3277#ifdef CONFIG_INTR_REMAP
3278static struct irq_chip msi_ir_chip = {
3279 .name = "IR-PCI-MSI",
3280 .unmask = unmask_msi_irq,
3281 .mask = mask_msi_irq,
3282 .ack = ack_x2apic_edge,
3283#ifdef CONFIG_SMP
3284 .set_affinity = ir_set_msi_irq_affinity,
3285#endif
3286 .retrigger = ioapic_retrigger_irq,
3287};
3288
3289/*
3290 * Map the PCI dev to the corresponding remapping hardware unit
3291 * and allocate 'nvec' consecutive interrupt-remapping table entries
3292 * in it.
3293 */
3294static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3295{
3296 struct intel_iommu *iommu;
3297 int index;
3298
3299 iommu = map_dev_to_ir(dev);
3300 if (!iommu) {
3301 printk(KERN_ERR
3302 "Unable to map PCI %s to iommu\n", pci_name(dev));
3303 return -ENOENT;
3304 }
3305
3306 index = alloc_irte(iommu, irq, nvec);
3307 if (index < 0) {
3308 printk(KERN_ERR
3309 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3310 pci_name(dev));
3311 return -ENOSPC;
3312 }
3313 return index;
3314}
3315#endif
1d025192
YL		 3316
3317static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc, int irq)
3318{
3319 int ret;
3320 struct msi_msg msg;
3321
3322 ret = msi_compose_msg(dev, irq, &msg);
3323 if (ret < 0)
3324 return ret;
3325
3326 set_irq_msi(irq, desc);
3327 write_msi_msg(irq, &msg);
3328
54168ed7
IM		 3329#ifdef CONFIG_INTR_REMAP
3330 if (irq_remapped(irq)) {
3331 struct irq_desc *desc = irq_to_desc(irq);
3332 /*
3333 * irq migration in process context
3334 */
3335 desc->status |= IRQ_MOVE_PCNTXT;
3336 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3337 } else
3338#endif
3339 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
1d025192
YL		 3340
3341 return 0;
3342}
3343
199751d7
YL		 3344static unsigned int build_irq_for_pci_dev(struct pci_dev *dev)
3345{
3346 unsigned int irq;
3347
3348 irq = dev->bus->number;
3349 irq <<= 8;
3350 irq |= dev->devfn;
3351 irq <<= 12;
3352
3353 return irq;
3354}
3355
f7feaca7 3356int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
3b7d1921 3357{
54168ed7
IM		 3358 unsigned int irq;
3359 int ret;
199751d7
YL		 3360 unsigned int irq_want;
3361
3362 irq_want = build_irq_for_pci_dev(dev) + 0x100;
3363
3364 irq = create_irq_nr(irq_want);
199751d7
YL		 3365 if (irq == 0)
3366 return -1;
f7feaca7 3367
54168ed7
IM		 3368#ifdef CONFIG_INTR_REMAP
3369 if (!intr_remapping_enabled)
3370 goto no_ir;
3371
3372 ret = msi_alloc_irte(dev, irq, 1);
3373 if (ret < 0)
3374 goto error;
3375no_ir:
3376#endif
1d025192 3377 ret = setup_msi_irq(dev, desc, irq);
f7feaca7
EB		 3378 if (ret < 0) {
3379 destroy_irq(irq);
3b7d1921 3380 return ret;
54168ed7 3381 }
7fe3730d 3382 return 0;
54168ed7
IM		 3383
3384#ifdef CONFIG_INTR_REMAP
3385error:
3386 destroy_irq(irq);
3387 return ret;
3388#endif
3b7d1921
EB		 3389}
3390
047c8fdb
YL		 3391int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3392{
54168ed7
IM		 3393 unsigned int irq;
3394 int ret, sub_handle;
3395 struct msi_desc *desc;
3396 unsigned int irq_want;
3397
3398#ifdef CONFIG_INTR_REMAP
3399 struct intel_iommu *iommu = 0;
3400 int index = 0;
3401#endif
3402
3403 irq_want = build_irq_for_pci_dev(dev) + 0x100;
3404 sub_handle = 0;
3405 list_for_each_entry(desc, &dev->msi_list, list) {
3406 irq = create_irq_nr(irq_want--);
3407 if (irq == 0)
3408 return -1;
3409#ifdef CONFIG_INTR_REMAP
3410 if (!intr_remapping_enabled)
3411 goto no_ir;
3412
3413 if (!sub_handle) {
3414 /*
3415 * allocate the consecutive block of IRTE's
3416 * for 'nvec'
3417 */
3418 index = msi_alloc_irte(dev, irq, nvec);
3419 if (index < 0) {
3420 ret = index;
3421 goto error;
3422 }
3423 } else {
3424 iommu = map_dev_to_ir(dev);
3425 if (!iommu) {
3426 ret = -ENOENT;
3427 goto error;
3428 }
3429 /*
3430 * setup the mapping between the irq and the IRTE
3431 * base index, the sub_handle pointing to the
3432 * appropriate interrupt remap table entry.
3433 */
3434 set_irte_irq(irq, iommu, index, sub_handle);
3435 }
3436no_ir:
3437#endif
3438 ret = setup_msi_irq(dev, desc, irq);
3439 if (ret < 0)
3440 goto error;
3441 sub_handle++;
3442 }
3443 return 0;
047c8fdb
YL		 3444
3445error:
54168ed7
IM		 3446 destroy_irq(irq);
3447 return ret;
047c8fdb
YL		 3448}
3449
3b7d1921
EB		 3450void arch_teardown_msi_irq(unsigned int irq)
3451{
f7feaca7 3452 destroy_irq(irq);
3b7d1921
EB		 3453}
3454
54168ed7
IM		 3455#ifdef CONFIG_DMAR
3456#ifdef CONFIG_SMP
3457static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
3458{
3459 struct irq_cfg *cfg;
3460 struct msi_msg msg;
3461 unsigned int dest;
3462 cpumask_t tmp;
3463 struct irq_desc *desc;
3464
3465 cpus_and(tmp, mask, cpu_online_map);
3466 if (cpus_empty(tmp))
3467 return;
3468
3469 if (assign_irq_vector(irq, mask))
3470 return;
3471
3472 cfg = irq_cfg(irq);
3473 cpus_and(tmp, cfg->domain, mask);
3474 dest = cpu_mask_to_apicid(tmp);
3475
3476 dmar_msi_read(irq, &msg);
3477
3478 msg.data &= ~MSI_DATA_VECTOR_MASK;
3479 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3480 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3481 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3482
3483 dmar_msi_write(irq, &msg);
3484 desc = irq_to_desc(irq);
3485 desc->affinity = mask;
3486}
3487#endif /* CONFIG_SMP */
3488
3489struct irq_chip dmar_msi_type = {
3490 .name = "DMAR_MSI",
3491 .unmask = dmar_msi_unmask,
3492 .mask = dmar_msi_mask,
3493 .ack = ack_apic_edge,
3494#ifdef CONFIG_SMP
3495 .set_affinity = dmar_msi_set_affinity,
3496#endif
3497 .retrigger = ioapic_retrigger_irq,
3498};
3499
3500int arch_setup_dmar_msi(unsigned int irq)
3501{
3502 int ret;
3503 struct msi_msg msg;
2d3fcc1c 3504
54168ed7
IM		 3505 ret = msi_compose_msg(NULL, irq, &msg);
3506 if (ret < 0)
3507 return ret;
3508 dmar_msi_write(irq, &msg);
3509 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3510 "edge");
3511 return 0;
3512}
3513#endif
3514
3515#endif /* CONFIG_PCI_MSI */
8b955b0d
EB		 3516/*
3517 * Hypertransport interrupt support
3518 */
3519#ifdef CONFIG_HT_IRQ
3520
3521#ifdef CONFIG_SMP
3522
497c9a19 3523static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
8b955b0d 3524{
ec68307c
EB		 3525 struct ht_irq_msg msg;
3526 fetch_ht_irq_msg(irq, &msg);
8b955b0d 3527
497c9a19 3528 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
ec68307c 3529 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
8b955b0d 3530
497c9a19 3531 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
ec68307c 3532 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
8b955b0d 3533
ec68307c 3534 write_ht_irq_msg(irq, &msg);
8b955b0d
EB		 3535}
3536
3537static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
3538{
497c9a19 3539 struct irq_cfg *cfg;
8b955b0d
EB		 3540 unsigned int dest;
3541 cpumask_t tmp;
54168ed7 3542 struct irq_desc *desc;
8b955b0d
EB		 3543
3544 cpus_and(tmp, mask, cpu_online_map);
3545 if (cpus_empty(tmp))
497c9a19 3546 return;
8b955b0d 3547
497c9a19
YL		 3548 if (assign_irq_vector(irq, mask))
3549 return;
8b955b0d 3550
497c9a19
YL		 3551 cfg = irq_cfg(irq);
3552 cpus_and(tmp, cfg->domain, mask);
3553 dest = cpu_mask_to_apicid(tmp);
8b955b0d 3554
497c9a19 3555 target_ht_irq(irq, dest, cfg->vector);
54168ed7
IM		 3556 desc = irq_to_desc(irq);
3557 desc->affinity = mask;
8b955b0d
EB		 3558}
3559#endif
3560
c37e108d 3561static struct irq_chip ht_irq_chip = {
8b955b0d
EB		 3562 .name = "PCI-HT",
3563 .mask = mask_ht_irq,
3564 .unmask = unmask_ht_irq,
1d025192 3565 .ack = ack_apic_edge,
8b955b0d
EB		 3566#ifdef CONFIG_SMP
3567 .set_affinity = set_ht_irq_affinity,
3568#endif
3569 .retrigger = ioapic_retrigger_irq,
3570};
3571
3572int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3573{
497c9a19
YL		 3574 struct irq_cfg *cfg;
3575 int err;
3576 cpumask_t tmp;
8b955b0d 3577
497c9a19
YL		 3578 tmp = TARGET_CPUS;
3579 err = assign_irq_vector(irq, tmp);
54168ed7 3580 if (!err) {
ec68307c 3581 struct ht_irq_msg msg;
8b955b0d 3582 unsigned dest;
8b955b0d 3583
497c9a19
YL		 3584 cfg = irq_cfg(irq);
3585 cpus_and(tmp, cfg->domain, tmp);
8b955b0d
EB		 3586 dest = cpu_mask_to_apicid(tmp);
3587
ec68307c 3588 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
8b955b0d 3589
ec68307c
EB		 3590 msg.address_lo =
3591 HT_IRQ_LOW_BASE |
8b955b0d 3592 HT_IRQ_LOW_DEST_ID(dest) |
497c9a19 3593 HT_IRQ_LOW_VECTOR(cfg->vector) |
8b955b0d
EB		 3594 ((INT_DEST_MODE == 0) ?
3595 HT_IRQ_LOW_DM_PHYSICAL :
3596 HT_IRQ_LOW_DM_LOGICAL) |
3597 HT_IRQ_LOW_RQEOI_EDGE |
3598 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3599 HT_IRQ_LOW_MT_FIXED :
3600 HT_IRQ_LOW_MT_ARBITRATED) |
3601 HT_IRQ_LOW_IRQ_MASKED;
3602
ec68307c 3603 write_ht_irq_msg(irq, &msg);
8b955b0d 3604
a460e745
IM		 3605 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3606 handle_edge_irq, "edge");
8b955b0d 3607 }
497c9a19 3608 return err;
8b955b0d
EB		 3609}
3610#endif /* CONFIG_HT_IRQ */
3611
9d6a4d08
YL		 3612int __init io_apic_get_redir_entries (int ioapic)
3613{
3614 union IO_APIC_reg_01 reg_01;
3615 unsigned long flags;
3616
3617 spin_lock_irqsave(&ioapic_lock, flags);
3618 reg_01.raw = io_apic_read(ioapic, 1);
3619 spin_unlock_irqrestore(&ioapic_lock, flags);
3620
3621 return reg_01.bits.entries;
3622}
3623
3624int __init probe_nr_irqs(void)
3625{
3626 int idx;
3627 int nr = 0;
052c0bff
YL		 3628#ifndef CONFIG_XEN
3629 int nr_min = 32;
3630#else
3631 int nr_min = NR_IRQS;
3632#endif
9d6a4d08
YL		 3633
3634 for (idx = 0; idx < nr_ioapics; idx++)
052c0bff 3635 nr += io_apic_get_redir_entries(idx) + 1;
9d6a4d08
YL		 3636
3637 /* double it for hotplug and msi and nmi */
3638 nr <<= 1;
3639
3640 /* something wrong ? */
052c0bff
YL		 3641 if (nr < nr_min)
3642 nr = nr_min;
9d6a4d08
YL		 3643
3644 return nr;
3645}
3646
1da177e4 3647/* --------------------------------------------------------------------------
54168ed7 3648 ACPI-based IOAPIC Configuration
1da177e4
LT		 3649 -------------------------------------------------------------------------- */
3650
888ba6c6 3651#ifdef CONFIG_ACPI
1da177e4 3652
54168ed7 3653#ifdef CONFIG_X86_32
36062448 3654int __init io_apic_get_unique_id(int ioapic, int apic_id)
1da177e4
LT		 3655{
3656 union IO_APIC_reg_00 reg_00;
3657 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3658 physid_mask_t tmp;
3659 unsigned long flags;
3660 int i = 0;
3661
3662 /*
36062448
PC		 3663 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3664 * buses (one for LAPICs, one for IOAPICs), where predecessors only
1da177e4 3665 * supports up to 16 on one shared APIC bus.
36062448 3666 *
1da177e4
LT		 3667 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3668 * advantage of new APIC bus architecture.
3669 */
3670
3671 if (physids_empty(apic_id_map))
3672 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
3673
3674 spin_lock_irqsave(&ioapic_lock, flags);
3675 reg_00.raw = io_apic_read(ioapic, 0);
3676 spin_unlock_irqrestore(&ioapic_lock, flags);
3677
3678 if (apic_id >= get_physical_broadcast()) {
3679 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3680 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3681 apic_id = reg_00.bits.ID;
3682 }
3683
3684 /*
36062448 3685 * Every APIC in a system must have a unique ID or we get lots of nice
1da177e4
LT		 3686 * 'stuck on smp_invalidate_needed IPI wait' messages.
3687 */
3688 if (check_apicid_used(apic_id_map, apic_id)) {
3689
3690 for (i = 0; i < get_physical_broadcast(); i++) {
3691 if (!check_apicid_used(apic_id_map, i))
3692 break;
3693 }
3694
3695 if (i == get_physical_broadcast())
3696 panic("Max apic_id exceeded!\n");
3697
3698 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3699 "trying %d\n", ioapic, apic_id, i);
3700
3701 apic_id = i;
36062448 3702 }
1da177e4
LT		 3703
3704 tmp = apicid_to_cpu_present(apic_id);
3705 physids_or(apic_id_map, apic_id_map, tmp);
3706
3707 if (reg_00.bits.ID != apic_id) {
3708 reg_00.bits.ID = apic_id;
3709
3710 spin_lock_irqsave(&ioapic_lock, flags);
3711 io_apic_write(ioapic, 0, reg_00.raw);
3712 reg_00.raw = io_apic_read(ioapic, 0);
3713 spin_unlock_irqrestore(&ioapic_lock, flags);
3714
3715 /* Sanity check */
6070f9ec
AD		 3716 if (reg_00.bits.ID != apic_id) {
3717 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3718 return -1;
3719 }
1da177e4
LT		 3720 }
3721
3722 apic_printk(APIC_VERBOSE, KERN_INFO
3723 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3724
3725 return apic_id;
3726}
3727
36062448 3728int __init io_apic_get_version(int ioapic)
1da177e4
LT		 3729{
3730 union IO_APIC_reg_01 reg_01;
3731 unsigned long flags;
3732
3733 spin_lock_irqsave(&ioapic_lock, flags);
3734 reg_01.raw = io_apic_read(ioapic, 1);
3735 spin_unlock_irqrestore(&ioapic_lock, flags);
3736
3737 return reg_01.bits.version;
3738}
54168ed7 3739#endif
1da177e4 3740
54168ed7 3741int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
1da177e4 3742{
1da177e4 3743 if (!IO_APIC_IRQ(irq)) {
54168ed7 3744 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
1da177e4
LT		 3745 ioapic);
3746 return -EINVAL;
3747 }
3748
1da177e4
LT		 3749 /*
3750 * IRQs < 16 are already in the irq_2_pin[] map
3751 */
3752 if (irq >= 16)
3753 add_pin_to_irq(irq, ioapic, pin);
3754
497c9a19 3755 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
1da177e4
LT		 3756
3757 return 0;
3758}
3759
54168ed7 3760
61fd47e0
SL		 3761int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3762{
3763 int i;
3764
3765 if (skip_ioapic_setup)
3766 return -1;
3767
3768 for (i = 0; i < mp_irq_entries; i++)
2fddb6e2
AS		 3769 if (mp_irqs[i].mp_irqtype == mp_INT &&
3770 mp_irqs[i].mp_srcbusirq == bus_irq)
61fd47e0
SL		 3771 break;
3772 if (i >= mp_irq_entries)
3773 return -1;
3774
3775 *trigger = irq_trigger(i);
3776 *polarity = irq_polarity(i);
3777 return 0;
3778}
3779
888ba6c6 3780#endif /* CONFIG_ACPI */
1a3f239d 3781
497c9a19
YL		 3782/*
3783 * This function currently is only a helper for the i386 smp boot process where
3784 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3785 * so mask in all cases should simply be TARGET_CPUS
3786 */
3787#ifdef CONFIG_SMP
3788void __init setup_ioapic_dest(void)
3789{
3790 int pin, ioapic, irq, irq_entry;
3791 struct irq_cfg *cfg;
497c9a19
YL		 3792
3793 if (skip_ioapic_setup == 1)
3794 return;
3795
3796 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
3797 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
3798 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3799 if (irq_entry == -1)
3800 continue;
3801 irq = pin_2_irq(irq_entry, ioapic, pin);
3802
3803 /* setup_IO_APIC_irqs could fail to get vector for some device
3804 * when you have too many devices, because at that time only boot
3805 * cpu is online.
3806 */
3807 cfg = irq_cfg(irq);
3808 if (!cfg->vector)
3809 setup_IO_APIC_irq(ioapic, pin, irq,
3810 irq_trigger(irq_entry),
3811 irq_polarity(irq_entry));
54168ed7
IM		 3812#ifdef CONFIG_INTR_REMAP
3813 else if (intr_remapping_enabled)
3814 set_ir_ioapic_affinity_irq(irq, TARGET_CPUS);
3815#endif
3816 else
497c9a19 3817 set_ioapic_affinity_irq(irq, TARGET_CPUS);
497c9a19
YL		 3818 }
3819
3820 }
3821}
3822#endif
3823
54168ed7
IM		 3824#define IOAPIC_RESOURCE_NAME_SIZE 11
3825
3826static struct resource *ioapic_resources;
3827
3828static struct resource * __init ioapic_setup_resources(void)
3829{
3830 unsigned long n;
3831 struct resource *res;
3832 char *mem;
3833 int i;
3834
3835 if (nr_ioapics <= 0)
3836 return NULL;
3837
3838 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3839 n *= nr_ioapics;
3840
3841 mem = alloc_bootmem(n);
3842 res = (void *)mem;
3843
3844 if (mem != NULL) {
3845 mem += sizeof(struct resource) * nr_ioapics;
3846
3847 for (i = 0; i < nr_ioapics; i++) {
3848 res[i].name = mem;
3849 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3850 sprintf(mem, "IOAPIC %u", i);
3851 mem += IOAPIC_RESOURCE_NAME_SIZE;
3852 }
3853 }
3854
3855 ioapic_resources = res;
3856
3857 return res;
3858}
54168ed7 3859
f3294a33
YL		 3860void __init ioapic_init_mappings(void)
3861{
3862 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3863 int i;
54168ed7 3864 struct resource *ioapic_res;
f3294a33 3865
54168ed7 3866 ioapic_res = ioapic_setup_resources();
f3294a33
YL		 3867 for (i = 0; i < nr_ioapics; i++) {
3868 if (smp_found_config) {
3869 ioapic_phys = mp_ioapics[i].mp_apicaddr;
54168ed7
IM		 3870#ifdef CONFIG_X86_32
3871 if (!ioapic_phys) {
3872 printk(KERN_ERR
3873 "WARNING: bogus zero IO-APIC "
3874 "address found in MPTABLE, "
3875 "disabling IO/APIC support!\n");
3876 smp_found_config = 0;
3877 skip_ioapic_setup = 1;
3878 goto fake_ioapic_page;
3879 }
3880#endif
f3294a33 3881 } else {
54168ed7 3882#ifdef CONFIG_X86_32
f3294a33 3883fake_ioapic_page:
54168ed7 3884#endif
f3294a33 3885 ioapic_phys = (unsigned long)
54168ed7 3886 alloc_bootmem_pages(PAGE_SIZE);
f3294a33
YL		 3887 ioapic_phys = __pa(ioapic_phys);
3888 }
3889 set_fixmap_nocache(idx, ioapic_phys);
54168ed7
IM		 3890 apic_printk(APIC_VERBOSE,
3891 "mapped IOAPIC to %08lx (%08lx)\n",
3892 __fix_to_virt(idx), ioapic_phys);
f3294a33 3893 idx++;
54168ed7 3894
54168ed7
IM		 3895 if (ioapic_res != NULL) {
3896 ioapic_res->start = ioapic_phys;
3897 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
3898 ioapic_res++;
3899 }
f3294a33
YL		 3900 }
3901}
3902
54168ed7
IM		 3903static int __init ioapic_insert_resources(void)
3904{
3905 int i;
3906 struct resource *r = ioapic_resources;
3907
3908 if (!r) {
3909 printk(KERN_ERR
3910 "IO APIC resources could be not be allocated.\n");
3911 return -1;
3912 }
3913
3914 for (i = 0; i < nr_ioapics; i++) {
3915 insert_resource(&iomem_resource, r);
3916 r++;
3917 }
3918
3919 return 0;
3920}
3921
3922/* Insert the IO APIC resources after PCI initialization has occured to handle
3923 * IO APICS that are mapped in on a BAR in PCI space. */
3924late_initcall(ioapic_insert_resources);
Linux 6.x block layer and io_uring tree(s)