Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 1994 Linus Torvalds |
3 | * | |
4 | * Pentium III FXSR, SSE support | |
5 | * General FPU state handling cleanups | |
6 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
7 | */ | |
129f6946 | 8 | #include <linux/module.h> |
44210111 | 9 | #include <linux/regset.h> |
f668964e | 10 | #include <linux/sched.h> |
61c4628b | 11 | #include <linux/bootmem.h> |
f668964e IM |
12 | |
13 | #include <asm/sigcontext.h> | |
1da177e4 | 14 | #include <asm/processor.h> |
1da177e4 | 15 | #include <asm/math_emu.h> |
1da177e4 | 16 | #include <asm/uaccess.h> |
f668964e IM |
17 | #include <asm/ptrace.h> |
18 | #include <asm/i387.h> | |
19 | #include <asm/user.h> | |
1da177e4 | 20 | |
44210111 | 21 | #ifdef CONFIG_X86_64 |
f668964e IM |
22 | # include <asm/sigcontext32.h> |
23 | # include <asm/user32.h> | |
44210111 | 24 | #else |
f668964e IM |
25 | # define save_i387_ia32 save_i387 |
26 | # define restore_i387_ia32 restore_i387 | |
27 | # define _fpstate_ia32 _fpstate | |
28 | # define user_i387_ia32_struct user_i387_struct | |
29 | # define user32_fxsr_struct user_fxsr_struct | |
44210111 RM |
30 | #endif |
31 | ||
1da177e4 | 32 | #ifdef CONFIG_MATH_EMULATION |
f668964e | 33 | # define HAVE_HWFP (boot_cpu_data.hard_math) |
1da177e4 | 34 | #else |
f668964e | 35 | # define HAVE_HWFP 1 |
1da177e4 LT |
36 | #endif |
37 | ||
f668964e | 38 | static unsigned int mxcsr_feature_mask __read_mostly = 0xffffffffu; |
61c4628b SS |
39 | unsigned int xstate_size; |
40 | static struct i387_fxsave_struct fx_scratch __cpuinitdata; | |
1da177e4 | 41 | |
61c4628b | 42 | void __cpuinit mxcsr_feature_mask_init(void) |
1da177e4 LT |
43 | { |
44 | unsigned long mask = 0; | |
f668964e | 45 | |
1da177e4 LT |
46 | clts(); |
47 | if (cpu_has_fxsr) { | |
61c4628b SS |
48 | memset(&fx_scratch, 0, sizeof(struct i387_fxsave_struct)); |
49 | asm volatile("fxsave %0" : : "m" (fx_scratch)); | |
50 | mask = fx_scratch.mxcsr_mask; | |
3b095a04 CG |
51 | if (mask == 0) |
52 | mask = 0x0000ffbf; | |
53 | } | |
1da177e4 LT |
54 | mxcsr_feature_mask &= mask; |
55 | stts(); | |
56 | } | |
57 | ||
61c4628b SS |
58 | void __init init_thread_xstate(void) |
59 | { | |
60 | if (cpu_has_fxsr) | |
61 | xstate_size = sizeof(struct i387_fxsave_struct); | |
62 | #ifdef CONFIG_X86_32 | |
63 | else | |
64 | xstate_size = sizeof(struct i387_fsave_struct); | |
65 | #endif | |
66 | init_task.thread.xstate = alloc_bootmem(xstate_size); | |
67 | } | |
68 | ||
44210111 RM |
69 | #ifdef CONFIG_X86_64 |
70 | /* | |
71 | * Called at bootup to set up the initial FPU state that is later cloned | |
72 | * into all processes. | |
73 | */ | |
74 | void __cpuinit fpu_init(void) | |
75 | { | |
76 | unsigned long oldcr0 = read_cr0(); | |
f668964e | 77 | |
44210111 RM |
78 | set_in_cr4(X86_CR4_OSFXSR); |
79 | set_in_cr4(X86_CR4_OSXMMEXCPT); | |
80 | ||
f668964e | 81 | write_cr0(oldcr0 & ~(X86_CR0_TS|X86_CR0_EM)); /* clear TS and EM */ |
44210111 RM |
82 | |
83 | mxcsr_feature_mask_init(); | |
84 | /* clean state in init */ | |
85 | current_thread_info()->status = 0; | |
86 | clear_used_math(); | |
87 | } | |
88 | #endif /* CONFIG_X86_64 */ | |
89 | ||
1da177e4 LT |
90 | /* |
91 | * The _current_ task is using the FPU for the first time | |
92 | * so initialize it and set the mxcsr to its default | |
93 | * value at reset if we support XMM instructions and then | |
94 | * remeber the current task has used the FPU. | |
95 | */ | |
96 | void init_fpu(struct task_struct *tsk) | |
97 | { | |
44210111 RM |
98 | if (tsk_used_math(tsk)) { |
99 | if (tsk == current) | |
100 | unlazy_fpu(tsk); | |
101 | return; | |
102 | } | |
103 | ||
1da177e4 | 104 | if (cpu_has_fxsr) { |
61c4628b SS |
105 | struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave; |
106 | ||
107 | memset(fx, 0, xstate_size); | |
108 | fx->cwd = 0x37f; | |
1da177e4 | 109 | if (cpu_has_xmm) |
61c4628b | 110 | fx->mxcsr = MXCSR_DEFAULT; |
1da177e4 | 111 | } else { |
61c4628b SS |
112 | struct i387_fsave_struct *fp = &tsk->thread.xstate->fsave; |
113 | memset(fp, 0, xstate_size); | |
114 | fp->cwd = 0xffff037fu; | |
115 | fp->swd = 0xffff0000u; | |
116 | fp->twd = 0xffffffffu; | |
117 | fp->fos = 0xffff0000u; | |
1da177e4 | 118 | } |
44210111 RM |
119 | /* |
120 | * Only the device not available exception or ptrace can call init_fpu. | |
121 | */ | |
1da177e4 LT |
122 | set_stopped_child_used_math(tsk); |
123 | } | |
124 | ||
44210111 RM |
125 | int fpregs_active(struct task_struct *target, const struct user_regset *regset) |
126 | { | |
127 | return tsk_used_math(target) ? regset->n : 0; | |
128 | } | |
1da177e4 | 129 | |
44210111 | 130 | int xfpregs_active(struct task_struct *target, const struct user_regset *regset) |
1da177e4 | 131 | { |
44210111 RM |
132 | return (cpu_has_fxsr && tsk_used_math(target)) ? regset->n : 0; |
133 | } | |
1da177e4 | 134 | |
44210111 RM |
135 | int xfpregs_get(struct task_struct *target, const struct user_regset *regset, |
136 | unsigned int pos, unsigned int count, | |
137 | void *kbuf, void __user *ubuf) | |
138 | { | |
139 | if (!cpu_has_fxsr) | |
140 | return -ENODEV; | |
141 | ||
18a86221 | 142 | init_fpu(target); |
44210111 RM |
143 | |
144 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
61c4628b | 145 | &target->thread.xstate->fxsave, 0, -1); |
1da177e4 | 146 | } |
44210111 RM |
147 | |
148 | int xfpregs_set(struct task_struct *target, const struct user_regset *regset, | |
149 | unsigned int pos, unsigned int count, | |
150 | const void *kbuf, const void __user *ubuf) | |
151 | { | |
152 | int ret; | |
153 | ||
154 | if (!cpu_has_fxsr) | |
155 | return -ENODEV; | |
156 | ||
18a86221 | 157 | init_fpu(target); |
44210111 RM |
158 | set_stopped_child_used_math(target); |
159 | ||
160 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
61c4628b | 161 | &target->thread.xstate->fxsave, 0, -1); |
44210111 RM |
162 | |
163 | /* | |
164 | * mxcsr reserved bits must be masked to zero for security reasons. | |
165 | */ | |
61c4628b | 166 | target->thread.xstate->fxsave.mxcsr &= mxcsr_feature_mask; |
44210111 RM |
167 | |
168 | return ret; | |
169 | } | |
170 | ||
171 | #if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION | |
1da177e4 | 172 | |
1da177e4 LT |
173 | /* |
174 | * FPU tag word conversions. | |
175 | */ | |
176 | ||
3b095a04 | 177 | static inline unsigned short twd_i387_to_fxsr(unsigned short twd) |
1da177e4 LT |
178 | { |
179 | unsigned int tmp; /* to avoid 16 bit prefixes in the code */ | |
3b095a04 | 180 | |
1da177e4 | 181 | /* Transform each pair of bits into 01 (valid) or 00 (empty) */ |
3b095a04 | 182 | tmp = ~twd; |
44210111 | 183 | tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */ |
3b095a04 CG |
184 | /* and move the valid bits to the lower byte. */ |
185 | tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */ | |
186 | tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */ | |
187 | tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */ | |
f668964e | 188 | |
3b095a04 | 189 | return tmp; |
1da177e4 LT |
190 | } |
191 | ||
1da177e4 | 192 | #define FPREG_ADDR(f, n) ((void *)&(f)->st_space + (n) * 16); |
44210111 RM |
193 | #define FP_EXP_TAG_VALID 0 |
194 | #define FP_EXP_TAG_ZERO 1 | |
195 | #define FP_EXP_TAG_SPECIAL 2 | |
196 | #define FP_EXP_TAG_EMPTY 3 | |
197 | ||
198 | static inline u32 twd_fxsr_to_i387(struct i387_fxsave_struct *fxsave) | |
199 | { | |
200 | struct _fpxreg *st; | |
201 | u32 tos = (fxsave->swd >> 11) & 7; | |
202 | u32 twd = (unsigned long) fxsave->twd; | |
203 | u32 tag; | |
204 | u32 ret = 0xffff0000u; | |
205 | int i; | |
1da177e4 | 206 | |
44210111 | 207 | for (i = 0; i < 8; i++, twd >>= 1) { |
3b095a04 CG |
208 | if (twd & 0x1) { |
209 | st = FPREG_ADDR(fxsave, (i - tos) & 7); | |
1da177e4 | 210 | |
3b095a04 | 211 | switch (st->exponent & 0x7fff) { |
1da177e4 | 212 | case 0x7fff: |
44210111 | 213 | tag = FP_EXP_TAG_SPECIAL; |
1da177e4 LT |
214 | break; |
215 | case 0x0000: | |
3b095a04 CG |
216 | if (!st->significand[0] && |
217 | !st->significand[1] && | |
218 | !st->significand[2] && | |
44210111 RM |
219 | !st->significand[3]) |
220 | tag = FP_EXP_TAG_ZERO; | |
221 | else | |
222 | tag = FP_EXP_TAG_SPECIAL; | |
1da177e4 LT |
223 | break; |
224 | default: | |
44210111 RM |
225 | if (st->significand[3] & 0x8000) |
226 | tag = FP_EXP_TAG_VALID; | |
227 | else | |
228 | tag = FP_EXP_TAG_SPECIAL; | |
1da177e4 LT |
229 | break; |
230 | } | |
231 | } else { | |
44210111 | 232 | tag = FP_EXP_TAG_EMPTY; |
1da177e4 | 233 | } |
44210111 | 234 | ret |= tag << (2 * i); |
1da177e4 LT |
235 | } |
236 | return ret; | |
237 | } | |
238 | ||
239 | /* | |
44210111 | 240 | * FXSR floating point environment conversions. |
1da177e4 LT |
241 | */ |
242 | ||
f668964e IM |
243 | static void |
244 | convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk) | |
1da177e4 | 245 | { |
61c4628b | 246 | struct i387_fxsave_struct *fxsave = &tsk->thread.xstate->fxsave; |
44210111 RM |
247 | struct _fpreg *to = (struct _fpreg *) &env->st_space[0]; |
248 | struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0]; | |
249 | int i; | |
1da177e4 | 250 | |
44210111 RM |
251 | env->cwd = fxsave->cwd | 0xffff0000u; |
252 | env->swd = fxsave->swd | 0xffff0000u; | |
253 | env->twd = twd_fxsr_to_i387(fxsave); | |
254 | ||
255 | #ifdef CONFIG_X86_64 | |
256 | env->fip = fxsave->rip; | |
257 | env->foo = fxsave->rdp; | |
258 | if (tsk == current) { | |
259 | /* | |
260 | * should be actually ds/cs at fpu exception time, but | |
261 | * that information is not available in 64bit mode. | |
262 | */ | |
f668964e IM |
263 | asm("mov %%ds, %[fos]" : [fos] "=r" (env->fos)); |
264 | asm("mov %%cs, %[fcs]" : [fcs] "=r" (env->fcs)); | |
1da177e4 | 265 | } else { |
44210111 | 266 | struct pt_regs *regs = task_pt_regs(tsk); |
f668964e | 267 | |
44210111 RM |
268 | env->fos = 0xffff0000 | tsk->thread.ds; |
269 | env->fcs = regs->cs; | |
1da177e4 | 270 | } |
44210111 RM |
271 | #else |
272 | env->fip = fxsave->fip; | |
609b5297 | 273 | env->fcs = (u16) fxsave->fcs | ((u32) fxsave->fop << 16); |
44210111 RM |
274 | env->foo = fxsave->foo; |
275 | env->fos = fxsave->fos; | |
276 | #endif | |
1da177e4 | 277 | |
44210111 RM |
278 | for (i = 0; i < 8; ++i) |
279 | memcpy(&to[i], &from[i], sizeof(to[0])); | |
1da177e4 LT |
280 | } |
281 | ||
44210111 RM |
282 | static void convert_to_fxsr(struct task_struct *tsk, |
283 | const struct user_i387_ia32_struct *env) | |
1da177e4 | 284 | |
1da177e4 | 285 | { |
61c4628b | 286 | struct i387_fxsave_struct *fxsave = &tsk->thread.xstate->fxsave; |
44210111 RM |
287 | struct _fpreg *from = (struct _fpreg *) &env->st_space[0]; |
288 | struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0]; | |
289 | int i; | |
1da177e4 | 290 | |
44210111 RM |
291 | fxsave->cwd = env->cwd; |
292 | fxsave->swd = env->swd; | |
293 | fxsave->twd = twd_i387_to_fxsr(env->twd); | |
294 | fxsave->fop = (u16) ((u32) env->fcs >> 16); | |
295 | #ifdef CONFIG_X86_64 | |
296 | fxsave->rip = env->fip; | |
297 | fxsave->rdp = env->foo; | |
298 | /* cs and ds ignored */ | |
299 | #else | |
300 | fxsave->fip = env->fip; | |
301 | fxsave->fcs = (env->fcs & 0xffff); | |
302 | fxsave->foo = env->foo; | |
303 | fxsave->fos = env->fos; | |
304 | #endif | |
1da177e4 | 305 | |
44210111 RM |
306 | for (i = 0; i < 8; ++i) |
307 | memcpy(&to[i], &from[i], sizeof(from[0])); | |
1da177e4 LT |
308 | } |
309 | ||
44210111 RM |
310 | int fpregs_get(struct task_struct *target, const struct user_regset *regset, |
311 | unsigned int pos, unsigned int count, | |
312 | void *kbuf, void __user *ubuf) | |
1da177e4 | 313 | { |
44210111 | 314 | struct user_i387_ia32_struct env; |
1da177e4 | 315 | |
44210111 RM |
316 | if (!HAVE_HWFP) |
317 | return fpregs_soft_get(target, regset, pos, count, kbuf, ubuf); | |
1da177e4 | 318 | |
18a86221 | 319 | init_fpu(target); |
1da177e4 | 320 | |
f668964e | 321 | if (!cpu_has_fxsr) { |
44210111 | 322 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
61c4628b SS |
323 | &target->thread.xstate->fsave, 0, |
324 | -1); | |
f668964e | 325 | } |
1da177e4 | 326 | |
44210111 RM |
327 | if (kbuf && pos == 0 && count == sizeof(env)) { |
328 | convert_from_fxsr(kbuf, target); | |
329 | return 0; | |
1da177e4 | 330 | } |
44210111 RM |
331 | |
332 | convert_from_fxsr(&env, target); | |
f668964e | 333 | |
44210111 | 334 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &env, 0, -1); |
1da177e4 LT |
335 | } |
336 | ||
44210111 RM |
337 | int fpregs_set(struct task_struct *target, const struct user_regset *regset, |
338 | unsigned int pos, unsigned int count, | |
339 | const void *kbuf, const void __user *ubuf) | |
1da177e4 | 340 | { |
44210111 RM |
341 | struct user_i387_ia32_struct env; |
342 | int ret; | |
1da177e4 | 343 | |
44210111 RM |
344 | if (!HAVE_HWFP) |
345 | return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf); | |
1da177e4 | 346 | |
18a86221 | 347 | init_fpu(target); |
44210111 RM |
348 | set_stopped_child_used_math(target); |
349 | ||
f668964e | 350 | if (!cpu_has_fxsr) { |
44210111 | 351 | return user_regset_copyin(&pos, &count, &kbuf, &ubuf, |
61c4628b | 352 | &target->thread.xstate->fsave, 0, -1); |
f668964e | 353 | } |
44210111 RM |
354 | |
355 | if (pos > 0 || count < sizeof(env)) | |
356 | convert_from_fxsr(&env, target); | |
357 | ||
358 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1); | |
359 | if (!ret) | |
360 | convert_to_fxsr(target, &env); | |
361 | ||
362 | return ret; | |
1da177e4 LT |
363 | } |
364 | ||
365 | /* | |
366 | * Signal frame handlers. | |
367 | */ | |
368 | ||
44210111 | 369 | static inline int save_i387_fsave(struct _fpstate_ia32 __user *buf) |
1da177e4 LT |
370 | { |
371 | struct task_struct *tsk = current; | |
61c4628b | 372 | struct i387_fsave_struct *fp = &tsk->thread.xstate->fsave; |
1da177e4 | 373 | |
3b095a04 | 374 | unlazy_fpu(tsk); |
61c4628b SS |
375 | fp->status = fp->swd; |
376 | if (__copy_to_user(buf, fp, sizeof(struct i387_fsave_struct))) | |
1da177e4 LT |
377 | return -1; |
378 | return 1; | |
379 | } | |
380 | ||
44210111 | 381 | static int save_i387_fxsave(struct _fpstate_ia32 __user *buf) |
1da177e4 LT |
382 | { |
383 | struct task_struct *tsk = current; | |
61c4628b | 384 | struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave; |
44210111 | 385 | struct user_i387_ia32_struct env; |
1da177e4 LT |
386 | int err = 0; |
387 | ||
3b095a04 | 388 | unlazy_fpu(tsk); |
1da177e4 | 389 | |
44210111 RM |
390 | convert_from_fxsr(&env, tsk); |
391 | if (__copy_to_user(buf, &env, sizeof(env))) | |
1da177e4 LT |
392 | return -1; |
393 | ||
61c4628b | 394 | err |= __put_user(fx->swd, &buf->status); |
3b095a04 CG |
395 | err |= __put_user(X86_FXSR_MAGIC, &buf->magic); |
396 | if (err) | |
1da177e4 LT |
397 | return -1; |
398 | ||
61c4628b | 399 | if (__copy_to_user(&buf->_fxsr_env[0], fx, |
3b095a04 | 400 | sizeof(struct i387_fxsave_struct))) |
1da177e4 LT |
401 | return -1; |
402 | return 1; | |
403 | } | |
404 | ||
44210111 | 405 | int save_i387_ia32(struct _fpstate_ia32 __user *buf) |
1da177e4 | 406 | { |
3b095a04 | 407 | if (!used_math()) |
1da177e4 | 408 | return 0; |
f668964e IM |
409 | /* |
410 | * This will cause a "finit" to be triggered by the next | |
1da177e4 LT |
411 | * attempted FPU operation by the 'current' process. |
412 | */ | |
413 | clear_used_math(); | |
414 | ||
f668964e | 415 | if (!HAVE_HWFP) { |
44210111 RM |
416 | return fpregs_soft_get(current, NULL, |
417 | 0, sizeof(struct user_i387_ia32_struct), | |
418 | NULL, buf) ? -1 : 1; | |
1da177e4 | 419 | } |
f668964e IM |
420 | |
421 | if (cpu_has_fxsr) | |
422 | return save_i387_fxsave(buf); | |
423 | else | |
424 | return save_i387_fsave(buf); | |
1da177e4 LT |
425 | } |
426 | ||
44210111 | 427 | static inline int restore_i387_fsave(struct _fpstate_ia32 __user *buf) |
1da177e4 LT |
428 | { |
429 | struct task_struct *tsk = current; | |
f668964e | 430 | |
3b095a04 | 431 | clear_fpu(tsk); |
61c4628b | 432 | return __copy_from_user(&tsk->thread.xstate->fsave, buf, |
3b095a04 | 433 | sizeof(struct i387_fsave_struct)); |
1da177e4 LT |
434 | } |
435 | ||
44210111 | 436 | static int restore_i387_fxsave(struct _fpstate_ia32 __user *buf) |
1da177e4 | 437 | { |
1da177e4 | 438 | struct task_struct *tsk = current; |
44210111 | 439 | struct user_i387_ia32_struct env; |
f668964e IM |
440 | int err; |
441 | ||
3b095a04 | 442 | clear_fpu(tsk); |
61c4628b | 443 | err = __copy_from_user(&tsk->thread.xstate->fxsave, &buf->_fxsr_env[0], |
3b095a04 | 444 | sizeof(struct i387_fxsave_struct)); |
1da177e4 | 445 | /* mxcsr reserved bits must be masked to zero for security reasons */ |
61c4628b | 446 | tsk->thread.xstate->fxsave.mxcsr &= mxcsr_feature_mask; |
44210111 RM |
447 | if (err || __copy_from_user(&env, buf, sizeof(env))) |
448 | return 1; | |
449 | convert_to_fxsr(tsk, &env); | |
f668964e | 450 | |
44210111 | 451 | return 0; |
1da177e4 LT |
452 | } |
453 | ||
44210111 | 454 | int restore_i387_ia32(struct _fpstate_ia32 __user *buf) |
1da177e4 LT |
455 | { |
456 | int err; | |
457 | ||
3b095a04 | 458 | if (HAVE_HWFP) { |
f668964e | 459 | if (cpu_has_fxsr) |
3b095a04 | 460 | err = restore_i387_fxsave(buf); |
f668964e | 461 | else |
3b095a04 | 462 | err = restore_i387_fsave(buf); |
1da177e4 | 463 | } else { |
44210111 RM |
464 | err = fpregs_soft_set(current, NULL, |
465 | 0, sizeof(struct user_i387_ia32_struct), | |
466 | NULL, buf) != 0; | |
1da177e4 LT |
467 | } |
468 | set_used_math(); | |
f668964e | 469 | |
1da177e4 LT |
470 | return err; |
471 | } | |
472 | ||
1da177e4 LT |
473 | /* |
474 | * FPU state for core dumps. | |
60b3b9af RM |
475 | * This is only used for a.out dumps now. |
476 | * It is declared generically using elf_fpregset_t (which is | |
477 | * struct user_i387_struct) but is in fact only used for 32-bit | |
478 | * dumps, so on 64-bit it is really struct user_i387_ia32_struct. | |
1da177e4 | 479 | */ |
3b095a04 | 480 | int dump_fpu(struct pt_regs *regs, struct user_i387_struct *fpu) |
1da177e4 | 481 | { |
1da177e4 | 482 | struct task_struct *tsk = current; |
f668964e | 483 | int fpvalid; |
1da177e4 LT |
484 | |
485 | fpvalid = !!used_math(); | |
60b3b9af RM |
486 | if (fpvalid) |
487 | fpvalid = !fpregs_get(tsk, NULL, | |
488 | 0, sizeof(struct user_i387_ia32_struct), | |
489 | fpu, NULL); | |
1da177e4 LT |
490 | |
491 | return fpvalid; | |
492 | } | |
129f6946 | 493 | EXPORT_SYMBOL(dump_fpu); |
1da177e4 | 494 | |
60b3b9af | 495 | #endif /* CONFIG_X86_32 || CONFIG_IA32_EMULATION */ |