[linux-2.6-block.git] / arch / x86 / kernel / hw_breakpoint.c

/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 * Copyright (C) 2007 Alan Stern
 * Copyright (C) 2009 IBM Corporation
 * Copyright (C) 2009 Frederic Weisbecker <fweisbec@gmail.com>
 *
 * Authors: Alan Stern <stern@rowland.harvard.edu>
 *          K.Prasad <prasad@linux.vnet.ibm.com>
 *          Frederic Weisbecker <fweisbec@gmail.com>
 */

/*
 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
 * using the CPU's debug registers.
 */

#include <linux/perf_event.h>
#include <linux/hw_breakpoint.h>
#include <linux/irqflags.h>
#include <linux/notifier.h>
#include <linux/kallsyms.h>
#include <linux/kprobes.h>
#include <linux/percpu.h>
#include <linux/kdebug.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/smp.h>

#include <asm/hw_breakpoint.h>
#include <asm/processor.h>
#include <asm/debugreg.h>

/* Per cpu debug control register value */
DEFINE_PER_CPU(unsigned long, cpu_dr7);
EXPORT_PER_CPU_SYMBOL(cpu_dr7);

/* Per cpu debug address registers values */
static DEFINE_PER_CPU(unsigned long, cpu_debugreg[HBP_NUM]);

/*
 * Stores the breakpoints currently in use on each breakpoint address
 * register for each cpus
 */
static DEFINE_PER_CPU(struct perf_event *, bp_per_reg[HBP_NUM]);


static inline unsigned long
__encode_dr7(int drnum, unsigned int len, unsigned int type)
{
	unsigned long bp_info;

	bp_info = (len | type) & 0xf;
	bp_info <<= (DR_CONTROL_SHIFT + drnum * DR_CONTROL_SIZE);
	bp_info |= (DR_GLOBAL_ENABLE << (drnum * DR_ENABLE_SIZE));

	return bp_info;
}

/*
 * Encode the length, type, Exact, and Enable bits for a particular breakpoint
 * as stored in debug register 7.
 */
unsigned long encode_dr7(int drnum, unsigned int len, unsigned int type)
{
	return __encode_dr7(drnum, len, type) | DR_GLOBAL_SLOWDOWN;
}

/*
 * Decode the length and type bits for a particular breakpoint as
 * stored in debug register 7.  Return the "enabled" status.
 */
int decode_dr7(unsigned long dr7, int bpnum, unsigned *len, unsigned *type)
{
	int bp_info = dr7 >> (DR_CONTROL_SHIFT + bpnum * DR_CONTROL_SIZE);

	*len = (bp_info & 0xc) | 0x40;
	*type = (bp_info & 0x3) | 0x80;

	return (dr7 >> (bpnum * DR_ENABLE_SIZE)) & 0x3;
}

/*
 * Install a perf counter breakpoint.
 *
 * We seek a free debug address register and use it for this
 * breakpoint. Eventually we enable it in the debug control register.
 *
 * Atomic: we hold the counter->ctx->lock and we only handle variables
 * and registers local to this cpu.
 */
int arch_install_hw_breakpoint(struct perf_event *bp)
{
	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
	unsigned long *dr7;
	int i;

	for (i = 0; i < HBP_NUM; i++) {
		struct perf_event **slot = this_cpu_ptr(&bp_per_reg[i]);

		if (!*slot) {
			*slot = bp;
			break;
		}
	}

	if (WARN_ONCE(i == HBP_NUM, "Can't find any breakpoint slot"))
		return -EBUSY;

	set_debugreg(info->address, i);
	__this_cpu_write(cpu_debugreg[i], info->address);

	dr7 = this_cpu_ptr(&cpu_dr7);
	*dr7 |= encode_dr7(i, info->len, info->type);

	set_debugreg(*dr7, 7);
	if (info->mask)
		set_dr_addr_mask(info->mask, i);

	return 0;
}

/*
 * Uninstall the breakpoint contained in the given counter.
 *
 * First we search the debug address register it uses and then we disable
 * it.
 *
 * Atomic: we hold the counter->ctx->lock and we only handle variables
 * and registers local to this cpu.
 */
void arch_uninstall_hw_breakpoint(struct perf_event *bp)
{
	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
	unsigned long *dr7;
	int i;

	for (i = 0; i < HBP_NUM; i++) {
		struct perf_event **slot = this_cpu_ptr(&bp_per_reg[i]);

		if (*slot == bp) {
			*slot = NULL;
			break;
		}
	}

	if (WARN_ONCE(i == HBP_NUM, "Can't find any breakpoint slot"))
		return;

	dr7 = this_cpu_ptr(&cpu_dr7);
	*dr7 &= ~__encode_dr7(i, info->len, info->type);

	set_debugreg(*dr7, 7);
	if (info->mask)
		set_dr_addr_mask(0, i);
}

/*
 * Check for virtual address in kernel space.
 */
int arch_check_bp_in_kernelspace(struct perf_event *bp)
{
	unsigned int len;
	unsigned long va;
	struct arch_hw_breakpoint *info = counter_arch_bp(bp);

	va = info->address;
	len = bp->attr.bp_len;

	return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
}

int arch_bp_generic_fields(int x86_len, int x86_type,
			   int *gen_len, int *gen_type)
{
	/* Type */
	switch (x86_type) {
	case X86_BREAKPOINT_EXECUTE:
		if (x86_len != X86_BREAKPOINT_LEN_X)
			return -EINVAL;

		*gen_type = HW_BREAKPOINT_X;
		*gen_len = sizeof(long);
		return 0;
	case X86_BREAKPOINT_WRITE:
		*gen_type = HW_BREAKPOINT_W;
		break;
	case X86_BREAKPOINT_RW:
		*gen_type = HW_BREAKPOINT_W | HW_BREAKPOINT_R;
		break;
	default:
		return -EINVAL;
	}

	/* Len */
	switch (x86_len) {
	case X86_BREAKPOINT_LEN_1:
		*gen_len = HW_BREAKPOINT_LEN_1;
		break;
	case X86_BREAKPOINT_LEN_2:
		*gen_len = HW_BREAKPOINT_LEN_2;
		break;
	case X86_BREAKPOINT_LEN_4:
		*gen_len = HW_BREAKPOINT_LEN_4;
		break;
#ifdef CONFIG_X86_64
	case X86_BREAKPOINT_LEN_8:
		*gen_len = HW_BREAKPOINT_LEN_8;
		break;
#endif
	default:
		return -EINVAL;
	}

	return 0;
}


static int arch_build_bp_info(struct perf_event *bp)
{
	struct arch_hw_breakpoint *info = counter_arch_bp(bp);

	info->address = bp->attr.bp_addr;

	/* Type */
	switch (bp->attr.bp_type) {
	case HW_BREAKPOINT_W:
		info->type = X86_BREAKPOINT_WRITE;
		break;
	case HW_BREAKPOINT_W | HW_BREAKPOINT_R:
		info->type = X86_BREAKPOINT_RW;
		break;
	case HW_BREAKPOINT_X:
		/*
		 * We don't allow kernel breakpoints in places that are not
		 * acceptable for kprobes.  On non-kprobes kernels, we don't
		 * allow kernel breakpoints at all.
		 */
		if (bp->attr.bp_addr >= TASK_SIZE_MAX) {
#ifdef CONFIG_KPROBES
			if (within_kprobe_blacklist(bp->attr.bp_addr))
				return -EINVAL;
#else
			return -EINVAL;
#endif
		}

		info->type = X86_BREAKPOINT_EXECUTE;
		/*
		 * x86 inst breakpoints need to have a specific undefined len.
		 * But we still need to check userspace is not trying to setup
		 * an unsupported length, to get a range breakpoint for example.
		 */
		if (bp->attr.bp_len == sizeof(long)) {
			info->len = X86_BREAKPOINT_LEN_X;
			return 0;
		}
	default:
		return -EINVAL;
	}

	/* Len */
	info->mask = 0;

	switch (bp->attr.bp_len) {
	case HW_BREAKPOINT_LEN_1:
		info->len = X86_BREAKPOINT_LEN_1;
		break;
	case HW_BREAKPOINT_LEN_2:
		info->len = X86_BREAKPOINT_LEN_2;
		break;
	case HW_BREAKPOINT_LEN_4:
		info->len = X86_BREAKPOINT_LEN_4;
		break;
#ifdef CONFIG_X86_64
	case HW_BREAKPOINT_LEN_8:
		info->len = X86_BREAKPOINT_LEN_8;
		break;
#endif
	default:
		/* AMD range breakpoint */
		if (!is_power_of_2(bp->attr.bp_len))
			return -EINVAL;
		if (bp->attr.bp_addr & (bp->attr.bp_len - 1))
			return -EINVAL;
		/*
		 * It's impossible to use a range breakpoint to fake out
		 * user vs kernel detection because bp_len - 1 can't
		 * have the high bit set.  If we ever allow range instruction
		 * breakpoints, then we'll have to check for kprobe-blacklisted
		 * addresses anywhere in the range.
		 */
		if (!cpu_has_bpext)
			return -EOPNOTSUPP;
		info->mask = bp->attr.bp_len - 1;
		info->len = X86_BREAKPOINT_LEN_1;
	}

	return 0;
}

/*
 * Validate the arch-specific HW Breakpoint register settings
 */
int arch_validate_hwbkpt_settings(struct perf_event *bp)
{
	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
	unsigned int align;
	int ret;


	ret = arch_build_bp_info(bp);
	if (ret)
		return ret;

	switch (info->len) {
	case X86_BREAKPOINT_LEN_1:
		align = 0;
		if (info->mask)
			align = info->mask;
		break;
	case X86_BREAKPOINT_LEN_2:
		align = 1;
		break;
	case X86_BREAKPOINT_LEN_4:
		align = 3;
		break;
#ifdef CONFIG_X86_64
	case X86_BREAKPOINT_LEN_8:
		align = 7;
		break;
#endif
	default:
		WARN_ON_ONCE(1);
	}

	/*
	 * Check that the low-order bits of the address are appropriate
	 * for the alignment implied by len.
	 */
	if (info->address & align)
		return -EINVAL;

	return 0;
}

/*
 * Dump the debug register contents to the user.
 * We can't dump our per cpu values because it
 * may contain cpu wide breakpoint, something that
 * doesn't belong to the current task.
 *
 * TODO: include non-ptrace user breakpoints (perf)
 */
void aout_dump_debugregs(struct user *dump)
{
	int i;
	int dr7 = 0;
	struct perf_event *bp;
	struct arch_hw_breakpoint *info;
	struct thread_struct *thread = &current->thread;

	for (i = 0; i < HBP_NUM; i++) {
		bp = thread->ptrace_bps[i];

		if (bp && !bp->attr.disabled) {
			dump->u_debugreg[i] = bp->attr.bp_addr;
			info = counter_arch_bp(bp);
			dr7 |= encode_dr7(i, info->len, info->type);
		} else {
			dump->u_debugreg[i] = 0;
		}
	}

	dump->u_debugreg[4] = 0;
	dump->u_debugreg[5] = 0;
	dump->u_debugreg[6] = current->thread.debugreg6;

	dump->u_debugreg[7] = dr7;
}
EXPORT_SYMBOL_GPL(aout_dump_debugregs);

/*
 * Release the user breakpoints used by ptrace
 */
void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
{
	int i;
	struct thread_struct *t = &tsk->thread;

	for (i = 0; i < HBP_NUM; i++) {
		unregister_hw_breakpoint(t->ptrace_bps[i]);
		t->ptrace_bps[i] = NULL;
	}

	t->debugreg6 = 0;
	t->ptrace_dr7 = 0;
}

void hw_breakpoint_restore(void)
{
	set_debugreg(__this_cpu_read(cpu_debugreg[0]), 0);
	set_debugreg(__this_cpu_read(cpu_debugreg[1]), 1);
	set_debugreg(__this_cpu_read(cpu_debugreg[2]), 2);
	set_debugreg(__this_cpu_read(cpu_debugreg[3]), 3);
	set_debugreg(current->thread.debugreg6, 6);
	set_debugreg(__this_cpu_read(cpu_dr7), 7);
}
EXPORT_SYMBOL_GPL(hw_breakpoint_restore);

/*
 * Handle debug exception notifications.
 *
 * Return value is either NOTIFY_STOP or NOTIFY_DONE as explained below.
 *
 * NOTIFY_DONE returned if one of the following conditions is true.
 * i) When the causative address is from user-space and the exception
 * is a valid one, i.e. not triggered as a result of lazy debug register
 * switching
 * ii) When there are more bits than trap<n> set in DR6 register (such
 * as BD, BS or BT) indicating that more than one debug condition is
 * met and requires some more action in do_debug().
 *
 * NOTIFY_STOP returned for all other cases
 *
 */
static int hw_breakpoint_handler(struct die_args *args)
{
	int i, cpu, rc = NOTIFY_STOP;
	struct perf_event *bp;
	unsigned long dr7, dr6;
	unsigned long *dr6_p;

	/* The DR6 value is pointed by args->err */
	dr6_p = (unsigned long *)ERR_PTR(args->err);
	dr6 = *dr6_p;

	/* If it's a single step, TRAP bits are random */
	if (dr6 & DR_STEP)
		return NOTIFY_DONE;

	/* Do an early return if no trap bits are set in DR6 */
	if ((dr6 & DR_TRAP_BITS) == 0)
		return NOTIFY_DONE;

	get_debugreg(dr7, 7);
	/* Disable breakpoints during exception handling */
	set_debugreg(0UL, 7);
	/*
	 * Assert that local interrupts are disabled
	 * Reset the DRn bits in the virtualized register value.
	 * The ptrace trigger routine will add in whatever is needed.
	 */
	current->thread.debugreg6 &= ~DR_TRAP_BITS;
	cpu = get_cpu();

	/* Handle all the breakpoints that were triggered */
	for (i = 0; i < HBP_NUM; ++i) {
		if (likely(!(dr6 & (DR_TRAP0 << i))))
			continue;

		/*
		 * The counter may be concurrently released but that can only
		 * occur from a call_rcu() path. We can then safely fetch
		 * the breakpoint, use its callback, touch its counter
		 * while we are in an rcu_read_lock() path.
		 */
		rcu_read_lock();

		bp = per_cpu(bp_per_reg[i], cpu);
		/*
		 * Reset the 'i'th TRAP bit in dr6 to denote completion of
		 * exception handling
		 */
		(*dr6_p) &= ~(DR_TRAP0 << i);
		/*
		 * bp can be NULL due to lazy debug register switching
		 * or due to concurrent perf counter removing.
		 */
		if (!bp) {
			rcu_read_unlock();
			break;
		}

		perf_bp_event(bp, args->regs);

		/*
		 * Set up resume flag to avoid breakpoint recursion when
		 * returning back to origin.
		 */
		if (bp->hw.info.type == X86_BREAKPOINT_EXECUTE)
			args->regs->flags |= X86_EFLAGS_RF;

		rcu_read_unlock();
	}
	/*
	 * Further processing in do_debug() is needed for a) user-space
	 * breakpoints (to generate signals) and b) when the system has
	 * taken exception due to multiple causes
	 */
	if ((current->thread.debugreg6 & DR_TRAP_BITS) ||
	    (dr6 & (~DR_TRAP_BITS)))
		rc = NOTIFY_DONE;

	set_debugreg(dr7, 7);
	put_cpu();

	return rc;
}

/*
 * Handle debug exception notifications.
 */
int hw_breakpoint_exceptions_notify(
		struct notifier_block *unused, unsigned long val, void *data)
{
	if (val != DIE_DEBUG)
		return NOTIFY_DONE;

	return hw_breakpoint_handler(data);
}

void hw_breakpoint_pmu_read(struct perf_event *bp)
{
	/* TODO */
}
Commit	Line	Data
0067f129 P	1	/*
	2	* This program is free software; you can redistribute it and/or modify
	3	* it under the terms of the GNU General Public License as published by
	4	* the Free Software Foundation; either version 2 of the License, or
	5	* (at your option) any later version.
	6	*
	7	* This program is distributed in the hope that it will be useful,
	8	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	9	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	10	* GNU General Public License for more details.
	11	*
	12	* You should have received a copy of the GNU General Public License
	13	* along with this program; if not, write to the Free Software
	14	* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	15	*
	16	* Copyright (C) 2007 Alan Stern
	17	* Copyright (C) 2009 IBM Corporation
24f1e32c	18	* Copyright (C) 2009 Frederic Weisbecker <fweisbec@gmail.com>
ba6909b7 P	19	*
	20	* Authors: Alan Stern <stern@rowland.harvard.edu>
	21	* K.Prasad <prasad@linux.vnet.ibm.com>
	22	* Frederic Weisbecker <fweisbec@gmail.com>
0067f129 P	23	*/
	24
	25	/*
	26	* HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
	27	* using the CPU's debug registers.
	28	*/
	29
24f1e32c FW	30	#include <linux/perf_event.h>
24f1e32c FW	31	#include <linux/hw_breakpoint.h>
0067f129 P	32	#include <linux/irqflags.h>
	33	#include <linux/notifier.h>
	34	#include <linux/kallsyms.h>
e5779e8e	35	#include <linux/kprobes.h>
0067f129 P	36	#include <linux/percpu.h>
	37	#include <linux/kdebug.h>
	38	#include <linux/kernel.h>
	39	#include <linux/module.h>
	40	#include <linux/sched.h>
0067f129 P	41	#include <linux/smp.h>
	42
	43	#include <asm/hw_breakpoint.h>
	44	#include <asm/processor.h>
	45	#include <asm/debugreg.h>
	46
24f1e32c	47	/* Per cpu debug control register value */
28b4e0d8 TH	48	DEFINE_PER_CPU(unsigned long, cpu_dr7);
28b4e0d8 TH	49	EXPORT_PER_CPU_SYMBOL(cpu_dr7);
24f1e32c FW	50
	51	/* Per cpu debug address registers values */
	52	static DEFINE_PER_CPU(unsigned long, cpu_debugreg[HBP_NUM]);
0067f129 P	53
0067f129 P	54	/*
24f1e32c FW	55	* Stores the breakpoints currently in use on each breakpoint address
24f1e32c FW	56	* register for each cpus
0067f129	57	*/
24f1e32c	58	static DEFINE_PER_CPU(struct perf_event *, bp_per_reg[HBP_NUM]);
0067f129 P	59
0067f129 P	60
2c31b795 FW	61	static inline unsigned long
2c31b795 FW	62	__encode_dr7(int drnum, unsigned int len, unsigned int type)
0067f129 P	63	{
	64	unsigned long bp_info;
	65
	66	bp_info = (len \| type) & 0xf;
	67	bp_info <<= (DR_CONTROL_SHIFT + drnum * DR_CONTROL_SIZE);
2c31b795 FW	68	bp_info \|= (DR_GLOBAL_ENABLE << (drnum * DR_ENABLE_SIZE));
2c31b795 FW	69
0067f129 P	70	return bp_info;
	71	}
	72
2c31b795 FW	73	/*
	74	* Encode the length, type, Exact, and Enable bits for a particular breakpoint
	75	* as stored in debug register 7.
	76	*/
	77	unsigned long encode_dr7(int drnum, unsigned int len, unsigned int type)
	78	{
	79	return __encode_dr7(drnum, len, type) \| DR_GLOBAL_SLOWDOWN;
	80	}
	81
24f1e32c FW	82	/*
	83	* Decode the length and type bits for a particular breakpoint as
	84	* stored in debug register 7. Return the "enabled" status.
	85	*/
	86	int decode_dr7(unsigned long dr7, int bpnum, unsigned len, unsigned type)
0067f129	87	{
24f1e32c	88	int bp_info = dr7 >> (DR_CONTROL_SHIFT + bpnum * DR_CONTROL_SIZE);
0067f129	89
24f1e32c FW	90	*len = (bp_info & 0xc) \| 0x40;
24f1e32c FW	91	*type = (bp_info & 0x3) \| 0x80;
0067f129	92
24f1e32c	93	return (dr7 >> (bpnum * DR_ENABLE_SIZE)) & 0x3;
0067f129 P	94	}
	95
	96	/*
24f1e32c FW	97	* Install a perf counter breakpoint.
	98	*
	99	* We seek a free debug address register and use it for this
	100	* breakpoint. Eventually we enable it in the debug control register.
	101	*
	102	* Atomic: we hold the counter->ctx->lock and we only handle variables
	103	* and registers local to this cpu.
0067f129	104	*/
24f1e32c	105	int arch_install_hw_breakpoint(struct perf_event *bp)
0067f129	106	{
24f1e32c FW	107	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
	108	unsigned long *dr7;
	109	int i;
	110
	111	for (i = 0; i < HBP_NUM; i++) {
89cbc767	112	struct perf_event **slot = this_cpu_ptr(&bp_per_reg[i]);
24f1e32c FW	113
	114	if (!*slot) {
	115	*slot = bp;
	116	break;
	117	}
0067f129 P	118	}
0067f129 P	119
24f1e32c FW	120	if (WARN_ONCE(i == HBP_NUM, "Can't find any breakpoint slot"))
	121	return -EBUSY;
	122
	123	set_debugreg(info->address, i);
0a3aee0d	124	__this_cpu_write(cpu_debugreg[i], info->address);
24f1e32c	125
89cbc767	126	dr7 = this_cpu_ptr(&cpu_dr7);
24f1e32c FW	127	*dr7 \|= encode_dr7(i, info->len, info->type);
	128
	129	set_debugreg(*dr7, 7);
d6d55f0b JS	130	if (info->mask)
d6d55f0b JS	131	set_dr_addr_mask(info->mask, i);
24f1e32c FW	132
24f1e32c FW	133	return 0;
0067f129 P	134	}
	135
	136	/*
24f1e32c FW	137	* Uninstall the breakpoint contained in the given counter.
	138	*
	139	* First we search the debug address register it uses and then we disable
	140	* it.
	141	*
	142	* Atomic: we hold the counter->ctx->lock and we only handle variables
	143	* and registers local to this cpu.
0067f129	144	*/
24f1e32c	145	void arch_uninstall_hw_breakpoint(struct perf_event *bp)
0067f129	146	{
24f1e32c FW	147	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
	148	unsigned long *dr7;
	149	int i;
	150
	151	for (i = 0; i < HBP_NUM; i++) {
89cbc767	152	struct perf_event **slot = this_cpu_ptr(&bp_per_reg[i]);
24f1e32c FW	153
	154	if (*slot == bp) {
	155	*slot = NULL;
	156	break;
	157	}
	158	}
	159
	160	if (WARN_ONCE(i == HBP_NUM, "Can't find any breakpoint slot"))
	161	return;
0067f129	162
89cbc767	163	dr7 = this_cpu_ptr(&cpu_dr7);
2c31b795	164	*dr7 &= ~__encode_dr7(i, info->len, info->type);
24f1e32c FW	165
24f1e32c FW	166	set_debugreg(*dr7, 7);
d6d55f0b JS	167	if (info->mask)
d6d55f0b JS	168	set_dr_addr_mask(0, i);
0067f129 P	169	}
0067f129 P	170
0067f129 P	171	/*
	172	* Check for virtual address in kernel space.
	173	*/
b2812d03	174	int arch_check_bp_in_kernelspace(struct perf_event *bp)
0067f129 P	175	{
0067f129 P	176	unsigned int len;
b2812d03 FW	177	unsigned long va;
b2812d03 FW	178	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
0067f129	179
b2812d03	180	va = info->address;
36748b95	181	len = bp->attr.bp_len;
0067f129 P	182
	183	return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
	184	}
	185
24f1e32c FW	186	int arch_bp_generic_fields(int x86_len, int x86_type,
24f1e32c FW	187	int gen_len, int gen_type)
0067f129	188	{
89e45aac FW	189	/* Type */
	190	switch (x86_type) {
	191	case X86_BREAKPOINT_EXECUTE:
	192	if (x86_len != X86_BREAKPOINT_LEN_X)
	193	return -EINVAL;
	194
	195	*gen_type = HW_BREAKPOINT_X;
f7809daf	196	*gen_len = sizeof(long);
89e45aac FW	197	return 0;
	198	case X86_BREAKPOINT_WRITE:
	199	*gen_type = HW_BREAKPOINT_W;
f7809daf	200	break;
89e45aac FW	201	case X86_BREAKPOINT_RW:
	202	*gen_type = HW_BREAKPOINT_W \| HW_BREAKPOINT_R;
	203	break;
	204	default:
	205	return -EINVAL;
	206	}
	207
	208	/* Len */
	209	switch (x86_len) {
24f1e32c FW	210	case X86_BREAKPOINT_LEN_1:
	211	*gen_len = HW_BREAKPOINT_LEN_1;
	212	break;
	213	case X86_BREAKPOINT_LEN_2:
	214	*gen_len = HW_BREAKPOINT_LEN_2;
	215	break;
	216	case X86_BREAKPOINT_LEN_4:
	217	*gen_len = HW_BREAKPOINT_LEN_4;
	218	break;
	219	#ifdef CONFIG_X86_64
	220	case X86_BREAKPOINT_LEN_8:
	221	*gen_len = HW_BREAKPOINT_LEN_8;
	222	break;
	223	#endif
	224	default:
	225	return -EINVAL;
	226	}
0067f129	227
24f1e32c FW	228	return 0;
	229	}
	230
	231
	232	static int arch_build_bp_info(struct perf_event *bp)
	233	{
	234	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
	235
	236	info->address = bp->attr.bp_addr;
	237
f7809daf FW	238	/* Type */
	239	switch (bp->attr.bp_type) {
	240	case HW_BREAKPOINT_W:
	241	info->type = X86_BREAKPOINT_WRITE;
	242	break;
	243	case HW_BREAKPOINT_W \| HW_BREAKPOINT_R:
	244	info->type = X86_BREAKPOINT_RW;
	245	break;
	246	case HW_BREAKPOINT_X:
e5779e8e AL	247	/*
	248	* We don't allow kernel breakpoints in places that are not
	249	* acceptable for kprobes. On non-kprobes kernels, we don't
	250	* allow kernel breakpoints at all.
	251	*/
	252	if (bp->attr.bp_addr >= TASK_SIZE_MAX) {
	253	#ifdef CONFIG_KPROBES
	254	if (within_kprobe_blacklist(bp->attr.bp_addr))
	255	return -EINVAL;
	256	#else
	257	return -EINVAL;
	258	#endif
	259	}
	260
f7809daf FW	261	info->type = X86_BREAKPOINT_EXECUTE;
	262	/*
	263	* x86 inst breakpoints need to have a specific undefined len.
	264	* But we still need to check userspace is not trying to setup
	265	* an unsupported length, to get a range breakpoint for example.
	266	*/
	267	if (bp->attr.bp_len == sizeof(long)) {
	268	info->len = X86_BREAKPOINT_LEN_X;
	269	return 0;
	270	}
	271	default:
	272	return -EINVAL;
	273	}
	274
24f1e32c	275	/* Len */
d6d55f0b JS	276	info->mask = 0;
d6d55f0b JS	277
24f1e32c	278	switch (bp->attr.bp_len) {
0067f129	279	case HW_BREAKPOINT_LEN_1:
24f1e32c	280	info->len = X86_BREAKPOINT_LEN_1;
0067f129 P	281	break;
0067f129 P	282	case HW_BREAKPOINT_LEN_2:
24f1e32c	283	info->len = X86_BREAKPOINT_LEN_2;
0067f129 P	284	break;
0067f129 P	285	case HW_BREAKPOINT_LEN_4:
24f1e32c	286	info->len = X86_BREAKPOINT_LEN_4;
0067f129 P	287	break;
	288	#ifdef CONFIG_X86_64
	289	case HW_BREAKPOINT_LEN_8:
24f1e32c FW	290	info->len = X86_BREAKPOINT_LEN_8;
	291	break;
	292	#endif
	293	default:
ab513927	294	/* AMD range breakpoint */
d6d55f0b JS	295	if (!is_power_of_2(bp->attr.bp_len))
d6d55f0b JS	296	return -EINVAL;
ab513927 AL	297	if (bp->attr.bp_addr & (bp->attr.bp_len - 1))
	298	return -EINVAL;
	299	/*
	300	* It's impossible to use a range breakpoint to fake out
	301	* user vs kernel detection because bp_len - 1 can't
	302	* have the high bit set. If we ever allow range instruction
	303	* breakpoints, then we'll have to check for kprobe-blacklisted
	304	* addresses anywhere in the range.
	305	*/
d6d55f0b JS	306	if (!cpu_has_bpext)
	307	return -EOPNOTSUPP;
	308	info->mask = bp->attr.bp_len - 1;
	309	info->len = X86_BREAKPOINT_LEN_1;
24f1e32c FW	310	}
24f1e32c FW	311
24f1e32c FW	312	return 0;
24f1e32c FW	313	}
d6d55f0b	314
24f1e32c FW	315	/*
	316	* Validate the arch-specific HW Breakpoint register settings
	317	*/
b2812d03	318	int arch_validate_hwbkpt_settings(struct perf_event *bp)
24f1e32c FW	319	{
	320	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
	321	unsigned int align;
	322	int ret;
	323
	324
	325	ret = arch_build_bp_info(bp);
	326	if (ret)
	327	return ret;
	328
24f1e32c FW	329	switch (info->len) {
	330	case X86_BREAKPOINT_LEN_1:
	331	align = 0;
d6d55f0b JS	332	if (info->mask)
d6d55f0b JS	333	align = info->mask;
24f1e32c FW	334	break;
	335	case X86_BREAKPOINT_LEN_2:
	336	align = 1;
	337	break;
	338	case X86_BREAKPOINT_LEN_4:
	339	align = 3;
	340	break;
	341	#ifdef CONFIG_X86_64
	342	case X86_BREAKPOINT_LEN_8:
0067f129 P	343	align = 7;
	344	break;
	345	#endif
	346	default:
d6d55f0b	347	WARN_ON_ONCE(1);
0067f129 P	348	}
0067f129 P	349
0067f129 P	350	/*
	351	* Check that the low-order bits of the address are appropriate
	352	* for the alignment implied by len.
	353	*/
24f1e32c	354	if (info->address & align)
0067f129 P	355	return -EINVAL;
0067f129 P	356
0067f129 P	357	return 0;
	358	}
	359
9f6b3c2c FW	360	/*
	361	* Dump the debug register contents to the user.
	362	* We can't dump our per cpu values because it
	363	* may contain cpu wide breakpoint, something that
	364	* doesn't belong to the current task.
	365	*
	366	* TODO: include non-ptrace user breakpoints (perf)
	367	*/
	368	void aout_dump_debugregs(struct user *dump)
	369	{
	370	int i;
	371	int dr7 = 0;
	372	struct perf_event *bp;
	373	struct arch_hw_breakpoint *info;
	374	struct thread_struct *thread = &current->thread;
	375
	376	for (i = 0; i < HBP_NUM; i++) {
	377	bp = thread->ptrace_bps[i];
	378
	379	if (bp && !bp->attr.disabled) {
	380	dump->u_debugreg[i] = bp->attr.bp_addr;
	381	info = counter_arch_bp(bp);
	382	dr7 \|= encode_dr7(i, info->len, info->type);
	383	} else {
	384	dump->u_debugreg[i] = 0;
	385	}
	386	}
	387
	388	dump->u_debugreg[4] = 0;
	389	dump->u_debugreg[5] = 0;
	390	dump->u_debugreg[6] = current->thread.debugreg6;
	391
	392	dump->u_debugreg[7] = dr7;
	393	}
68efa37d	394	EXPORT_SYMBOL_GPL(aout_dump_debugregs);
9f6b3c2c	395
24f1e32c FW	396	/*
	397	* Release the user breakpoints used by ptrace
	398	*/
	399	void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
0067f129	400	{
24f1e32c FW	401	int i;
	402	struct thread_struct *t = &tsk->thread;
	403
	404	for (i = 0; i < HBP_NUM; i++) {
	405	unregister_hw_breakpoint(t->ptrace_bps[i]);
	406	t->ptrace_bps[i] = NULL;
	407	}
f7da04c9 ON	408
	409	t->debugreg6 = 0;
	410	t->ptrace_dr7 = 0;
0067f129 P	411	}
0067f129 P	412
24f1e32c	413	void hw_breakpoint_restore(void)
0067f129	414	{
0a3aee0d TH	415	set_debugreg(__this_cpu_read(cpu_debugreg[0]), 0);
	416	set_debugreg(__this_cpu_read(cpu_debugreg[1]), 1);
	417	set_debugreg(__this_cpu_read(cpu_debugreg[2]), 2);
	418	set_debugreg(__this_cpu_read(cpu_debugreg[3]), 3);
24f1e32c	419	set_debugreg(current->thread.debugreg6, 6);
0a3aee0d	420	set_debugreg(__this_cpu_read(cpu_dr7), 7);
0067f129	421	}
24f1e32c	422	EXPORT_SYMBOL_GPL(hw_breakpoint_restore);
0067f129 P	423
	424	/*
	425	* Handle debug exception notifications.
	426	*
	427	* Return value is either NOTIFY_STOP or NOTIFY_DONE as explained below.
	428	*
	429	* NOTIFY_DONE returned if one of the following conditions is true.
	430	* i) When the causative address is from user-space and the exception
	431	* is a valid one, i.e. not triggered as a result of lazy debug register
	432	* switching
	433	* ii) When there are more bits than trap<n> set in DR6 register (such
	434	* as BD, BS or BT) indicating that more than one debug condition is
	435	* met and requires some more action in do_debug().
	436	*
	437	* NOTIFY_STOP returned for all other cases
	438	*
	439	*/
9c54b616	440	static int hw_breakpoint_handler(struct die_args *args)
0067f129 P	441	{
0067f129 P	442	int i, cpu, rc = NOTIFY_STOP;
24f1e32c	443	struct perf_event *bp;
62edab90 P	444	unsigned long dr7, dr6;
	445	unsigned long *dr6_p;
	446
	447	/* The DR6 value is pointed by args->err */
	448	dr6_p = (unsigned long *)ERR_PTR(args->err);
	449	dr6 = *dr6_p;
0067f129	450
6c0aca28 FW	451	/* If it's a single step, TRAP bits are random */
	452	if (dr6 & DR_STEP)
	453	return NOTIFY_DONE;
	454
0067f129 P	455	/* Do an early return if no trap bits are set in DR6 */
	456	if ((dr6 & DR_TRAP_BITS) == 0)
	457	return NOTIFY_DONE;
	458
0067f129 P	459	get_debugreg(dr7, 7);
	460	/* Disable breakpoints during exception handling */
	461	set_debugreg(0UL, 7);
	462	/*
	463	* Assert that local interrupts are disabled
	464	* Reset the DRn bits in the virtualized register value.
	465	* The ptrace trigger routine will add in whatever is needed.
	466	*/
	467	current->thread.debugreg6 &= ~DR_TRAP_BITS;
	468	cpu = get_cpu();
	469
	470	/* Handle all the breakpoints that were triggered */
	471	for (i = 0; i < HBP_NUM; ++i) {
	472	if (likely(!(dr6 & (DR_TRAP0 << i))))
	473	continue;
24f1e32c	474
0067f129	475	/*
24f1e32c FW	476	* The counter may be concurrently released but that can only
	477	* occur from a call_rcu() path. We can then safely fetch
	478	* the breakpoint, use its callback, touch its counter
	479	* while we are in an rcu_read_lock() path.
0067f129	480	*/
24f1e32c FW	481	rcu_read_lock();
	482
	483	bp = per_cpu(bp_per_reg[i], cpu);
62edab90 P	484	/*
	485	* Reset the 'i'th TRAP bit in dr6 to denote completion of
	486	* exception handling
	487	*/
	488	(*dr6_p) &= ~(DR_TRAP0 << i);
0067f129 P	489	/*
0067f129 P	490	* bp can be NULL due to lazy debug register switching
24f1e32c	491	* or due to concurrent perf counter removing.
0067f129	492	*/
24f1e32c FW	493	if (!bp) {
	494	rcu_read_unlock();
	495	break;
	496	}
	497
b326e956	498	perf_bp_event(bp, args->regs);
0067f129	499
0c4519e8 FW	500	/*
	501	* Set up resume flag to avoid breakpoint recursion when
	502	* returning back to origin.
	503	*/
	504	if (bp->hw.info.type == X86_BREAKPOINT_EXECUTE)
	505	args->regs->flags \|= X86_EFLAGS_RF;
	506
24f1e32c	507	rcu_read_unlock();
0067f129	508	}
e0e53db6 P	509	/*
	510	* Further processing in do_debug() is needed for a) user-space
	511	* breakpoints (to generate signals) and b) when the system has
	512	* taken exception due to multiple causes
	513	*/
	514	if ((current->thread.debugreg6 & DR_TRAP_BITS) \|\|
	515	(dr6 & (~DR_TRAP_BITS)))
0067f129 P	516	rc = NOTIFY_DONE;
	517
	518	set_debugreg(dr7, 7);
eadb8a09	519	put_cpu();
24f1e32c	520
0067f129 P	521	return rc;
	522	}
	523
	524	/*
	525	* Handle debug exception notifications.
	526	*/
9c54b616	527	int hw_breakpoint_exceptions_notify(
0067f129 P	528	struct notifier_block unused, unsigned long val, void data)
	529	{
	530	if (val != DIE_DEBUG)
	531	return NOTIFY_DONE;
	532
	533	return hw_breakpoint_handler(data);
	534	}
24f1e32c FW	535
	536	void hw_breakpoint_pmu_read(struct perf_event *bp)
	537	{
	538	/* TODO */
	539	}