[linux-2.6-block.git] / arch / x86 / kernel / head_64.S

/*
 *  linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit
 *
 *  Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
 *  Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
 *  Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
 *  Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
 *  Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
 */


#include <linux/linkage.h>
#include <linux/threads.h>
#include <linux/init.h>
#include <asm/segment.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/msr.h>
#include <asm/cache.h>
#include <asm/processor-flags.h>
#include <asm/percpu.h>
#include <asm/nops.h>
#include "../entry/calling.h"

#ifdef CONFIG_PARAVIRT
#include <asm/asm-offsets.h>
#include <asm/paravirt.h>
#define GET_CR2_INTO(reg) GET_CR2_INTO_RAX ; movq %rax, reg
#else
#define GET_CR2_INTO(reg) movq %cr2, reg
#define INTERRUPT_RETURN iretq
#endif

/* we are not able to switch in one step to the final KERNEL ADDRESS SPACE
 * because we need identity-mapped pages.
 *
 */

#define pud_index(x)	(((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))

L4_PAGE_OFFSET = pgd_index(__PAGE_OFFSET)
L4_START_KERNEL = pgd_index(__START_KERNEL_map)
L3_START_KERNEL = pud_index(__START_KERNEL_map)

	.text
	__HEAD
	.code64
	.globl startup_64
startup_64:
	/*
	 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
	 * and someone has loaded an identity mapped page table
	 * for us.  These identity mapped page tables map all of the
	 * kernel pages and possibly all of memory.
	 *
	 * %rsi holds a physical pointer to real_mode_data.
	 *
	 * We come here either directly from a 64bit bootloader, or from
	 * arch/x86/boot/compressed/head_64.S.
	 *
	 * We only come here initially at boot nothing else comes here.
	 *
	 * Since we may be loaded at an address different from what we were
	 * compiled to run at we first fixup the physical addresses in our page
	 * tables and then reload them.
	 */

	/*
	 * Setup stack for verify_cpu(). "-8" because stack_start is defined
	 * this way, see below. Our best guess is a NULL ptr for stack
	 * termination heuristics and we don't want to break anything which
	 * might depend on it (kgdb, ...).
	 */
	leaq	(__end_init_task - 8)(%rip), %rsp

	/* Sanitize CPU configuration */
	call verify_cpu

	/*
	 * Compute the delta between the address I am compiled to run at and the
	 * address I am actually running at.
	 */
	leaq	_text(%rip), %rbp
	subq	$_text - __START_KERNEL_map, %rbp

	/* Is the address not 2M aligned? */
	testl	$~PMD_PAGE_MASK, %ebp
	jnz	bad_address

	/*
	 * Is the address too large?
	 */
	leaq	_text(%rip), %rax
	shrq	$MAX_PHYSMEM_BITS, %rax
	jnz	bad_address

	/*
	 * Fixup the physical addresses in the page table
	 */
	addq	%rbp, early_level4_pgt + (L4_START_KERNEL*8)(%rip)

	addq	%rbp, level3_kernel_pgt + (510*8)(%rip)
	addq	%rbp, level3_kernel_pgt + (511*8)(%rip)

	addq	%rbp, level2_fixmap_pgt + (506*8)(%rip)

	/*
	 * Set up the identity mapping for the switchover.  These
	 * entries should *NOT* have the global bit set!  This also
	 * creates a bunch of nonsense entries but that is fine --
	 * it avoids problems around wraparound.
	 */
	leaq	_text(%rip), %rdi
	leaq	early_level4_pgt(%rip), %rbx

	movq	%rdi, %rax
	shrq	$PGDIR_SHIFT, %rax

	leaq	(4096 + _KERNPG_TABLE)(%rbx), %rdx
	movq	%rdx, 0(%rbx,%rax,8)
	movq	%rdx, 8(%rbx,%rax,8)

	addq	$4096, %rdx
	movq	%rdi, %rax
	shrq	$PUD_SHIFT, %rax
	andl	$(PTRS_PER_PUD-1), %eax
	movq	%rdx, 4096(%rbx,%rax,8)
	incl	%eax
	andl	$(PTRS_PER_PUD-1), %eax
	movq	%rdx, 4096(%rbx,%rax,8)

	addq	$8192, %rbx
	movq	%rdi, %rax
	shrq	$PMD_SHIFT, %rdi
	addq	$(__PAGE_KERNEL_LARGE_EXEC & ~_PAGE_GLOBAL), %rax
	leaq	(_end - 1)(%rip), %rcx
	shrq	$PMD_SHIFT, %rcx
	subq	%rdi, %rcx
	incl	%ecx

1:
	andq	$(PTRS_PER_PMD - 1), %rdi
	movq	%rax, (%rbx,%rdi,8)
	incq	%rdi
	addq	$PMD_SIZE, %rax
	decl	%ecx
	jnz	1b

	/*
	 * Fixup the kernel text+data virtual addresses. Note that
	 * we might write invalid pmds, when the kernel is relocated
	 * cleanup_highmap() fixes this up along with the mappings
	 * beyond _end.
	 */
	leaq	level2_kernel_pgt(%rip), %rdi
	leaq	4096(%rdi), %r8
	/* See if it is a valid page table entry */
1:	testb	$1, 0(%rdi)
	jz	2f
	addq	%rbp, 0(%rdi)
	/* Go to the next page */
2:	addq	$8, %rdi
	cmp	%r8, %rdi
	jne	1b

	/* Fixup phys_base */
	addq	%rbp, phys_base(%rip)

	movq	$(early_level4_pgt - __START_KERNEL_map), %rax
	jmp 1f
ENTRY(secondary_startup_64)
	/*
	 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
	 * and someone has loaded a mapped page table.
	 *
	 * %rsi holds a physical pointer to real_mode_data.
	 *
	 * We come here either from startup_64 (using physical addresses)
	 * or from trampoline.S (using virtual addresses).
	 *
	 * Using virtual addresses from trampoline.S removes the need
	 * to have any identity mapped pages in the kernel page table
	 * after the boot processor executes this code.
	 */

	/* Sanitize CPU configuration */
	call verify_cpu

	movq	$(init_level4_pgt - __START_KERNEL_map), %rax
1:

	/* Enable PAE mode and PGE */
	movl	$(X86_CR4_PAE | X86_CR4_PGE), %ecx
	movq	%rcx, %cr4

	/* Setup early boot stage 4 level pagetables. */
	addq	phys_base(%rip), %rax
	movq	%rax, %cr3

	/* Ensure I am executing from virtual addresses */
	movq	$1f, %rax
	jmp	*%rax
1:

	/* Check if nx is implemented */
	movl	$0x80000001, %eax
	cpuid
	movl	%edx,%edi

	/* Setup EFER (Extended Feature Enable Register) */
	movl	$MSR_EFER, %ecx
	rdmsr
	btsl	$_EFER_SCE, %eax	/* Enable System Call */
	btl	$20,%edi		/* No Execute supported? */
	jnc     1f
	btsl	$_EFER_NX, %eax
	btsq	$_PAGE_BIT_NX,early_pmd_flags(%rip)
1:	wrmsr				/* Make changes effective */

	/* Setup cr0 */
#define CR0_STATE	(X86_CR0_PE | X86_CR0_MP | X86_CR0_ET | \
			 X86_CR0_NE | X86_CR0_WP | X86_CR0_AM | \
			 X86_CR0_PG)
	movl	$CR0_STATE, %eax
	/* Make changes effective */
	movq	%rax, %cr0

	/* Setup a boot time stack */
	movq stack_start(%rip), %rsp

	/* zero EFLAGS after setting rsp */
	pushq $0
	popfq

	/*
	 * We must switch to a new descriptor in kernel space for the GDT
	 * because soon the kernel won't have access anymore to the userspace
	 * addresses where we're currently running on. We have to do that here
	 * because in 32bit we couldn't load a 64bit linear address.
	 */
	lgdt	early_gdt_descr(%rip)

	/* set up data segments */
	xorl %eax,%eax
	movl %eax,%ds
	movl %eax,%ss
	movl %eax,%es

	/*
	 * We don't really need to load %fs or %gs, but load them anyway
	 * to kill any stale realmode selectors.  This allows execution
	 * under VT hardware.
	 */
	movl %eax,%fs
	movl %eax,%gs

	/* Set up %gs.
	 *
	 * The base of %gs always points to the bottom of the irqstack
	 * union.  If the stack protector canary is enabled, it is
	 * located at %gs:40.  Note that, on SMP, the boot cpu uses
	 * init data section till per cpu areas are set up.
	 */
	movl	$MSR_GS_BASE,%ecx
	movl	initial_gs(%rip),%eax
	movl	initial_gs+4(%rip),%edx
	wrmsr	

	/* rsi is pointer to real mode structure with interesting info.
	   pass it to C */
	movq	%rsi, %rdi
	
	/* Finally jump to run C code and to be on real kernel address
	 * Since we are running on identity-mapped space we have to jump
	 * to the full 64bit address, this is only possible as indirect
	 * jump.  In addition we need to ensure %cs is set so we make this
	 * a far return.
	 *
	 * Note: do not change to far jump indirect with 64bit offset.
	 *
	 * AMD does not support far jump indirect with 64bit offset.
	 * AMD64 Architecture Programmer's Manual, Volume 3: states only
	 *	JMP FAR mem16:16 FF /5 Far jump indirect,
	 *		with the target specified by a far pointer in memory.
	 *	JMP FAR mem16:32 FF /5 Far jump indirect,
	 *		with the target specified by a far pointer in memory.
	 *
	 * Intel64 does support 64bit offset.
	 * Software Developer Manual Vol 2: states:
	 *	FF /5 JMP m16:16 Jump far, absolute indirect,
	 *		address given in m16:16
	 *	FF /5 JMP m16:32 Jump far, absolute indirect,
	 *		address given in m16:32.
	 *	REX.W + FF /5 JMP m16:64 Jump far, absolute indirect,
	 *		address given in m16:64.
	 */
	movq	initial_code(%rip),%rax
	pushq	$0		# fake return address to stop unwinder
	pushq	$__KERNEL_CS	# set correct cs
	pushq	%rax		# target address in negative space
	lretq

#include "verify_cpu.S"

#ifdef CONFIG_HOTPLUG_CPU
/*
 * Boot CPU0 entry point. It's called from play_dead(). Everything has been set
 * up already except stack. We just set up stack here. Then call
 * start_secondary().
 */
ENTRY(start_cpu0)
	movq stack_start(%rip),%rsp
	movq	initial_code(%rip),%rax
	pushq	$0		# fake return address to stop unwinder
	pushq	$__KERNEL_CS	# set correct cs
	pushq	%rax		# target address in negative space
	lretq
ENDPROC(start_cpu0)
#endif

	/* SMP bootup changes these two */
	__REFDATA
	.balign	8
	GLOBAL(initial_code)
	.quad	x86_64_start_kernel
	GLOBAL(initial_gs)
	.quad	INIT_PER_CPU_VAR(irq_stack_union)

	GLOBAL(stack_start)
	.quad  init_thread_union+THREAD_SIZE-8
	.word  0
	__FINITDATA

bad_address:
	jmp bad_address

	__INIT
ENTRY(early_idt_handler_array)
	# 104(%rsp) %rflags
	#  96(%rsp) %cs
	#  88(%rsp) %rip
	#  80(%rsp) error code
	i = 0
	.rept NUM_EXCEPTION_VECTORS
	.ifeq (EXCEPTION_ERRCODE_MASK >> i) & 1
	pushq $0		# Dummy error code, to make stack frame uniform
	.endif
	pushq $i		# 72(%rsp) Vector number
	jmp early_idt_handler_common
	i = i + 1
	.fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc
	.endr
ENDPROC(early_idt_handler_array)

early_idt_handler_common:
	/*
	 * The stack is the hardware frame, an error code or zero, and the
	 * vector number.
	 */
	cld

	incl early_recursion_flag(%rip)

	/* The vector number is currently in the pt_regs->di slot. */
	pushq %rsi				/* pt_regs->si */
	movq 8(%rsp), %rsi			/* RSI = vector number */
	movq %rdi, 8(%rsp)			/* pt_regs->di = RDI */
	pushq %rdx				/* pt_regs->dx */
	pushq %rcx				/* pt_regs->cx */
	pushq %rax				/* pt_regs->ax */
	pushq %r8				/* pt_regs->r8 */
	pushq %r9				/* pt_regs->r9 */
	pushq %r10				/* pt_regs->r10 */
	pushq %r11				/* pt_regs->r11 */
	pushq %rbx				/* pt_regs->bx */
	pushq %rbp				/* pt_regs->bp */
	pushq %r12				/* pt_regs->r12 */
	pushq %r13				/* pt_regs->r13 */
	pushq %r14				/* pt_regs->r14 */
	pushq %r15				/* pt_regs->r15 */

	cmpq $14,%rsi		/* Page fault? */
	jnz 10f
	GET_CR2_INTO(%rdi)	/* Can clobber any volatile register if pv */
	call early_make_pgtable
	andl %eax,%eax
	jz 20f			/* All good */

10:
	movq %rsp,%rdi		/* RDI = pt_regs; RSI is already trapnr */
	call early_fixup_exception

20:
	decl early_recursion_flag(%rip)
	jmp restore_regs_and_iret
ENDPROC(early_idt_handler_common)

	__INITDATA

	.balign 4
GLOBAL(early_recursion_flag)
	.long 0

#define NEXT_PAGE(name) \
	.balign	PAGE_SIZE; \
GLOBAL(name)

/* Automate the creation of 1 to 1 mapping pmd entries */
#define PMDS(START, PERM, COUNT)			\
	i = 0 ;						\
	.rept (COUNT) ;					\
	.quad	(START) + (i << PMD_SHIFT) + (PERM) ;	\
	i = i + 1 ;					\
	.endr

	__INITDATA
NEXT_PAGE(early_level4_pgt)
	.fill	511,8,0
	.quad	level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE

NEXT_PAGE(early_dynamic_pgts)
	.fill	512*EARLY_DYNAMIC_PAGE_TABLES,8,0

	.data

#ifndef CONFIG_XEN
NEXT_PAGE(init_level4_pgt)
	.fill	512,8,0
#else
NEXT_PAGE(init_level4_pgt)
	.quad   level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
	.org    init_level4_pgt + L4_PAGE_OFFSET*8, 0
	.quad   level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
	.org    init_level4_pgt + L4_START_KERNEL*8, 0
	/* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
	.quad   level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE

NEXT_PAGE(level3_ident_pgt)
	.quad	level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
	.fill	511, 8, 0
NEXT_PAGE(level2_ident_pgt)
	/* Since I easily can, map the first 1G.
	 * Don't set NX because code runs from these pages.
	 */
	PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD)
#endif

NEXT_PAGE(level3_kernel_pgt)
	.fill	L3_START_KERNEL,8,0
	/* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
	.quad	level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE
	.quad	level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE

NEXT_PAGE(level2_kernel_pgt)
	/*
	 * 512 MB kernel mapping. We spend a full page on this pagetable
	 * anyway.
	 *
	 * The kernel code+data+bss must not be bigger than that.
	 *
	 * (NOTE: at +512MB starts the module area, see MODULES_VADDR.
	 *  If you want to increase this then increase MODULES_VADDR
	 *  too.)
	 */
	PMDS(0, __PAGE_KERNEL_LARGE_EXEC,
		KERNEL_IMAGE_SIZE/PMD_SIZE)

NEXT_PAGE(level2_fixmap_pgt)
	.fill	506,8,0
	.quad	level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
	/* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */
	.fill	5,8,0

NEXT_PAGE(level1_fixmap_pgt)
	.fill	512,8,0

#undef PMDS

	.data
	.align 16
	.globl early_gdt_descr
early_gdt_descr:
	.word	GDT_ENTRIES*8-1
early_gdt_descr_base:
	.quad	INIT_PER_CPU_VAR(gdt_page)

ENTRY(phys_base)
	/* This must match the first entry in level2_kernel_pgt */
	.quad   0x0000000000000000

#include "../../x86/xen/xen-head.S"
	
	__PAGE_ALIGNED_BSS
NEXT_PAGE(empty_zero_page)
	.skip PAGE_SIZE
Commit	Line	Data
1da177e4	1	/*
5b171e82	2	* linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit
1da177e4 LT	3	*
	4	* Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
	5	* Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
	6	* Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
	7	* Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
1ab60e0f	8	* Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
1da177e4 LT	9	*/
	10
	11
	12	#include <linux/linkage.h>
	13	#include <linux/threads.h>
f6c2e333	14	#include <linux/init.h>
1da177e4	15	#include <asm/segment.h>
67dcbb6b	16	#include <asm/pgtable.h>
1da177e4 LT	17	#include <asm/page.h>
	18	#include <asm/msr.h>
	19	#include <asm/cache.h>
369101da	20	#include <asm/processor-flags.h>
b12d8db8	21	#include <asm/percpu.h>
9900aa2f	22	#include <asm/nops.h>
7bbcdb1c	23	#include "../entry/calling.h"
1ab60e0f	24
49a69787 GOC	25	#ifdef CONFIG_PARAVIRT
	26	#include <asm/asm-offsets.h>
	27	#include <asm/paravirt.h>
ffc4bc9c	28	#define GET_CR2_INTO(reg) GET_CR2_INTO_RAX ; movq %rax, reg
49a69787	29	#else
ffc4bc9c	30	#define GET_CR2_INTO(reg) movq %cr2, reg
9900aa2f	31	#define INTERRUPT_RETURN iretq
49a69787 GOC	32	#endif
49a69787 GOC	33
3ad2f3fb	34	/* we are not able to switch in one step to the final KERNEL ADDRESS SPACE
1ab60e0f VG	35	* because we need identity-mapped pages.
1ab60e0f VG	36	*
1da177e4 LT	37	*/
1da177e4 LT	38
a6523748 EH	39	#define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
	40
	41	L4_PAGE_OFFSET = pgd_index(__PAGE_OFFSET)
a6523748 EH	42	L4_START_KERNEL = pgd_index(__START_KERNEL_map)
	43	L3_START_KERNEL = pud_index(__START_KERNEL_map)
	44
1da177e4	45	.text
4ae59b91	46	__HEAD
1ab60e0f VG	47	.code64
	48	.globl startup_64
	49	startup_64:
1da177e4	50	/*
1256276c	51	* At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
1ab60e0f VG	52	* and someone has loaded an identity mapped page table
	53	* for us. These identity mapped page tables map all of the
	54	* kernel pages and possibly all of memory.
	55	*
8170e6be	56	* %rsi holds a physical pointer to real_mode_data.
1ab60e0f VG	57	*
1ab60e0f VG	58	* We come here either directly from a 64bit bootloader, or from
5b171e82	59	* arch/x86/boot/compressed/head_64.S.
1ab60e0f VG	60	*
	61	* We only come here initially at boot nothing else comes here.
	62	*
	63	* Since we may be loaded at an address different from what we were
	64	* compiled to run at we first fixup the physical addresses in our page
	65	* tables and then reload them.
1da177e4 LT	66	*/
1da177e4 LT	67
91ed140d BP	68	/*
	69	* Setup stack for verify_cpu(). "-8" because stack_start is defined
	70	* this way, see below. Our best guess is a NULL ptr for stack
	71	* termination heuristics and we don't want to break anything which
	72	* might depend on it (kgdb, ...).
	73	*/
	74	leaq (__end_init_task - 8)(%rip), %rsp
	75
04633df0 BP	76	/* Sanitize CPU configuration */
	77	call verify_cpu
	78
8170e6be PA	79	/*
8170e6be PA	80	* Compute the delta between the address I am compiled to run at and the
1ab60e0f	81	* address I am actually running at.
1da177e4	82	*/
1ab60e0f VG	83	leaq _text(%rip), %rbp
	84	subq $_text - __START_KERNEL_map, %rbp
	85
	86	/* Is the address not 2M aligned? */
a4733143	87	testl $~PMD_PAGE_MASK, %ebp
1ab60e0f VG	88	jnz bad_address
1ab60e0f VG	89
8170e6be PA	90	/*
8170e6be PA	91	* Is the address too large?
1da177e4	92	*/
8170e6be PA	93	leaq _text(%rip), %rax
	94	shrq $MAX_PHYSMEM_BITS, %rax
	95	jnz bad_address
1ab60e0f	96
8170e6be PA	97	/*
	98	* Fixup the physical addresses in the page table
	99	*/
	100	addq %rbp, early_level4_pgt + (L4_START_KERNEL*8)(%rip)
b1c931e3	101
1ab60e0f	102	addq %rbp, level3_kernel_pgt + (510*8)(%rip)
b1c931e3 EB	103	addq %rbp, level3_kernel_pgt + (511*8)(%rip)
	104
	105	addq %rbp, level2_fixmap_pgt + (506*8)(%rip)
1ab60e0f	106
8170e6be PA	107	/*
	108	* Set up the identity mapping for the switchover. These
	109	* entries should NOT have the global bit set! This also
	110	* creates a bunch of nonsense entries but that is fine --
	111	* it avoids problems around wraparound.
	112	*/
1ab60e0f	113	leaq _text(%rip), %rdi
8170e6be	114	leaq early_level4_pgt(%rip), %rbx
1ab60e0f VG	115
1ab60e0f VG	116	movq %rdi, %rax
8170e6be	117	shrq $PGDIR_SHIFT, %rax
1ab60e0f	118
8170e6be PA	119	leaq (4096 + _KERNPG_TABLE)(%rbx), %rdx
	120	movq %rdx, 0(%rbx,%rax,8)
	121	movq %rdx, 8(%rbx,%rax,8)
1ab60e0f	122
8170e6be	123	addq $4096, %rdx
1ab60e0f	124	movq %rdi, %rax
8170e6be PA	125	shrq $PUD_SHIFT, %rax
8170e6be PA	126	andl $(PTRS_PER_PUD-1), %eax
e9d0626e ZY	127	movq %rdx, 4096(%rbx,%rax,8)
	128	incl %eax
	129	andl $(PTRS_PER_PUD-1), %eax
	130	movq %rdx, 4096(%rbx,%rax,8)
8170e6be PA	131
	132	addq $8192, %rbx
	133	movq %rdi, %rax
	134	shrq $PMD_SHIFT, %rdi
	135	addq $(__PAGE_KERNEL_LARGE_EXEC & ~_PAGE_GLOBAL), %rax
	136	leaq (_end - 1)(%rip), %rcx
	137	shrq $PMD_SHIFT, %rcx
	138	subq %rdi, %rcx
	139	incl %ecx
	140
	141	1:
	142	andq $(PTRS_PER_PMD - 1), %rdi
	143	movq %rax, (%rbx,%rdi,8)
	144	incq %rdi
	145	addq $PMD_SIZE, %rax
	146	decl %ecx
	147	jnz 1b
1ab60e0f	148
31eedd82 TG	149	/*
	150	* Fixup the kernel text+data virtual addresses. Note that
	151	* we might write invalid pmds, when the kernel is relocated
	152	* cleanup_highmap() fixes this up along with the mappings
	153	* beyond _end.
1ab60e0f VG	154	*/
	155	leaq level2_kernel_pgt(%rip), %rdi
	156	leaq 4096(%rdi), %r8
	157	/* See if it is a valid page table entry */
3e1aa7cb	158	1: testb $1, 0(%rdi)
1ab60e0f VG	159	jz 2f
	160	addq %rbp, 0(%rdi)
	161	/* Go to the next page */
	162	2: addq $8, %rdi
	163	cmp %r8, %rdi
	164	jne 1b
	165
	166	/* Fixup phys_base */
	167	addq %rbp, phys_base(%rip)
1da177e4	168
8170e6be PA	169	movq $(early_level4_pgt - __START_KERNEL_map), %rax
8170e6be PA	170	jmp 1f
90b1c208	171	ENTRY(secondary_startup_64)
1ab60e0f	172	/*
1256276c	173	* At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
1ab60e0f VG	174	* and someone has loaded a mapped page table.
1ab60e0f VG	175	*
8170e6be	176	* %rsi holds a physical pointer to real_mode_data.
1ab60e0f VG	177	*
	178	* We come here either from startup_64 (using physical addresses)
	179	* or from trampoline.S (using virtual addresses).
	180	*
	181	* Using virtual addresses from trampoline.S removes the need
	182	* to have any identity mapped pages in the kernel page table
	183	* after the boot processor executes this code.
1da177e4 LT	184	*/
1da177e4 LT	185
04633df0 BP	186	/* Sanitize CPU configuration */
	187	call verify_cpu
	188
8170e6be PA	189	movq $(init_level4_pgt - __START_KERNEL_map), %rax
	190	1:
	191
1da177e4	192	/* Enable PAE mode and PGE */
8170e6be PA	193	movl $(X86_CR4_PAE \| X86_CR4_PGE), %ecx
8170e6be PA	194	movq %rcx, %cr4
1da177e4 LT	195
1da177e4 LT	196	/* Setup early boot stage 4 level pagetables. */
1ab60e0f	197	addq phys_base(%rip), %rax
1da177e4 LT	198	movq %rax, %cr3
1da177e4 LT	199
1ab60e0f VG	200	/* Ensure I am executing from virtual addresses */
	201	movq $1f, %rax
	202	jmp *%rax
	203	1:
	204
1da177e4 LT	205	/* Check if nx is implemented */
	206	movl $0x80000001, %eax
	207	cpuid
	208	movl %edx,%edi
	209
	210	/* Setup EFER (Extended Feature Enable Register) */
	211	movl $MSR_EFER, %ecx
	212	rdmsr
1ab60e0f VG	213	btsl $_EFER_SCE, %eax /* Enable System Call */
1ab60e0f VG	214	btl $20,%edi /* No Execute supported? */
1da177e4 LT	215	jnc 1f
1da177e4 LT	216	btsl $_EFER_NX, %eax
78d77df7	217	btsq $_PAGE_BIT_NX,early_pmd_flags(%rip)
1ab60e0f	218	1: wrmsr /* Make changes effective */
1da177e4 LT	219
1da177e4 LT	220	/* Setup cr0 */
369101da CG	221	#define CR0_STATE (X86_CR0_PE \| X86_CR0_MP \| X86_CR0_ET \| \
	222	X86_CR0_NE \| X86_CR0_WP \| X86_CR0_AM \| \
	223	X86_CR0_PG)
	224	movl $CR0_STATE, %eax
1da177e4 LT	225	/* Make changes effective */
	226	movq %rax, %cr0
	227
	228	/* Setup a boot time stack */
8170e6be	229	movq stack_start(%rip), %rsp
1da177e4 LT	230
	231	/* zero EFLAGS after setting rsp */
	232	pushq $0
	233	popfq
	234
	235	/*
	236	* We must switch to a new descriptor in kernel space for the GDT
	237	* because soon the kernel won't have access anymore to the userspace
	238	* addresses where we're currently running on. We have to do that here
	239	* because in 32bit we couldn't load a 64bit linear address.
	240	*/
a939098a	241	lgdt early_gdt_descr(%rip)
1da177e4	242
8ec6993d BG	243	/* set up data segments */
8ec6993d BG	244	xorl %eax,%eax
ffb60175 ZA	245	movl %eax,%ds
	246	movl %eax,%ss
	247	movl %eax,%es
	248
	249	/*
	250	* We don't really need to load %fs or %gs, but load them anyway
	251	* to kill any stale realmode selectors. This allows execution
	252	* under VT hardware.
	253	*/
	254	movl %eax,%fs
	255	movl %eax,%gs
	256
f32ff538 TH	257	/* Set up %gs.
f32ff538 TH	258	*
947e76cd BG	259	* The base of %gs always points to the bottom of the irqstack
	260	* union. If the stack protector canary is enabled, it is
	261	* located at %gs:40. Note that, on SMP, the boot cpu uses
	262	* init data section till per cpu areas are set up.
f32ff538	263	*/
1da177e4	264	movl $MSR_GS_BASE,%ecx
650fb439 BG	265	movl initial_gs(%rip),%eax
650fb439 BG	266	movl initial_gs+4(%rip),%edx
1da177e4 LT	267	wrmsr
1da177e4 LT	268
8170e6be	269	/* rsi is pointer to real mode structure with interesting info.
1da177e4	270	pass it to C */
8170e6be	271	movq %rsi, %rdi
1da177e4 LT	272
	273	/* Finally jump to run C code and to be on real kernel address
	274	* Since we are running on identity-mapped space we have to jump
26374c7b EB	275	* to the full 64bit address, this is only possible as indirect
	276	* jump. In addition we need to ensure %cs is set so we make this
	277	* a far return.
8170e6be PA	278	*
	279	* Note: do not change to far jump indirect with 64bit offset.
	280	*
	281	* AMD does not support far jump indirect with 64bit offset.
	282	* AMD64 Architecture Programmer's Manual, Volume 3: states only
	283	* JMP FAR mem16:16 FF /5 Far jump indirect,
	284	* with the target specified by a far pointer in memory.
	285	* JMP FAR mem16:32 FF /5 Far jump indirect,
	286	* with the target specified by a far pointer in memory.
	287	*
	288	* Intel64 does support 64bit offset.
	289	* Software Developer Manual Vol 2: states:
	290	* FF /5 JMP m16:16 Jump far, absolute indirect,
	291	* address given in m16:16
	292	* FF /5 JMP m16:32 Jump far, absolute indirect,
	293	* address given in m16:32.
	294	* REX.W + FF /5 JMP m16:64 Jump far, absolute indirect,
	295	* address given in m16:64.
1da177e4 LT	296	*/
1da177e4 LT	297	movq initial_code(%rip),%rax
26374c7b EB	298	pushq $0 # fake return address to stop unwinder
	299	pushq $__KERNEL_CS # set correct cs
	300	pushq %rax # target address in negative space
	301	lretq
1da177e4	302
04633df0 BP	303	#include "verify_cpu.S"
04633df0 BP	304
42e78e97 FY	305	#ifdef CONFIG_HOTPLUG_CPU
	306	/*
	307	* Boot CPU0 entry point. It's called from play_dead(). Everything has been set
	308	* up already except stack. We just set up stack here. Then call
	309	* start_secondary().
	310	*/
	311	ENTRY(start_cpu0)
	312	movq stack_start(%rip),%rsp
	313	movq initial_code(%rip),%rax
	314	pushq $0 # fake return address to stop unwinder
	315	pushq $__KERNEL_CS # set correct cs
	316	pushq %rax # target address in negative space
	317	lretq
	318	ENDPROC(start_cpu0)
	319	#endif
	320
e57113bc	321	/* SMP bootup changes these two */
da5968ae	322	__REFDATA
8170e6be PA	323	.balign 8
8170e6be PA	324	GLOBAL(initial_code)
1da177e4	325	.quad x86_64_start_kernel
8170e6be	326	GLOBAL(initial_gs)
2add8e23	327	.quad INIT_PER_CPU_VAR(irq_stack_union)
f1fbabb3	328
8170e6be	329	GLOBAL(stack_start)
1da177e4	330	.quad init_thread_union+THREAD_SIZE-8
9cf4f298	331	.word 0
b9af7c0d	332	__FINITDATA
1da177e4	333
1ab60e0f VG	334	bad_address:
	335	jmp bad_address
	336
8170e6be	337	__INIT
cdeb6048	338	ENTRY(early_idt_handler_array)
9900aa2f PA	339	# 104(%rsp) %rflags
	340	# 96(%rsp) %cs
	341	# 88(%rsp) %rip
	342	# 80(%rsp) error code
749c970a AK	343	i = 0
749c970a AK	344	.rept NUM_EXCEPTION_VECTORS
cdeb6048	345	.ifeq (EXCEPTION_ERRCODE_MASK >> i) & 1
9900aa2f PA	346	pushq $0 # Dummy error code, to make stack frame uniform
	347	.endif
	348	pushq $i # 72(%rsp) Vector number
cdeb6048	349	jmp early_idt_handler_common
749c970a	350	i = i + 1
cdeb6048	351	.fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc
749c970a	352	.endr
cdeb6048	353	ENDPROC(early_idt_handler_array)
8866cd9d	354
cdeb6048 AL	355	early_idt_handler_common:
	356	/*
	357	* The stack is the hardware frame, an error code or zero, and the
	358	* vector number.
	359	*/
9900aa2f PA	360	cld
9900aa2f PA	361
b957591f	362	incl early_recursion_flag(%rip)
9900aa2f	363
7bbcdb1c AL	364	/* The vector number is currently in the pt_regs->di slot. */
	365	pushq %rsi /* pt_regs->si */
	366	movq 8(%rsp), %rsi /* RSI = vector number */
	367	movq %rdi, 8(%rsp) /* pt_regs->di = RDI */
	368	pushq %rdx /* pt_regs->dx */
	369	pushq %rcx /* pt_regs->cx */
	370	pushq %rax /* pt_regs->ax */
	371	pushq %r8 /* pt_regs->r8 */
	372	pushq %r9 /* pt_regs->r9 */
	373	pushq %r10 /* pt_regs->r10 */
	374	pushq %r11 /* pt_regs->r11 */
	375	pushq %rbx /* pt_regs->bx */
	376	pushq %rbp /* pt_regs->bp */
	377	pushq %r12 /* pt_regs->r12 */
	378	pushq %r13 /* pt_regs->r13 */
	379	pushq %r14 /* pt_regs->r14 */
	380	pushq %r15 /* pt_regs->r15 */
	381
7bbcdb1c	382	cmpq $14,%rsi /* Page fault? */
8170e6be	383	jnz 10f
7bbcdb1c	384	GET_CR2_INTO(%rdi) /* Can clobber any volatile register if pv */
8170e6be PA	385	call early_make_pgtable
8170e6be PA	386	andl %eax,%eax
7bbcdb1c	387	jz 20f /* All good */
9900aa2f	388
8170e6be	389	10:
7bbcdb1c	390	movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */
9900aa2f	391	call early_fixup_exception
076f9776	392
0e861fbb	393	20:
9900aa2f	394	decl early_recursion_flag(%rip)
7bbcdb1c	395	jmp restore_regs_and_iret
cdeb6048	396	ENDPROC(early_idt_handler_common)
9900aa2f	397
8170e6be PA	398	__INITDATA
8170e6be PA	399
9900aa2f	400	.balign 4
0e861fbb	401	GLOBAL(early_recursion_flag)
b957591f	402	.long 0
1da177e4	403
f0cf5d1a	404	#define NEXT_PAGE(name) \
67dcbb6b	405	.balign PAGE_SIZE; \
8170e6be	406	GLOBAL(name)
f0cf5d1a	407
67dcbb6b	408	/* Automate the creation of 1 to 1 mapping pmd entries */
0e192b99 CG	409	#define PMDS(START, PERM, COUNT) \
	410	i = 0 ; \
	411	.rept (COUNT) ; \
	412	.quad (START) + (i << PMD_SHIFT) + (PERM) ; \
	413	i = i + 1 ; \
67dcbb6b VG	414	.endr
67dcbb6b VG	415
8170e6be PA	416	__INITDATA
	417	NEXT_PAGE(early_level4_pgt)
	418	.fill 511,8,0
	419	.quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE
	420
	421	NEXT_PAGE(early_dynamic_pgts)
	422	.fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0
	423
b9af7c0d	424	.data
8170e6be PA	425
8170e6be PA	426	#ifndef CONFIG_XEN
f0cf5d1a	427	NEXT_PAGE(init_level4_pgt)
8170e6be PA	428	.fill 512,8,0
	429	#else
	430	NEXT_PAGE(init_level4_pgt)
	431	.quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
	432	.org init_level4_pgt + L4_PAGE_OFFSET*8, 0
	433	.quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
	434	.org init_level4_pgt + L4_START_KERNEL*8, 0
cfd243d4	435	/* (2^48-(2102410241024))/(2^39) = 511 /
8170e6be	436	.quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE
1da177e4	437
f0cf5d1a	438	NEXT_PAGE(level3_ident_pgt)
67dcbb6b	439	.quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
8170e6be PA	440	.fill 511, 8, 0
	441	NEXT_PAGE(level2_ident_pgt)
	442	/* Since I easily can, map the first 1G.
	443	* Don't set NX because code runs from these pages.
	444	*/
	445	PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD)
	446	#endif
1da177e4	447
f0cf5d1a	448	NEXT_PAGE(level3_kernel_pgt)
a6523748	449	.fill L3_START_KERNEL,8,0
1da177e4	450	/* (2^48-(2102410241024)-((2^39)511))/(2^30) = 510 */
67dcbb6b	451	.quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE
b1c931e3 EB	452	.quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
b1c931e3 EB	453
f0cf5d1a	454	NEXT_PAGE(level2_kernel_pgt)
88f3aec7	455	/*
85eb69a1	456	* 512 MB kernel mapping. We spend a full page on this pagetable
88f3aec7 IM	457	* anyway.
	458	*
	459	* The kernel code+data+bss must not be bigger than that.
	460	*
85eb69a1	461	* (NOTE: at +512MB starts the module area, see MODULES_VADDR.
88f3aec7 IM	462	* If you want to increase this then increase MODULES_VADDR
	463	* too.)
	464	*/
8490638c	465	PMDS(0, __PAGE_KERNEL_LARGE_EXEC,
d4afe414	466	KERNEL_IMAGE_SIZE/PMD_SIZE)
1da177e4	467
8170e6be PA	468	NEXT_PAGE(level2_fixmap_pgt)
	469	.fill 506,8,0
	470	.quad level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
	471	/* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */
	472	.fill 5,8,0
	473
	474	NEXT_PAGE(level1_fixmap_pgt)
	475	.fill 512,8,0
1ab60e0f	476
67dcbb6b	477	#undef PMDS
1da177e4	478
f0cf5d1a	479	.data
1da177e4	480	.align 16
a939098a GC	481	.globl early_gdt_descr
	482	early_gdt_descr:
	483	.word GDT_ENTRIES*8-1
3e5d8f97	484	early_gdt_descr_base:
2add8e23	485	.quad INIT_PER_CPU_VAR(gdt_page)
1da177e4	486
1ab60e0f VG	487	ENTRY(phys_base)
	488	/* This must match the first entry in level2_kernel_pgt */
	489	.quad 0x0000000000000000
	490
8c5e5ac3	491	#include "../../x86/xen/xen-head.S"
1da177e4	492
02b7da37	493	__PAGE_ALIGNED_BSS
8170e6be	494	NEXT_PAGE(empty_zero_page)
e57113bc	495	.skip PAGE_SIZE
ef7f0d6a	496