[linux-2.6-block.git] / arch / x86 / kernel / head_64.S

/*
 *  linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit
 *
 *  Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
 *  Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
 *  Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
 *  Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
 *  Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
 */


#include <linux/linkage.h>
#include <linux/threads.h>
#include <linux/init.h>
#include <asm/segment.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/msr.h>
#include <asm/cache.h>
#include <asm/processor-flags.h>
#include <asm/percpu.h>
#include <asm/nops.h>

#ifdef CONFIG_PARAVIRT
#include <asm/asm-offsets.h>
#include <asm/paravirt.h>
#define GET_CR2_INTO(reg) GET_CR2_INTO_RAX ; movq %rax, reg
#else
#define GET_CR2_INTO(reg) movq %cr2, reg
#define INTERRUPT_RETURN iretq
#endif

/* we are not able to switch in one step to the final KERNEL ADDRESS SPACE
 * because we need identity-mapped pages.
 *
 */

#define pud_index(x)	(((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))

L4_PAGE_OFFSET = pgd_index(__PAGE_OFFSET)
L3_PAGE_OFFSET = pud_index(__PAGE_OFFSET)
L4_START_KERNEL = pgd_index(__START_KERNEL_map)
L3_START_KERNEL = pud_index(__START_KERNEL_map)

	.text
	__HEAD
	.code64
	.globl startup_64
startup_64:

	/*
	 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1,
	 * and someone has loaded an identity mapped page table
	 * for us.  These identity mapped page tables map all of the
	 * kernel pages and possibly all of memory.
	 *
	 * %esi holds a physical pointer to real_mode_data.
	 *
	 * We come here either directly from a 64bit bootloader, or from
	 * arch/x86_64/boot/compressed/head.S.
	 *
	 * We only come here initially at boot nothing else comes here.
	 *
	 * Since we may be loaded at an address different from what we were
	 * compiled to run at we first fixup the physical addresses in our page
	 * tables and then reload them.
	 */

	/* Compute the delta between the address I am compiled to run at and the
	 * address I am actually running at.
	 */
	leaq	_text(%rip), %rbp
	subq	$_text - __START_KERNEL_map, %rbp

	/* Is the address not 2M aligned? */
	movq	%rbp, %rax
	andl	$~PMD_PAGE_MASK, %eax
	testl	%eax, %eax
	jnz	bad_address

	/* Is the address too large? */
	leaq	_text(%rip), %rdx
	movq	$PGDIR_SIZE, %rax
	cmpq	%rax, %rdx
	jae	bad_address

	/* Fixup the physical addresses in the page table
	 */
	addq	%rbp, init_level4_pgt + 0(%rip)
	addq	%rbp, init_level4_pgt + (L4_PAGE_OFFSET*8)(%rip)
	addq	%rbp, init_level4_pgt + (L4_START_KERNEL*8)(%rip)

	addq	%rbp, level3_ident_pgt + 0(%rip)

	addq	%rbp, level3_kernel_pgt + (510*8)(%rip)
	addq	%rbp, level3_kernel_pgt + (511*8)(%rip)

	addq	%rbp, level2_fixmap_pgt + (506*8)(%rip)

	/* Add an Identity mapping if I am above 1G */
	leaq	_text(%rip), %rdi
	andq	$PMD_PAGE_MASK, %rdi

	movq	%rdi, %rax
	shrq	$PUD_SHIFT, %rax
	andq	$(PTRS_PER_PUD - 1), %rax
	jz	ident_complete

	leaq	(level2_spare_pgt - __START_KERNEL_map + _KERNPG_TABLE)(%rbp), %rdx
	leaq	level3_ident_pgt(%rip), %rbx
	movq	%rdx, 0(%rbx, %rax, 8)

	movq	%rdi, %rax
	shrq	$PMD_SHIFT, %rax
	andq	$(PTRS_PER_PMD - 1), %rax
	leaq	__PAGE_KERNEL_IDENT_LARGE_EXEC(%rdi), %rdx
	leaq	level2_spare_pgt(%rip), %rbx
	movq	%rdx, 0(%rbx, %rax, 8)
ident_complete:

	/*
	 * Fixup the kernel text+data virtual addresses. Note that
	 * we might write invalid pmds, when the kernel is relocated
	 * cleanup_highmap() fixes this up along with the mappings
	 * beyond _end.
	 */

	leaq	level2_kernel_pgt(%rip), %rdi
	leaq	4096(%rdi), %r8
	/* See if it is a valid page table entry */
1:	testq	$1, 0(%rdi)
	jz	2f
	addq	%rbp, 0(%rdi)
	/* Go to the next page */
2:	addq	$8, %rdi
	cmp	%r8, %rdi
	jne	1b

	/* Fixup phys_base */
	addq	%rbp, phys_base(%rip)

	/* Due to ENTRY(), sometimes the empty space gets filled with
	 * zeros. Better take a jmp than relying on empty space being
	 * filled with 0x90 (nop)
	 */
	jmp secondary_startup_64
ENTRY(secondary_startup_64)
	/*
	 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1,
	 * and someone has loaded a mapped page table.
	 *
	 * %esi holds a physical pointer to real_mode_data.
	 *
	 * We come here either from startup_64 (using physical addresses)
	 * or from trampoline.S (using virtual addresses).
	 *
	 * Using virtual addresses from trampoline.S removes the need
	 * to have any identity mapped pages in the kernel page table
	 * after the boot processor executes this code.
	 */

	/* Enable PAE mode and PGE */
	movl	$(X86_CR4_PAE | X86_CR4_PGE), %eax
	movq	%rax, %cr4

	/* Setup early boot stage 4 level pagetables. */
	movq	$(init_level4_pgt - __START_KERNEL_map), %rax
	addq	phys_base(%rip), %rax
	movq	%rax, %cr3

	/* Ensure I am executing from virtual addresses */
	movq	$1f, %rax
	jmp	*%rax
1:

	/* Check if nx is implemented */
	movl	$0x80000001, %eax
	cpuid
	movl	%edx,%edi

	/* Setup EFER (Extended Feature Enable Register) */
	movl	$MSR_EFER, %ecx
	rdmsr
	btsl	$_EFER_SCE, %eax	/* Enable System Call */
	btl	$20,%edi		/* No Execute supported? */
	jnc     1f
	btsl	$_EFER_NX, %eax
1:	wrmsr				/* Make changes effective */

	/* Setup cr0 */
#define CR0_STATE	(X86_CR0_PE | X86_CR0_MP | X86_CR0_ET | \
			 X86_CR0_NE | X86_CR0_WP | X86_CR0_AM | \
			 X86_CR0_PG)
	movl	$CR0_STATE, %eax
	/* Make changes effective */
	movq	%rax, %cr0

	/* Setup a boot time stack */
	movq stack_start(%rip),%rsp

	/* zero EFLAGS after setting rsp */
	pushq $0
	popfq

	/*
	 * We must switch to a new descriptor in kernel space for the GDT
	 * because soon the kernel won't have access anymore to the userspace
	 * addresses where we're currently running on. We have to do that here
	 * because in 32bit we couldn't load a 64bit linear address.
	 */
	lgdt	early_gdt_descr(%rip)

	/* set up data segments */
	xorl %eax,%eax
	movl %eax,%ds
	movl %eax,%ss
	movl %eax,%es

	/*
	 * We don't really need to load %fs or %gs, but load them anyway
	 * to kill any stale realmode selectors.  This allows execution
	 * under VT hardware.
	 */
	movl %eax,%fs
	movl %eax,%gs

	/* Set up %gs.
	 *
	 * The base of %gs always points to the bottom of the irqstack
	 * union.  If the stack protector canary is enabled, it is
	 * located at %gs:40.  Note that, on SMP, the boot cpu uses
	 * init data section till per cpu areas are set up.
	 */
	movl	$MSR_GS_BASE,%ecx
	movl	initial_gs(%rip),%eax
	movl	initial_gs+4(%rip),%edx
	wrmsr	

	/* esi is pointer to real mode structure with interesting info.
	   pass it to C */
	movl	%esi, %edi
	
	/* Finally jump to run C code and to be on real kernel address
	 * Since we are running on identity-mapped space we have to jump
	 * to the full 64bit address, this is only possible as indirect
	 * jump.  In addition we need to ensure %cs is set so we make this
	 * a far return.
	 */
	movq	initial_code(%rip),%rax
	pushq	$0		# fake return address to stop unwinder
	pushq	$__KERNEL_CS	# set correct cs
	pushq	%rax		# target address in negative space
	lretq

	/* SMP bootup changes these two */
	__REFDATA
	.align	8
	ENTRY(initial_code)
	.quad	x86_64_start_kernel
	ENTRY(initial_gs)
	.quad	INIT_PER_CPU_VAR(irq_stack_union)

	ENTRY(stack_start)
	.quad  init_thread_union+THREAD_SIZE-8
	.word  0
	__FINITDATA

bad_address:
	jmp bad_address

	.section ".init.text","ax"
	.globl early_idt_handlers
early_idt_handlers:
	# 104(%rsp) %rflags
	#  96(%rsp) %cs
	#  88(%rsp) %rip
	#  80(%rsp) error code
	i = 0
	.rept NUM_EXCEPTION_VECTORS
	.if (EXCEPTION_ERRCODE_MASK >> i) & 1
	ASM_NOP2
	.else
	pushq $0		# Dummy error code, to make stack frame uniform
	.endif
	pushq $i		# 72(%rsp) Vector number
	jmp early_idt_handler
	i = i + 1
	.endr

ENTRY(early_idt_handler)
	cld

	cmpl $2,early_recursion_flag(%rip)
	jz  1f
	incl early_recursion_flag(%rip)

	pushq %rax		# 64(%rsp)
	pushq %rcx		# 56(%rsp)
	pushq %rdx		# 48(%rsp)
	pushq %rsi		# 40(%rsp)
	pushq %rdi		# 32(%rsp)
	pushq %r8		# 24(%rsp)
	pushq %r9		# 16(%rsp)
	pushq %r10		#  8(%rsp)
	pushq %r11		#  0(%rsp)

	cmpl $__KERNEL_CS,96(%rsp)
	jne 10f

	leaq 88(%rsp),%rdi	# Pointer to %rip
	call early_fixup_exception
	andl %eax,%eax
	jnz 20f			# Found an exception entry

10:
#ifdef CONFIG_EARLY_PRINTK
	GET_CR2_INTO(%r9)	# can clobber any volatile register if pv
	movl 80(%rsp),%r8d	# error code
	movl 72(%rsp),%esi	# vector number
	movl 96(%rsp),%edx	# %cs
	movq 88(%rsp),%rcx	# %rip
	xorl %eax,%eax
	leaq early_idt_msg(%rip),%rdi
	call early_printk
	cmpl $2,early_recursion_flag(%rip)
	jz  1f
	call dump_stack
#ifdef CONFIG_KALLSYMS	
	leaq early_idt_ripmsg(%rip),%rdi
	movq 40(%rsp),%rsi	# %rip again
	call __print_symbol
#endif
#endif /* EARLY_PRINTK */
1:	hlt
	jmp 1b

20:	# Exception table entry found
	popq %r11
	popq %r10
	popq %r9
	popq %r8
	popq %rdi
	popq %rsi
	popq %rdx
	popq %rcx
	popq %rax
	addq $16,%rsp		# drop vector number and error code
	decl early_recursion_flag(%rip)
	INTERRUPT_RETURN

	.balign 4
early_recursion_flag:
	.long 0

#ifdef CONFIG_EARLY_PRINTK
early_idt_msg:
	.asciz "PANIC: early exception %02lx rip %lx:%lx error %lx cr2 %lx\n"
early_idt_ripmsg:
	.asciz "RIP %s\n"
#endif /* CONFIG_EARLY_PRINTK */
	.previous

#define NEXT_PAGE(name) \
	.balign	PAGE_SIZE; \
ENTRY(name)

/* Automate the creation of 1 to 1 mapping pmd entries */
#define PMDS(START, PERM, COUNT)			\
	i = 0 ;						\
	.rept (COUNT) ;					\
	.quad	(START) + (i << PMD_SHIFT) + (PERM) ;	\
	i = i + 1 ;					\
	.endr

	.data
	/*
	 * This default setting generates an ident mapping at address 0x100000
	 * and a mapping for the kernel that precisely maps virtual address
	 * 0xffffffff80000000 to physical address 0x000000. (always using
	 * 2Mbyte large pages provided by PAE mode)
	 */
NEXT_PAGE(init_level4_pgt)
	.quad	level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
	.org	init_level4_pgt + L4_PAGE_OFFSET*8, 0
	.quad	level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
	.org	init_level4_pgt + L4_START_KERNEL*8, 0
	/* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
	.quad	level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE

NEXT_PAGE(level3_ident_pgt)
	.quad	level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
	.fill	511,8,0

NEXT_PAGE(level3_kernel_pgt)
	.fill	L3_START_KERNEL,8,0
	/* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
	.quad	level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE
	.quad	level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE

NEXT_PAGE(level2_fixmap_pgt)
	.fill	506,8,0
	.quad	level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
	/* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */
	.fill	5,8,0

NEXT_PAGE(level1_fixmap_pgt)
	.fill	512,8,0

NEXT_PAGE(level2_ident_pgt)
	/* Since I easily can, map the first 1G.
	 * Don't set NX because code runs from these pages.
	 */
	PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD)

NEXT_PAGE(level2_kernel_pgt)
	/*
	 * 512 MB kernel mapping. We spend a full page on this pagetable
	 * anyway.
	 *
	 * The kernel code+data+bss must not be bigger than that.
	 *
	 * (NOTE: at +512MB starts the module area, see MODULES_VADDR.
	 *  If you want to increase this then increase MODULES_VADDR
	 *  too.)
	 */
	PMDS(0, __PAGE_KERNEL_LARGE_EXEC,
		KERNEL_IMAGE_SIZE/PMD_SIZE)

NEXT_PAGE(level2_spare_pgt)
	.fill   512, 8, 0

#undef PMDS
#undef NEXT_PAGE

	.data
	.align 16
	.globl early_gdt_descr
early_gdt_descr:
	.word	GDT_ENTRIES*8-1
early_gdt_descr_base:
	.quad	INIT_PER_CPU_VAR(gdt_page)

ENTRY(phys_base)
	/* This must match the first entry in level2_kernel_pgt */
	.quad   0x0000000000000000

#include "../../x86/xen/xen-head.S"
	
	.section .bss, "aw", @nobits
	.align L1_CACHE_BYTES
ENTRY(idt_table)
	.skip IDT_ENTRIES * 16

	.align L1_CACHE_BYTES
ENTRY(nmi_idt_table)
	.skip IDT_ENTRIES * 16

	__PAGE_ALIGNED_BSS
	.align PAGE_SIZE
ENTRY(empty_zero_page)
	.skip PAGE_SIZE
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit
	3	*
	4	* Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
	5	* Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
	6	* Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
	7	* Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
1ab60e0f	8	* Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
1da177e4 LT	9	*/
	10
	11
	12	#include <linux/linkage.h>
	13	#include <linux/threads.h>
f6c2e333	14	#include <linux/init.h>
1da177e4	15	#include <asm/segment.h>
67dcbb6b	16	#include <asm/pgtable.h>
1da177e4 LT	17	#include <asm/page.h>
	18	#include <asm/msr.h>
	19	#include <asm/cache.h>
369101da	20	#include <asm/processor-flags.h>
b12d8db8	21	#include <asm/percpu.h>
9900aa2f	22	#include <asm/nops.h>
1ab60e0f	23
49a69787 GOC	24	#ifdef CONFIG_PARAVIRT
	25	#include <asm/asm-offsets.h>
	26	#include <asm/paravirt.h>
ffc4bc9c	27	#define GET_CR2_INTO(reg) GET_CR2_INTO_RAX ; movq %rax, reg
49a69787	28	#else
ffc4bc9c	29	#define GET_CR2_INTO(reg) movq %cr2, reg
9900aa2f	30	#define INTERRUPT_RETURN iretq
49a69787 GOC	31	#endif
49a69787 GOC	32
3ad2f3fb	33	/* we are not able to switch in one step to the final KERNEL ADDRESS SPACE
1ab60e0f VG	34	* because we need identity-mapped pages.
1ab60e0f VG	35	*
1da177e4 LT	36	*/
1da177e4 LT	37
a6523748 EH	38	#define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
	39
	40	L4_PAGE_OFFSET = pgd_index(__PAGE_OFFSET)
	41	L3_PAGE_OFFSET = pud_index(__PAGE_OFFSET)
	42	L4_START_KERNEL = pgd_index(__START_KERNEL_map)
	43	L3_START_KERNEL = pud_index(__START_KERNEL_map)
	44
1da177e4	45	.text
4ae59b91	46	__HEAD
1ab60e0f VG	47	.code64
	48	.globl startup_64
	49	startup_64:
	50
1da177e4	51	/*
1ab60e0f VG	52	* At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1,
	53	* and someone has loaded an identity mapped page table
	54	* for us. These identity mapped page tables map all of the
	55	* kernel pages and possibly all of memory.
	56	*
	57	* %esi holds a physical pointer to real_mode_data.
	58	*
	59	* We come here either directly from a 64bit bootloader, or from
	60	* arch/x86_64/boot/compressed/head.S.
	61	*
	62	* We only come here initially at boot nothing else comes here.
	63	*
	64	* Since we may be loaded at an address different from what we were
	65	* compiled to run at we first fixup the physical addresses in our page
	66	* tables and then reload them.
1da177e4 LT	67	*/
1da177e4 LT	68
1ab60e0f VG	69	/* Compute the delta between the address I am compiled to run at and the
1ab60e0f VG	70	* address I am actually running at.
1da177e4	71	*/
1ab60e0f VG	72	leaq _text(%rip), %rbp
	73	subq $_text - __START_KERNEL_map, %rbp
	74
	75	/* Is the address not 2M aligned? */
	76	movq %rbp, %rax
31422c51	77	andl $~PMD_PAGE_MASK, %eax
1ab60e0f VG	78	testl %eax, %eax
	79	jnz bad_address
	80
	81	/* Is the address too large? */
	82	leaq _text(%rip), %rdx
	83	movq $PGDIR_SIZE, %rax
	84	cmpq %rax, %rdx
	85	jae bad_address
	86
	87	/* Fixup the physical addresses in the page table
1da177e4	88	*/
1ab60e0f	89	addq %rbp, init_level4_pgt + 0(%rip)
a6523748 EH	90	addq %rbp, init_level4_pgt + (L4_PAGE_OFFSET*8)(%rip)
a6523748 EH	91	addq %rbp, init_level4_pgt + (L4_START_KERNEL*8)(%rip)
1ab60e0f VG	92
1ab60e0f VG	93	addq %rbp, level3_ident_pgt + 0(%rip)
b1c931e3	94
1ab60e0f	95	addq %rbp, level3_kernel_pgt + (510*8)(%rip)
b1c931e3 EB	96	addq %rbp, level3_kernel_pgt + (511*8)(%rip)
	97
	98	addq %rbp, level2_fixmap_pgt + (506*8)(%rip)
1ab60e0f VG	99
	100	/* Add an Identity mapping if I am above 1G */
	101	leaq _text(%rip), %rdi
31422c51	102	andq $PMD_PAGE_MASK, %rdi
1ab60e0f VG	103
	104	movq %rdi, %rax
	105	shrq $PUD_SHIFT, %rax
	106	andq $(PTRS_PER_PUD - 1), %rax
	107	jz ident_complete
	108
	109	leaq (level2_spare_pgt - __START_KERNEL_map + _KERNPG_TABLE)(%rbp), %rdx
	110	leaq level3_ident_pgt(%rip), %rbx
	111	movq %rdx, 0(%rbx, %rax, 8)
	112
	113	movq %rdi, %rax
	114	shrq $PMD_SHIFT, %rax
	115	andq $(PTRS_PER_PMD - 1), %rax
b2bc2731	116	leaq __PAGE_KERNEL_IDENT_LARGE_EXEC(%rdi), %rdx
1ab60e0f VG	117	leaq level2_spare_pgt(%rip), %rbx
	118	movq %rdx, 0(%rbx, %rax, 8)
	119	ident_complete:
	120
31eedd82 TG	121	/*
	122	* Fixup the kernel text+data virtual addresses. Note that
	123	* we might write invalid pmds, when the kernel is relocated
	124	* cleanup_highmap() fixes this up along with the mappings
	125	* beyond _end.
1ab60e0f	126	*/
31eedd82	127
1ab60e0f VG	128	leaq level2_kernel_pgt(%rip), %rdi
	129	leaq 4096(%rdi), %r8
	130	/* See if it is a valid page table entry */
	131	1: testq $1, 0(%rdi)
	132	jz 2f
	133	addq %rbp, 0(%rdi)
	134	/* Go to the next page */
	135	2: addq $8, %rdi
	136	cmp %r8, %rdi
	137	jne 1b
	138
	139	/* Fixup phys_base */
	140	addq %rbp, phys_base(%rip)
1da177e4	141
1ab60e0f VG	142	/* Due to ENTRY(), sometimes the empty space gets filled with
	143	* zeros. Better take a jmp than relying on empty space being
	144	* filled with 0x90 (nop)
1da177e4	145	*/
1ab60e0f	146	jmp secondary_startup_64
90b1c208	147	ENTRY(secondary_startup_64)
1ab60e0f VG	148	/*
	149	* At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1,
	150	* and someone has loaded a mapped page table.
	151	*
	152	* %esi holds a physical pointer to real_mode_data.
	153	*
	154	* We come here either from startup_64 (using physical addresses)
	155	* or from trampoline.S (using virtual addresses).
	156	*
	157	* Using virtual addresses from trampoline.S removes the need
	158	* to have any identity mapped pages in the kernel page table
	159	* after the boot processor executes this code.
1da177e4 LT	160	*/
	161
	162	/* Enable PAE mode and PGE */
05139d8f	163	movl $(X86_CR4_PAE \| X86_CR4_PGE), %eax
1da177e4 LT	164	movq %rax, %cr4
	165
	166	/* Setup early boot stage 4 level pagetables. */
cfd243d4	167	movq $(init_level4_pgt - __START_KERNEL_map), %rax
1ab60e0f	168	addq phys_base(%rip), %rax
1da177e4 LT	169	movq %rax, %cr3
1da177e4 LT	170
1ab60e0f VG	171	/* Ensure I am executing from virtual addresses */
	172	movq $1f, %rax
	173	jmp *%rax
	174	1:
	175
1da177e4 LT	176	/* Check if nx is implemented */
	177	movl $0x80000001, %eax
	178	cpuid
	179	movl %edx,%edi
	180
	181	/* Setup EFER (Extended Feature Enable Register) */
	182	movl $MSR_EFER, %ecx
	183	rdmsr
1ab60e0f VG	184	btsl $_EFER_SCE, %eax /* Enable System Call */
1ab60e0f VG	185	btl $20,%edi /* No Execute supported? */
1da177e4 LT	186	jnc 1f
1da177e4 LT	187	btsl $_EFER_NX, %eax
1ab60e0f	188	1: wrmsr /* Make changes effective */
1da177e4 LT	189
1da177e4 LT	190	/* Setup cr0 */
369101da CG	191	#define CR0_STATE (X86_CR0_PE \| X86_CR0_MP \| X86_CR0_ET \| \
	192	X86_CR0_NE \| X86_CR0_WP \| X86_CR0_AM \| \
	193	X86_CR0_PG)
	194	movl $CR0_STATE, %eax
1da177e4 LT	195	/* Make changes effective */
	196	movq %rax, %cr0
	197
	198	/* Setup a boot time stack */
9cf4f298	199	movq stack_start(%rip),%rsp
1da177e4 LT	200
	201	/* zero EFLAGS after setting rsp */
	202	pushq $0
	203	popfq
	204
	205	/*
	206	* We must switch to a new descriptor in kernel space for the GDT
	207	* because soon the kernel won't have access anymore to the userspace
	208	* addresses where we're currently running on. We have to do that here
	209	* because in 32bit we couldn't load a 64bit linear address.
	210	*/
a939098a	211	lgdt early_gdt_descr(%rip)
1da177e4	212
8ec6993d BG	213	/* set up data segments */
8ec6993d BG	214	xorl %eax,%eax
ffb60175 ZA	215	movl %eax,%ds
	216	movl %eax,%ss
	217	movl %eax,%es
	218
	219	/*
	220	* We don't really need to load %fs or %gs, but load them anyway
	221	* to kill any stale realmode selectors. This allows execution
	222	* under VT hardware.
	223	*/
	224	movl %eax,%fs
	225	movl %eax,%gs
	226
f32ff538 TH	227	/* Set up %gs.
f32ff538 TH	228	*
947e76cd BG	229	* The base of %gs always points to the bottom of the irqstack
	230	* union. If the stack protector canary is enabled, it is
	231	* located at %gs:40. Note that, on SMP, the boot cpu uses
	232	* init data section till per cpu areas are set up.
f32ff538	233	*/
1da177e4	234	movl $MSR_GS_BASE,%ecx
650fb439 BG	235	movl initial_gs(%rip),%eax
650fb439 BG	236	movl initial_gs+4(%rip),%edx
1da177e4 LT	237	wrmsr
1da177e4 LT	238
1da177e4 LT	239	/* esi is pointer to real mode structure with interesting info.
	240	pass it to C */
	241	movl %esi, %edi
	242
	243	/* Finally jump to run C code and to be on real kernel address
	244	* Since we are running on identity-mapped space we have to jump
26374c7b EB	245	* to the full 64bit address, this is only possible as indirect
	246	* jump. In addition we need to ensure %cs is set so we make this
	247	* a far return.
1da177e4 LT	248	*/
1da177e4 LT	249	movq initial_code(%rip),%rax
26374c7b EB	250	pushq $0 # fake return address to stop unwinder
	251	pushq $__KERNEL_CS # set correct cs
	252	pushq %rax # target address in negative space
	253	lretq
1da177e4	254
e57113bc	255	/* SMP bootup changes these two */
da5968ae	256	__REFDATA
e57113bc	257	.align 8
f1fbabb3	258	ENTRY(initial_code)
1da177e4	259	.quad x86_64_start_kernel
f32ff538	260	ENTRY(initial_gs)
2add8e23	261	.quad INIT_PER_CPU_VAR(irq_stack_union)
f1fbabb3	262
9cf4f298	263	ENTRY(stack_start)
1da177e4	264	.quad init_thread_union+THREAD_SIZE-8
9cf4f298	265	.word 0
b9af7c0d	266	__FINITDATA
1da177e4	267
1ab60e0f VG	268	bad_address:
	269	jmp bad_address
	270
41bd4eac	271	.section ".init.text","ax"
8866cd9d RM	272	.globl early_idt_handlers
8866cd9d RM	273	early_idt_handlers:
9900aa2f PA	274	# 104(%rsp) %rflags
	275	# 96(%rsp) %cs
	276	# 88(%rsp) %rip
	277	# 80(%rsp) error code
749c970a AK	278	i = 0
749c970a AK	279	.rept NUM_EXCEPTION_VECTORS
9900aa2f PA	280	.if (EXCEPTION_ERRCODE_MASK >> i) & 1
	281	ASM_NOP2
	282	.else
	283	pushq $0 # Dummy error code, to make stack frame uniform
	284	.endif
	285	pushq $i # 72(%rsp) Vector number
749c970a AK	286	jmp early_idt_handler
	287	i = i + 1
	288	.endr
8866cd9d	289
1da177e4	290	ENTRY(early_idt_handler)
9900aa2f PA	291	cld
9900aa2f PA	292
b957591f AK	293	cmpl $2,early_recursion_flag(%rip)
	294	jz 1f
	295	incl early_recursion_flag(%rip)
9900aa2f PA	296
	297	pushq %rax # 64(%rsp)
	298	pushq %rcx # 56(%rsp)
	299	pushq %rdx # 48(%rsp)
	300	pushq %rsi # 40(%rsp)
	301	pushq %rdi # 32(%rsp)
	302	pushq %r8 # 24(%rsp)
	303	pushq %r9 # 16(%rsp)
	304	pushq %r10 # 8(%rsp)
	305	pushq %r11 # 0(%rsp)
	306
	307	cmpl $__KERNEL_CS,96(%rsp)
	308	jne 10f
	309
	310	leaq 88(%rsp),%rdi # Pointer to %rip
	311	call early_fixup_exception
	312	andl %eax,%eax
	313	jnz 20f # Found an exception entry
	314
	315	10:
	316	#ifdef CONFIG_EARLY_PRINTK
	317	GET_CR2_INTO(%r9) # can clobber any volatile register if pv
	318	movl 80(%rsp),%r8d # error code
	319	movl 72(%rsp),%esi # vector number
	320	movl 96(%rsp),%edx # %cs
	321	movq 88(%rsp),%rcx # %rip
8866cd9d	322	xorl %eax,%eax
1da177e4 LT	323	leaq early_idt_msg(%rip),%rdi
1da177e4 LT	324	call early_printk
b957591f AK	325	cmpl $2,early_recursion_flag(%rip)
	326	jz 1f
	327	call dump_stack
6574ffd7 AK	328	#ifdef CONFIG_KALLSYMS
6574ffd7 AK	329	leaq early_idt_ripmsg(%rip),%rdi
9900aa2f	330	movq 40(%rsp),%rsi # %rip again
6574ffd7 AK	331	call __print_symbol
6574ffd7 AK	332	#endif
076f9776	333	#endif /* EARLY_PRINTK */
1da177e4 LT	334	1: hlt
1da177e4 LT	335	jmp 1b
076f9776	336
9900aa2f PA	337	20: # Exception table entry found
	338	popq %r11
	339	popq %r10
	340	popq %r9
	341	popq %r8
	342	popq %rdi
	343	popq %rsi
	344	popq %rdx
	345	popq %rcx
	346	popq %rax
	347	addq $16,%rsp # drop vector number and error code
	348	decl early_recursion_flag(%rip)
	349	INTERRUPT_RETURN
	350
	351	.balign 4
b957591f AK	352	early_recursion_flag:
b957591f AK	353	.long 0
1da177e4	354
9900aa2f	355	#ifdef CONFIG_EARLY_PRINTK
1da177e4	356	early_idt_msg:
8866cd9d	357	.asciz "PANIC: early exception %02lx rip %lx:%lx error %lx cr2 %lx\n"
6574ffd7 AK	358	early_idt_ripmsg:
6574ffd7 AK	359	.asciz "RIP %s\n"
076f9776	360	#endif /* CONFIG_EARLY_PRINTK */
41bd4eac	361	.previous
1da177e4	362
f0cf5d1a	363	#define NEXT_PAGE(name) \
67dcbb6b	364	.balign PAGE_SIZE; \
f0cf5d1a JB	365	ENTRY(name)
f0cf5d1a JB	366
67dcbb6b	367	/* Automate the creation of 1 to 1 mapping pmd entries */
0e192b99 CG	368	#define PMDS(START, PERM, COUNT) \
	369	i = 0 ; \
	370	.rept (COUNT) ; \
	371	.quad (START) + (i << PMD_SHIFT) + (PERM) ; \
	372	i = i + 1 ; \
67dcbb6b VG	373	.endr
67dcbb6b VG	374
b9af7c0d	375	.data
cfd243d4 VG	376	/*
	377	* This default setting generates an ident mapping at address 0x100000
	378	* and a mapping for the kernel that precisely maps virtual address
	379	* 0xffffffff80000000 to physical address 0x000000. (always using
	380	* 2Mbyte large pages provided by PAE mode)
	381	*/
f0cf5d1a	382	NEXT_PAGE(init_level4_pgt)
cfd243d4	383	.quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
a6523748	384	.org init_level4_pgt + L4_PAGE_OFFSET*8, 0
cfd243d4	385	.quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
a6523748	386	.org init_level4_pgt + L4_START_KERNEL*8, 0
cfd243d4 VG	387	/* (2^48-(2102410241024))/(2^39) = 511 /
cfd243d4 VG	388	.quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE
1da177e4	389
f0cf5d1a	390	NEXT_PAGE(level3_ident_pgt)
67dcbb6b	391	.quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
1da177e4 LT	392	.fill 511,8,0
1da177e4 LT	393
f0cf5d1a	394	NEXT_PAGE(level3_kernel_pgt)
a6523748	395	.fill L3_START_KERNEL,8,0
1da177e4	396	/* (2^48-(2102410241024)-((2^39)511))/(2^30) = 510 */
67dcbb6b	397	.quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE
b1c931e3 EB	398	.quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
	399
	400	NEXT_PAGE(level2_fixmap_pgt)
6596f242 IM	401	.fill 506,8,0
	402	.quad level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
	403	/* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */
	404	.fill 5,8,0
	405
	406	NEXT_PAGE(level1_fixmap_pgt)
b1c931e3	407	.fill 512,8,0
1da177e4	408
f0cf5d1a	409	NEXT_PAGE(level2_ident_pgt)
67dcbb6b VG	410	/* Since I easily can, map the first 1G.
	411	* Don't set NX because code runs from these pages.
	412	*/
b2bc2731	413	PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD)
1ab60e0f	414
f0cf5d1a	415	NEXT_PAGE(level2_kernel_pgt)
88f3aec7	416	/*
85eb69a1	417	* 512 MB kernel mapping. We spend a full page on this pagetable
88f3aec7 IM	418	* anyway.
	419	*
	420	* The kernel code+data+bss must not be bigger than that.
	421	*
85eb69a1	422	* (NOTE: at +512MB starts the module area, see MODULES_VADDR.
88f3aec7 IM	423	* If you want to increase this then increase MODULES_VADDR
	424	* too.)
	425	*/
8490638c	426	PMDS(0, __PAGE_KERNEL_LARGE_EXEC,
d4afe414	427	KERNEL_IMAGE_SIZE/PMD_SIZE)
1da177e4	428
1ab60e0f	429	NEXT_PAGE(level2_spare_pgt)
88f3aec7	430	.fill 512, 8, 0
1ab60e0f	431
67dcbb6b	432	#undef PMDS
f0cf5d1a	433	#undef NEXT_PAGE
1da177e4	434
f0cf5d1a	435	.data
1da177e4	436	.align 16
a939098a GC	437	.globl early_gdt_descr
	438	early_gdt_descr:
	439	.word GDT_ENTRIES*8-1
3e5d8f97	440	early_gdt_descr_base:
2add8e23	441	.quad INIT_PER_CPU_VAR(gdt_page)
1da177e4	442
1ab60e0f VG	443	ENTRY(phys_base)
	444	/* This must match the first entry in level2_kernel_pgt */
	445	.quad 0x0000000000000000
	446
8c5e5ac3	447	#include "../../x86/xen/xen-head.S"
1da177e4	448
e57113bc JB	449	.section .bss, "aw", @nobits
	450	.align L1_CACHE_BYTES
	451	ENTRY(idt_table)
5e112ae2	452	.skip IDT_ENTRIES * 16
1da177e4	453
228bdaa9 SR	454	.align L1_CACHE_BYTES
	455	ENTRY(nmi_idt_table)
	456	.skip IDT_ENTRIES * 16
	457
02b7da37	458	__PAGE_ALIGNED_BSS
e57113bc JB	459	.align PAGE_SIZE
	460	ENTRY(empty_zero_page)
	461	.skip PAGE_SIZE