Commit | Line | Data |
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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
1da177e4 | 2 | /* |
5b171e82 | 3 | * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit |
1da177e4 LT |
4 | * |
5 | * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE | |
6 | * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> | |
7 | * Copyright (C) 2000 Karsten Keil <kkeil@suse.de> | |
8 | * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de> | |
1ab60e0f | 9 | * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com> |
1da177e4 LT |
10 | */ |
11 | ||
12 | ||
13 | #include <linux/linkage.h> | |
14 | #include <linux/threads.h> | |
f6c2e333 | 15 | #include <linux/init.h> |
1da177e4 | 16 | #include <asm/segment.h> |
67dcbb6b | 17 | #include <asm/pgtable.h> |
1da177e4 LT |
18 | #include <asm/page.h> |
19 | #include <asm/msr.h> | |
20 | #include <asm/cache.h> | |
369101da | 21 | #include <asm/processor-flags.h> |
b12d8db8 | 22 | #include <asm/percpu.h> |
9900aa2f | 23 | #include <asm/nops.h> |
7bbcdb1c | 24 | #include "../entry/calling.h" |
784d5699 | 25 | #include <asm/export.h> |
bd89004f | 26 | #include <asm/nospec-branch.h> |
05ab1d8a | 27 | #include <asm/fixmap.h> |
1ab60e0f | 28 | |
fdc0269e | 29 | #ifdef CONFIG_PARAVIRT_XXL |
49a69787 GOC |
30 | #include <asm/asm-offsets.h> |
31 | #include <asm/paravirt.h> | |
ffc4bc9c | 32 | #define GET_CR2_INTO(reg) GET_CR2_INTO_RAX ; movq %rax, reg |
49a69787 | 33 | #else |
ffc4bc9c | 34 | #define GET_CR2_INTO(reg) movq %cr2, reg |
9900aa2f | 35 | #define INTERRUPT_RETURN iretq |
49a69787 GOC |
36 | #endif |
37 | ||
3ad2f3fb | 38 | /* we are not able to switch in one step to the final KERNEL ADDRESS SPACE |
1ab60e0f VG |
39 | * because we need identity-mapped pages. |
40 | * | |
1da177e4 LT |
41 | */ |
42 | ||
b9952ec7 | 43 | #define l4_index(x) (((x) >> 39) & 511) |
a6523748 EH |
44 | #define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) |
45 | ||
b9952ec7 KS |
46 | L4_PAGE_OFFSET = l4_index(__PAGE_OFFSET_BASE_L4) |
47 | L4_START_KERNEL = l4_index(__START_KERNEL_map) | |
48 | ||
a6523748 EH |
49 | L3_START_KERNEL = pud_index(__START_KERNEL_map) |
50 | ||
1da177e4 | 51 | .text |
4ae59b91 | 52 | __HEAD |
1ab60e0f VG |
53 | .code64 |
54 | .globl startup_64 | |
55 | startup_64: | |
2704fbb6 | 56 | UNWIND_HINT_EMPTY |
1da177e4 | 57 | /* |
1256276c | 58 | * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, |
1ab60e0f VG |
59 | * and someone has loaded an identity mapped page table |
60 | * for us. These identity mapped page tables map all of the | |
61 | * kernel pages and possibly all of memory. | |
62 | * | |
8170e6be | 63 | * %rsi holds a physical pointer to real_mode_data. |
1ab60e0f VG |
64 | * |
65 | * We come here either directly from a 64bit bootloader, or from | |
5b171e82 | 66 | * arch/x86/boot/compressed/head_64.S. |
1ab60e0f VG |
67 | * |
68 | * We only come here initially at boot nothing else comes here. | |
69 | * | |
70 | * Since we may be loaded at an address different from what we were | |
71 | * compiled to run at we first fixup the physical addresses in our page | |
72 | * tables and then reload them. | |
1da177e4 LT |
73 | */ |
74 | ||
22dc3918 JP |
75 | /* Set up the stack for verify_cpu(), similar to initial_stack below */ |
76 | leaq (__end_init_task - SIZEOF_PTREGS)(%rip), %rsp | |
91ed140d | 77 | |
04633df0 BP |
78 | /* Sanitize CPU configuration */ |
79 | call verify_cpu | |
80 | ||
5868f365 TL |
81 | /* |
82 | * Perform pagetable fixups. Additionally, if SME is active, encrypt | |
83 | * the kernel and retrieve the modifier (SME encryption mask if SME | |
84 | * is active) to be added to the initial pgdir entry that will be | |
85 | * programmed into CR3. | |
86 | */ | |
1ab60e0f | 87 | leaq _text(%rip), %rdi |
c88d7150 KS |
88 | pushq %rsi |
89 | call __startup_64 | |
90 | popq %rsi | |
1da177e4 | 91 | |
5868f365 TL |
92 | /* Form the CR3 value being sure to include the CR3 modifier */ |
93 | addq $(early_top_pgt - __START_KERNEL_map), %rax | |
8170e6be | 94 | jmp 1f |
90b1c208 | 95 | ENTRY(secondary_startup_64) |
2704fbb6 | 96 | UNWIND_HINT_EMPTY |
1ab60e0f | 97 | /* |
1256276c | 98 | * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, |
1ab60e0f VG |
99 | * and someone has loaded a mapped page table. |
100 | * | |
8170e6be | 101 | * %rsi holds a physical pointer to real_mode_data. |
1ab60e0f VG |
102 | * |
103 | * We come here either from startup_64 (using physical addresses) | |
104 | * or from trampoline.S (using virtual addresses). | |
105 | * | |
106 | * Using virtual addresses from trampoline.S removes the need | |
107 | * to have any identity mapped pages in the kernel page table | |
108 | * after the boot processor executes this code. | |
1da177e4 LT |
109 | */ |
110 | ||
04633df0 BP |
111 | /* Sanitize CPU configuration */ |
112 | call verify_cpu | |
113 | ||
5868f365 TL |
114 | /* |
115 | * Retrieve the modifier (SME encryption mask if SME is active) to be | |
116 | * added to the initial pgdir entry that will be programmed into CR3. | |
117 | */ | |
118 | pushq %rsi | |
119 | call __startup_secondary_64 | |
120 | popq %rsi | |
121 | ||
122 | /* Form the CR3 value being sure to include the CR3 modifier */ | |
123 | addq $(init_top_pgt - __START_KERNEL_map), %rax | |
8170e6be PA |
124 | 1: |
125 | ||
032370b9 | 126 | /* Enable PAE mode, PGE and LA57 */ |
8170e6be | 127 | movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx |
032370b9 | 128 | #ifdef CONFIG_X86_5LEVEL |
39b95522 | 129 | testl $1, __pgtable_l5_enabled(%rip) |
6f9dd329 | 130 | jz 1f |
032370b9 | 131 | orl $X86_CR4_LA57, %ecx |
6f9dd329 | 132 | 1: |
032370b9 | 133 | #endif |
8170e6be | 134 | movq %rcx, %cr4 |
1da177e4 | 135 | |
032370b9 | 136 | /* Setup early boot stage 4-/5-level pagetables. */ |
1ab60e0f | 137 | addq phys_base(%rip), %rax |
1da177e4 LT |
138 | movq %rax, %cr3 |
139 | ||
1ab60e0f VG |
140 | /* Ensure I am executing from virtual addresses */ |
141 | movq $1f, %rax | |
bd89004f | 142 | ANNOTATE_RETPOLINE_SAFE |
1ab60e0f VG |
143 | jmp *%rax |
144 | 1: | |
2704fbb6 | 145 | UNWIND_HINT_EMPTY |
1ab60e0f | 146 | |
1da177e4 LT |
147 | /* Check if nx is implemented */ |
148 | movl $0x80000001, %eax | |
149 | cpuid | |
150 | movl %edx,%edi | |
151 | ||
152 | /* Setup EFER (Extended Feature Enable Register) */ | |
153 | movl $MSR_EFER, %ecx | |
154 | rdmsr | |
1ab60e0f VG |
155 | btsl $_EFER_SCE, %eax /* Enable System Call */ |
156 | btl $20,%edi /* No Execute supported? */ | |
1da177e4 LT |
157 | jnc 1f |
158 | btsl $_EFER_NX, %eax | |
78d77df7 | 159 | btsq $_PAGE_BIT_NX,early_pmd_flags(%rip) |
1ab60e0f | 160 | 1: wrmsr /* Make changes effective */ |
1da177e4 LT |
161 | |
162 | /* Setup cr0 */ | |
369101da | 163 | movl $CR0_STATE, %eax |
1da177e4 LT |
164 | /* Make changes effective */ |
165 | movq %rax, %cr0 | |
166 | ||
167 | /* Setup a boot time stack */ | |
b32f96c7 | 168 | movq initial_stack(%rip), %rsp |
1da177e4 LT |
169 | |
170 | /* zero EFLAGS after setting rsp */ | |
171 | pushq $0 | |
172 | popfq | |
173 | ||
174 | /* | |
175 | * We must switch to a new descriptor in kernel space for the GDT | |
176 | * because soon the kernel won't have access anymore to the userspace | |
177 | * addresses where we're currently running on. We have to do that here | |
178 | * because in 32bit we couldn't load a 64bit linear address. | |
179 | */ | |
a939098a | 180 | lgdt early_gdt_descr(%rip) |
1da177e4 | 181 | |
8ec6993d BG |
182 | /* set up data segments */ |
183 | xorl %eax,%eax | |
ffb60175 ZA |
184 | movl %eax,%ds |
185 | movl %eax,%ss | |
186 | movl %eax,%es | |
187 | ||
188 | /* | |
189 | * We don't really need to load %fs or %gs, but load them anyway | |
190 | * to kill any stale realmode selectors. This allows execution | |
191 | * under VT hardware. | |
192 | */ | |
193 | movl %eax,%fs | |
194 | movl %eax,%gs | |
195 | ||
f32ff538 TH |
196 | /* Set up %gs. |
197 | * | |
947e76cd BG |
198 | * The base of %gs always points to the bottom of the irqstack |
199 | * union. If the stack protector canary is enabled, it is | |
200 | * located at %gs:40. Note that, on SMP, the boot cpu uses | |
201 | * init data section till per cpu areas are set up. | |
f32ff538 | 202 | */ |
1da177e4 | 203 | movl $MSR_GS_BASE,%ecx |
650fb439 BG |
204 | movl initial_gs(%rip),%eax |
205 | movl initial_gs+4(%rip),%edx | |
a9468df5 | 206 | wrmsr |
1da177e4 | 207 | |
8170e6be | 208 | /* rsi is pointer to real mode structure with interesting info. |
1da177e4 | 209 | pass it to C */ |
8170e6be | 210 | movq %rsi, %rdi |
a9468df5 | 211 | |
79d243a0 | 212 | .Ljump_to_C_code: |
a9468df5 JP |
213 | /* |
214 | * Jump to run C code and to be on a real kernel address. | |
1da177e4 | 215 | * Since we are running on identity-mapped space we have to jump |
26374c7b EB |
216 | * to the full 64bit address, this is only possible as indirect |
217 | * jump. In addition we need to ensure %cs is set so we make this | |
218 | * a far return. | |
8170e6be PA |
219 | * |
220 | * Note: do not change to far jump indirect with 64bit offset. | |
221 | * | |
222 | * AMD does not support far jump indirect with 64bit offset. | |
223 | * AMD64 Architecture Programmer's Manual, Volume 3: states only | |
224 | * JMP FAR mem16:16 FF /5 Far jump indirect, | |
225 | * with the target specified by a far pointer in memory. | |
226 | * JMP FAR mem16:32 FF /5 Far jump indirect, | |
227 | * with the target specified by a far pointer in memory. | |
228 | * | |
229 | * Intel64 does support 64bit offset. | |
230 | * Software Developer Manual Vol 2: states: | |
231 | * FF /5 JMP m16:16 Jump far, absolute indirect, | |
232 | * address given in m16:16 | |
233 | * FF /5 JMP m16:32 Jump far, absolute indirect, | |
234 | * address given in m16:32. | |
235 | * REX.W + FF /5 JMP m16:64 Jump far, absolute indirect, | |
236 | * address given in m16:64. | |
1da177e4 | 237 | */ |
31dcfec1 | 238 | pushq $.Lafter_lret # put return address on stack for unwinder |
a7bea830 | 239 | xorl %ebp, %ebp # clear frame pointer |
595c1e64 | 240 | movq initial_code(%rip), %rax |
26374c7b EB |
241 | pushq $__KERNEL_CS # set correct cs |
242 | pushq %rax # target address in negative space | |
243 | lretq | |
31dcfec1 | 244 | .Lafter_lret: |
015a2ea5 | 245 | END(secondary_startup_64) |
1da177e4 | 246 | |
04633df0 BP |
247 | #include "verify_cpu.S" |
248 | ||
42e78e97 FY |
249 | #ifdef CONFIG_HOTPLUG_CPU |
250 | /* | |
251 | * Boot CPU0 entry point. It's called from play_dead(). Everything has been set | |
252 | * up already except stack. We just set up stack here. Then call | |
79d243a0 | 253 | * start_secondary() via .Ljump_to_C_code. |
42e78e97 FY |
254 | */ |
255 | ENTRY(start_cpu0) | |
a9468df5 | 256 | movq initial_stack(%rip), %rsp |
2704fbb6 | 257 | UNWIND_HINT_EMPTY |
79d243a0 | 258 | jmp .Ljump_to_C_code |
42e78e97 FY |
259 | ENDPROC(start_cpu0) |
260 | #endif | |
261 | ||
b32f96c7 | 262 | /* Both SMP bootup and ACPI suspend change these variables */ |
da5968ae | 263 | __REFDATA |
8170e6be PA |
264 | .balign 8 |
265 | GLOBAL(initial_code) | |
1da177e4 | 266 | .quad x86_64_start_kernel |
8170e6be | 267 | GLOBAL(initial_gs) |
2add8e23 | 268 | .quad INIT_PER_CPU_VAR(irq_stack_union) |
b32f96c7 | 269 | GLOBAL(initial_stack) |
22dc3918 JP |
270 | /* |
271 | * The SIZEOF_PTREGS gap is a convention which helps the in-kernel | |
272 | * unwinder reliably detect the end of the stack. | |
273 | */ | |
274 | .quad init_thread_union + THREAD_SIZE - SIZEOF_PTREGS | |
b9af7c0d | 275 | __FINITDATA |
1da177e4 | 276 | |
8170e6be | 277 | __INIT |
cdeb6048 | 278 | ENTRY(early_idt_handler_array) |
749c970a AK |
279 | i = 0 |
280 | .rept NUM_EXCEPTION_VECTORS | |
82c62fa0 | 281 | .if ((EXCEPTION_ERRCODE_MASK >> i) & 1) == 0 |
2704fbb6 JP |
282 | UNWIND_HINT_IRET_REGS |
283 | pushq $0 # Dummy error code, to make stack frame uniform | |
284 | .else | |
285 | UNWIND_HINT_IRET_REGS offset=8 | |
9900aa2f PA |
286 | .endif |
287 | pushq $i # 72(%rsp) Vector number | |
cdeb6048 | 288 | jmp early_idt_handler_common |
2704fbb6 | 289 | UNWIND_HINT_IRET_REGS |
749c970a | 290 | i = i + 1 |
cdeb6048 | 291 | .fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc |
749c970a | 292 | .endr |
2704fbb6 | 293 | UNWIND_HINT_IRET_REGS offset=16 |
015a2ea5 | 294 | END(early_idt_handler_array) |
8866cd9d | 295 | |
cdeb6048 AL |
296 | early_idt_handler_common: |
297 | /* | |
298 | * The stack is the hardware frame, an error code or zero, and the | |
299 | * vector number. | |
300 | */ | |
9900aa2f PA |
301 | cld |
302 | ||
b957591f | 303 | incl early_recursion_flag(%rip) |
9900aa2f | 304 | |
7bbcdb1c AL |
305 | /* The vector number is currently in the pt_regs->di slot. */ |
306 | pushq %rsi /* pt_regs->si */ | |
307 | movq 8(%rsp), %rsi /* RSI = vector number */ | |
308 | movq %rdi, 8(%rsp) /* pt_regs->di = RDI */ | |
309 | pushq %rdx /* pt_regs->dx */ | |
310 | pushq %rcx /* pt_regs->cx */ | |
311 | pushq %rax /* pt_regs->ax */ | |
312 | pushq %r8 /* pt_regs->r8 */ | |
313 | pushq %r9 /* pt_regs->r9 */ | |
314 | pushq %r10 /* pt_regs->r10 */ | |
315 | pushq %r11 /* pt_regs->r11 */ | |
316 | pushq %rbx /* pt_regs->bx */ | |
317 | pushq %rbp /* pt_regs->bp */ | |
318 | pushq %r12 /* pt_regs->r12 */ | |
319 | pushq %r13 /* pt_regs->r13 */ | |
320 | pushq %r14 /* pt_regs->r14 */ | |
321 | pushq %r15 /* pt_regs->r15 */ | |
2704fbb6 | 322 | UNWIND_HINT_REGS |
7bbcdb1c | 323 | |
7bbcdb1c | 324 | cmpq $14,%rsi /* Page fault? */ |
8170e6be | 325 | jnz 10f |
7bbcdb1c | 326 | GET_CR2_INTO(%rdi) /* Can clobber any volatile register if pv */ |
8170e6be PA |
327 | call early_make_pgtable |
328 | andl %eax,%eax | |
7bbcdb1c | 329 | jz 20f /* All good */ |
9900aa2f | 330 | |
8170e6be | 331 | 10: |
7bbcdb1c | 332 | movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */ |
9900aa2f | 333 | call early_fixup_exception |
076f9776 | 334 | |
0e861fbb | 335 | 20: |
9900aa2f | 336 | decl early_recursion_flag(%rip) |
26c4ef9c | 337 | jmp restore_regs_and_return_to_kernel |
015a2ea5 | 338 | END(early_idt_handler_common) |
9900aa2f | 339 | |
8170e6be PA |
340 | __INITDATA |
341 | ||
9900aa2f | 342 | .balign 4 |
0e861fbb | 343 | GLOBAL(early_recursion_flag) |
b957591f | 344 | .long 0 |
1da177e4 | 345 | |
f0cf5d1a | 346 | #define NEXT_PAGE(name) \ |
67dcbb6b | 347 | .balign PAGE_SIZE; \ |
8170e6be | 348 | GLOBAL(name) |
f0cf5d1a | 349 | |
d9e9a641 DH |
350 | #ifdef CONFIG_PAGE_TABLE_ISOLATION |
351 | /* | |
352 | * Each PGD needs to be 8k long and 8k aligned. We do not | |
353 | * ever go out to userspace with these, so we do not | |
354 | * strictly *need* the second page, but this allows us to | |
355 | * have a single set_pgd() implementation that does not | |
356 | * need to worry about whether it has 4k or 8k to work | |
357 | * with. | |
358 | * | |
359 | * This ensures PGDs are 8k long: | |
360 | */ | |
361 | #define PTI_USER_PGD_FILL 512 | |
362 | /* This ensures they are 8k-aligned: */ | |
363 | #define NEXT_PGD_PAGE(name) \ | |
364 | .balign 2 * PAGE_SIZE; \ | |
365 | GLOBAL(name) | |
366 | #else | |
367 | #define NEXT_PGD_PAGE(name) NEXT_PAGE(name) | |
368 | #define PTI_USER_PGD_FILL 0 | |
369 | #endif | |
370 | ||
67dcbb6b | 371 | /* Automate the creation of 1 to 1 mapping pmd entries */ |
0e192b99 CG |
372 | #define PMDS(START, PERM, COUNT) \ |
373 | i = 0 ; \ | |
374 | .rept (COUNT) ; \ | |
375 | .quad (START) + (i << PMD_SHIFT) + (PERM) ; \ | |
376 | i = i + 1 ; \ | |
67dcbb6b VG |
377 | .endr |
378 | ||
8170e6be | 379 | __INITDATA |
d9e9a641 | 380 | NEXT_PGD_PAGE(early_top_pgt) |
6f9dd329 | 381 | .fill 512,8,0 |
d9e9a641 | 382 | .fill PTI_USER_PGD_FILL,8,0 |
8170e6be PA |
383 | |
384 | NEXT_PAGE(early_dynamic_pgts) | |
385 | .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0 | |
386 | ||
b9af7c0d | 387 | .data |
8170e6be | 388 | |
7733607f | 389 | #if defined(CONFIG_XEN_PV) || defined(CONFIG_PVH) |
d9e9a641 | 390 | NEXT_PGD_PAGE(init_top_pgt) |
21729f81 | 391 | .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC |
b9952ec7 | 392 | .org init_top_pgt + L4_PAGE_OFFSET*8, 0 |
21729f81 | 393 | .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC |
b9952ec7 | 394 | .org init_top_pgt + L4_START_KERNEL*8, 0 |
cfd243d4 | 395 | /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */ |
21729f81 | 396 | .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC |
d9e9a641 | 397 | .fill PTI_USER_PGD_FILL,8,0 |
1da177e4 | 398 | |
f0cf5d1a | 399 | NEXT_PAGE(level3_ident_pgt) |
21729f81 | 400 | .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC |
8170e6be PA |
401 | .fill 511, 8, 0 |
402 | NEXT_PAGE(level2_ident_pgt) | |
430d4005 DH |
403 | /* |
404 | * Since I easily can, map the first 1G. | |
8170e6be | 405 | * Don't set NX because code runs from these pages. |
430d4005 DH |
406 | * |
407 | * Note: This sets _PAGE_GLOBAL despite whether | |
408 | * the CPU supports it or it is enabled. But, | |
409 | * the CPU should ignore the bit. | |
8170e6be PA |
410 | */ |
411 | PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD) | |
4375c299 | 412 | #else |
d9e9a641 | 413 | NEXT_PGD_PAGE(init_top_pgt) |
4375c299 | 414 | .fill 512,8,0 |
d9e9a641 | 415 | .fill PTI_USER_PGD_FILL,8,0 |
8170e6be | 416 | #endif |
1da177e4 | 417 | |
032370b9 KS |
418 | #ifdef CONFIG_X86_5LEVEL |
419 | NEXT_PAGE(level4_kernel_pgt) | |
420 | .fill 511,8,0 | |
21729f81 | 421 | .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC |
032370b9 KS |
422 | #endif |
423 | ||
f0cf5d1a | 424 | NEXT_PAGE(level3_kernel_pgt) |
a6523748 | 425 | .fill L3_START_KERNEL,8,0 |
1da177e4 | 426 | /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */ |
21729f81 TL |
427 | .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC |
428 | .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC | |
b1c931e3 | 429 | |
f0cf5d1a | 430 | NEXT_PAGE(level2_kernel_pgt) |
88f3aec7 | 431 | /* |
85eb69a1 | 432 | * 512 MB kernel mapping. We spend a full page on this pagetable |
88f3aec7 IM |
433 | * anyway. |
434 | * | |
435 | * The kernel code+data+bss must not be bigger than that. | |
436 | * | |
85eb69a1 | 437 | * (NOTE: at +512MB starts the module area, see MODULES_VADDR. |
88f3aec7 IM |
438 | * If you want to increase this then increase MODULES_VADDR |
439 | * too.) | |
430d4005 DH |
440 | * |
441 | * This table is eventually used by the kernel during normal | |
442 | * runtime. Care must be taken to clear out undesired bits | |
443 | * later, like _PAGE_RW or _PAGE_GLOBAL in some cases. | |
88f3aec7 | 444 | */ |
8490638c | 445 | PMDS(0, __PAGE_KERNEL_LARGE_EXEC, |
d4afe414 | 446 | KERNEL_IMAGE_SIZE/PMD_SIZE) |
1da177e4 | 447 | |
8170e6be | 448 | NEXT_PAGE(level2_fixmap_pgt) |
05ab1d8a FT |
449 | .fill (512 - 4 - FIXMAP_PMD_NUM),8,0 |
450 | pgtno = 0 | |
451 | .rept (FIXMAP_PMD_NUM) | |
452 | .quad level1_fixmap_pgt + (pgtno << PAGE_SHIFT) - __START_KERNEL_map \ | |
453 | + _PAGE_TABLE_NOENC; | |
454 | pgtno = pgtno + 1 | |
455 | .endr | |
456 | /* 6 MB reserved space + a 2MB hole */ | |
457 | .fill 4,8,0 | |
8170e6be PA |
458 | |
459 | NEXT_PAGE(level1_fixmap_pgt) | |
05ab1d8a | 460 | .rept (FIXMAP_PMD_NUM) |
8170e6be | 461 | .fill 512,8,0 |
05ab1d8a | 462 | .endr |
1ab60e0f | 463 | |
67dcbb6b | 464 | #undef PMDS |
1da177e4 | 465 | |
f0cf5d1a | 466 | .data |
1da177e4 | 467 | .align 16 |
a939098a GC |
468 | .globl early_gdt_descr |
469 | early_gdt_descr: | |
470 | .word GDT_ENTRIES*8-1 | |
3e5d8f97 | 471 | early_gdt_descr_base: |
2add8e23 | 472 | .quad INIT_PER_CPU_VAR(gdt_page) |
1da177e4 | 473 | |
1ab60e0f VG |
474 | ENTRY(phys_base) |
475 | /* This must match the first entry in level2_kernel_pgt */ | |
476 | .quad 0x0000000000000000 | |
784d5699 | 477 | EXPORT_SYMBOL(phys_base) |
1ab60e0f | 478 | |
8c5e5ac3 | 479 | #include "../../x86/xen/xen-head.S" |
2704fbb6 | 480 | |
02b7da37 | 481 | __PAGE_ALIGNED_BSS |
8170e6be | 482 | NEXT_PAGE(empty_zero_page) |
e57113bc | 483 | .skip PAGE_SIZE |
784d5699 | 484 | EXPORT_SYMBOL(empty_zero_page) |
ef7f0d6a | 485 |