Commit | Line | Data |
---|---|---|
ac23d4ee JS |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * SGI UV APIC functions (note: not an Intel compatible APIC) | |
7 | * | |
9f5314fb | 8 | * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved. |
ac23d4ee JS |
9 | */ |
10 | ||
83f5d894 | 11 | #include <linux/kernel.h> |
ac23d4ee | 12 | #include <linux/threads.h> |
7f1baa06 | 13 | #include <linux/cpu.h> |
ac23d4ee JS |
14 | #include <linux/cpumask.h> |
15 | #include <linux/string.h> | |
ac23d4ee JS |
16 | #include <linux/ctype.h> |
17 | #include <linux/init.h> | |
18 | #include <linux/sched.h> | |
ac23d4ee | 19 | #include <linux/module.h> |
0c81c746 | 20 | #include <linux/hardirq.h> |
7f1baa06 | 21 | #include <linux/timer.h> |
a3d732f9 | 22 | #include <linux/proc_fs.h> |
7f1baa06 | 23 | #include <asm/current.h> |
ac23d4ee JS |
24 | #include <asm/smp.h> |
25 | #include <asm/ipi.h> | |
26 | #include <asm/genapic.h> | |
83f5d894 | 27 | #include <asm/pgtable.h> |
bdbcdd48 | 28 | #include <asm/uv/uv.h> |
ac23d4ee JS |
29 | #include <asm/uv/uv_mmrs.h> |
30 | #include <asm/uv/uv_hub.h> | |
7019cc2d | 31 | #include <asm/uv/bios.h> |
ac23d4ee | 32 | |
510b3725 YL |
33 | DEFINE_PER_CPU(int, x2apic_extra_bits); |
34 | ||
1b9b89e7 YL |
35 | static enum uv_system_type uv_system_type; |
36 | ||
f8827c01 | 37 | static int uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id) |
1b9b89e7 YL |
38 | { |
39 | if (!strcmp(oem_id, "SGI")) { | |
40 | if (!strcmp(oem_table_id, "UVL")) | |
41 | uv_system_type = UV_LEGACY_APIC; | |
42 | else if (!strcmp(oem_table_id, "UVX")) | |
43 | uv_system_type = UV_X2APIC; | |
44 | else if (!strcmp(oem_table_id, "UVH")) { | |
45 | uv_system_type = UV_NON_UNIQUE_APIC; | |
46 | return 1; | |
47 | } | |
48 | } | |
49 | return 0; | |
50 | } | |
51 | ||
52 | enum uv_system_type get_uv_system_type(void) | |
53 | { | |
54 | return uv_system_type; | |
55 | } | |
56 | ||
57 | int is_uv_system(void) | |
58 | { | |
59 | return uv_system_type != UV_NONE; | |
60 | } | |
8067794b | 61 | EXPORT_SYMBOL_GPL(is_uv_system); |
1b9b89e7 | 62 | |
ac23d4ee JS |
63 | DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); |
64 | EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info); | |
65 | ||
66 | struct uv_blade_info *uv_blade_info; | |
67 | EXPORT_SYMBOL_GPL(uv_blade_info); | |
68 | ||
69 | short *uv_node_to_blade; | |
70 | EXPORT_SYMBOL_GPL(uv_node_to_blade); | |
71 | ||
72 | short *uv_cpu_to_blade; | |
73 | EXPORT_SYMBOL_GPL(uv_cpu_to_blade); | |
74 | ||
75 | short uv_possible_blades; | |
76 | EXPORT_SYMBOL_GPL(uv_possible_blades); | |
77 | ||
7019cc2d RA |
78 | unsigned long sn_rtc_cycles_per_second; |
79 | EXPORT_SYMBOL(sn_rtc_cycles_per_second); | |
80 | ||
ac23d4ee JS |
81 | /* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */ |
82 | ||
bcda016e | 83 | static const struct cpumask *uv_target_cpus(void) |
ac23d4ee | 84 | { |
bcda016e | 85 | return cpumask_of(0); |
ac23d4ee JS |
86 | } |
87 | ||
bcda016e | 88 | static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask) |
ac23d4ee | 89 | { |
bcda016e MT |
90 | cpumask_clear(retmask); |
91 | cpumask_set_cpu(cpu, retmask); | |
ac23d4ee JS |
92 | } |
93 | ||
94 | int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip) | |
95 | { | |
96 | unsigned long val; | |
9f5314fb | 97 | int pnode; |
ac23d4ee | 98 | |
9f5314fb | 99 | pnode = uv_apicid_to_pnode(phys_apicid); |
ac23d4ee JS |
100 | val = (1UL << UVH_IPI_INT_SEND_SHFT) | |
101 | (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | | |
102 | (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | | |
34d05591 | 103 | APIC_DM_INIT; |
9f5314fb | 104 | uv_write_global_mmr64(pnode, UVH_IPI_INT, val); |
34d05591 JS |
105 | mdelay(10); |
106 | ||
107 | val = (1UL << UVH_IPI_INT_SEND_SHFT) | | |
108 | (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | | |
109 | (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | | |
110 | APIC_DM_STARTUP; | |
9f5314fb | 111 | uv_write_global_mmr64(pnode, UVH_IPI_INT, val); |
ac23d4ee JS |
112 | return 0; |
113 | } | |
114 | ||
115 | static void uv_send_IPI_one(int cpu, int vector) | |
116 | { | |
34d05591 | 117 | unsigned long val, apicid, lapicid; |
9f5314fb | 118 | int pnode; |
ac23d4ee | 119 | |
1e0b5d00 | 120 | apicid = per_cpu(x86_cpu_to_apicid, cpu); |
dac5f412 | 121 | lapicid = apicid & 0x3f; /* ZZZ macro needed */ |
9f5314fb | 122 | pnode = uv_apicid_to_pnode(apicid); |
dac5f412 IM |
123 | |
124 | val = ( 1UL << UVH_IPI_INT_SEND_SHFT ) | | |
125 | ( lapicid << UVH_IPI_INT_APIC_ID_SHFT ) | | |
126 | ( vector << UVH_IPI_INT_VECTOR_SHFT ); | |
127 | ||
9f5314fb | 128 | uv_write_global_mmr64(pnode, UVH_IPI_INT, val); |
ac23d4ee JS |
129 | } |
130 | ||
bcda016e | 131 | static void uv_send_IPI_mask(const struct cpumask *mask, int vector) |
ac23d4ee JS |
132 | { |
133 | unsigned int cpu; | |
134 | ||
bcda016e | 135 | for_each_cpu(cpu, mask) |
e7986739 MT |
136 | uv_send_IPI_one(cpu, vector); |
137 | } | |
138 | ||
bcda016e | 139 | static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) |
e7986739 | 140 | { |
e7986739 | 141 | unsigned int this_cpu = smp_processor_id(); |
dac5f412 | 142 | unsigned int cpu; |
e7986739 | 143 | |
dac5f412 | 144 | for_each_cpu(cpu, mask) { |
e7986739 | 145 | if (cpu != this_cpu) |
ac23d4ee | 146 | uv_send_IPI_one(cpu, vector); |
dac5f412 | 147 | } |
ac23d4ee JS |
148 | } |
149 | ||
150 | static void uv_send_IPI_allbutself(int vector) | |
151 | { | |
e7986739 | 152 | unsigned int this_cpu = smp_processor_id(); |
dac5f412 | 153 | unsigned int cpu; |
ac23d4ee | 154 | |
dac5f412 | 155 | for_each_online_cpu(cpu) { |
e7986739 MT |
156 | if (cpu != this_cpu) |
157 | uv_send_IPI_one(cpu, vector); | |
dac5f412 | 158 | } |
ac23d4ee JS |
159 | } |
160 | ||
161 | static void uv_send_IPI_all(int vector) | |
162 | { | |
bcda016e | 163 | uv_send_IPI_mask(cpu_online_mask, vector); |
ac23d4ee JS |
164 | } |
165 | ||
166 | static int uv_apic_id_registered(void) | |
167 | { | |
168 | return 1; | |
169 | } | |
170 | ||
277d1f58 | 171 | static void uv_init_apic_ldr(void) |
5c520a67 SS |
172 | { |
173 | } | |
174 | ||
bcda016e | 175 | static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask) |
ac23d4ee | 176 | { |
ac23d4ee JS |
177 | /* |
178 | * We're using fixed IRQ delivery, can only return one phys APIC ID. | |
179 | * May as well be the first. | |
180 | */ | |
debccb3e IM |
181 | int cpu = cpumask_first(cpumask); |
182 | ||
247bc6ca | 183 | if ((unsigned)cpu < nr_cpu_ids) |
ac23d4ee JS |
184 | return per_cpu(x86_cpu_to_apicid, cpu); |
185 | else | |
186 | return BAD_APICID; | |
187 | } | |
188 | ||
debccb3e IM |
189 | static unsigned int |
190 | uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask, | |
191 | const struct cpumask *andmask) | |
95d313cf MT |
192 | { |
193 | int cpu; | |
194 | ||
195 | /* | |
196 | * We're using fixed IRQ delivery, can only return one phys APIC ID. | |
197 | * May as well be the first. | |
198 | */ | |
debccb3e | 199 | for_each_cpu_and(cpu, cpumask, andmask) { |
a775a38b MT |
200 | if (cpumask_test_cpu(cpu, cpu_online_mask)) |
201 | break; | |
debccb3e | 202 | } |
6eeb7c5a MT |
203 | if (cpu < nr_cpu_ids) |
204 | return per_cpu(x86_cpu_to_apicid, cpu); | |
debccb3e | 205 | |
95d313cf MT |
206 | return BAD_APICID; |
207 | } | |
208 | ||
ca6c8ed4 | 209 | static unsigned int x2apic_get_apic_id(unsigned long x) |
0c81c746 SS |
210 | { |
211 | unsigned int id; | |
212 | ||
213 | WARN_ON(preemptible() && num_online_cpus() > 1); | |
f910a9dc | 214 | id = x | __get_cpu_var(x2apic_extra_bits); |
0c81c746 SS |
215 | |
216 | return id; | |
217 | } | |
218 | ||
1b9b89e7 | 219 | static unsigned long set_apic_id(unsigned int id) |
f910a9dc YL |
220 | { |
221 | unsigned long x; | |
222 | ||
223 | /* maskout x2apic_extra_bits ? */ | |
224 | x = id; | |
225 | return x; | |
226 | } | |
227 | ||
228 | static unsigned int uv_read_apic_id(void) | |
229 | { | |
230 | ||
ca6c8ed4 | 231 | return x2apic_get_apic_id(apic_read(APIC_ID)); |
f910a9dc YL |
232 | } |
233 | ||
d4c9a9f3 | 234 | static int uv_phys_pkg_id(int initial_apicid, int index_msb) |
ac23d4ee | 235 | { |
0c81c746 | 236 | return uv_read_apic_id() >> index_msb; |
ac23d4ee JS |
237 | } |
238 | ||
ac23d4ee JS |
239 | static void uv_send_IPI_self(int vector) |
240 | { | |
241 | apic_write(APIC_SELF_IPI, vector); | |
242 | } | |
ac23d4ee JS |
243 | |
244 | struct genapic apic_x2apic_uv_x = { | |
c7967329 IM |
245 | |
246 | .name = "UV large system", | |
247 | .probe = NULL, | |
248 | .acpi_madt_oem_check = uv_acpi_madt_oem_check, | |
249 | .apic_id_registered = uv_apic_id_registered, | |
250 | ||
f8987a10 | 251 | .irq_delivery_mode = dest_Fixed, |
0b06e734 | 252 | .irq_dest_mode = 1, /* logical */ |
c7967329 IM |
253 | |
254 | .target_cpus = uv_target_cpus, | |
08125d3e | 255 | .disable_esr = 0, |
bdb1a9b6 | 256 | .dest_logical = APIC_DEST_LOGICAL, |
c7967329 IM |
257 | .check_apicid_used = NULL, |
258 | .check_apicid_present = NULL, | |
259 | ||
c7967329 IM |
260 | .vector_allocation_domain = uv_vector_allocation_domain, |
261 | .init_apic_ldr = uv_init_apic_ldr, | |
262 | ||
263 | .ioapic_phys_id_map = NULL, | |
264 | .setup_apic_routing = NULL, | |
265 | .multi_timer_check = NULL, | |
266 | .apicid_to_node = NULL, | |
267 | .cpu_to_logical_apicid = NULL, | |
a21769a4 | 268 | .cpu_present_to_apicid = default_cpu_present_to_apicid, |
c7967329 IM |
269 | .apicid_to_cpu_present = NULL, |
270 | .setup_portio_remap = NULL, | |
a27a6210 | 271 | .check_phys_apicid_present = default_check_phys_apicid_present, |
c7967329 | 272 | .enable_apic_mode = NULL, |
d4c9a9f3 | 273 | .phys_pkg_id = uv_phys_pkg_id, |
c7967329 IM |
274 | .mps_oem_check = NULL, |
275 | ||
ca6c8ed4 | 276 | .get_apic_id = x2apic_get_apic_id, |
c7967329 IM |
277 | .set_apic_id = set_apic_id, |
278 | .apic_id_mask = 0xFFFFFFFFu, | |
279 | ||
280 | .cpu_mask_to_apicid = uv_cpu_mask_to_apicid, | |
281 | .cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and, | |
282 | ||
283 | .send_IPI_mask = uv_send_IPI_mask, | |
284 | .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself, | |
285 | .send_IPI_allbutself = uv_send_IPI_allbutself, | |
286 | .send_IPI_all = uv_send_IPI_all, | |
287 | .send_IPI_self = uv_send_IPI_self, | |
288 | ||
289 | .wakeup_cpu = NULL, | |
290 | .trampoline_phys_low = 0, | |
291 | .trampoline_phys_high = 0, | |
292 | .wait_for_init_deassert = NULL, | |
293 | .smp_callin_clear_local_apic = NULL, | |
294 | .store_NMI_vector = NULL, | |
295 | .restore_NMI_vector = NULL, | |
296 | .inquire_remote_apic = NULL, | |
ac23d4ee JS |
297 | }; |
298 | ||
9f5314fb | 299 | static __cpuinit void set_x2apic_extra_bits(int pnode) |
ac23d4ee | 300 | { |
9f5314fb | 301 | __get_cpu_var(x2apic_extra_bits) = (pnode << 6); |
ac23d4ee JS |
302 | } |
303 | ||
304 | /* | |
305 | * Called on boot cpu. | |
306 | */ | |
9f5314fb JS |
307 | static __init int boot_pnode_to_blade(int pnode) |
308 | { | |
309 | int blade; | |
310 | ||
311 | for (blade = 0; blade < uv_num_possible_blades(); blade++) | |
312 | if (pnode == uv_blade_info[blade].pnode) | |
313 | return blade; | |
314 | BUG(); | |
315 | } | |
316 | ||
317 | struct redir_addr { | |
318 | unsigned long redirect; | |
319 | unsigned long alias; | |
320 | }; | |
321 | ||
322 | #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT | |
323 | ||
324 | static __initdata struct redir_addr redir_addrs[] = { | |
325 | {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG}, | |
326 | {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG}, | |
327 | {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG}, | |
328 | }; | |
329 | ||
330 | static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size) | |
331 | { | |
332 | union uvh_si_alias0_overlay_config_u alias; | |
333 | union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect; | |
334 | int i; | |
335 | ||
336 | for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) { | |
337 | alias.v = uv_read_local_mmr(redir_addrs[i].alias); | |
338 | if (alias.s.base == 0) { | |
339 | *size = (1UL << alias.s.m_alias); | |
340 | redirect.v = uv_read_local_mmr(redir_addrs[i].redirect); | |
341 | *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT; | |
342 | return; | |
343 | } | |
344 | } | |
345 | BUG(); | |
346 | } | |
347 | ||
83f5d894 JS |
348 | static __init void map_low_mmrs(void) |
349 | { | |
350 | init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE); | |
351 | init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE); | |
352 | } | |
353 | ||
354 | enum map_type {map_wb, map_uc}; | |
355 | ||
d2f904bb JS |
356 | static __init void map_high(char *id, unsigned long base, int shift, |
357 | int max_pnode, enum map_type map_type) | |
83f5d894 JS |
358 | { |
359 | unsigned long bytes, paddr; | |
360 | ||
361 | paddr = base << shift; | |
d2f904bb | 362 | bytes = (1UL << shift) * (max_pnode + 1); |
83f5d894 JS |
363 | printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, |
364 | paddr + bytes); | |
365 | if (map_type == map_uc) | |
366 | init_extra_mapping_uc(paddr, bytes); | |
367 | else | |
368 | init_extra_mapping_wb(paddr, bytes); | |
369 | ||
370 | } | |
371 | static __init void map_gru_high(int max_pnode) | |
372 | { | |
373 | union uvh_rh_gam_gru_overlay_config_mmr_u gru; | |
374 | int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
375 | ||
376 | gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR); | |
377 | if (gru.s.enable) | |
d2f904bb | 378 | map_high("GRU", gru.s.base, shift, max_pnode, map_wb); |
83f5d894 JS |
379 | } |
380 | ||
381 | static __init void map_config_high(int max_pnode) | |
382 | { | |
383 | union uvh_rh_gam_cfg_overlay_config_mmr_u cfg; | |
384 | int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
385 | ||
386 | cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR); | |
387 | if (cfg.s.enable) | |
d2f904bb | 388 | map_high("CONFIG", cfg.s.base, shift, max_pnode, map_uc); |
83f5d894 JS |
389 | } |
390 | ||
391 | static __init void map_mmr_high(int max_pnode) | |
392 | { | |
393 | union uvh_rh_gam_mmr_overlay_config_mmr_u mmr; | |
394 | int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
395 | ||
396 | mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR); | |
397 | if (mmr.s.enable) | |
d2f904bb | 398 | map_high("MMR", mmr.s.base, shift, max_pnode, map_uc); |
83f5d894 JS |
399 | } |
400 | ||
401 | static __init void map_mmioh_high(int max_pnode) | |
402 | { | |
403 | union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh; | |
404 | int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
405 | ||
406 | mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR); | |
407 | if (mmioh.s.enable) | |
d2f904bb | 408 | map_high("MMIOH", mmioh.s.base, shift, max_pnode, map_uc); |
83f5d894 JS |
409 | } |
410 | ||
7019cc2d RA |
411 | static __init void uv_rtc_init(void) |
412 | { | |
922402f1 RA |
413 | long status; |
414 | u64 ticks_per_sec; | |
7019cc2d | 415 | |
922402f1 RA |
416 | status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, |
417 | &ticks_per_sec); | |
418 | if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) { | |
7019cc2d RA |
419 | printk(KERN_WARNING |
420 | "unable to determine platform RTC clock frequency, " | |
421 | "guessing.\n"); | |
422 | /* BIOS gives wrong value for clock freq. so guess */ | |
423 | sn_rtc_cycles_per_second = 1000000000000UL / 30000UL; | |
424 | } else | |
425 | sn_rtc_cycles_per_second = ticks_per_sec; | |
426 | } | |
427 | ||
7f1baa06 MT |
428 | /* |
429 | * percpu heartbeat timer | |
430 | */ | |
431 | static void uv_heartbeat(unsigned long ignored) | |
432 | { | |
433 | struct timer_list *timer = &uv_hub_info->scir.timer; | |
434 | unsigned char bits = uv_hub_info->scir.state; | |
435 | ||
436 | /* flip heartbeat bit */ | |
437 | bits ^= SCIR_CPU_HEARTBEAT; | |
438 | ||
69a72a0e MT |
439 | /* is this cpu idle? */ |
440 | if (idle_cpu(raw_smp_processor_id())) | |
7f1baa06 MT |
441 | bits &= ~SCIR_CPU_ACTIVITY; |
442 | else | |
443 | bits |= SCIR_CPU_ACTIVITY; | |
444 | ||
445 | /* update system controller interface reg */ | |
446 | uv_set_scir_bits(bits); | |
447 | ||
448 | /* enable next timer period */ | |
449 | mod_timer(timer, jiffies + SCIR_CPU_HB_INTERVAL); | |
450 | } | |
451 | ||
452 | static void __cpuinit uv_heartbeat_enable(int cpu) | |
453 | { | |
454 | if (!uv_cpu_hub_info(cpu)->scir.enabled) { | |
455 | struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer; | |
456 | ||
457 | uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY); | |
458 | setup_timer(timer, uv_heartbeat, cpu); | |
459 | timer->expires = jiffies + SCIR_CPU_HB_INTERVAL; | |
460 | add_timer_on(timer, cpu); | |
461 | uv_cpu_hub_info(cpu)->scir.enabled = 1; | |
462 | } | |
463 | ||
464 | /* check boot cpu */ | |
465 | if (!uv_cpu_hub_info(0)->scir.enabled) | |
466 | uv_heartbeat_enable(0); | |
467 | } | |
468 | ||
77be80e4 | 469 | #ifdef CONFIG_HOTPLUG_CPU |
7f1baa06 MT |
470 | static void __cpuinit uv_heartbeat_disable(int cpu) |
471 | { | |
472 | if (uv_cpu_hub_info(cpu)->scir.enabled) { | |
473 | uv_cpu_hub_info(cpu)->scir.enabled = 0; | |
474 | del_timer(&uv_cpu_hub_info(cpu)->scir.timer); | |
475 | } | |
476 | uv_set_cpu_scir_bits(cpu, 0xff); | |
477 | } | |
478 | ||
7f1baa06 MT |
479 | /* |
480 | * cpu hotplug notifier | |
481 | */ | |
482 | static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self, | |
483 | unsigned long action, void *hcpu) | |
484 | { | |
485 | long cpu = (long)hcpu; | |
486 | ||
487 | switch (action) { | |
488 | case CPU_ONLINE: | |
489 | uv_heartbeat_enable(cpu); | |
490 | break; | |
491 | case CPU_DOWN_PREPARE: | |
492 | uv_heartbeat_disable(cpu); | |
493 | break; | |
494 | default: | |
495 | break; | |
496 | } | |
497 | return NOTIFY_OK; | |
498 | } | |
499 | ||
500 | static __init void uv_scir_register_cpu_notifier(void) | |
501 | { | |
502 | hotcpu_notifier(uv_scir_cpu_notify, 0); | |
503 | } | |
504 | ||
505 | #else /* !CONFIG_HOTPLUG_CPU */ | |
506 | ||
507 | static __init void uv_scir_register_cpu_notifier(void) | |
508 | { | |
509 | } | |
510 | ||
511 | static __init int uv_init_heartbeat(void) | |
512 | { | |
513 | int cpu; | |
514 | ||
515 | if (is_uv_system()) | |
516 | for_each_online_cpu(cpu) | |
517 | uv_heartbeat_enable(cpu); | |
518 | return 0; | |
519 | } | |
520 | ||
521 | late_initcall(uv_init_heartbeat); | |
522 | ||
523 | #endif /* !CONFIG_HOTPLUG_CPU */ | |
524 | ||
8da077d6 JS |
525 | /* |
526 | * Called on each cpu to initialize the per_cpu UV data area. | |
527 | * ZZZ hotplug not supported yet | |
528 | */ | |
529 | void __cpuinit uv_cpu_init(void) | |
530 | { | |
531 | /* CPU 0 initilization will be done via uv_system_init. */ | |
532 | if (!uv_blade_info) | |
533 | return; | |
534 | ||
535 | uv_blade_info[uv_numa_blade_id()].nr_online_cpus++; | |
536 | ||
537 | if (get_uv_system_type() == UV_NON_UNIQUE_APIC) | |
538 | set_x2apic_extra_bits(uv_hub_info->pnode); | |
539 | } | |
540 | ||
c4bd1fda MS |
541 | |
542 | void __init uv_system_init(void) | |
ac23d4ee JS |
543 | { |
544 | union uvh_si_addr_map_config_u m_n_config; | |
9f5314fb JS |
545 | union uvh_node_id_u node_id; |
546 | unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size; | |
547 | int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val; | |
83f5d894 | 548 | int max_pnode = 0; |
9f5314fb | 549 | unsigned long mmr_base, present; |
ac23d4ee | 550 | |
83f5d894 JS |
551 | map_low_mmrs(); |
552 | ||
ac23d4ee | 553 | m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG); |
9f5314fb JS |
554 | m_val = m_n_config.s.m_skt; |
555 | n_val = m_n_config.s.n_skt; | |
ac23d4ee JS |
556 | mmr_base = |
557 | uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) & | |
558 | ~UV_MMR_ENABLE; | |
559 | printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base); | |
560 | ||
9f5314fb JS |
561 | for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) |
562 | uv_possible_blades += | |
563 | hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8)); | |
ac23d4ee JS |
564 | printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades()); |
565 | ||
566 | bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades(); | |
ef020ab0 | 567 | uv_blade_info = kmalloc(bytes, GFP_KERNEL); |
ac23d4ee | 568 | |
9f5314fb JS |
569 | get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size); |
570 | ||
ac23d4ee | 571 | bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes(); |
ef020ab0 | 572 | uv_node_to_blade = kmalloc(bytes, GFP_KERNEL); |
ac23d4ee JS |
573 | memset(uv_node_to_blade, 255, bytes); |
574 | ||
575 | bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus(); | |
ef020ab0 | 576 | uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL); |
ac23d4ee JS |
577 | memset(uv_cpu_to_blade, 255, bytes); |
578 | ||
9f5314fb JS |
579 | blade = 0; |
580 | for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) { | |
581 | present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8); | |
582 | for (j = 0; j < 64; j++) { | |
583 | if (!test_bit(j, &present)) | |
584 | continue; | |
585 | uv_blade_info[blade].pnode = (i * 64 + j); | |
586 | uv_blade_info[blade].nr_possible_cpus = 0; | |
ac23d4ee | 587 | uv_blade_info[blade].nr_online_cpus = 0; |
9f5314fb | 588 | blade++; |
ac23d4ee | 589 | } |
9f5314fb | 590 | } |
ac23d4ee | 591 | |
9f5314fb JS |
592 | node_id.v = uv_read_local_mmr(UVH_NODE_ID); |
593 | gnode_upper = (((unsigned long)node_id.s.node_id) & | |
594 | ~((1 << n_val) - 1)) << m_val; | |
595 | ||
7f594232 | 596 | uv_bios_init(); |
922402f1 | 597 | uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, |
b0f20989 | 598 | &sn_coherency_id, &sn_region_size); |
7019cc2d RA |
599 | uv_rtc_init(); |
600 | ||
9f5314fb JS |
601 | for_each_present_cpu(cpu) { |
602 | nid = cpu_to_node(cpu); | |
603 | pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu)); | |
604 | blade = boot_pnode_to_blade(pnode); | |
605 | lcpu = uv_blade_info[blade].nr_possible_cpus; | |
606 | uv_blade_info[blade].nr_possible_cpus++; | |
607 | ||
608 | uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base; | |
189f67c4 | 609 | uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size; |
9f5314fb JS |
610 | uv_cpu_hub_info(cpu)->m_val = m_val; |
611 | uv_cpu_hub_info(cpu)->n_val = m_val; | |
ac23d4ee JS |
612 | uv_cpu_hub_info(cpu)->numa_blade_id = blade; |
613 | uv_cpu_hub_info(cpu)->blade_processor_id = lcpu; | |
9f5314fb JS |
614 | uv_cpu_hub_info(cpu)->pnode = pnode; |
615 | uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1; | |
616 | uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1; | |
617 | uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper; | |
ac23d4ee | 618 | uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base; |
b0f20989 | 619 | uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id; |
7f1baa06 | 620 | uv_cpu_hub_info(cpu)->scir.offset = SCIR_LOCAL_MMR_BASE + lcpu; |
ac23d4ee JS |
621 | uv_node_to_blade[nid] = blade; |
622 | uv_cpu_to_blade[cpu] = blade; | |
83f5d894 | 623 | max_pnode = max(pnode, max_pnode); |
ac23d4ee | 624 | |
83f5d894 | 625 | printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, " |
9f5314fb JS |
626 | "lcpu %d, blade %d\n", |
627 | cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid, | |
628 | lcpu, blade); | |
ac23d4ee | 629 | } |
83f5d894 JS |
630 | |
631 | map_gru_high(max_pnode); | |
632 | map_mmr_high(max_pnode); | |
633 | map_config_high(max_pnode); | |
634 | map_mmioh_high(max_pnode); | |
ac23d4ee | 635 | |
8da077d6 | 636 | uv_cpu_init(); |
7f1baa06 | 637 | uv_scir_register_cpu_notifier(); |
a3d732f9 | 638 | proc_mkdir("sgi_uv", NULL); |
ac23d4ee | 639 | } |