Commit | Line | Data |
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2d9579a1 SS |
1 | #include <linux/threads.h> |
2 | #include <linux/cpumask.h> | |
3 | #include <linux/string.h> | |
4 | #include <linux/kernel.h> | |
5 | #include <linux/ctype.h> | |
6 | #include <linux/init.h> | |
1b9b89e7 YL |
7 | #include <linux/dmar.h> |
8 | ||
2d9579a1 SS |
9 | #include <asm/smp.h> |
10 | #include <asm/ipi.h> | |
11 | #include <asm/genapic.h> | |
12 | ||
1b9b89e7 YL |
13 | static int x2apic_phys; |
14 | ||
15 | static int set_x2apic_phys_mode(char *arg) | |
16 | { | |
17 | x2apic_phys = 1; | |
18 | return 0; | |
19 | } | |
20 | early_param("x2apic_phys", set_x2apic_phys_mode); | |
21 | ||
3cfba089 | 22 | static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id) |
1b9b89e7 | 23 | { |
d25ae38b | 24 | if (cpu_has_x2apic && x2apic_phys) |
1b9b89e7 YL |
25 | return 1; |
26 | ||
27 | return 0; | |
28 | } | |
2d9579a1 SS |
29 | |
30 | /* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */ | |
31 | ||
bcda016e | 32 | static const struct cpumask *x2apic_target_cpus(void) |
2d9579a1 | 33 | { |
bcda016e | 34 | return cpumask_of(0); |
2d9579a1 SS |
35 | } |
36 | ||
bcda016e | 37 | static void x2apic_vector_allocation_domain(int cpu, struct cpumask *retmask) |
2d9579a1 | 38 | { |
bcda016e MT |
39 | cpumask_clear(retmask); |
40 | cpumask_set_cpu(cpu, retmask); | |
2d9579a1 SS |
41 | } |
42 | ||
43 | static void __x2apic_send_IPI_dest(unsigned int apicid, int vector, | |
44 | unsigned int dest) | |
45 | { | |
46 | unsigned long cfg; | |
47 | ||
48 | cfg = __prepare_ICR(0, vector, dest); | |
49 | ||
50 | /* | |
51 | * send the IPI. | |
52 | */ | |
53 | x2apic_icr_write(cfg, apicid); | |
54 | } | |
55 | ||
bcda016e | 56 | static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector) |
2d9579a1 | 57 | { |
2d9579a1 | 58 | unsigned long query_cpu; |
dac5f412 | 59 | unsigned long flags; |
2d9579a1 SS |
60 | |
61 | local_irq_save(flags); | |
bcda016e | 62 | for_each_cpu(query_cpu, mask) { |
2d9579a1 SS |
63 | __x2apic_send_IPI_dest(per_cpu(x86_cpu_to_apicid, query_cpu), |
64 | vector, APIC_DEST_PHYSICAL); | |
65 | } | |
66 | local_irq_restore(flags); | |
67 | } | |
68 | ||
dac5f412 IM |
69 | static void |
70 | x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) | |
2d9579a1 | 71 | { |
e7986739 | 72 | unsigned long this_cpu = smp_processor_id(); |
dac5f412 IM |
73 | unsigned long query_cpu; |
74 | unsigned long flags; | |
e7986739 MT |
75 | |
76 | local_irq_save(flags); | |
bcda016e | 77 | for_each_cpu(query_cpu, mask) { |
e7986739 MT |
78 | if (query_cpu != this_cpu) |
79 | __x2apic_send_IPI_dest( | |
80 | per_cpu(x86_cpu_to_apicid, query_cpu), | |
81 | vector, APIC_DEST_PHYSICAL); | |
82 | } | |
83 | local_irq_restore(flags); | |
84 | } | |
2d9579a1 | 85 | |
e7986739 MT |
86 | static void x2apic_send_IPI_allbutself(int vector) |
87 | { | |
e7986739 | 88 | unsigned long this_cpu = smp_processor_id(); |
dac5f412 IM |
89 | unsigned long query_cpu; |
90 | unsigned long flags; | |
2d9579a1 | 91 | |
e7986739 | 92 | local_irq_save(flags); |
dac5f412 IM |
93 | for_each_online_cpu(query_cpu) { |
94 | if (query_cpu == this_cpu) | |
95 | continue; | |
96 | __x2apic_send_IPI_dest(per_cpu(x86_cpu_to_apicid, query_cpu), | |
97 | vector, APIC_DEST_PHYSICAL); | |
98 | } | |
e7986739 | 99 | local_irq_restore(flags); |
2d9579a1 SS |
100 | } |
101 | ||
102 | static void x2apic_send_IPI_all(int vector) | |
103 | { | |
bcda016e | 104 | x2apic_send_IPI_mask(cpu_online_mask, vector); |
2d9579a1 SS |
105 | } |
106 | ||
107 | static int x2apic_apic_id_registered(void) | |
108 | { | |
109 | return 1; | |
110 | } | |
111 | ||
bcda016e | 112 | static unsigned int x2apic_cpu_mask_to_apicid(const struct cpumask *cpumask) |
2d9579a1 | 113 | { |
2d9579a1 SS |
114 | /* |
115 | * We're using fixed IRQ delivery, can only return one phys APIC ID. | |
116 | * May as well be the first. | |
117 | */ | |
debccb3e IM |
118 | int cpu = cpumask_first(cpumask); |
119 | ||
e7986739 | 120 | if ((unsigned)cpu < nr_cpu_ids) |
2d9579a1 SS |
121 | return per_cpu(x86_cpu_to_apicid, cpu); |
122 | else | |
123 | return BAD_APICID; | |
124 | } | |
125 | ||
debccb3e IM |
126 | static unsigned int |
127 | x2apic_cpu_mask_to_apicid_and(const struct cpumask *cpumask, | |
128 | const struct cpumask *andmask) | |
95d313cf MT |
129 | { |
130 | int cpu; | |
131 | ||
132 | /* | |
133 | * We're using fixed IRQ delivery, can only return one phys APIC ID. | |
134 | * May as well be the first. | |
135 | */ | |
debccb3e | 136 | for_each_cpu_and(cpu, cpumask, andmask) { |
a775a38b MT |
137 | if (cpumask_test_cpu(cpu, cpu_online_mask)) |
138 | break; | |
debccb3e IM |
139 | } |
140 | ||
6eeb7c5a MT |
141 | if (cpu < nr_cpu_ids) |
142 | return per_cpu(x86_cpu_to_apicid, cpu); | |
debccb3e | 143 | |
95d313cf MT |
144 | return BAD_APICID; |
145 | } | |
146 | ||
ca6c8ed4 | 147 | static unsigned int x2apic_phys_get_apic_id(unsigned long x) |
f910a9dc | 148 | { |
dac5f412 | 149 | return x; |
f910a9dc YL |
150 | } |
151 | ||
152 | static unsigned long set_apic_id(unsigned int id) | |
153 | { | |
dac5f412 | 154 | return id; |
f910a9dc YL |
155 | } |
156 | ||
d4c9a9f3 | 157 | static int x2apic_phys_pkg_id(int initial_apicid, int index_msb) |
2d9579a1 | 158 | { |
e17941b0 | 159 | return current_cpu_data.initial_apicid >> index_msb; |
2d9579a1 SS |
160 | } |
161 | ||
4d08d97f | 162 | static void x2apic_send_IPI_self(int vector) |
2d9579a1 SS |
163 | { |
164 | apic_write(APIC_SELF_IPI, vector); | |
165 | } | |
166 | ||
4d08d97f | 167 | static void init_x2apic_ldr(void) |
2d9579a1 | 168 | { |
2d9579a1 SS |
169 | } |
170 | ||
171 | struct genapic apic_x2apic_phys = { | |
05c155c2 IM |
172 | |
173 | .name = "physical x2apic", | |
174 | .probe = NULL, | |
175 | .acpi_madt_oem_check = x2apic_acpi_madt_oem_check, | |
176 | .apic_id_registered = x2apic_apic_id_registered, | |
177 | ||
f8987a10 | 178 | .irq_delivery_mode = dest_Fixed, |
0b06e734 | 179 | .irq_dest_mode = 0, /* physical */ |
05c155c2 IM |
180 | |
181 | .target_cpus = x2apic_target_cpus, | |
08125d3e | 182 | .disable_esr = 0, |
bdb1a9b6 | 183 | .dest_logical = 0, |
05c155c2 IM |
184 | .check_apicid_used = NULL, |
185 | .check_apicid_present = NULL, | |
186 | ||
05c155c2 IM |
187 | .vector_allocation_domain = x2apic_vector_allocation_domain, |
188 | .init_apic_ldr = init_x2apic_ldr, | |
189 | ||
190 | .ioapic_phys_id_map = NULL, | |
191 | .setup_apic_routing = NULL, | |
192 | .multi_timer_check = NULL, | |
193 | .apicid_to_node = NULL, | |
194 | .cpu_to_logical_apicid = NULL, | |
a21769a4 | 195 | .cpu_present_to_apicid = default_cpu_present_to_apicid, |
05c155c2 IM |
196 | .apicid_to_cpu_present = NULL, |
197 | .setup_portio_remap = NULL, | |
a27a6210 | 198 | .check_phys_apicid_present = default_check_phys_apicid_present, |
05c155c2 | 199 | .enable_apic_mode = NULL, |
d4c9a9f3 | 200 | .phys_pkg_id = x2apic_phys_pkg_id, |
05c155c2 IM |
201 | .mps_oem_check = NULL, |
202 | ||
ca6c8ed4 | 203 | .get_apic_id = x2apic_phys_get_apic_id, |
05c155c2 IM |
204 | .set_apic_id = set_apic_id, |
205 | .apic_id_mask = 0xFFFFFFFFu, | |
206 | ||
207 | .cpu_mask_to_apicid = x2apic_cpu_mask_to_apicid, | |
208 | .cpu_mask_to_apicid_and = x2apic_cpu_mask_to_apicid_and, | |
209 | ||
210 | .send_IPI_mask = x2apic_send_IPI_mask, | |
211 | .send_IPI_mask_allbutself = x2apic_send_IPI_mask_allbutself, | |
212 | .send_IPI_allbutself = x2apic_send_IPI_allbutself, | |
213 | .send_IPI_all = x2apic_send_IPI_all, | |
214 | .send_IPI_self = x2apic_send_IPI_self, | |
215 | ||
216 | .wakeup_cpu = NULL, | |
217 | .trampoline_phys_low = 0, | |
218 | .trampoline_phys_high = 0, | |
219 | .wait_for_init_deassert = NULL, | |
220 | .smp_callin_clear_local_apic = NULL, | |
221 | .store_NMI_vector = NULL, | |
222 | .restore_NMI_vector = NULL, | |
223 | .inquire_remote_apic = NULL, | |
2d9579a1 | 224 | }; |