[linux-2.6-block.git] / arch / x86 / kernel / genx2apic_phys.c

#include <linux/threads.h>
#include <linux/cpumask.h>
#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/ctype.h>
#include <linux/init.h>
#include <linux/dmar.h>

#include <asm/smp.h>
#include <asm/ipi.h>
#include <asm/genapic.h>

static int x2apic_phys;

static int set_x2apic_phys_mode(char *arg)
{
	x2apic_phys = 1;
	return 0;
}
early_param("x2apic_phys", set_x2apic_phys_mode);

static int __init x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
{
	if (cpu_has_x2apic && intr_remapping_enabled && x2apic_phys)
		return 1;

	return 0;
}

/* Start with all IRQs pointing to boot CPU.  IRQ balancing will shift them. */

static cpumask_t x2apic_target_cpus(void)
{
	return cpumask_of_cpu(0);
}

static cpumask_t x2apic_vector_allocation_domain(int cpu)
{
	cpumask_t domain = CPU_MASK_NONE;
	cpu_set(cpu, domain);
	return domain;
}

static void __x2apic_send_IPI_dest(unsigned int apicid, int vector,
				   unsigned int dest)
{
	unsigned long cfg;

	cfg = __prepare_ICR(0, vector, dest);

	/*
	 * send the IPI.
	 */
	x2apic_icr_write(cfg, apicid);
}

static void x2apic_send_IPI_mask(cpumask_t mask, int vector)
{
	unsigned long flags;
	unsigned long query_cpu;

	local_irq_save(flags);
	for_each_cpu_mask(query_cpu, mask) {
		__x2apic_send_IPI_dest(per_cpu(x86_cpu_to_apicid, query_cpu),
				       vector, APIC_DEST_PHYSICAL);
	}
	local_irq_restore(flags);
}

static void x2apic_send_IPI_allbutself(int vector)
{
	cpumask_t mask = cpu_online_map;

	cpu_clear(smp_processor_id(), mask);

	if (!cpus_empty(mask))
		x2apic_send_IPI_mask(mask, vector);
}

static void x2apic_send_IPI_all(int vector)
{
	x2apic_send_IPI_mask(cpu_online_map, vector);
}

static int x2apic_apic_id_registered(void)
{
	return 1;
}

static unsigned int x2apic_cpu_mask_to_apicid(cpumask_t cpumask)
{
	int cpu;

	/*
	 * We're using fixed IRQ delivery, can only return one phys APIC ID.
	 * May as well be the first.
	 */
	cpu = first_cpu(cpumask);
	if ((unsigned)cpu < NR_CPUS)
		return per_cpu(x86_cpu_to_apicid, cpu);
	else
		return BAD_APICID;
}

static unsigned int get_apic_id(unsigned long x)
{
	unsigned int id;

	id = x;
	return id;
}

static unsigned long set_apic_id(unsigned int id)
{
	unsigned long x;

	x = id;
	return x;
}

static unsigned int x2apic_read_id(void)
{
	return apic_read(APIC_ID);
}

static unsigned int phys_pkg_id(int index_msb)
{
	return x2apic_read_id() >> index_msb;
}

void x2apic_send_IPI_self(int vector)
{
	apic_write(APIC_SELF_IPI, vector);
}

void init_x2apic_ldr(void)
{
	return;
}

struct genapic apic_x2apic_phys = {
	.name = "physical x2apic",
	.acpi_madt_oem_check = x2apic_acpi_madt_oem_check,
	.int_delivery_mode = dest_Fixed,
	.int_dest_mode = (APIC_DEST_PHYSICAL != 0),
	.target_cpus = x2apic_target_cpus,
	.vector_allocation_domain = x2apic_vector_allocation_domain,
	.apic_id_registered = x2apic_apic_id_registered,
	.init_apic_ldr = init_x2apic_ldr,
	.send_IPI_all = x2apic_send_IPI_all,
	.send_IPI_allbutself = x2apic_send_IPI_allbutself,
	.send_IPI_mask = x2apic_send_IPI_mask,
	.send_IPI_self = x2apic_send_IPI_self,
	.cpu_mask_to_apicid = x2apic_cpu_mask_to_apicid,
	.phys_pkg_id = phys_pkg_id,
	.get_apic_id = get_apic_id,
	.set_apic_id = set_apic_id,
	.apic_id_mask = (0xFFFFFFFFu),
};
Commit	Line	Data
2d9579a1 SS	1	#include <linux/threads.h>
	2	#include <linux/cpumask.h>
	3	#include <linux/string.h>
	4	#include <linux/kernel.h>
	5	#include <linux/ctype.h>
	6	#include <linux/init.h>
1b9b89e7 YL	7	#include <linux/dmar.h>
1b9b89e7 YL	8
2d9579a1 SS	9	#include <asm/smp.h>
	10	#include <asm/ipi.h>
	11	#include <asm/genapic.h>
	12
1b9b89e7 YL	13	static int x2apic_phys;
	14
	15	static int set_x2apic_phys_mode(char *arg)
	16	{
	17	x2apic_phys = 1;
	18	return 0;
	19	}
	20	early_param("x2apic_phys", set_x2apic_phys_mode);
	21
	22	static int __init x2apic_acpi_madt_oem_check(char oem_id, char oem_table_id)
	23	{
	24	if (cpu_has_x2apic && intr_remapping_enabled && x2apic_phys)
	25	return 1;
	26
	27	return 0;
	28	}
2d9579a1 SS	29
	30	/* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */
	31
	32	static cpumask_t x2apic_target_cpus(void)
	33	{
	34	return cpumask_of_cpu(0);
	35	}
	36
	37	static cpumask_t x2apic_vector_allocation_domain(int cpu)
	38	{
	39	cpumask_t domain = CPU_MASK_NONE;
	40	cpu_set(cpu, domain);
	41	return domain;
	42	}
	43
	44	static void __x2apic_send_IPI_dest(unsigned int apicid, int vector,
	45	unsigned int dest)
	46	{
	47	unsigned long cfg;
	48
	49	cfg = __prepare_ICR(0, vector, dest);
	50
	51	/*
	52	* send the IPI.
	53	*/
	54	x2apic_icr_write(cfg, apicid);
	55	}
	56
	57	static void x2apic_send_IPI_mask(cpumask_t mask, int vector)
	58	{
	59	unsigned long flags;
	60	unsigned long query_cpu;
	61
	62	local_irq_save(flags);
	63	for_each_cpu_mask(query_cpu, mask) {
	64	__x2apic_send_IPI_dest(per_cpu(x86_cpu_to_apicid, query_cpu),
	65	vector, APIC_DEST_PHYSICAL);
	66	}
	67	local_irq_restore(flags);
	68	}
	69
	70	static void x2apic_send_IPI_allbutself(int vector)
	71	{
	72	cpumask_t mask = cpu_online_map;
	73
	74	cpu_clear(smp_processor_id(), mask);
	75
	76	if (!cpus_empty(mask))
	77	x2apic_send_IPI_mask(mask, vector);
	78	}
	79
	80	static void x2apic_send_IPI_all(int vector)
	81	{
	82	x2apic_send_IPI_mask(cpu_online_map, vector);
	83	}
	84
	85	static int x2apic_apic_id_registered(void)
	86	{
	87	return 1;
	88	}
	89
	90	static unsigned int x2apic_cpu_mask_to_apicid(cpumask_t cpumask)
	91	{
	92	int cpu;
93
94	/*
95	* We're using fixed IRQ delivery, can only return one phys APIC ID.
96	* May as well be the first.
97	*/
98	cpu = first_cpu(cpumask);
99	if ((unsigned)cpu < NR_CPUS)
100	return per_cpu(x86_cpu_to_apicid, cpu);
101	else
102	return BAD_APICID;
103	}
104
f910a9dc YL	105	static unsigned int get_apic_id(unsigned long x)
	106	{
	107	unsigned int id;
	108
	109	id = x;
	110	return id;
	111	}
	112
	113	static unsigned long set_apic_id(unsigned int id)
	114	{
	115	unsigned long x;
	116
	117	x = id;
	118	return x;
	119	}
	120
2d9579a1 SS	121	static unsigned int x2apic_read_id(void)
	122	{
	123	return apic_read(APIC_ID);
	124	}
	125
	126	static unsigned int phys_pkg_id(int index_msb)
	127	{
	128	return x2apic_read_id() >> index_msb;
	129	}
	130
	131	void x2apic_send_IPI_self(int vector)
	132	{
	133	apic_write(APIC_SELF_IPI, vector);
	134	}
	135
	136	void init_x2apic_ldr(void)
	137	{
	138	return;
	139	}
	140
	141	struct genapic apic_x2apic_phys = {
	142	.name = "physical x2apic",
1b9b89e7	143	.acpi_madt_oem_check = x2apic_acpi_madt_oem_check,
2d9579a1 SS	144	.int_delivery_mode = dest_Fixed,
	145	.int_dest_mode = (APIC_DEST_PHYSICAL != 0),
	146	.target_cpus = x2apic_target_cpus,
	147	.vector_allocation_domain = x2apic_vector_allocation_domain,
	148	.apic_id_registered = x2apic_apic_id_registered,
	149	.init_apic_ldr = init_x2apic_ldr,
	150	.send_IPI_all = x2apic_send_IPI_all,
	151	.send_IPI_allbutself = x2apic_send_IPI_allbutself,
	152	.send_IPI_mask = x2apic_send_IPI_mask,
	153	.send_IPI_self = x2apic_send_IPI_self,
	154	.cpu_mask_to_apicid = x2apic_cpu_mask_to_apicid,
	155	.phys_pkg_id = phys_pkg_id,
f910a9dc YL	156	.get_apic_id = get_apic_id,
	157	.set_apic_id = set_apic_id,
	158	.apic_id_mask = (0xFFFFFFFFu),
2d9579a1	159	};