Commit | Line | Data |
---|---|---|
2decb194 | 1 | /* |
3f79410c | 2 | * Routines to identify additional cpu features that are scattered in |
2decb194 PA |
3 | * cpuid space. |
4 | */ | |
5 | #include <linux/cpu.h> | |
6 | ||
eb243d1d | 7 | #include <asm/memtype.h> |
ad3bc25a | 8 | #include <asm/apic.h> |
2decb194 PA |
9 | #include <asm/processor.h> |
10 | ||
ad3bc25a | 11 | #include "cpu.h" |
2decb194 PA |
12 | |
13 | struct cpuid_bit { | |
14 | u16 feature; | |
15 | u8 reg; | |
16 | u8 bit; | |
17 | u32 level; | |
18 | u32 sub_leaf; | |
19 | }; | |
20 | ||
9f72f855 SH |
21 | /* |
22 | * Please keep the leaf sorted by cpuid_bit.level for faster search. | |
23 | * X86_FEATURE_MBA is supported by both Intel and AMD. But the CPUID | |
24 | * levels are different and there is a separate entry for each. | |
25 | */ | |
47bdf337 HC |
26 | static const struct cpuid_bit cpuid_bits[] = { |
27 | { X86_FEATURE_APERFMPERF, CPUID_ECX, 0, 0x00000006, 0 }, | |
7ce7f35b | 28 | { X86_FEATURE_EPB, CPUID_ECX, 3, 0x00000006, 0 }, |
00a2f23e | 29 | { X86_FEATURE_INTEL_PPIN, CPUID_EBX, 0, 0x00000007, 1 }, |
acec0ce0 FY |
30 | { X86_FEATURE_CQM_LLC, CPUID_EDX, 1, 0x0000000f, 0 }, |
31 | { X86_FEATURE_CQM_OCCUP_LLC, CPUID_EDX, 0, 0x0000000f, 1 }, | |
32 | { X86_FEATURE_CQM_MBM_TOTAL, CPUID_EDX, 1, 0x0000000f, 1 }, | |
33 | { X86_FEATURE_CQM_MBM_LOCAL, CPUID_EDX, 2, 0x0000000f, 1 }, | |
7ce7f35b TG |
34 | { X86_FEATURE_CAT_L3, CPUID_EBX, 1, 0x00000010, 0 }, |
35 | { X86_FEATURE_CAT_L2, CPUID_EBX, 2, 0x00000010, 0 }, | |
36 | { X86_FEATURE_CDP_L3, CPUID_ECX, 2, 0x00000010, 1 }, | |
a511e793 | 37 | { X86_FEATURE_CDP_L2, CPUID_ECX, 2, 0x00000010, 2 }, |
ab66a33b | 38 | { X86_FEATURE_MBA, CPUID_EBX, 3, 0x00000010, 0 }, |
e48cb1a3 | 39 | { X86_FEATURE_PER_THREAD_MBA, CPUID_ECX, 0, 0x00000010, 3 }, |
b8921dcc SC |
40 | { X86_FEATURE_SGX1, CPUID_EAX, 0, 0x00000012, 0 }, |
41 | { X86_FEATURE_SGX2, CPUID_EAX, 1, 0x00000012, 0 }, | |
7ce7f35b TG |
42 | { X86_FEATURE_HW_PSTATE, CPUID_EDX, 7, 0x80000007, 0 }, |
43 | { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 }, | |
47bdf337 | 44 | { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, |
9f72f855 | 45 | { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, |
d6d0c7f6 | 46 | { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, |
47bdf337 | 47 | { 0, 0, 0, 0, 0 } |
2decb194 PA |
48 | }; |
49 | ||
148f9bb8 | 50 | void init_scattered_cpuid_features(struct cpuinfo_x86 *c) |
2decb194 PA |
51 | { |
52 | u32 max_level; | |
53 | u32 regs[4]; | |
54 | const struct cpuid_bit *cb; | |
55 | ||
2decb194 PA |
56 | for (cb = cpuid_bits; cb->feature; cb++) { |
57 | ||
58 | /* Verify that the level is valid */ | |
59 | max_level = cpuid_eax(cb->level & 0xffff0000); | |
60 | if (max_level < cb->level || | |
61 | max_level > (cb->level | 0xffff)) | |
62 | continue; | |
63 | ||
47f10a36 HC |
64 | cpuid_count(cb->level, cb->sub_leaf, ®s[CPUID_EAX], |
65 | ®s[CPUID_EBX], ®s[CPUID_ECX], | |
66 | ®s[CPUID_EDX]); | |
2decb194 PA |
67 | |
68 | if (regs[cb->reg] & (1 << cb->bit)) | |
69 | set_cpu_cap(c, cb->feature); | |
70 | } | |
71 | } |