Commit | Line | Data |
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de0428a7 KW |
1 | #include <linux/perf_event.h> |
2 | #include <linux/types.h> | |
3 | ||
4 | #include <asm/perf_event.h> | |
5 | #include <asm/msr.h> | |
3e702ff6 | 6 | #include <asm/insn.h> |
de0428a7 KW |
7 | |
8 | #include "perf_event.h" | |
caff2bef PZ |
9 | |
10 | enum { | |
11 | LBR_FORMAT_32 = 0x00, | |
12 | LBR_FORMAT_LIP = 0x01, | |
13 | LBR_FORMAT_EIP = 0x02, | |
14 | LBR_FORMAT_EIP_FLAGS = 0x03, | |
135c5612 | 15 | LBR_FORMAT_EIP_FLAGS2 = 0x04, |
50eab8f6 AK |
16 | LBR_FORMAT_INFO = 0x05, |
17 | LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_INFO, | |
135c5612 AK |
18 | }; |
19 | ||
20 | static enum { | |
21 | LBR_EIP_FLAGS = 1, | |
22 | LBR_TSX = 2, | |
23 | } lbr_desc[LBR_FORMAT_MAX_KNOWN + 1] = { | |
24 | [LBR_FORMAT_EIP_FLAGS] = LBR_EIP_FLAGS, | |
25 | [LBR_FORMAT_EIP_FLAGS2] = LBR_EIP_FLAGS | LBR_TSX, | |
caff2bef PZ |
26 | }; |
27 | ||
c5cc2cd9 SE |
28 | /* |
29 | * Intel LBR_SELECT bits | |
30 | * Intel Vol3a, April 2011, Section 16.7 Table 16-10 | |
31 | * | |
32 | * Hardware branch filter (not available on all CPUs) | |
33 | */ | |
34 | #define LBR_KERNEL_BIT 0 /* do not capture at ring0 */ | |
35 | #define LBR_USER_BIT 1 /* do not capture at ring > 0 */ | |
36 | #define LBR_JCC_BIT 2 /* do not capture conditional branches */ | |
37 | #define LBR_REL_CALL_BIT 3 /* do not capture relative calls */ | |
38 | #define LBR_IND_CALL_BIT 4 /* do not capture indirect calls */ | |
39 | #define LBR_RETURN_BIT 5 /* do not capture near returns */ | |
40 | #define LBR_IND_JMP_BIT 6 /* do not capture indirect jumps */ | |
41 | #define LBR_REL_JMP_BIT 7 /* do not capture relative jumps */ | |
42 | #define LBR_FAR_BIT 8 /* do not capture far branches */ | |
e9d7f7cd | 43 | #define LBR_CALL_STACK_BIT 9 /* enable call stack */ |
c5cc2cd9 SE |
44 | |
45 | #define LBR_KERNEL (1 << LBR_KERNEL_BIT) | |
46 | #define LBR_USER (1 << LBR_USER_BIT) | |
47 | #define LBR_JCC (1 << LBR_JCC_BIT) | |
48 | #define LBR_REL_CALL (1 << LBR_REL_CALL_BIT) | |
49 | #define LBR_IND_CALL (1 << LBR_IND_CALL_BIT) | |
50 | #define LBR_RETURN (1 << LBR_RETURN_BIT) | |
51 | #define LBR_REL_JMP (1 << LBR_REL_JMP_BIT) | |
52 | #define LBR_IND_JMP (1 << LBR_IND_JMP_BIT) | |
53 | #define LBR_FAR (1 << LBR_FAR_BIT) | |
e9d7f7cd | 54 | #define LBR_CALL_STACK (1 << LBR_CALL_STACK_BIT) |
c5cc2cd9 SE |
55 | |
56 | #define LBR_PLM (LBR_KERNEL | LBR_USER) | |
57 | ||
58 | #define LBR_SEL_MASK 0x1ff /* valid bits in LBR_SELECT */ | |
59 | #define LBR_NOT_SUPP -1 /* LBR filter not supported */ | |
60 | #define LBR_IGN 0 /* ignored */ | |
61 | ||
62 | #define LBR_ANY \ | |
63 | (LBR_JCC |\ | |
64 | LBR_REL_CALL |\ | |
65 | LBR_IND_CALL |\ | |
66 | LBR_RETURN |\ | |
67 | LBR_REL_JMP |\ | |
68 | LBR_IND_JMP |\ | |
69 | LBR_FAR) | |
70 | ||
71 | #define LBR_FROM_FLAG_MISPRED (1ULL << 63) | |
135c5612 AK |
72 | #define LBR_FROM_FLAG_IN_TX (1ULL << 62) |
73 | #define LBR_FROM_FLAG_ABORT (1ULL << 61) | |
c5cc2cd9 | 74 | |
3e702ff6 SE |
75 | /* |
76 | * x86control flow change classification | |
77 | * x86control flow changes include branches, interrupts, traps, faults | |
78 | */ | |
79 | enum { | |
e9d7f7cd YZ |
80 | X86_BR_NONE = 0, /* unknown */ |
81 | ||
82 | X86_BR_USER = 1 << 0, /* branch target is user */ | |
83 | X86_BR_KERNEL = 1 << 1, /* branch target is kernel */ | |
84 | ||
85 | X86_BR_CALL = 1 << 2, /* call */ | |
86 | X86_BR_RET = 1 << 3, /* return */ | |
87 | X86_BR_SYSCALL = 1 << 4, /* syscall */ | |
88 | X86_BR_SYSRET = 1 << 5, /* syscall return */ | |
89 | X86_BR_INT = 1 << 6, /* sw interrupt */ | |
90 | X86_BR_IRET = 1 << 7, /* return from interrupt */ | |
91 | X86_BR_JCC = 1 << 8, /* conditional */ | |
92 | X86_BR_JMP = 1 << 9, /* jump */ | |
93 | X86_BR_IRQ = 1 << 10,/* hw interrupt or trap or fault */ | |
94 | X86_BR_IND_CALL = 1 << 11,/* indirect calls */ | |
95 | X86_BR_ABORT = 1 << 12,/* transaction abort */ | |
96 | X86_BR_IN_TX = 1 << 13,/* in transaction */ | |
97 | X86_BR_NO_TX = 1 << 14,/* not in transaction */ | |
aa54ae9b YZ |
98 | X86_BR_ZERO_CALL = 1 << 15,/* zero length call */ |
99 | X86_BR_CALL_STACK = 1 << 16,/* call stack */ | |
7b74cfb2 | 100 | X86_BR_IND_JMP = 1 << 17,/* indirect jump */ |
3e702ff6 SE |
101 | }; |
102 | ||
103 | #define X86_BR_PLM (X86_BR_USER | X86_BR_KERNEL) | |
135c5612 | 104 | #define X86_BR_ANYTX (X86_BR_NO_TX | X86_BR_IN_TX) |
3e702ff6 SE |
105 | |
106 | #define X86_BR_ANY \ | |
107 | (X86_BR_CALL |\ | |
108 | X86_BR_RET |\ | |
109 | X86_BR_SYSCALL |\ | |
110 | X86_BR_SYSRET |\ | |
111 | X86_BR_INT |\ | |
112 | X86_BR_IRET |\ | |
113 | X86_BR_JCC |\ | |
114 | X86_BR_JMP |\ | |
115 | X86_BR_IRQ |\ | |
135c5612 | 116 | X86_BR_ABORT |\ |
aa54ae9b | 117 | X86_BR_IND_CALL |\ |
7b74cfb2 | 118 | X86_BR_IND_JMP |\ |
aa54ae9b | 119 | X86_BR_ZERO_CALL) |
3e702ff6 SE |
120 | |
121 | #define X86_BR_ALL (X86_BR_PLM | X86_BR_ANY) | |
122 | ||
123 | #define X86_BR_ANY_CALL \ | |
124 | (X86_BR_CALL |\ | |
125 | X86_BR_IND_CALL |\ | |
aa54ae9b | 126 | X86_BR_ZERO_CALL |\ |
3e702ff6 SE |
127 | X86_BR_SYSCALL |\ |
128 | X86_BR_IRQ |\ | |
129 | X86_BR_INT) | |
130 | ||
131 | static void intel_pmu_lbr_filter(struct cpu_hw_events *cpuc); | |
132 | ||
caff2bef PZ |
133 | /* |
134 | * We only support LBR implementations that have FREEZE_LBRS_ON_PMI | |
135 | * otherwise it becomes near impossible to get a reliable stack. | |
136 | */ | |
137 | ||
1a78d937 | 138 | static void __intel_pmu_lbr_enable(bool pmi) |
caff2bef | 139 | { |
89cbc767 | 140 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
cd1f11de | 141 | u64 debugctl, lbr_select = 0, orig_debugctl; |
60ce0fbd | 142 | |
425507fa AK |
143 | /* |
144 | * No need to unfreeze manually, as v4 can do that as part | |
145 | * of the GLOBAL_STATUS ack. | |
146 | */ | |
147 | if (pmi && x86_pmu.version >= 4) | |
148 | return; | |
149 | ||
1a78d937 AK |
150 | /* |
151 | * No need to reprogram LBR_SELECT in a PMI, as it | |
152 | * did not change. | |
153 | */ | |
154 | if (cpuc->lbr_sel && !pmi) { | |
2c70d008 YZ |
155 | lbr_select = cpuc->lbr_sel->config; |
156 | wrmsrl(MSR_LBR_SELECT, lbr_select); | |
157 | } | |
caff2bef PZ |
158 | |
159 | rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); | |
cd1f11de | 160 | orig_debugctl = debugctl; |
2c70d008 YZ |
161 | debugctl |= DEBUGCTLMSR_LBR; |
162 | /* | |
163 | * LBR callstack does not work well with FREEZE_LBRS_ON_PMI. | |
164 | * If FREEZE_LBRS_ON_PMI is set, PMI near call/return instructions | |
165 | * may cause superfluous increase/decrease of LBR_TOS. | |
166 | */ | |
167 | if (!(lbr_select & LBR_CALL_STACK)) | |
168 | debugctl |= DEBUGCTLMSR_FREEZE_LBRS_ON_PMI; | |
cd1f11de AK |
169 | if (orig_debugctl != debugctl) |
170 | wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); | |
caff2bef PZ |
171 | } |
172 | ||
173 | static void __intel_pmu_lbr_disable(void) | |
174 | { | |
175 | u64 debugctl; | |
176 | ||
177 | rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); | |
7c5ecaf7 | 178 | debugctl &= ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI); |
caff2bef PZ |
179 | wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); |
180 | } | |
181 | ||
182 | static void intel_pmu_lbr_reset_32(void) | |
183 | { | |
184 | int i; | |
185 | ||
186 | for (i = 0; i < x86_pmu.lbr_nr; i++) | |
187 | wrmsrl(x86_pmu.lbr_from + i, 0); | |
188 | } | |
189 | ||
190 | static void intel_pmu_lbr_reset_64(void) | |
191 | { | |
192 | int i; | |
193 | ||
194 | for (i = 0; i < x86_pmu.lbr_nr; i++) { | |
195 | wrmsrl(x86_pmu.lbr_from + i, 0); | |
196 | wrmsrl(x86_pmu.lbr_to + i, 0); | |
50eab8f6 AK |
197 | if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO) |
198 | wrmsrl(MSR_LBR_INFO_0 + i, 0); | |
caff2bef PZ |
199 | } |
200 | } | |
201 | ||
de0428a7 | 202 | void intel_pmu_lbr_reset(void) |
caff2bef | 203 | { |
74846d35 PZ |
204 | if (!x86_pmu.lbr_nr) |
205 | return; | |
206 | ||
8db909a7 | 207 | if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) |
caff2bef PZ |
208 | intel_pmu_lbr_reset_32(); |
209 | else | |
210 | intel_pmu_lbr_reset_64(); | |
211 | } | |
212 | ||
76cb2c61 YZ |
213 | /* |
214 | * TOS = most recently recorded branch | |
215 | */ | |
216 | static inline u64 intel_pmu_lbr_tos(void) | |
217 | { | |
218 | u64 tos; | |
219 | ||
220 | rdmsrl(x86_pmu.lbr_tos, tos); | |
221 | return tos; | |
222 | } | |
223 | ||
224 | enum { | |
225 | LBR_NONE, | |
226 | LBR_VALID, | |
227 | }; | |
228 | ||
229 | static void __intel_pmu_lbr_restore(struct x86_perf_task_context *task_ctx) | |
230 | { | |
231 | int i; | |
232 | unsigned lbr_idx, mask; | |
233 | u64 tos; | |
234 | ||
235 | if (task_ctx->lbr_callstack_users == 0 || | |
236 | task_ctx->lbr_stack_state == LBR_NONE) { | |
237 | intel_pmu_lbr_reset(); | |
238 | return; | |
239 | } | |
240 | ||
241 | mask = x86_pmu.lbr_nr - 1; | |
242 | tos = intel_pmu_lbr_tos(); | |
243 | for (i = 0; i < x86_pmu.lbr_nr; i++) { | |
244 | lbr_idx = (tos - i) & mask; | |
245 | wrmsrl(x86_pmu.lbr_from + lbr_idx, task_ctx->lbr_from[i]); | |
246 | wrmsrl(x86_pmu.lbr_to + lbr_idx, task_ctx->lbr_to[i]); | |
50eab8f6 AK |
247 | if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO) |
248 | wrmsrl(MSR_LBR_INFO_0 + i, task_ctx->lbr_info[i]); | |
76cb2c61 YZ |
249 | } |
250 | task_ctx->lbr_stack_state = LBR_NONE; | |
251 | } | |
252 | ||
253 | static void __intel_pmu_lbr_save(struct x86_perf_task_context *task_ctx) | |
254 | { | |
255 | int i; | |
256 | unsigned lbr_idx, mask; | |
257 | u64 tos; | |
258 | ||
259 | if (task_ctx->lbr_callstack_users == 0) { | |
260 | task_ctx->lbr_stack_state = LBR_NONE; | |
261 | return; | |
262 | } | |
263 | ||
264 | mask = x86_pmu.lbr_nr - 1; | |
265 | tos = intel_pmu_lbr_tos(); | |
266 | for (i = 0; i < x86_pmu.lbr_nr; i++) { | |
267 | lbr_idx = (tos - i) & mask; | |
268 | rdmsrl(x86_pmu.lbr_from + lbr_idx, task_ctx->lbr_from[i]); | |
269 | rdmsrl(x86_pmu.lbr_to + lbr_idx, task_ctx->lbr_to[i]); | |
50eab8f6 AK |
270 | if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO) |
271 | rdmsrl(MSR_LBR_INFO_0 + i, task_ctx->lbr_info[i]); | |
76cb2c61 YZ |
272 | } |
273 | task_ctx->lbr_stack_state = LBR_VALID; | |
274 | } | |
275 | ||
2a0ad3b3 YZ |
276 | void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in) |
277 | { | |
278 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); | |
76cb2c61 | 279 | struct x86_perf_task_context *task_ctx; |
2a0ad3b3 | 280 | |
76cb2c61 YZ |
281 | /* |
282 | * If LBR callstack feature is enabled and the stack was saved when | |
283 | * the task was scheduled out, restore the stack. Otherwise flush | |
284 | * the LBR stack. | |
285 | */ | |
286 | task_ctx = ctx ? ctx->task_ctx_data : NULL; | |
287 | if (task_ctx) { | |
288 | if (sched_in) { | |
289 | __intel_pmu_lbr_restore(task_ctx); | |
290 | cpuc->lbr_context = ctx; | |
291 | } else { | |
292 | __intel_pmu_lbr_save(task_ctx); | |
293 | } | |
294 | return; | |
295 | } | |
296 | ||
2a0ad3b3 YZ |
297 | /* |
298 | * When sampling the branck stack in system-wide, it may be | |
299 | * necessary to flush the stack on context switch. This happens | |
300 | * when the branch stack does not tag its entries with the pid | |
301 | * of the current task. Otherwise it becomes impossible to | |
302 | * associate a branch entry with a task. This ambiguity is more | |
303 | * likely to appear when the branch stack supports priv level | |
304 | * filtering and the user sets it to monitor only at the user | |
305 | * level (which could be a useful measurement in system-wide | |
306 | * mode). In that case, the risk is high of having a branch | |
307 | * stack with branch from multiple tasks. | |
308 | */ | |
309 | if (sched_in) { | |
310 | intel_pmu_lbr_reset(); | |
311 | cpuc->lbr_context = ctx; | |
312 | } | |
313 | } | |
314 | ||
63f0c1d8 YZ |
315 | static inline bool branch_user_callstack(unsigned br_sel) |
316 | { | |
317 | return (br_sel & X86_BR_USER) && (br_sel & X86_BR_CALL_STACK); | |
318 | } | |
319 | ||
de0428a7 | 320 | void intel_pmu_lbr_enable(struct perf_event *event) |
caff2bef | 321 | { |
89cbc767 | 322 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
63f0c1d8 | 323 | struct x86_perf_task_context *task_ctx; |
caff2bef PZ |
324 | |
325 | if (!x86_pmu.lbr_nr) | |
326 | return; | |
327 | ||
caff2bef | 328 | /* |
b83a46e7 PZ |
329 | * Reset the LBR stack if we changed task context to |
330 | * avoid data leaks. | |
caff2bef | 331 | */ |
b83a46e7 | 332 | if (event->ctx->task && cpuc->lbr_context != event->ctx) { |
caff2bef PZ |
333 | intel_pmu_lbr_reset(); |
334 | cpuc->lbr_context = event->ctx; | |
335 | } | |
3e702ff6 | 336 | cpuc->br_sel = event->hw.branch_reg.reg; |
caff2bef | 337 | |
63f0c1d8 YZ |
338 | if (branch_user_callstack(cpuc->br_sel) && event->ctx && |
339 | event->ctx->task_ctx_data) { | |
340 | task_ctx = event->ctx->task_ctx_data; | |
341 | task_ctx->lbr_callstack_users++; | |
342 | } | |
343 | ||
caff2bef | 344 | cpuc->lbr_users++; |
2a0ad3b3 | 345 | perf_sched_cb_inc(event->ctx->pmu); |
caff2bef PZ |
346 | } |
347 | ||
de0428a7 | 348 | void intel_pmu_lbr_disable(struct perf_event *event) |
caff2bef | 349 | { |
89cbc767 | 350 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
63f0c1d8 | 351 | struct x86_perf_task_context *task_ctx; |
caff2bef PZ |
352 | |
353 | if (!x86_pmu.lbr_nr) | |
354 | return; | |
355 | ||
63f0c1d8 YZ |
356 | if (branch_user_callstack(cpuc->br_sel) && event->ctx && |
357 | event->ctx->task_ctx_data) { | |
358 | task_ctx = event->ctx->task_ctx_data; | |
359 | task_ctx->lbr_callstack_users--; | |
360 | } | |
361 | ||
caff2bef | 362 | cpuc->lbr_users--; |
b83a46e7 | 363 | WARN_ON_ONCE(cpuc->lbr_users < 0); |
2a0ad3b3 | 364 | perf_sched_cb_dec(event->ctx->pmu); |
2df202bf | 365 | |
60ce0fbd | 366 | if (cpuc->enabled && !cpuc->lbr_users) { |
2df202bf | 367 | __intel_pmu_lbr_disable(); |
60ce0fbd SE |
368 | /* avoid stale pointer */ |
369 | cpuc->lbr_context = NULL; | |
370 | } | |
caff2bef PZ |
371 | } |
372 | ||
1a78d937 | 373 | void intel_pmu_lbr_enable_all(bool pmi) |
caff2bef | 374 | { |
89cbc767 | 375 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
caff2bef PZ |
376 | |
377 | if (cpuc->lbr_users) | |
1a78d937 | 378 | __intel_pmu_lbr_enable(pmi); |
caff2bef PZ |
379 | } |
380 | ||
de0428a7 | 381 | void intel_pmu_lbr_disable_all(void) |
caff2bef | 382 | { |
89cbc767 | 383 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
caff2bef PZ |
384 | |
385 | if (cpuc->lbr_users) | |
386 | __intel_pmu_lbr_disable(); | |
387 | } | |
388 | ||
caff2bef PZ |
389 | static void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc) |
390 | { | |
391 | unsigned long mask = x86_pmu.lbr_nr - 1; | |
392 | u64 tos = intel_pmu_lbr_tos(); | |
393 | int i; | |
394 | ||
63fb3f9b | 395 | for (i = 0; i < x86_pmu.lbr_nr; i++) { |
caff2bef PZ |
396 | unsigned long lbr_idx = (tos - i) & mask; |
397 | union { | |
398 | struct { | |
399 | u32 from; | |
400 | u32 to; | |
401 | }; | |
402 | u64 lbr; | |
403 | } msr_lastbranch; | |
404 | ||
405 | rdmsrl(x86_pmu.lbr_from + lbr_idx, msr_lastbranch.lbr); | |
406 | ||
bce38cd5 SE |
407 | cpuc->lbr_entries[i].from = msr_lastbranch.from; |
408 | cpuc->lbr_entries[i].to = msr_lastbranch.to; | |
409 | cpuc->lbr_entries[i].mispred = 0; | |
410 | cpuc->lbr_entries[i].predicted = 0; | |
411 | cpuc->lbr_entries[i].reserved = 0; | |
caff2bef PZ |
412 | } |
413 | cpuc->lbr_stack.nr = i; | |
414 | } | |
415 | ||
caff2bef PZ |
416 | /* |
417 | * Due to lack of segmentation in Linux the effective address (offset) | |
418 | * is the same as the linear address, allowing us to merge the LIP and EIP | |
419 | * LBR formats. | |
420 | */ | |
421 | static void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc) | |
422 | { | |
423 | unsigned long mask = x86_pmu.lbr_nr - 1; | |
8db909a7 | 424 | int lbr_format = x86_pmu.intel_cap.lbr_format; |
caff2bef PZ |
425 | u64 tos = intel_pmu_lbr_tos(); |
426 | int i; | |
b7af41a1 | 427 | int out = 0; |
caff2bef | 428 | |
63fb3f9b | 429 | for (i = 0; i < x86_pmu.lbr_nr; i++) { |
caff2bef | 430 | unsigned long lbr_idx = (tos - i) & mask; |
135c5612 AK |
431 | u64 from, to, mis = 0, pred = 0, in_tx = 0, abort = 0; |
432 | int skip = 0; | |
50eab8f6 | 433 | u16 cycles = 0; |
135c5612 | 434 | int lbr_flags = lbr_desc[lbr_format]; |
caff2bef PZ |
435 | |
436 | rdmsrl(x86_pmu.lbr_from + lbr_idx, from); | |
437 | rdmsrl(x86_pmu.lbr_to + lbr_idx, to); | |
438 | ||
50eab8f6 AK |
439 | if (lbr_format == LBR_FORMAT_INFO) { |
440 | u64 info; | |
441 | ||
442 | rdmsrl(MSR_LBR_INFO_0 + lbr_idx, info); | |
443 | mis = !!(info & LBR_INFO_MISPRED); | |
444 | pred = !mis; | |
445 | in_tx = !!(info & LBR_INFO_IN_TX); | |
446 | abort = !!(info & LBR_INFO_ABORT); | |
447 | cycles = (info & LBR_INFO_CYCLES); | |
448 | } | |
135c5612 | 449 | if (lbr_flags & LBR_EIP_FLAGS) { |
bce38cd5 SE |
450 | mis = !!(from & LBR_FROM_FLAG_MISPRED); |
451 | pred = !mis; | |
135c5612 AK |
452 | skip = 1; |
453 | } | |
454 | if (lbr_flags & LBR_TSX) { | |
455 | in_tx = !!(from & LBR_FROM_FLAG_IN_TX); | |
456 | abort = !!(from & LBR_FROM_FLAG_ABORT); | |
457 | skip = 3; | |
caff2bef | 458 | } |
135c5612 | 459 | from = (u64)((((s64)from) << skip) >> skip); |
caff2bef | 460 | |
b7af41a1 AK |
461 | /* |
462 | * Some CPUs report duplicated abort records, | |
463 | * with the second entry not having an abort bit set. | |
464 | * Skip them here. This loop runs backwards, | |
465 | * so we need to undo the previous record. | |
466 | * If the abort just happened outside the window | |
467 | * the extra entry cannot be removed. | |
468 | */ | |
469 | if (abort && x86_pmu.lbr_double_abort && out > 0) | |
470 | out--; | |
471 | ||
472 | cpuc->lbr_entries[out].from = from; | |
473 | cpuc->lbr_entries[out].to = to; | |
474 | cpuc->lbr_entries[out].mispred = mis; | |
475 | cpuc->lbr_entries[out].predicted = pred; | |
476 | cpuc->lbr_entries[out].in_tx = in_tx; | |
477 | cpuc->lbr_entries[out].abort = abort; | |
50eab8f6 | 478 | cpuc->lbr_entries[out].cycles = cycles; |
b7af41a1 AK |
479 | cpuc->lbr_entries[out].reserved = 0; |
480 | out++; | |
caff2bef | 481 | } |
b7af41a1 | 482 | cpuc->lbr_stack.nr = out; |
caff2bef PZ |
483 | } |
484 | ||
de0428a7 | 485 | void intel_pmu_lbr_read(void) |
caff2bef | 486 | { |
89cbc767 | 487 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
caff2bef PZ |
488 | |
489 | if (!cpuc->lbr_users) | |
490 | return; | |
491 | ||
8db909a7 | 492 | if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) |
caff2bef PZ |
493 | intel_pmu_lbr_read_32(cpuc); |
494 | else | |
495 | intel_pmu_lbr_read_64(cpuc); | |
3e702ff6 SE |
496 | |
497 | intel_pmu_lbr_filter(cpuc); | |
498 | } | |
499 | ||
500 | /* | |
501 | * SW filter is used: | |
502 | * - in case there is no HW filter | |
503 | * - in case the HW filter has errata or limitations | |
504 | */ | |
e9d7f7cd | 505 | static int intel_pmu_setup_sw_lbr_filter(struct perf_event *event) |
3e702ff6 SE |
506 | { |
507 | u64 br_type = event->attr.branch_sample_type; | |
508 | int mask = 0; | |
509 | ||
510 | if (br_type & PERF_SAMPLE_BRANCH_USER) | |
511 | mask |= X86_BR_USER; | |
512 | ||
2b923c8f | 513 | if (br_type & PERF_SAMPLE_BRANCH_KERNEL) |
3e702ff6 SE |
514 | mask |= X86_BR_KERNEL; |
515 | ||
516 | /* we ignore BRANCH_HV here */ | |
517 | ||
518 | if (br_type & PERF_SAMPLE_BRANCH_ANY) | |
519 | mask |= X86_BR_ANY; | |
520 | ||
521 | if (br_type & PERF_SAMPLE_BRANCH_ANY_CALL) | |
522 | mask |= X86_BR_ANY_CALL; | |
523 | ||
524 | if (br_type & PERF_SAMPLE_BRANCH_ANY_RETURN) | |
525 | mask |= X86_BR_RET | X86_BR_IRET | X86_BR_SYSRET; | |
526 | ||
527 | if (br_type & PERF_SAMPLE_BRANCH_IND_CALL) | |
528 | mask |= X86_BR_IND_CALL; | |
135c5612 AK |
529 | |
530 | if (br_type & PERF_SAMPLE_BRANCH_ABORT_TX) | |
531 | mask |= X86_BR_ABORT; | |
532 | ||
533 | if (br_type & PERF_SAMPLE_BRANCH_IN_TX) | |
534 | mask |= X86_BR_IN_TX; | |
535 | ||
536 | if (br_type & PERF_SAMPLE_BRANCH_NO_TX) | |
537 | mask |= X86_BR_NO_TX; | |
538 | ||
37548914 AK |
539 | if (br_type & PERF_SAMPLE_BRANCH_COND) |
540 | mask |= X86_BR_JCC; | |
541 | ||
e9d7f7cd YZ |
542 | if (br_type & PERF_SAMPLE_BRANCH_CALL_STACK) { |
543 | if (!x86_pmu_has_lbr_callstack()) | |
544 | return -EOPNOTSUPP; | |
545 | if (mask & ~(X86_BR_USER | X86_BR_KERNEL)) | |
546 | return -EINVAL; | |
547 | mask |= X86_BR_CALL | X86_BR_IND_CALL | X86_BR_RET | | |
548 | X86_BR_CALL_STACK; | |
549 | } | |
550 | ||
7b74cfb2 SE |
551 | if (br_type & PERF_SAMPLE_BRANCH_IND_JUMP) |
552 | mask |= X86_BR_IND_JMP; | |
553 | ||
3e702ff6 SE |
554 | /* |
555 | * stash actual user request into reg, it may | |
556 | * be used by fixup code for some CPU | |
557 | */ | |
558 | event->hw.branch_reg.reg = mask; | |
e9d7f7cd | 559 | return 0; |
caff2bef PZ |
560 | } |
561 | ||
60ce0fbd SE |
562 | /* |
563 | * setup the HW LBR filter | |
564 | * Used only when available, may not be enough to disambiguate | |
565 | * all branches, may need the help of the SW filter | |
566 | */ | |
567 | static int intel_pmu_setup_hw_lbr_filter(struct perf_event *event) | |
568 | { | |
569 | struct hw_perf_event_extra *reg; | |
570 | u64 br_type = event->attr.branch_sample_type; | |
27ac905b YZ |
571 | u64 mask = 0, v; |
572 | int i; | |
60ce0fbd | 573 | |
2c44b193 | 574 | for (i = 0; i < PERF_SAMPLE_BRANCH_MAX_SHIFT; i++) { |
27ac905b | 575 | if (!(br_type & (1ULL << i))) |
60ce0fbd SE |
576 | continue; |
577 | ||
27ac905b | 578 | v = x86_pmu.lbr_sel_map[i]; |
60ce0fbd SE |
579 | if (v == LBR_NOT_SUPP) |
580 | return -EOPNOTSUPP; | |
60ce0fbd | 581 | |
3e702ff6 SE |
582 | if (v != LBR_IGN) |
583 | mask |= v; | |
60ce0fbd SE |
584 | } |
585 | reg = &event->hw.branch_reg; | |
586 | reg->idx = EXTRA_REG_LBR; | |
587 | ||
e9d7f7cd YZ |
588 | /* |
589 | * The first 9 bits (LBR_SEL_MASK) in LBR_SELECT operate | |
590 | * in suppress mode. So LBR_SELECT should be set to | |
591 | * (~mask & LBR_SEL_MASK) | (mask & ~LBR_SEL_MASK) | |
592 | */ | |
593 | reg->config = mask ^ x86_pmu.lbr_sel_mask; | |
60ce0fbd SE |
594 | |
595 | return 0; | |
596 | } | |
597 | ||
60ce0fbd SE |
598 | int intel_pmu_setup_lbr_filter(struct perf_event *event) |
599 | { | |
3e702ff6 | 600 | int ret = 0; |
60ce0fbd SE |
601 | |
602 | /* | |
603 | * no LBR on this PMU | |
604 | */ | |
605 | if (!x86_pmu.lbr_nr) | |
606 | return -EOPNOTSUPP; | |
607 | ||
608 | /* | |
3e702ff6 | 609 | * setup SW LBR filter |
60ce0fbd | 610 | */ |
e9d7f7cd YZ |
611 | ret = intel_pmu_setup_sw_lbr_filter(event); |
612 | if (ret) | |
613 | return ret; | |
3e702ff6 SE |
614 | |
615 | /* | |
616 | * setup HW LBR filter, if any | |
617 | */ | |
618 | if (x86_pmu.lbr_sel_map) | |
619 | ret = intel_pmu_setup_hw_lbr_filter(event); | |
620 | ||
621 | return ret; | |
622 | } | |
623 | ||
624 | /* | |
625 | * return the type of control flow change at address "from" | |
626 | * intruction is not necessarily a branch (in case of interrupt). | |
627 | * | |
628 | * The branch type returned also includes the priv level of the | |
629 | * target of the control flow change (X86_BR_USER, X86_BR_KERNEL). | |
630 | * | |
631 | * If a branch type is unknown OR the instruction cannot be | |
632 | * decoded (e.g., text page not present), then X86_BR_NONE is | |
633 | * returned. | |
634 | */ | |
135c5612 | 635 | static int branch_type(unsigned long from, unsigned long to, int abort) |
3e702ff6 SE |
636 | { |
637 | struct insn insn; | |
638 | void *addr; | |
6ba48ff4 | 639 | int bytes_read, bytes_left; |
3e702ff6 SE |
640 | int ret = X86_BR_NONE; |
641 | int ext, to_plm, from_plm; | |
642 | u8 buf[MAX_INSN_SIZE]; | |
643 | int is64 = 0; | |
644 | ||
645 | to_plm = kernel_ip(to) ? X86_BR_KERNEL : X86_BR_USER; | |
646 | from_plm = kernel_ip(from) ? X86_BR_KERNEL : X86_BR_USER; | |
647 | ||
648 | /* | |
649 | * maybe zero if lbr did not fill up after a reset by the time | |
650 | * we get a PMU interrupt | |
651 | */ | |
652 | if (from == 0 || to == 0) | |
653 | return X86_BR_NONE; | |
654 | ||
135c5612 AK |
655 | if (abort) |
656 | return X86_BR_ABORT | to_plm; | |
657 | ||
3e702ff6 SE |
658 | if (from_plm == X86_BR_USER) { |
659 | /* | |
660 | * can happen if measuring at the user level only | |
661 | * and we interrupt in a kernel thread, e.g., idle. | |
662 | */ | |
663 | if (!current->mm) | |
664 | return X86_BR_NONE; | |
665 | ||
666 | /* may fail if text not present */ | |
6ba48ff4 DH |
667 | bytes_left = copy_from_user_nmi(buf, (void __user *)from, |
668 | MAX_INSN_SIZE); | |
669 | bytes_read = MAX_INSN_SIZE - bytes_left; | |
670 | if (!bytes_read) | |
3e702ff6 SE |
671 | return X86_BR_NONE; |
672 | ||
673 | addr = buf; | |
6e15eb3b PZ |
674 | } else { |
675 | /* | |
676 | * The LBR logs any address in the IP, even if the IP just | |
677 | * faulted. This means userspace can control the from address. | |
678 | * Ensure we don't blindy read any address by validating it is | |
679 | * a known text address. | |
680 | */ | |
6ba48ff4 | 681 | if (kernel_text_address(from)) { |
6e15eb3b | 682 | addr = (void *)from; |
6ba48ff4 DH |
683 | /* |
684 | * Assume we can get the maximum possible size | |
685 | * when grabbing kernel data. This is not | |
686 | * _strictly_ true since we could possibly be | |
687 | * executing up next to a memory hole, but | |
688 | * it is very unlikely to be a problem. | |
689 | */ | |
690 | bytes_read = MAX_INSN_SIZE; | |
691 | } else { | |
6e15eb3b | 692 | return X86_BR_NONE; |
6ba48ff4 | 693 | } |
6e15eb3b | 694 | } |
3e702ff6 SE |
695 | |
696 | /* | |
697 | * decoder needs to know the ABI especially | |
698 | * on 64-bit systems running 32-bit apps | |
699 | */ | |
700 | #ifdef CONFIG_X86_64 | |
701 | is64 = kernel_ip((unsigned long)addr) || !test_thread_flag(TIF_IA32); | |
702 | #endif | |
6ba48ff4 | 703 | insn_init(&insn, addr, bytes_read, is64); |
3e702ff6 | 704 | insn_get_opcode(&insn); |
6ba48ff4 DH |
705 | if (!insn.opcode.got) |
706 | return X86_BR_ABORT; | |
3e702ff6 SE |
707 | |
708 | switch (insn.opcode.bytes[0]) { | |
709 | case 0xf: | |
710 | switch (insn.opcode.bytes[1]) { | |
711 | case 0x05: /* syscall */ | |
712 | case 0x34: /* sysenter */ | |
713 | ret = X86_BR_SYSCALL; | |
714 | break; | |
715 | case 0x07: /* sysret */ | |
716 | case 0x35: /* sysexit */ | |
717 | ret = X86_BR_SYSRET; | |
718 | break; | |
719 | case 0x80 ... 0x8f: /* conditional */ | |
720 | ret = X86_BR_JCC; | |
721 | break; | |
722 | default: | |
723 | ret = X86_BR_NONE; | |
724 | } | |
725 | break; | |
726 | case 0x70 ... 0x7f: /* conditional */ | |
727 | ret = X86_BR_JCC; | |
728 | break; | |
729 | case 0xc2: /* near ret */ | |
730 | case 0xc3: /* near ret */ | |
731 | case 0xca: /* far ret */ | |
732 | case 0xcb: /* far ret */ | |
733 | ret = X86_BR_RET; | |
734 | break; | |
735 | case 0xcf: /* iret */ | |
736 | ret = X86_BR_IRET; | |
737 | break; | |
738 | case 0xcc ... 0xce: /* int */ | |
739 | ret = X86_BR_INT; | |
740 | break; | |
741 | case 0xe8: /* call near rel */ | |
aa54ae9b YZ |
742 | insn_get_immediate(&insn); |
743 | if (insn.immediate1.value == 0) { | |
744 | /* zero length call */ | |
745 | ret = X86_BR_ZERO_CALL; | |
746 | break; | |
747 | } | |
3e702ff6 SE |
748 | case 0x9a: /* call far absolute */ |
749 | ret = X86_BR_CALL; | |
750 | break; | |
751 | case 0xe0 ... 0xe3: /* loop jmp */ | |
752 | ret = X86_BR_JCC; | |
753 | break; | |
754 | case 0xe9 ... 0xeb: /* jmp */ | |
755 | ret = X86_BR_JMP; | |
756 | break; | |
757 | case 0xff: /* call near absolute, call far absolute ind */ | |
758 | insn_get_modrm(&insn); | |
759 | ext = (insn.modrm.bytes[0] >> 3) & 0x7; | |
760 | switch (ext) { | |
761 | case 2: /* near ind call */ | |
762 | case 3: /* far ind call */ | |
763 | ret = X86_BR_IND_CALL; | |
764 | break; | |
765 | case 4: | |
766 | case 5: | |
7b74cfb2 | 767 | ret = X86_BR_IND_JMP; |
3e702ff6 SE |
768 | break; |
769 | } | |
770 | break; | |
771 | default: | |
772 | ret = X86_BR_NONE; | |
60ce0fbd SE |
773 | } |
774 | /* | |
3e702ff6 SE |
775 | * interrupts, traps, faults (and thus ring transition) may |
776 | * occur on any instructions. Thus, to classify them correctly, | |
777 | * we need to first look at the from and to priv levels. If they | |
778 | * are different and to is in the kernel, then it indicates | |
779 | * a ring transition. If the from instruction is not a ring | |
780 | * transition instr (syscall, systenter, int), then it means | |
781 | * it was a irq, trap or fault. | |
782 | * | |
783 | * we have no way of detecting kernel to kernel faults. | |
784 | */ | |
785 | if (from_plm == X86_BR_USER && to_plm == X86_BR_KERNEL | |
786 | && ret != X86_BR_SYSCALL && ret != X86_BR_INT) | |
787 | ret = X86_BR_IRQ; | |
788 | ||
789 | /* | |
790 | * branch priv level determined by target as | |
791 | * is done by HW when LBR_SELECT is implemented | |
60ce0fbd | 792 | */ |
3e702ff6 SE |
793 | if (ret != X86_BR_NONE) |
794 | ret |= to_plm; | |
60ce0fbd | 795 | |
3e702ff6 SE |
796 | return ret; |
797 | } | |
798 | ||
799 | /* | |
800 | * implement actual branch filter based on user demand. | |
801 | * Hardware may not exactly satisfy that request, thus | |
802 | * we need to inspect opcodes. Mismatched branches are | |
803 | * discarded. Therefore, the number of branches returned | |
804 | * in PERF_SAMPLE_BRANCH_STACK sample may vary. | |
805 | */ | |
806 | static void | |
807 | intel_pmu_lbr_filter(struct cpu_hw_events *cpuc) | |
808 | { | |
809 | u64 from, to; | |
810 | int br_sel = cpuc->br_sel; | |
811 | int i, j, type; | |
812 | bool compress = false; | |
813 | ||
814 | /* if sampling all branches, then nothing to filter */ | |
815 | if ((br_sel & X86_BR_ALL) == X86_BR_ALL) | |
816 | return; | |
817 | ||
818 | for (i = 0; i < cpuc->lbr_stack.nr; i++) { | |
819 | ||
820 | from = cpuc->lbr_entries[i].from; | |
821 | to = cpuc->lbr_entries[i].to; | |
822 | ||
135c5612 AK |
823 | type = branch_type(from, to, cpuc->lbr_entries[i].abort); |
824 | if (type != X86_BR_NONE && (br_sel & X86_BR_ANYTX)) { | |
825 | if (cpuc->lbr_entries[i].in_tx) | |
826 | type |= X86_BR_IN_TX; | |
827 | else | |
828 | type |= X86_BR_NO_TX; | |
829 | } | |
3e702ff6 SE |
830 | |
831 | /* if type does not correspond, then discard */ | |
832 | if (type == X86_BR_NONE || (br_sel & type) != type) { | |
833 | cpuc->lbr_entries[i].from = 0; | |
834 | compress = true; | |
835 | } | |
836 | } | |
837 | ||
838 | if (!compress) | |
839 | return; | |
840 | ||
841 | /* remove all entries with from=0 */ | |
842 | for (i = 0; i < cpuc->lbr_stack.nr; ) { | |
843 | if (!cpuc->lbr_entries[i].from) { | |
844 | j = i; | |
845 | while (++j < cpuc->lbr_stack.nr) | |
846 | cpuc->lbr_entries[j-1] = cpuc->lbr_entries[j]; | |
847 | cpuc->lbr_stack.nr--; | |
848 | if (!cpuc->lbr_entries[i].from) | |
849 | continue; | |
850 | } | |
851 | i++; | |
852 | } | |
60ce0fbd SE |
853 | } |
854 | ||
c5cc2cd9 SE |
855 | /* |
856 | * Map interface branch filters onto LBR filters | |
857 | */ | |
2c44b193 | 858 | static const int nhm_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX_SHIFT] = { |
27ac905b YZ |
859 | [PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_ANY, |
860 | [PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_USER, | |
861 | [PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_KERNEL, | |
862 | [PERF_SAMPLE_BRANCH_HV_SHIFT] = LBR_IGN, | |
863 | [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT] = LBR_RETURN | LBR_REL_JMP | |
864 | | LBR_IND_JMP | LBR_FAR, | |
c5cc2cd9 SE |
865 | /* |
866 | * NHM/WSM erratum: must include REL_JMP+IND_JMP to get CALL branches | |
867 | */ | |
27ac905b | 868 | [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT] = |
c5cc2cd9 SE |
869 | LBR_REL_CALL | LBR_IND_CALL | LBR_REL_JMP | LBR_IND_JMP | LBR_FAR, |
870 | /* | |
871 | * NHM/WSM erratum: must include IND_JMP to capture IND_CALL | |
872 | */ | |
27ac905b YZ |
873 | [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = LBR_IND_CALL | LBR_IND_JMP, |
874 | [PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_JCC, | |
7b74cfb2 | 875 | [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT] = LBR_IND_JMP, |
c5cc2cd9 SE |
876 | }; |
877 | ||
2c44b193 | 878 | static const int snb_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX_SHIFT] = { |
27ac905b YZ |
879 | [PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_ANY, |
880 | [PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_USER, | |
881 | [PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_KERNEL, | |
882 | [PERF_SAMPLE_BRANCH_HV_SHIFT] = LBR_IGN, | |
883 | [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT] = LBR_RETURN | LBR_FAR, | |
884 | [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT] = LBR_REL_CALL | LBR_IND_CALL | |
885 | | LBR_FAR, | |
886 | [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = LBR_IND_CALL, | |
887 | [PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_JCC, | |
7b74cfb2 | 888 | [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT] = LBR_IND_JMP, |
c5cc2cd9 SE |
889 | }; |
890 | ||
2c44b193 | 891 | static const int hsw_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX_SHIFT] = { |
e9d7f7cd YZ |
892 | [PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_ANY, |
893 | [PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_USER, | |
894 | [PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_KERNEL, | |
895 | [PERF_SAMPLE_BRANCH_HV_SHIFT] = LBR_IGN, | |
896 | [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT] = LBR_RETURN | LBR_FAR, | |
897 | [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT] = LBR_REL_CALL | LBR_IND_CALL | |
898 | | LBR_FAR, | |
899 | [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = LBR_IND_CALL, | |
900 | [PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_JCC, | |
901 | [PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] = LBR_REL_CALL | LBR_IND_CALL | |
902 | | LBR_RETURN | LBR_CALL_STACK, | |
7b74cfb2 | 903 | [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT] = LBR_IND_JMP, |
e9d7f7cd YZ |
904 | }; |
905 | ||
c5cc2cd9 | 906 | /* core */ |
066ce64c | 907 | void __init intel_pmu_lbr_init_core(void) |
caff2bef | 908 | { |
caff2bef | 909 | x86_pmu.lbr_nr = 4; |
225ce539 SE |
910 | x86_pmu.lbr_tos = MSR_LBR_TOS; |
911 | x86_pmu.lbr_from = MSR_LBR_CORE_FROM; | |
912 | x86_pmu.lbr_to = MSR_LBR_CORE_TO; | |
c5cc2cd9 | 913 | |
3e702ff6 SE |
914 | /* |
915 | * SW branch filter usage: | |
916 | * - compensate for lack of HW filter | |
917 | */ | |
c5cc2cd9 | 918 | pr_cont("4-deep LBR, "); |
caff2bef PZ |
919 | } |
920 | ||
c5cc2cd9 | 921 | /* nehalem/westmere */ |
066ce64c | 922 | void __init intel_pmu_lbr_init_nhm(void) |
caff2bef | 923 | { |
caff2bef | 924 | x86_pmu.lbr_nr = 16; |
225ce539 SE |
925 | x86_pmu.lbr_tos = MSR_LBR_TOS; |
926 | x86_pmu.lbr_from = MSR_LBR_NHM_FROM; | |
927 | x86_pmu.lbr_to = MSR_LBR_NHM_TO; | |
c5cc2cd9 SE |
928 | |
929 | x86_pmu.lbr_sel_mask = LBR_SEL_MASK; | |
930 | x86_pmu.lbr_sel_map = nhm_lbr_sel_map; | |
931 | ||
3e702ff6 SE |
932 | /* |
933 | * SW branch filter usage: | |
934 | * - workaround LBR_SEL errata (see above) | |
935 | * - support syscall, sysret capture. | |
936 | * That requires LBR_FAR but that means far | |
937 | * jmp need to be filtered out | |
938 | */ | |
c5cc2cd9 | 939 | pr_cont("16-deep LBR, "); |
caff2bef PZ |
940 | } |
941 | ||
c5cc2cd9 | 942 | /* sandy bridge */ |
066ce64c | 943 | void __init intel_pmu_lbr_init_snb(void) |
c5cc2cd9 SE |
944 | { |
945 | x86_pmu.lbr_nr = 16; | |
946 | x86_pmu.lbr_tos = MSR_LBR_TOS; | |
947 | x86_pmu.lbr_from = MSR_LBR_NHM_FROM; | |
948 | x86_pmu.lbr_to = MSR_LBR_NHM_TO; | |
949 | ||
950 | x86_pmu.lbr_sel_mask = LBR_SEL_MASK; | |
951 | x86_pmu.lbr_sel_map = snb_lbr_sel_map; | |
952 | ||
3e702ff6 SE |
953 | /* |
954 | * SW branch filter usage: | |
955 | * - support syscall, sysret capture. | |
956 | * That requires LBR_FAR but that means far | |
957 | * jmp need to be filtered out | |
958 | */ | |
c5cc2cd9 SE |
959 | pr_cont("16-deep LBR, "); |
960 | } | |
961 | ||
e9d7f7cd YZ |
962 | /* haswell */ |
963 | void intel_pmu_lbr_init_hsw(void) | |
964 | { | |
965 | x86_pmu.lbr_nr = 16; | |
966 | x86_pmu.lbr_tos = MSR_LBR_TOS; | |
967 | x86_pmu.lbr_from = MSR_LBR_NHM_FROM; | |
968 | x86_pmu.lbr_to = MSR_LBR_NHM_TO; | |
969 | ||
970 | x86_pmu.lbr_sel_mask = LBR_SEL_MASK; | |
971 | x86_pmu.lbr_sel_map = hsw_lbr_sel_map; | |
972 | ||
973 | pr_cont("16-deep LBR, "); | |
974 | } | |
975 | ||
c5cc2cd9 | 976 | /* atom */ |
066ce64c | 977 | void __init intel_pmu_lbr_init_atom(void) |
caff2bef | 978 | { |
88c9a65e SE |
979 | /* |
980 | * only models starting at stepping 10 seems | |
981 | * to have an operational LBR which can freeze | |
982 | * on PMU interrupt | |
983 | */ | |
3ec18cd8 SE |
984 | if (boot_cpu_data.x86_model == 28 |
985 | && boot_cpu_data.x86_mask < 10) { | |
88c9a65e SE |
986 | pr_cont("LBR disabled due to erratum"); |
987 | return; | |
988 | } | |
989 | ||
caff2bef | 990 | x86_pmu.lbr_nr = 8; |
225ce539 SE |
991 | x86_pmu.lbr_tos = MSR_LBR_TOS; |
992 | x86_pmu.lbr_from = MSR_LBR_CORE_FROM; | |
993 | x86_pmu.lbr_to = MSR_LBR_CORE_TO; | |
c5cc2cd9 | 994 | |
3e702ff6 SE |
995 | /* |
996 | * SW branch filter usage: | |
997 | * - compensate for lack of HW filter | |
998 | */ | |
c5cc2cd9 | 999 | pr_cont("8-deep LBR, "); |
caff2bef | 1000 | } |