Commit | Line | Data |
---|---|---|
241771ef | 1 | /* |
cdd6c482 | 2 | * Performance events x86 architecture code |
241771ef | 3 | * |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
30dd568c | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
1da53e02 | 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
241771ef IM |
11 | * |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | ||
cdd6c482 | 15 | #include <linux/perf_event.h> |
241771ef IM |
16 | #include <linux/capability.h> |
17 | #include <linux/notifier.h> | |
18 | #include <linux/hardirq.h> | |
19 | #include <linux/kprobes.h> | |
4ac13294 | 20 | #include <linux/module.h> |
241771ef IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/sched.h> | |
d7d59fb3 | 23 | #include <linux/uaccess.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
30dd568c | 25 | #include <linux/cpu.h> |
272d30be | 26 | #include <linux/bitops.h> |
0c9d42ed | 27 | #include <linux/device.h> |
241771ef | 28 | |
241771ef | 29 | #include <asm/apic.h> |
d7d59fb3 | 30 | #include <asm/stacktrace.h> |
4e935e47 | 31 | #include <asm/nmi.h> |
69092624 | 32 | #include <asm/smp.h> |
c8e5910e | 33 | #include <asm/alternative.h> |
7911d3f7 | 34 | #include <asm/mmu_context.h> |
375074cc | 35 | #include <asm/tlbflush.h> |
e3f3541c | 36 | #include <asm/timer.h> |
d07bdfd3 PZ |
37 | #include <asm/desc.h> |
38 | #include <asm/ldt.h> | |
241771ef | 39 | |
de0428a7 KW |
40 | #include "perf_event.h" |
41 | ||
de0428a7 | 42 | struct x86_pmu x86_pmu __read_mostly; |
efc9f05d | 43 | |
de0428a7 | 44 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
b0f3f28e PZ |
45 | .enabled = 1, |
46 | }; | |
241771ef | 47 | |
a6673429 AL |
48 | struct static_key rdpmc_always_available = STATIC_KEY_INIT_FALSE; |
49 | ||
de0428a7 | 50 | u64 __read_mostly hw_cache_event_ids |
8326f44d IM |
51 | [PERF_COUNT_HW_CACHE_MAX] |
52 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
53 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
de0428a7 | 54 | u64 __read_mostly hw_cache_extra_regs |
e994d7d2 AK |
55 | [PERF_COUNT_HW_CACHE_MAX] |
56 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
57 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
8326f44d | 58 | |
ee06094f | 59 | /* |
cdd6c482 IM |
60 | * Propagate event elapsed time into the generic event. |
61 | * Can only be executed on the CPU where the event is active. | |
ee06094f IM |
62 | * Returns the delta events processed. |
63 | */ | |
de0428a7 | 64 | u64 x86_perf_event_update(struct perf_event *event) |
ee06094f | 65 | { |
cc2ad4ba | 66 | struct hw_perf_event *hwc = &event->hw; |
948b1bb8 | 67 | int shift = 64 - x86_pmu.cntval_bits; |
ec3232bd | 68 | u64 prev_raw_count, new_raw_count; |
cc2ad4ba | 69 | int idx = hwc->idx; |
ec3232bd | 70 | s64 delta; |
ee06094f | 71 | |
15c7ad51 | 72 | if (idx == INTEL_PMC_IDX_FIXED_BTS) |
30dd568c MM |
73 | return 0; |
74 | ||
ee06094f | 75 | /* |
cdd6c482 | 76 | * Careful: an NMI might modify the previous event value. |
ee06094f IM |
77 | * |
78 | * Our tactic to handle this is to first atomically read and | |
79 | * exchange a new raw count - then add that new-prev delta | |
cdd6c482 | 80 | * count to the generic event atomically: |
ee06094f IM |
81 | */ |
82 | again: | |
e7850595 | 83 | prev_raw_count = local64_read(&hwc->prev_count); |
c48b6053 | 84 | rdpmcl(hwc->event_base_rdpmc, new_raw_count); |
ee06094f | 85 | |
e7850595 | 86 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
ee06094f IM |
87 | new_raw_count) != prev_raw_count) |
88 | goto again; | |
89 | ||
90 | /* | |
91 | * Now we have the new raw value and have updated the prev | |
92 | * timestamp already. We can now calculate the elapsed delta | |
cdd6c482 | 93 | * (event-)time and add that to the generic event. |
ee06094f IM |
94 | * |
95 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 96 | * of the count. |
ee06094f | 97 | */ |
ec3232bd PZ |
98 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
99 | delta >>= shift; | |
ee06094f | 100 | |
e7850595 PZ |
101 | local64_add(delta, &event->count); |
102 | local64_sub(delta, &hwc->period_left); | |
4b7bfd0d RR |
103 | |
104 | return new_raw_count; | |
ee06094f IM |
105 | } |
106 | ||
a7e3ed1e AK |
107 | /* |
108 | * Find and validate any extra registers to set up. | |
109 | */ | |
110 | static int x86_pmu_extra_regs(u64 config, struct perf_event *event) | |
111 | { | |
efc9f05d | 112 | struct hw_perf_event_extra *reg; |
a7e3ed1e AK |
113 | struct extra_reg *er; |
114 | ||
efc9f05d | 115 | reg = &event->hw.extra_reg; |
a7e3ed1e AK |
116 | |
117 | if (!x86_pmu.extra_regs) | |
118 | return 0; | |
119 | ||
120 | for (er = x86_pmu.extra_regs; er->msr; er++) { | |
121 | if (er->event != (config & er->config_mask)) | |
122 | continue; | |
123 | if (event->attr.config1 & ~er->valid_mask) | |
124 | return -EINVAL; | |
338b522c KL |
125 | /* Check if the extra msrs can be safely accessed*/ |
126 | if (!er->extra_msr_access) | |
127 | return -ENXIO; | |
efc9f05d SE |
128 | |
129 | reg->idx = er->idx; | |
130 | reg->config = event->attr.config1; | |
131 | reg->reg = er->msr; | |
a7e3ed1e AK |
132 | break; |
133 | } | |
134 | return 0; | |
135 | } | |
136 | ||
cdd6c482 | 137 | static atomic_t active_events; |
4e935e47 PZ |
138 | static DEFINE_MUTEX(pmc_reserve_mutex); |
139 | ||
b27ea29c RR |
140 | #ifdef CONFIG_X86_LOCAL_APIC |
141 | ||
4e935e47 PZ |
142 | static bool reserve_pmc_hardware(void) |
143 | { | |
144 | int i; | |
145 | ||
948b1bb8 | 146 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 147 | if (!reserve_perfctr_nmi(x86_pmu_event_addr(i))) |
4e935e47 PZ |
148 | goto perfctr_fail; |
149 | } | |
150 | ||
948b1bb8 | 151 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 152 | if (!reserve_evntsel_nmi(x86_pmu_config_addr(i))) |
4e935e47 PZ |
153 | goto eventsel_fail; |
154 | } | |
155 | ||
156 | return true; | |
157 | ||
158 | eventsel_fail: | |
159 | for (i--; i >= 0; i--) | |
41bf4989 | 160 | release_evntsel_nmi(x86_pmu_config_addr(i)); |
4e935e47 | 161 | |
948b1bb8 | 162 | i = x86_pmu.num_counters; |
4e935e47 PZ |
163 | |
164 | perfctr_fail: | |
165 | for (i--; i >= 0; i--) | |
41bf4989 | 166 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
4e935e47 | 167 | |
4e935e47 PZ |
168 | return false; |
169 | } | |
170 | ||
171 | static void release_pmc_hardware(void) | |
172 | { | |
173 | int i; | |
174 | ||
948b1bb8 | 175 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 RR |
176 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
177 | release_evntsel_nmi(x86_pmu_config_addr(i)); | |
4e935e47 | 178 | } |
4e935e47 PZ |
179 | } |
180 | ||
b27ea29c RR |
181 | #else |
182 | ||
183 | static bool reserve_pmc_hardware(void) { return true; } | |
184 | static void release_pmc_hardware(void) {} | |
185 | ||
186 | #endif | |
187 | ||
33c6d6a7 DZ |
188 | static bool check_hw_exists(void) |
189 | { | |
a5ebe0ba GD |
190 | u64 val, val_fail, val_new= ~0; |
191 | int i, reg, reg_fail, ret = 0; | |
192 | int bios_fail = 0; | |
33c6d6a7 | 193 | |
4407204c PZ |
194 | /* |
195 | * Check to see if the BIOS enabled any of the counters, if so | |
196 | * complain and bail. | |
197 | */ | |
198 | for (i = 0; i < x86_pmu.num_counters; i++) { | |
41bf4989 | 199 | reg = x86_pmu_config_addr(i); |
4407204c PZ |
200 | ret = rdmsrl_safe(reg, &val); |
201 | if (ret) | |
202 | goto msr_fail; | |
a5ebe0ba GD |
203 | if (val & ARCH_PERFMON_EVENTSEL_ENABLE) { |
204 | bios_fail = 1; | |
205 | val_fail = val; | |
206 | reg_fail = reg; | |
207 | } | |
4407204c PZ |
208 | } |
209 | ||
210 | if (x86_pmu.num_counters_fixed) { | |
211 | reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
212 | ret = rdmsrl_safe(reg, &val); | |
213 | if (ret) | |
214 | goto msr_fail; | |
215 | for (i = 0; i < x86_pmu.num_counters_fixed; i++) { | |
a5ebe0ba GD |
216 | if (val & (0x03 << i*4)) { |
217 | bios_fail = 1; | |
218 | val_fail = val; | |
219 | reg_fail = reg; | |
220 | } | |
4407204c PZ |
221 | } |
222 | } | |
223 | ||
224 | /* | |
bffd5fc2 AP |
225 | * Read the current value, change it and read it back to see if it |
226 | * matches, this is needed to detect certain hardware emulators | |
227 | * (qemu/kvm) that don't trap on the MSR access and always return 0s. | |
4407204c | 228 | */ |
f285f92f | 229 | reg = x86_pmu_event_addr(0); |
bffd5fc2 AP |
230 | if (rdmsrl_safe(reg, &val)) |
231 | goto msr_fail; | |
232 | val ^= 0xffffUL; | |
f285f92f RR |
233 | ret = wrmsrl_safe(reg, val); |
234 | ret |= rdmsrl_safe(reg, &val_new); | |
33c6d6a7 | 235 | if (ret || val != val_new) |
4407204c | 236 | goto msr_fail; |
33c6d6a7 | 237 | |
45daae57 IM |
238 | /* |
239 | * We still allow the PMU driver to operate: | |
240 | */ | |
a5ebe0ba GD |
241 | if (bios_fail) { |
242 | printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n"); | |
243 | printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg_fail, val_fail); | |
244 | } | |
45daae57 IM |
245 | |
246 | return true; | |
4407204c PZ |
247 | |
248 | msr_fail: | |
249 | printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n"); | |
65d71fe1 PZI |
250 | printk("%sFailed to access perfctr msr (MSR %x is %Lx)\n", |
251 | boot_cpu_has(X86_FEATURE_HYPERVISOR) ? KERN_INFO : KERN_ERR, | |
252 | reg, val_new); | |
45daae57 | 253 | |
4407204c | 254 | return false; |
33c6d6a7 DZ |
255 | } |
256 | ||
cdd6c482 | 257 | static void hw_perf_event_destroy(struct perf_event *event) |
4e935e47 | 258 | { |
cdd6c482 | 259 | if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) { |
4e935e47 | 260 | release_pmc_hardware(); |
ca037701 | 261 | release_ds_buffers(); |
4e935e47 PZ |
262 | mutex_unlock(&pmc_reserve_mutex); |
263 | } | |
264 | } | |
265 | ||
48070342 AS |
266 | void hw_perf_lbr_event_destroy(struct perf_event *event) |
267 | { | |
268 | hw_perf_event_destroy(event); | |
269 | ||
270 | /* undo the lbr/bts event accounting */ | |
271 | x86_del_exclusive(x86_lbr_exclusive_lbr); | |
272 | } | |
273 | ||
85cf9dba RR |
274 | static inline int x86_pmu_initialized(void) |
275 | { | |
276 | return x86_pmu.handle_irq != NULL; | |
277 | } | |
278 | ||
8326f44d | 279 | static inline int |
e994d7d2 | 280 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event) |
8326f44d | 281 | { |
e994d7d2 | 282 | struct perf_event_attr *attr = &event->attr; |
8326f44d IM |
283 | unsigned int cache_type, cache_op, cache_result; |
284 | u64 config, val; | |
285 | ||
286 | config = attr->config; | |
287 | ||
288 | cache_type = (config >> 0) & 0xff; | |
289 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
290 | return -EINVAL; | |
291 | ||
292 | cache_op = (config >> 8) & 0xff; | |
293 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
294 | return -EINVAL; | |
295 | ||
296 | cache_result = (config >> 16) & 0xff; | |
297 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
298 | return -EINVAL; | |
299 | ||
300 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; | |
301 | ||
302 | if (val == 0) | |
303 | return -ENOENT; | |
304 | ||
305 | if (val == -1) | |
306 | return -EINVAL; | |
307 | ||
308 | hwc->config |= val; | |
e994d7d2 AK |
309 | attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result]; |
310 | return x86_pmu_extra_regs(val, event); | |
8326f44d IM |
311 | } |
312 | ||
48070342 AS |
313 | /* |
314 | * Check if we can create event of a certain type (that no conflicting events | |
315 | * are present). | |
316 | */ | |
317 | int x86_add_exclusive(unsigned int what) | |
318 | { | |
319 | int ret = -EBUSY, i; | |
320 | ||
321 | if (atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) | |
322 | return 0; | |
323 | ||
324 | mutex_lock(&pmc_reserve_mutex); | |
325 | for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) | |
326 | if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i])) | |
327 | goto out; | |
328 | ||
329 | atomic_inc(&x86_pmu.lbr_exclusive[what]); | |
330 | ret = 0; | |
331 | ||
332 | out: | |
333 | mutex_unlock(&pmc_reserve_mutex); | |
334 | return ret; | |
335 | } | |
336 | ||
337 | void x86_del_exclusive(unsigned int what) | |
338 | { | |
339 | atomic_dec(&x86_pmu.lbr_exclusive[what]); | |
340 | } | |
341 | ||
de0428a7 | 342 | int x86_setup_perfctr(struct perf_event *event) |
c1726f34 RR |
343 | { |
344 | struct perf_event_attr *attr = &event->attr; | |
345 | struct hw_perf_event *hwc = &event->hw; | |
346 | u64 config; | |
347 | ||
6c7e550f | 348 | if (!is_sampling_event(event)) { |
c1726f34 RR |
349 | hwc->sample_period = x86_pmu.max_period; |
350 | hwc->last_period = hwc->sample_period; | |
e7850595 | 351 | local64_set(&hwc->period_left, hwc->sample_period); |
c1726f34 RR |
352 | } |
353 | ||
354 | if (attr->type == PERF_TYPE_RAW) | |
ed13ec58 | 355 | return x86_pmu_extra_regs(event->attr.config, event); |
c1726f34 RR |
356 | |
357 | if (attr->type == PERF_TYPE_HW_CACHE) | |
e994d7d2 | 358 | return set_ext_hw_attr(hwc, event); |
c1726f34 RR |
359 | |
360 | if (attr->config >= x86_pmu.max_events) | |
361 | return -EINVAL; | |
362 | ||
363 | /* | |
364 | * The generic map: | |
365 | */ | |
366 | config = x86_pmu.event_map(attr->config); | |
367 | ||
368 | if (config == 0) | |
369 | return -ENOENT; | |
370 | ||
371 | if (config == -1LL) | |
372 | return -EINVAL; | |
373 | ||
374 | /* | |
375 | * Branch tracing: | |
376 | */ | |
18a073a3 PZ |
377 | if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS && |
378 | !attr->freq && hwc->sample_period == 1) { | |
c1726f34 | 379 | /* BTS is not supported by this architecture. */ |
6809b6ea | 380 | if (!x86_pmu.bts_active) |
c1726f34 RR |
381 | return -EOPNOTSUPP; |
382 | ||
383 | /* BTS is currently only allowed for user-mode. */ | |
384 | if (!attr->exclude_kernel) | |
385 | return -EOPNOTSUPP; | |
48070342 AS |
386 | |
387 | /* disallow bts if conflicting events are present */ | |
388 | if (x86_add_exclusive(x86_lbr_exclusive_lbr)) | |
389 | return -EBUSY; | |
390 | ||
391 | event->destroy = hw_perf_lbr_event_destroy; | |
c1726f34 RR |
392 | } |
393 | ||
394 | hwc->config |= config; | |
395 | ||
396 | return 0; | |
397 | } | |
4261e0e0 | 398 | |
ff3fb511 SE |
399 | /* |
400 | * check that branch_sample_type is compatible with | |
401 | * settings needed for precise_ip > 1 which implies | |
402 | * using the LBR to capture ALL taken branches at the | |
403 | * priv levels of the measurement | |
404 | */ | |
405 | static inline int precise_br_compat(struct perf_event *event) | |
406 | { | |
407 | u64 m = event->attr.branch_sample_type; | |
408 | u64 b = 0; | |
409 | ||
410 | /* must capture all branches */ | |
411 | if (!(m & PERF_SAMPLE_BRANCH_ANY)) | |
412 | return 0; | |
413 | ||
414 | m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER; | |
415 | ||
416 | if (!event->attr.exclude_user) | |
417 | b |= PERF_SAMPLE_BRANCH_USER; | |
418 | ||
419 | if (!event->attr.exclude_kernel) | |
420 | b |= PERF_SAMPLE_BRANCH_KERNEL; | |
421 | ||
422 | /* | |
423 | * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86 | |
424 | */ | |
425 | ||
426 | return m == b; | |
427 | } | |
428 | ||
de0428a7 | 429 | int x86_pmu_hw_config(struct perf_event *event) |
a072738e | 430 | { |
ab608344 PZ |
431 | if (event->attr.precise_ip) { |
432 | int precise = 0; | |
433 | ||
434 | /* Support for constant skid */ | |
c93dc84c | 435 | if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) { |
ab608344 PZ |
436 | precise++; |
437 | ||
5553be26 | 438 | /* Support for IP fixup */ |
03de874a | 439 | if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2) |
5553be26 PZ |
440 | precise++; |
441 | } | |
ab608344 PZ |
442 | |
443 | if (event->attr.precise_ip > precise) | |
444 | return -EOPNOTSUPP; | |
4b854900 YZ |
445 | } |
446 | /* | |
447 | * check that PEBS LBR correction does not conflict with | |
448 | * whatever the user is asking with attr->branch_sample_type | |
449 | */ | |
450 | if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) { | |
451 | u64 *br_type = &event->attr.branch_sample_type; | |
452 | ||
453 | if (has_branch_stack(event)) { | |
454 | if (!precise_br_compat(event)) | |
455 | return -EOPNOTSUPP; | |
456 | ||
457 | /* branch_sample_type is compatible */ | |
458 | ||
459 | } else { | |
460 | /* | |
461 | * user did not specify branch_sample_type | |
462 | * | |
463 | * For PEBS fixups, we capture all | |
464 | * the branches at the priv level of the | |
465 | * event. | |
466 | */ | |
467 | *br_type = PERF_SAMPLE_BRANCH_ANY; | |
468 | ||
469 | if (!event->attr.exclude_user) | |
470 | *br_type |= PERF_SAMPLE_BRANCH_USER; | |
471 | ||
472 | if (!event->attr.exclude_kernel) | |
473 | *br_type |= PERF_SAMPLE_BRANCH_KERNEL; | |
ff3fb511 | 474 | } |
ab608344 PZ |
475 | } |
476 | ||
e18bf526 YZ |
477 | if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK) |
478 | event->attach_state |= PERF_ATTACH_TASK_DATA; | |
479 | ||
a072738e CG |
480 | /* |
481 | * Generate PMC IRQs: | |
482 | * (keep 'enabled' bit clear for now) | |
483 | */ | |
b4cdc5c2 | 484 | event->hw.config = ARCH_PERFMON_EVENTSEL_INT; |
a072738e CG |
485 | |
486 | /* | |
487 | * Count user and OS events unless requested not to | |
488 | */ | |
b4cdc5c2 PZ |
489 | if (!event->attr.exclude_user) |
490 | event->hw.config |= ARCH_PERFMON_EVENTSEL_USR; | |
491 | if (!event->attr.exclude_kernel) | |
492 | event->hw.config |= ARCH_PERFMON_EVENTSEL_OS; | |
a072738e | 493 | |
b4cdc5c2 PZ |
494 | if (event->attr.type == PERF_TYPE_RAW) |
495 | event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; | |
a072738e | 496 | |
294fe0f5 AK |
497 | if (event->attr.sample_period && x86_pmu.limit_period) { |
498 | if (x86_pmu.limit_period(event, event->attr.sample_period) > | |
499 | event->attr.sample_period) | |
500 | return -EINVAL; | |
501 | } | |
502 | ||
9d0fcba6 | 503 | return x86_setup_perfctr(event); |
a098f448 RR |
504 | } |
505 | ||
241771ef | 506 | /* |
0d48696f | 507 | * Setup the hardware configuration for a given attr_type |
241771ef | 508 | */ |
b0a873eb | 509 | static int __x86_pmu_event_init(struct perf_event *event) |
241771ef | 510 | { |
4e935e47 | 511 | int err; |
241771ef | 512 | |
85cf9dba RR |
513 | if (!x86_pmu_initialized()) |
514 | return -ENODEV; | |
241771ef | 515 | |
4e935e47 | 516 | err = 0; |
cdd6c482 | 517 | if (!atomic_inc_not_zero(&active_events)) { |
4e935e47 | 518 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 519 | if (atomic_read(&active_events) == 0) { |
30dd568c MM |
520 | if (!reserve_pmc_hardware()) |
521 | err = -EBUSY; | |
f80c9e30 PZ |
522 | else |
523 | reserve_ds_buffers(); | |
30dd568c MM |
524 | } |
525 | if (!err) | |
cdd6c482 | 526 | atomic_inc(&active_events); |
4e935e47 PZ |
527 | mutex_unlock(&pmc_reserve_mutex); |
528 | } | |
529 | if (err) | |
530 | return err; | |
531 | ||
cdd6c482 | 532 | event->destroy = hw_perf_event_destroy; |
a1792cda | 533 | |
4261e0e0 RR |
534 | event->hw.idx = -1; |
535 | event->hw.last_cpu = -1; | |
536 | event->hw.last_tag = ~0ULL; | |
b690081d | 537 | |
efc9f05d SE |
538 | /* mark unused */ |
539 | event->hw.extra_reg.idx = EXTRA_REG_NONE; | |
b36817e8 SE |
540 | event->hw.branch_reg.idx = EXTRA_REG_NONE; |
541 | ||
9d0fcba6 | 542 | return x86_pmu.hw_config(event); |
4261e0e0 RR |
543 | } |
544 | ||
de0428a7 | 545 | void x86_pmu_disable_all(void) |
f87ad35d | 546 | { |
89cbc767 | 547 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
9e35ad38 PZ |
548 | int idx; |
549 | ||
948b1bb8 | 550 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
b0f3f28e PZ |
551 | u64 val; |
552 | ||
43f6201a | 553 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 554 | continue; |
41bf4989 | 555 | rdmsrl(x86_pmu_config_addr(idx), val); |
bb1165d6 | 556 | if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) |
4295ee62 | 557 | continue; |
bb1165d6 | 558 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
41bf4989 | 559 | wrmsrl(x86_pmu_config_addr(idx), val); |
f87ad35d | 560 | } |
f87ad35d JSR |
561 | } |
562 | ||
a4eaf7f1 | 563 | static void x86_pmu_disable(struct pmu *pmu) |
b56a3802 | 564 | { |
89cbc767 | 565 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
1da53e02 | 566 | |
85cf9dba | 567 | if (!x86_pmu_initialized()) |
9e35ad38 | 568 | return; |
1da53e02 | 569 | |
1a6e21f7 PZ |
570 | if (!cpuc->enabled) |
571 | return; | |
572 | ||
573 | cpuc->n_added = 0; | |
574 | cpuc->enabled = 0; | |
575 | barrier(); | |
1da53e02 SE |
576 | |
577 | x86_pmu.disable_all(); | |
b56a3802 | 578 | } |
241771ef | 579 | |
de0428a7 | 580 | void x86_pmu_enable_all(int added) |
f87ad35d | 581 | { |
89cbc767 | 582 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
f87ad35d JSR |
583 | int idx; |
584 | ||
948b1bb8 | 585 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
d45dd923 | 586 | struct hw_perf_event *hwc = &cpuc->events[idx]->hw; |
b0f3f28e | 587 | |
43f6201a | 588 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 589 | continue; |
984b838c | 590 | |
d45dd923 | 591 | __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); |
f87ad35d JSR |
592 | } |
593 | } | |
594 | ||
51b0fe39 | 595 | static struct pmu pmu; |
1da53e02 SE |
596 | |
597 | static inline int is_x86_event(struct perf_event *event) | |
598 | { | |
599 | return event->pmu == &pmu; | |
600 | } | |
601 | ||
1e2ad28f RR |
602 | /* |
603 | * Event scheduler state: | |
604 | * | |
605 | * Assign events iterating over all events and counters, beginning | |
606 | * with events with least weights first. Keep the current iterator | |
607 | * state in struct sched_state. | |
608 | */ | |
609 | struct sched_state { | |
610 | int weight; | |
611 | int event; /* event index */ | |
612 | int counter; /* counter index */ | |
613 | int unassigned; /* number of events to be assigned left */ | |
cc1790cf | 614 | int nr_gp; /* number of GP counters used */ |
1e2ad28f RR |
615 | unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
616 | }; | |
617 | ||
bc1738f6 RR |
618 | /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */ |
619 | #define SCHED_STATES_MAX 2 | |
620 | ||
1e2ad28f RR |
621 | struct perf_sched { |
622 | int max_weight; | |
623 | int max_events; | |
cc1790cf PZ |
624 | int max_gp; |
625 | int saved_states; | |
b371b594 | 626 | struct event_constraint **constraints; |
1e2ad28f | 627 | struct sched_state state; |
bc1738f6 | 628 | struct sched_state saved[SCHED_STATES_MAX]; |
1e2ad28f RR |
629 | }; |
630 | ||
631 | /* | |
632 | * Initialize interator that runs through all events and counters. | |
633 | */ | |
b371b594 | 634 | static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints, |
cc1790cf | 635 | int num, int wmin, int wmax, int gpmax) |
1e2ad28f RR |
636 | { |
637 | int idx; | |
638 | ||
639 | memset(sched, 0, sizeof(*sched)); | |
640 | sched->max_events = num; | |
641 | sched->max_weight = wmax; | |
cc1790cf | 642 | sched->max_gp = gpmax; |
b371b594 | 643 | sched->constraints = constraints; |
1e2ad28f RR |
644 | |
645 | for (idx = 0; idx < num; idx++) { | |
b371b594 | 646 | if (constraints[idx]->weight == wmin) |
1e2ad28f RR |
647 | break; |
648 | } | |
649 | ||
650 | sched->state.event = idx; /* start with min weight */ | |
651 | sched->state.weight = wmin; | |
652 | sched->state.unassigned = num; | |
653 | } | |
654 | ||
bc1738f6 RR |
655 | static void perf_sched_save_state(struct perf_sched *sched) |
656 | { | |
657 | if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX)) | |
658 | return; | |
659 | ||
660 | sched->saved[sched->saved_states] = sched->state; | |
661 | sched->saved_states++; | |
662 | } | |
663 | ||
664 | static bool perf_sched_restore_state(struct perf_sched *sched) | |
665 | { | |
666 | if (!sched->saved_states) | |
667 | return false; | |
668 | ||
669 | sched->saved_states--; | |
670 | sched->state = sched->saved[sched->saved_states]; | |
671 | ||
672 | /* continue with next counter: */ | |
673 | clear_bit(sched->state.counter++, sched->state.used); | |
674 | ||
675 | return true; | |
676 | } | |
677 | ||
1e2ad28f RR |
678 | /* |
679 | * Select a counter for the current event to schedule. Return true on | |
680 | * success. | |
681 | */ | |
bc1738f6 | 682 | static bool __perf_sched_find_counter(struct perf_sched *sched) |
1e2ad28f RR |
683 | { |
684 | struct event_constraint *c; | |
685 | int idx; | |
686 | ||
687 | if (!sched->state.unassigned) | |
688 | return false; | |
689 | ||
690 | if (sched->state.event >= sched->max_events) | |
691 | return false; | |
692 | ||
b371b594 | 693 | c = sched->constraints[sched->state.event]; |
4defea85 | 694 | /* Prefer fixed purpose counters */ |
15c7ad51 RR |
695 | if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) { |
696 | idx = INTEL_PMC_IDX_FIXED; | |
307b1cd7 | 697 | for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) { |
4defea85 PZ |
698 | if (!__test_and_set_bit(idx, sched->state.used)) |
699 | goto done; | |
700 | } | |
701 | } | |
cc1790cf | 702 | |
1e2ad28f RR |
703 | /* Grab the first unused counter starting with idx */ |
704 | idx = sched->state.counter; | |
15c7ad51 | 705 | for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) { |
cc1790cf PZ |
706 | if (!__test_and_set_bit(idx, sched->state.used)) { |
707 | if (sched->state.nr_gp++ >= sched->max_gp) | |
708 | return false; | |
709 | ||
4defea85 | 710 | goto done; |
cc1790cf | 711 | } |
1e2ad28f | 712 | } |
1e2ad28f | 713 | |
4defea85 PZ |
714 | return false; |
715 | ||
716 | done: | |
717 | sched->state.counter = idx; | |
1e2ad28f | 718 | |
bc1738f6 RR |
719 | if (c->overlap) |
720 | perf_sched_save_state(sched); | |
721 | ||
722 | return true; | |
723 | } | |
724 | ||
725 | static bool perf_sched_find_counter(struct perf_sched *sched) | |
726 | { | |
727 | while (!__perf_sched_find_counter(sched)) { | |
728 | if (!perf_sched_restore_state(sched)) | |
729 | return false; | |
730 | } | |
731 | ||
1e2ad28f RR |
732 | return true; |
733 | } | |
734 | ||
735 | /* | |
736 | * Go through all unassigned events and find the next one to schedule. | |
737 | * Take events with the least weight first. Return true on success. | |
738 | */ | |
739 | static bool perf_sched_next_event(struct perf_sched *sched) | |
740 | { | |
741 | struct event_constraint *c; | |
742 | ||
743 | if (!sched->state.unassigned || !--sched->state.unassigned) | |
744 | return false; | |
745 | ||
746 | do { | |
747 | /* next event */ | |
748 | sched->state.event++; | |
749 | if (sched->state.event >= sched->max_events) { | |
750 | /* next weight */ | |
751 | sched->state.event = 0; | |
752 | sched->state.weight++; | |
753 | if (sched->state.weight > sched->max_weight) | |
754 | return false; | |
755 | } | |
b371b594 | 756 | c = sched->constraints[sched->state.event]; |
1e2ad28f RR |
757 | } while (c->weight != sched->state.weight); |
758 | ||
759 | sched->state.counter = 0; /* start with first counter */ | |
760 | ||
761 | return true; | |
762 | } | |
763 | ||
764 | /* | |
765 | * Assign a counter for each event. | |
766 | */ | |
b371b594 | 767 | int perf_assign_events(struct event_constraint **constraints, int n, |
cc1790cf | 768 | int wmin, int wmax, int gpmax, int *assign) |
1e2ad28f RR |
769 | { |
770 | struct perf_sched sched; | |
771 | ||
cc1790cf | 772 | perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax); |
1e2ad28f RR |
773 | |
774 | do { | |
775 | if (!perf_sched_find_counter(&sched)) | |
776 | break; /* failed */ | |
777 | if (assign) | |
778 | assign[sched.state.event] = sched.state.counter; | |
779 | } while (perf_sched_next_event(&sched)); | |
780 | ||
781 | return sched.state.unassigned; | |
782 | } | |
4a3dc121 | 783 | EXPORT_SYMBOL_GPL(perf_assign_events); |
1e2ad28f | 784 | |
de0428a7 | 785 | int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) |
1da53e02 | 786 | { |
43b45780 | 787 | struct event_constraint *c; |
1da53e02 | 788 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
2f7f73a5 | 789 | struct perf_event *e; |
e979121b | 790 | int i, wmin, wmax, unsched = 0; |
1da53e02 SE |
791 | struct hw_perf_event *hwc; |
792 | ||
793 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
794 | ||
c5362c0c MD |
795 | if (x86_pmu.start_scheduling) |
796 | x86_pmu.start_scheduling(cpuc); | |
797 | ||
1e2ad28f | 798 | for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) { |
b371b594 | 799 | cpuc->event_constraint[i] = NULL; |
79cba822 | 800 | c = x86_pmu.get_event_constraints(cpuc, i, cpuc->event_list[i]); |
b371b594 | 801 | cpuc->event_constraint[i] = c; |
43b45780 | 802 | |
1e2ad28f RR |
803 | wmin = min(wmin, c->weight); |
804 | wmax = max(wmax, c->weight); | |
1da53e02 SE |
805 | } |
806 | ||
8113070d SE |
807 | /* |
808 | * fastpath, try to reuse previous register | |
809 | */ | |
c933c1a6 | 810 | for (i = 0; i < n; i++) { |
8113070d | 811 | hwc = &cpuc->event_list[i]->hw; |
b371b594 | 812 | c = cpuc->event_constraint[i]; |
8113070d SE |
813 | |
814 | /* never assigned */ | |
815 | if (hwc->idx == -1) | |
816 | break; | |
817 | ||
818 | /* constraint still honored */ | |
63b14649 | 819 | if (!test_bit(hwc->idx, c->idxmsk)) |
8113070d SE |
820 | break; |
821 | ||
822 | /* not already used */ | |
823 | if (test_bit(hwc->idx, used_mask)) | |
824 | break; | |
825 | ||
34538ee7 | 826 | __set_bit(hwc->idx, used_mask); |
8113070d SE |
827 | if (assign) |
828 | assign[i] = hwc->idx; | |
829 | } | |
8113070d | 830 | |
1e2ad28f | 831 | /* slow path */ |
b371b594 | 832 | if (i != n) { |
cc1790cf PZ |
833 | int gpmax = x86_pmu.num_counters; |
834 | ||
835 | /* | |
836 | * Do not allow scheduling of more than half the available | |
837 | * generic counters. | |
838 | * | |
839 | * This helps avoid counter starvation of sibling thread by | |
840 | * ensuring at most half the counters cannot be in exclusive | |
841 | * mode. There is no designated counters for the limits. Any | |
842 | * N/2 counters can be used. This helps with events with | |
843 | * specific counter constraints. | |
844 | */ | |
845 | if (is_ht_workaround_enabled() && !cpuc->is_fake && | |
846 | READ_ONCE(cpuc->excl_cntrs->exclusive_present)) | |
847 | gpmax /= 2; | |
848 | ||
b371b594 | 849 | unsched = perf_assign_events(cpuc->event_constraint, n, wmin, |
cc1790cf | 850 | wmax, gpmax, assign); |
b371b594 | 851 | } |
8113070d | 852 | |
2f7f73a5 | 853 | /* |
e979121b MD |
854 | * In case of success (unsched = 0), mark events as committed, |
855 | * so we do not put_constraint() in case new events are added | |
856 | * and fail to be scheduled | |
857 | * | |
858 | * We invoke the lower level commit callback to lock the resource | |
859 | * | |
860 | * We do not need to do all of this in case we are called to | |
861 | * validate an event group (assign == NULL) | |
2f7f73a5 | 862 | */ |
e979121b | 863 | if (!unsched && assign) { |
2f7f73a5 SE |
864 | for (i = 0; i < n; i++) { |
865 | e = cpuc->event_list[i]; | |
866 | e->hw.flags |= PERF_X86_EVENT_COMMITTED; | |
c5362c0c | 867 | if (x86_pmu.commit_scheduling) |
b371b594 | 868 | x86_pmu.commit_scheduling(cpuc, i, assign[i]); |
2f7f73a5 SE |
869 | } |
870 | } | |
e979121b MD |
871 | |
872 | if (!assign || unsched) { | |
873 | ||
1da53e02 | 874 | for (i = 0; i < n; i++) { |
2f7f73a5 SE |
875 | e = cpuc->event_list[i]; |
876 | /* | |
877 | * do not put_constraint() on comitted events, | |
878 | * because they are good to go | |
879 | */ | |
880 | if ((e->hw.flags & PERF_X86_EVENT_COMMITTED)) | |
881 | continue; | |
882 | ||
e979121b MD |
883 | /* |
884 | * release events that failed scheduling | |
885 | */ | |
1da53e02 | 886 | if (x86_pmu.put_event_constraints) |
2f7f73a5 | 887 | x86_pmu.put_event_constraints(cpuc, e); |
1da53e02 SE |
888 | } |
889 | } | |
c5362c0c MD |
890 | |
891 | if (x86_pmu.stop_scheduling) | |
892 | x86_pmu.stop_scheduling(cpuc); | |
893 | ||
e979121b | 894 | return unsched ? -EINVAL : 0; |
1da53e02 SE |
895 | } |
896 | ||
897 | /* | |
898 | * dogrp: true if must collect siblings events (group) | |
899 | * returns total number of events and error code | |
900 | */ | |
901 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) | |
902 | { | |
903 | struct perf_event *event; | |
904 | int n, max_count; | |
905 | ||
948b1bb8 | 906 | max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed; |
1da53e02 SE |
907 | |
908 | /* current number of events already accepted */ | |
909 | n = cpuc->n_events; | |
910 | ||
911 | if (is_x86_event(leader)) { | |
912 | if (n >= max_count) | |
aa2bc1ad | 913 | return -EINVAL; |
1da53e02 SE |
914 | cpuc->event_list[n] = leader; |
915 | n++; | |
916 | } | |
917 | if (!dogrp) | |
918 | return n; | |
919 | ||
920 | list_for_each_entry(event, &leader->sibling_list, group_entry) { | |
921 | if (!is_x86_event(event) || | |
8113070d | 922 | event->state <= PERF_EVENT_STATE_OFF) |
1da53e02 SE |
923 | continue; |
924 | ||
925 | if (n >= max_count) | |
aa2bc1ad | 926 | return -EINVAL; |
1da53e02 SE |
927 | |
928 | cpuc->event_list[n] = event; | |
929 | n++; | |
930 | } | |
931 | return n; | |
932 | } | |
933 | ||
1da53e02 | 934 | static inline void x86_assign_hw_event(struct perf_event *event, |
447a194b | 935 | struct cpu_hw_events *cpuc, int i) |
1da53e02 | 936 | { |
447a194b SE |
937 | struct hw_perf_event *hwc = &event->hw; |
938 | ||
939 | hwc->idx = cpuc->assign[i]; | |
940 | hwc->last_cpu = smp_processor_id(); | |
941 | hwc->last_tag = ++cpuc->tags[i]; | |
1da53e02 | 942 | |
15c7ad51 | 943 | if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) { |
1da53e02 SE |
944 | hwc->config_base = 0; |
945 | hwc->event_base = 0; | |
15c7ad51 | 946 | } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) { |
1da53e02 | 947 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
15c7ad51 RR |
948 | hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED); |
949 | hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30; | |
1da53e02 | 950 | } else { |
73d6e522 RR |
951 | hwc->config_base = x86_pmu_config_addr(hwc->idx); |
952 | hwc->event_base = x86_pmu_event_addr(hwc->idx); | |
0fbdad07 | 953 | hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx); |
1da53e02 SE |
954 | } |
955 | } | |
956 | ||
447a194b SE |
957 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
958 | struct cpu_hw_events *cpuc, | |
959 | int i) | |
960 | { | |
961 | return hwc->idx == cpuc->assign[i] && | |
962 | hwc->last_cpu == smp_processor_id() && | |
963 | hwc->last_tag == cpuc->tags[i]; | |
964 | } | |
965 | ||
a4eaf7f1 | 966 | static void x86_pmu_start(struct perf_event *event, int flags); |
2e841873 | 967 | |
a4eaf7f1 | 968 | static void x86_pmu_enable(struct pmu *pmu) |
ee06094f | 969 | { |
89cbc767 | 970 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
1da53e02 SE |
971 | struct perf_event *event; |
972 | struct hw_perf_event *hwc; | |
11164cd4 | 973 | int i, added = cpuc->n_added; |
1da53e02 | 974 | |
85cf9dba | 975 | if (!x86_pmu_initialized()) |
2b9ff0db | 976 | return; |
1a6e21f7 PZ |
977 | |
978 | if (cpuc->enabled) | |
979 | return; | |
980 | ||
1da53e02 | 981 | if (cpuc->n_added) { |
19925ce7 | 982 | int n_running = cpuc->n_events - cpuc->n_added; |
1da53e02 SE |
983 | /* |
984 | * apply assignment obtained either from | |
985 | * hw_perf_group_sched_in() or x86_pmu_enable() | |
986 | * | |
987 | * step1: save events moving to new counters | |
1da53e02 | 988 | */ |
19925ce7 | 989 | for (i = 0; i < n_running; i++) { |
1da53e02 SE |
990 | event = cpuc->event_list[i]; |
991 | hwc = &event->hw; | |
992 | ||
447a194b SE |
993 | /* |
994 | * we can avoid reprogramming counter if: | |
995 | * - assigned same counter as last time | |
996 | * - running on same CPU as last time | |
997 | * - no other event has used the counter since | |
998 | */ | |
999 | if (hwc->idx == -1 || | |
1000 | match_prev_assignment(hwc, cpuc, i)) | |
1da53e02 SE |
1001 | continue; |
1002 | ||
a4eaf7f1 PZ |
1003 | /* |
1004 | * Ensure we don't accidentally enable a stopped | |
1005 | * counter simply because we rescheduled. | |
1006 | */ | |
1007 | if (hwc->state & PERF_HES_STOPPED) | |
1008 | hwc->state |= PERF_HES_ARCH; | |
1009 | ||
1010 | x86_pmu_stop(event, PERF_EF_UPDATE); | |
1da53e02 SE |
1011 | } |
1012 | ||
c347a2f1 PZ |
1013 | /* |
1014 | * step2: reprogram moved events into new counters | |
1015 | */ | |
1da53e02 | 1016 | for (i = 0; i < cpuc->n_events; i++) { |
1da53e02 SE |
1017 | event = cpuc->event_list[i]; |
1018 | hwc = &event->hw; | |
1019 | ||
45e16a68 | 1020 | if (!match_prev_assignment(hwc, cpuc, i)) |
447a194b | 1021 | x86_assign_hw_event(event, cpuc, i); |
45e16a68 PZ |
1022 | else if (i < n_running) |
1023 | continue; | |
1da53e02 | 1024 | |
a4eaf7f1 PZ |
1025 | if (hwc->state & PERF_HES_ARCH) |
1026 | continue; | |
1027 | ||
1028 | x86_pmu_start(event, PERF_EF_RELOAD); | |
1da53e02 SE |
1029 | } |
1030 | cpuc->n_added = 0; | |
1031 | perf_events_lapic_init(); | |
1032 | } | |
1a6e21f7 PZ |
1033 | |
1034 | cpuc->enabled = 1; | |
1035 | barrier(); | |
1036 | ||
11164cd4 | 1037 | x86_pmu.enable_all(added); |
ee06094f | 1038 | } |
ee06094f | 1039 | |
245b2e70 | 1040 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
241771ef | 1041 | |
ee06094f IM |
1042 | /* |
1043 | * Set the next IRQ period, based on the hwc->period_left value. | |
cdd6c482 | 1044 | * To be called with the event disabled in hw: |
ee06094f | 1045 | */ |
de0428a7 | 1046 | int x86_perf_event_set_period(struct perf_event *event) |
241771ef | 1047 | { |
07088edb | 1048 | struct hw_perf_event *hwc = &event->hw; |
e7850595 | 1049 | s64 left = local64_read(&hwc->period_left); |
e4abb5d4 | 1050 | s64 period = hwc->sample_period; |
7645a24c | 1051 | int ret = 0, idx = hwc->idx; |
ee06094f | 1052 | |
15c7ad51 | 1053 | if (idx == INTEL_PMC_IDX_FIXED_BTS) |
30dd568c MM |
1054 | return 0; |
1055 | ||
ee06094f | 1056 | /* |
af901ca1 | 1057 | * If we are way outside a reasonable range then just skip forward: |
ee06094f IM |
1058 | */ |
1059 | if (unlikely(left <= -period)) { | |
1060 | left = period; | |
e7850595 | 1061 | local64_set(&hwc->period_left, left); |
9e350de3 | 1062 | hwc->last_period = period; |
e4abb5d4 | 1063 | ret = 1; |
ee06094f IM |
1064 | } |
1065 | ||
1066 | if (unlikely(left <= 0)) { | |
1067 | left += period; | |
e7850595 | 1068 | local64_set(&hwc->period_left, left); |
9e350de3 | 1069 | hwc->last_period = period; |
e4abb5d4 | 1070 | ret = 1; |
ee06094f | 1071 | } |
1c80f4b5 | 1072 | /* |
dfc65094 | 1073 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
1c80f4b5 IM |
1074 | */ |
1075 | if (unlikely(left < 2)) | |
1076 | left = 2; | |
241771ef | 1077 | |
e4abb5d4 PZ |
1078 | if (left > x86_pmu.max_period) |
1079 | left = x86_pmu.max_period; | |
1080 | ||
294fe0f5 AK |
1081 | if (x86_pmu.limit_period) |
1082 | left = x86_pmu.limit_period(event, left); | |
1083 | ||
245b2e70 | 1084 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
ee06094f IM |
1085 | |
1086 | /* | |
cdd6c482 | 1087 | * The hw event starts counting from this event offset, |
ee06094f IM |
1088 | * mark it to be able to extra future deltas: |
1089 | */ | |
e7850595 | 1090 | local64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 1091 | |
73d6e522 | 1092 | wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac CG |
1093 | |
1094 | /* | |
1095 | * Due to erratum on certan cpu we need | |
1096 | * a second write to be sure the register | |
1097 | * is updated properly | |
1098 | */ | |
1099 | if (x86_pmu.perfctr_second_write) { | |
73d6e522 | 1100 | wrmsrl(hwc->event_base, |
948b1bb8 | 1101 | (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac | 1102 | } |
e4abb5d4 | 1103 | |
cdd6c482 | 1104 | perf_event_update_userpage(event); |
194002b2 | 1105 | |
e4abb5d4 | 1106 | return ret; |
2f18d1e8 IM |
1107 | } |
1108 | ||
de0428a7 | 1109 | void x86_pmu_enable_event(struct perf_event *event) |
7c90cc45 | 1110 | { |
0a3aee0d | 1111 | if (__this_cpu_read(cpu_hw_events.enabled)) |
31fa58af RR |
1112 | __x86_pmu_enable_event(&event->hw, |
1113 | ARCH_PERFMON_EVENTSEL_ENABLE); | |
241771ef IM |
1114 | } |
1115 | ||
b690081d | 1116 | /* |
a4eaf7f1 | 1117 | * Add a single event to the PMU. |
1da53e02 SE |
1118 | * |
1119 | * The event is added to the group of enabled events | |
1120 | * but only if it can be scehduled with existing events. | |
fe9081cc | 1121 | */ |
a4eaf7f1 | 1122 | static int x86_pmu_add(struct perf_event *event, int flags) |
fe9081cc | 1123 | { |
89cbc767 | 1124 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
1da53e02 SE |
1125 | struct hw_perf_event *hwc; |
1126 | int assign[X86_PMC_IDX_MAX]; | |
1127 | int n, n0, ret; | |
fe9081cc | 1128 | |
1da53e02 | 1129 | hwc = &event->hw; |
fe9081cc | 1130 | |
1da53e02 | 1131 | n0 = cpuc->n_events; |
24cd7f54 PZ |
1132 | ret = n = collect_events(cpuc, event, false); |
1133 | if (ret < 0) | |
1134 | goto out; | |
53b441a5 | 1135 | |
a4eaf7f1 PZ |
1136 | hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; |
1137 | if (!(flags & PERF_EF_START)) | |
1138 | hwc->state |= PERF_HES_ARCH; | |
1139 | ||
4d1c52b0 LM |
1140 | /* |
1141 | * If group events scheduling transaction was started, | |
0d2eb44f | 1142 | * skip the schedulability test here, it will be performed |
c347a2f1 | 1143 | * at commit time (->commit_txn) as a whole. |
4d1c52b0 | 1144 | */ |
8d2cacbb | 1145 | if (cpuc->group_flag & PERF_EVENT_TXN) |
24cd7f54 | 1146 | goto done_collect; |
4d1c52b0 | 1147 | |
a072738e | 1148 | ret = x86_pmu.schedule_events(cpuc, n, assign); |
1da53e02 | 1149 | if (ret) |
24cd7f54 | 1150 | goto out; |
1da53e02 SE |
1151 | /* |
1152 | * copy new assignment, now we know it is possible | |
1153 | * will be used by hw_perf_enable() | |
1154 | */ | |
1155 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
7e2ae347 | 1156 | |
24cd7f54 | 1157 | done_collect: |
c347a2f1 PZ |
1158 | /* |
1159 | * Commit the collect_events() state. See x86_pmu_del() and | |
1160 | * x86_pmu_*_txn(). | |
1161 | */ | |
1da53e02 | 1162 | cpuc->n_events = n; |
356e1f2e | 1163 | cpuc->n_added += n - n0; |
90151c35 | 1164 | cpuc->n_txn += n - n0; |
95cdd2e7 | 1165 | |
24cd7f54 PZ |
1166 | ret = 0; |
1167 | out: | |
24cd7f54 | 1168 | return ret; |
241771ef IM |
1169 | } |
1170 | ||
a4eaf7f1 | 1171 | static void x86_pmu_start(struct perf_event *event, int flags) |
d76a0812 | 1172 | { |
89cbc767 | 1173 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
c08053e6 PZ |
1174 | int idx = event->hw.idx; |
1175 | ||
a4eaf7f1 PZ |
1176 | if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) |
1177 | return; | |
1178 | ||
1179 | if (WARN_ON_ONCE(idx == -1)) | |
1180 | return; | |
1181 | ||
1182 | if (flags & PERF_EF_RELOAD) { | |
1183 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
1184 | x86_perf_event_set_period(event); | |
1185 | } | |
1186 | ||
1187 | event->hw.state = 0; | |
d76a0812 | 1188 | |
c08053e6 PZ |
1189 | cpuc->events[idx] = event; |
1190 | __set_bit(idx, cpuc->active_mask); | |
63e6be6d | 1191 | __set_bit(idx, cpuc->running); |
aff3d91a | 1192 | x86_pmu.enable(event); |
c08053e6 | 1193 | perf_event_update_userpage(event); |
a78ac325 PZ |
1194 | } |
1195 | ||
cdd6c482 | 1196 | void perf_event_print_debug(void) |
241771ef | 1197 | { |
2f18d1e8 | 1198 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
da3e606d | 1199 | u64 pebs, debugctl; |
cdd6c482 | 1200 | struct cpu_hw_events *cpuc; |
5bb9efe3 | 1201 | unsigned long flags; |
1e125676 IM |
1202 | int cpu, idx; |
1203 | ||
948b1bb8 | 1204 | if (!x86_pmu.num_counters) |
1e125676 | 1205 | return; |
241771ef | 1206 | |
5bb9efe3 | 1207 | local_irq_save(flags); |
241771ef IM |
1208 | |
1209 | cpu = smp_processor_id(); | |
cdd6c482 | 1210 | cpuc = &per_cpu(cpu_hw_events, cpu); |
241771ef | 1211 | |
faa28ae0 | 1212 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
1213 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
1214 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
1215 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
1216 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
1217 | ||
1218 | pr_info("\n"); | |
1219 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
1220 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
1221 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
1222 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
15fde110 AK |
1223 | if (x86_pmu.pebs_constraints) { |
1224 | rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); | |
1225 | pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); | |
1226 | } | |
da3e606d AK |
1227 | if (x86_pmu.lbr_nr) { |
1228 | rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); | |
1229 | pr_info("CPU#%d: debugctl: %016llx\n", cpu, debugctl); | |
1230 | } | |
f87ad35d | 1231 | } |
7645a24c | 1232 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
241771ef | 1233 | |
948b1bb8 | 1234 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
41bf4989 RR |
1235 | rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl); |
1236 | rdmsrl(x86_pmu_event_addr(idx), pmc_count); | |
241771ef | 1237 | |
245b2e70 | 1238 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
241771ef | 1239 | |
a1ef58f4 | 1240 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 1241 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 1242 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 1243 | cpu, idx, pmc_count); |
a1ef58f4 | 1244 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 1245 | cpu, idx, prev_left); |
241771ef | 1246 | } |
948b1bb8 | 1247 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
2f18d1e8 IM |
1248 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
1249 | ||
a1ef58f4 | 1250 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
1251 | cpu, idx, pmc_count); |
1252 | } | |
5bb9efe3 | 1253 | local_irq_restore(flags); |
241771ef IM |
1254 | } |
1255 | ||
de0428a7 | 1256 | void x86_pmu_stop(struct perf_event *event, int flags) |
241771ef | 1257 | { |
89cbc767 | 1258 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
cdd6c482 | 1259 | struct hw_perf_event *hwc = &event->hw; |
241771ef | 1260 | |
a4eaf7f1 PZ |
1261 | if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) { |
1262 | x86_pmu.disable(event); | |
1263 | cpuc->events[hwc->idx] = NULL; | |
1264 | WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); | |
1265 | hwc->state |= PERF_HES_STOPPED; | |
1266 | } | |
30dd568c | 1267 | |
a4eaf7f1 PZ |
1268 | if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { |
1269 | /* | |
1270 | * Drain the remaining delta count out of a event | |
1271 | * that we are disabling: | |
1272 | */ | |
1273 | x86_perf_event_update(event); | |
1274 | hwc->state |= PERF_HES_UPTODATE; | |
1275 | } | |
2e841873 PZ |
1276 | } |
1277 | ||
a4eaf7f1 | 1278 | static void x86_pmu_del(struct perf_event *event, int flags) |
2e841873 | 1279 | { |
89cbc767 | 1280 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
2e841873 PZ |
1281 | int i; |
1282 | ||
2f7f73a5 SE |
1283 | /* |
1284 | * event is descheduled | |
1285 | */ | |
1286 | event->hw.flags &= ~PERF_X86_EVENT_COMMITTED; | |
1287 | ||
90151c35 SE |
1288 | /* |
1289 | * If we're called during a txn, we don't need to do anything. | |
1290 | * The events never got scheduled and ->cancel_txn will truncate | |
1291 | * the event_list. | |
c347a2f1 PZ |
1292 | * |
1293 | * XXX assumes any ->del() called during a TXN will only be on | |
1294 | * an event added during that same TXN. | |
90151c35 | 1295 | */ |
8d2cacbb | 1296 | if (cpuc->group_flag & PERF_EVENT_TXN) |
90151c35 SE |
1297 | return; |
1298 | ||
c347a2f1 PZ |
1299 | /* |
1300 | * Not a TXN, therefore cleanup properly. | |
1301 | */ | |
a4eaf7f1 | 1302 | x86_pmu_stop(event, PERF_EF_UPDATE); |
194002b2 | 1303 | |
1da53e02 | 1304 | for (i = 0; i < cpuc->n_events; i++) { |
c347a2f1 PZ |
1305 | if (event == cpuc->event_list[i]) |
1306 | break; | |
1307 | } | |
1da53e02 | 1308 | |
c347a2f1 PZ |
1309 | if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */ |
1310 | return; | |
26e61e89 | 1311 | |
c347a2f1 PZ |
1312 | /* If we have a newly added event; make sure to decrease n_added. */ |
1313 | if (i >= cpuc->n_events - cpuc->n_added) | |
1314 | --cpuc->n_added; | |
1da53e02 | 1315 | |
c347a2f1 PZ |
1316 | if (x86_pmu.put_event_constraints) |
1317 | x86_pmu.put_event_constraints(cpuc, event); | |
1318 | ||
1319 | /* Delete the array entry. */ | |
b371b594 | 1320 | while (++i < cpuc->n_events) { |
c347a2f1 | 1321 | cpuc->event_list[i-1] = cpuc->event_list[i]; |
b371b594 PZ |
1322 | cpuc->event_constraint[i-1] = cpuc->event_constraint[i]; |
1323 | } | |
c347a2f1 | 1324 | --cpuc->n_events; |
1da53e02 | 1325 | |
cdd6c482 | 1326 | perf_event_update_userpage(event); |
241771ef IM |
1327 | } |
1328 | ||
de0428a7 | 1329 | int x86_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 1330 | { |
df1a132b | 1331 | struct perf_sample_data data; |
cdd6c482 IM |
1332 | struct cpu_hw_events *cpuc; |
1333 | struct perf_event *event; | |
11d1578f | 1334 | int idx, handled = 0; |
9029a5e3 IM |
1335 | u64 val; |
1336 | ||
89cbc767 | 1337 | cpuc = this_cpu_ptr(&cpu_hw_events); |
962bf7a6 | 1338 | |
2bce5dac DZ |
1339 | /* |
1340 | * Some chipsets need to unmask the LVTPC in a particular spot | |
1341 | * inside the nmi handler. As a result, the unmasking was pushed | |
1342 | * into all the nmi handlers. | |
1343 | * | |
1344 | * This generic handler doesn't seem to have any issues where the | |
1345 | * unmasking occurs so it was left at the top. | |
1346 | */ | |
1347 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
1348 | ||
948b1bb8 | 1349 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
63e6be6d RR |
1350 | if (!test_bit(idx, cpuc->active_mask)) { |
1351 | /* | |
1352 | * Though we deactivated the counter some cpus | |
1353 | * might still deliver spurious interrupts still | |
1354 | * in flight. Catch them: | |
1355 | */ | |
1356 | if (__test_and_clear_bit(idx, cpuc->running)) | |
1357 | handled++; | |
a29aa8a7 | 1358 | continue; |
63e6be6d | 1359 | } |
962bf7a6 | 1360 | |
cdd6c482 | 1361 | event = cpuc->events[idx]; |
a4016a79 | 1362 | |
cc2ad4ba | 1363 | val = x86_perf_event_update(event); |
948b1bb8 | 1364 | if (val & (1ULL << (x86_pmu.cntval_bits - 1))) |
48e22d56 | 1365 | continue; |
962bf7a6 | 1366 | |
9e350de3 | 1367 | /* |
cdd6c482 | 1368 | * event overflow |
9e350de3 | 1369 | */ |
4177c42a | 1370 | handled++; |
fd0d000b | 1371 | perf_sample_data_init(&data, 0, event->hw.last_period); |
9e350de3 | 1372 | |
07088edb | 1373 | if (!x86_perf_event_set_period(event)) |
e4abb5d4 PZ |
1374 | continue; |
1375 | ||
a8b0ca17 | 1376 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 1377 | x86_pmu_stop(event, 0); |
a29aa8a7 | 1378 | } |
962bf7a6 | 1379 | |
9e350de3 PZ |
1380 | if (handled) |
1381 | inc_irq_stat(apic_perf_irqs); | |
1382 | ||
a29aa8a7 RR |
1383 | return handled; |
1384 | } | |
39d81eab | 1385 | |
cdd6c482 | 1386 | void perf_events_lapic_init(void) |
241771ef | 1387 | { |
04da8a43 | 1388 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
241771ef | 1389 | return; |
85cf9dba | 1390 | |
241771ef | 1391 | /* |
c323d95f | 1392 | * Always use NMI for PMU |
241771ef | 1393 | */ |
c323d95f | 1394 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
241771ef IM |
1395 | } |
1396 | ||
9326638c | 1397 | static int |
9c48f1c6 | 1398 | perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs) |
241771ef | 1399 | { |
14c63f17 DH |
1400 | u64 start_clock; |
1401 | u64 finish_clock; | |
e8a923cc | 1402 | int ret; |
14c63f17 | 1403 | |
cdd6c482 | 1404 | if (!atomic_read(&active_events)) |
9c48f1c6 | 1405 | return NMI_DONE; |
4177c42a | 1406 | |
e8a923cc | 1407 | start_clock = sched_clock(); |
14c63f17 | 1408 | ret = x86_pmu.handle_irq(regs); |
e8a923cc | 1409 | finish_clock = sched_clock(); |
14c63f17 DH |
1410 | |
1411 | perf_sample_event_took(finish_clock - start_clock); | |
1412 | ||
1413 | return ret; | |
241771ef | 1414 | } |
9326638c | 1415 | NOKPROBE_SYMBOL(perf_event_nmi_handler); |
241771ef | 1416 | |
de0428a7 KW |
1417 | struct event_constraint emptyconstraint; |
1418 | struct event_constraint unconstrained; | |
f87ad35d | 1419 | |
148f9bb8 | 1420 | static int |
3f6da390 PZ |
1421 | x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) |
1422 | { | |
1423 | unsigned int cpu = (long)hcpu; | |
7fdba1ca | 1424 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); |
90413464 | 1425 | int i, ret = NOTIFY_OK; |
3f6da390 PZ |
1426 | |
1427 | switch (action & ~CPU_TASKS_FROZEN) { | |
1428 | case CPU_UP_PREPARE: | |
90413464 SE |
1429 | for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) |
1430 | cpuc->kfree_on_online[i] = NULL; | |
3f6da390 | 1431 | if (x86_pmu.cpu_prepare) |
b38b24ea | 1432 | ret = x86_pmu.cpu_prepare(cpu); |
3f6da390 PZ |
1433 | break; |
1434 | ||
1435 | case CPU_STARTING: | |
1436 | if (x86_pmu.cpu_starting) | |
1437 | x86_pmu.cpu_starting(cpu); | |
1438 | break; | |
1439 | ||
7fdba1ca | 1440 | case CPU_ONLINE: |
90413464 SE |
1441 | for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) { |
1442 | kfree(cpuc->kfree_on_online[i]); | |
1443 | cpuc->kfree_on_online[i] = NULL; | |
1444 | } | |
7fdba1ca PZ |
1445 | break; |
1446 | ||
3f6da390 PZ |
1447 | case CPU_DYING: |
1448 | if (x86_pmu.cpu_dying) | |
1449 | x86_pmu.cpu_dying(cpu); | |
1450 | break; | |
1451 | ||
b38b24ea | 1452 | case CPU_UP_CANCELED: |
3f6da390 PZ |
1453 | case CPU_DEAD: |
1454 | if (x86_pmu.cpu_dead) | |
1455 | x86_pmu.cpu_dead(cpu); | |
1456 | break; | |
1457 | ||
1458 | default: | |
1459 | break; | |
1460 | } | |
1461 | ||
b38b24ea | 1462 | return ret; |
3f6da390 PZ |
1463 | } |
1464 | ||
12558038 CG |
1465 | static void __init pmu_check_apic(void) |
1466 | { | |
1467 | if (cpu_has_apic) | |
1468 | return; | |
1469 | ||
1470 | x86_pmu.apic = 0; | |
1471 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); | |
1472 | pr_info("no hardware sampling interrupt available.\n"); | |
c184c980 VW |
1473 | |
1474 | /* | |
1475 | * If we have a PMU initialized but no APIC | |
1476 | * interrupts, we cannot sample hardware | |
1477 | * events (user-space has to fall back and | |
1478 | * sample via a hrtimer based software event): | |
1479 | */ | |
1480 | pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT; | |
1481 | ||
12558038 CG |
1482 | } |
1483 | ||
641cc938 JO |
1484 | static struct attribute_group x86_pmu_format_group = { |
1485 | .name = "format", | |
1486 | .attrs = NULL, | |
1487 | }; | |
1488 | ||
8300daa2 JO |
1489 | /* |
1490 | * Remove all undefined events (x86_pmu.event_map(id) == 0) | |
1491 | * out of events_attr attributes. | |
1492 | */ | |
1493 | static void __init filter_events(struct attribute **attrs) | |
1494 | { | |
3a54aaa0 SE |
1495 | struct device_attribute *d; |
1496 | struct perf_pmu_events_attr *pmu_attr; | |
8300daa2 JO |
1497 | int i, j; |
1498 | ||
1499 | for (i = 0; attrs[i]; i++) { | |
3a54aaa0 SE |
1500 | d = (struct device_attribute *)attrs[i]; |
1501 | pmu_attr = container_of(d, struct perf_pmu_events_attr, attr); | |
1502 | /* str trumps id */ | |
1503 | if (pmu_attr->event_str) | |
1504 | continue; | |
8300daa2 JO |
1505 | if (x86_pmu.event_map(i)) |
1506 | continue; | |
1507 | ||
1508 | for (j = i; attrs[j]; j++) | |
1509 | attrs[j] = attrs[j + 1]; | |
1510 | ||
1511 | /* Check the shifted attr. */ | |
1512 | i--; | |
1513 | } | |
1514 | } | |
1515 | ||
1a6461b1 AK |
1516 | /* Merge two pointer arrays */ |
1517 | static __init struct attribute **merge_attr(struct attribute **a, struct attribute **b) | |
1518 | { | |
1519 | struct attribute **new; | |
1520 | int j, i; | |
1521 | ||
1522 | for (j = 0; a[j]; j++) | |
1523 | ; | |
1524 | for (i = 0; b[i]; i++) | |
1525 | j++; | |
1526 | j++; | |
1527 | ||
1528 | new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL); | |
1529 | if (!new) | |
1530 | return NULL; | |
1531 | ||
1532 | j = 0; | |
1533 | for (i = 0; a[i]; i++) | |
1534 | new[j++] = a[i]; | |
1535 | for (i = 0; b[i]; i++) | |
1536 | new[j++] = b[i]; | |
1537 | new[j] = NULL; | |
1538 | ||
1539 | return new; | |
1540 | } | |
1541 | ||
f20093ee | 1542 | ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, |
a4747393 JO |
1543 | char *page) |
1544 | { | |
1545 | struct perf_pmu_events_attr *pmu_attr = \ | |
1546 | container_of(attr, struct perf_pmu_events_attr, attr); | |
a4747393 | 1547 | u64 config = x86_pmu.event_map(pmu_attr->id); |
a4747393 | 1548 | |
3a54aaa0 SE |
1549 | /* string trumps id */ |
1550 | if (pmu_attr->event_str) | |
1551 | return sprintf(page, "%s", pmu_attr->event_str); | |
a4747393 | 1552 | |
3a54aaa0 SE |
1553 | return x86_pmu.events_sysfs_show(page, config); |
1554 | } | |
a4747393 JO |
1555 | |
1556 | EVENT_ATTR(cpu-cycles, CPU_CYCLES ); | |
1557 | EVENT_ATTR(instructions, INSTRUCTIONS ); | |
1558 | EVENT_ATTR(cache-references, CACHE_REFERENCES ); | |
1559 | EVENT_ATTR(cache-misses, CACHE_MISSES ); | |
1560 | EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS ); | |
1561 | EVENT_ATTR(branch-misses, BRANCH_MISSES ); | |
1562 | EVENT_ATTR(bus-cycles, BUS_CYCLES ); | |
1563 | EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND ); | |
1564 | EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND ); | |
1565 | EVENT_ATTR(ref-cycles, REF_CPU_CYCLES ); | |
1566 | ||
1567 | static struct attribute *empty_attrs; | |
1568 | ||
95d18aa2 | 1569 | static struct attribute *events_attr[] = { |
a4747393 JO |
1570 | EVENT_PTR(CPU_CYCLES), |
1571 | EVENT_PTR(INSTRUCTIONS), | |
1572 | EVENT_PTR(CACHE_REFERENCES), | |
1573 | EVENT_PTR(CACHE_MISSES), | |
1574 | EVENT_PTR(BRANCH_INSTRUCTIONS), | |
1575 | EVENT_PTR(BRANCH_MISSES), | |
1576 | EVENT_PTR(BUS_CYCLES), | |
1577 | EVENT_PTR(STALLED_CYCLES_FRONTEND), | |
1578 | EVENT_PTR(STALLED_CYCLES_BACKEND), | |
1579 | EVENT_PTR(REF_CPU_CYCLES), | |
1580 | NULL, | |
1581 | }; | |
1582 | ||
1583 | static struct attribute_group x86_pmu_events_group = { | |
1584 | .name = "events", | |
1585 | .attrs = events_attr, | |
1586 | }; | |
1587 | ||
0bf79d44 | 1588 | ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event) |
43c032fe | 1589 | { |
43c032fe JO |
1590 | u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8; |
1591 | u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24; | |
1592 | bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE); | |
1593 | bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL); | |
1594 | bool any = (config & ARCH_PERFMON_EVENTSEL_ANY); | |
1595 | bool inv = (config & ARCH_PERFMON_EVENTSEL_INV); | |
1596 | ssize_t ret; | |
1597 | ||
1598 | /* | |
1599 | * We have whole page size to spend and just little data | |
1600 | * to write, so we can safely use sprintf. | |
1601 | */ | |
1602 | ret = sprintf(page, "event=0x%02llx", event); | |
1603 | ||
1604 | if (umask) | |
1605 | ret += sprintf(page + ret, ",umask=0x%02llx", umask); | |
1606 | ||
1607 | if (edge) | |
1608 | ret += sprintf(page + ret, ",edge"); | |
1609 | ||
1610 | if (pc) | |
1611 | ret += sprintf(page + ret, ",pc"); | |
1612 | ||
1613 | if (any) | |
1614 | ret += sprintf(page + ret, ",any"); | |
1615 | ||
1616 | if (inv) | |
1617 | ret += sprintf(page + ret, ",inv"); | |
1618 | ||
1619 | if (cmask) | |
1620 | ret += sprintf(page + ret, ",cmask=0x%02llx", cmask); | |
1621 | ||
1622 | ret += sprintf(page + ret, "\n"); | |
1623 | ||
1624 | return ret; | |
1625 | } | |
1626 | ||
dda99116 | 1627 | static int __init init_hw_perf_events(void) |
b56a3802 | 1628 | { |
c1d6f42f | 1629 | struct x86_pmu_quirk *quirk; |
72eae04d RR |
1630 | int err; |
1631 | ||
cdd6c482 | 1632 | pr_info("Performance Events: "); |
1123e3ad | 1633 | |
b56a3802 JSR |
1634 | switch (boot_cpu_data.x86_vendor) { |
1635 | case X86_VENDOR_INTEL: | |
72eae04d | 1636 | err = intel_pmu_init(); |
b56a3802 | 1637 | break; |
f87ad35d | 1638 | case X86_VENDOR_AMD: |
72eae04d | 1639 | err = amd_pmu_init(); |
f87ad35d | 1640 | break; |
4138960a | 1641 | default: |
8a3da6c7 | 1642 | err = -ENOTSUPP; |
b56a3802 | 1643 | } |
1123e3ad | 1644 | if (err != 0) { |
cdd6c482 | 1645 | pr_cont("no PMU driver, software events only.\n"); |
004417a6 | 1646 | return 0; |
1123e3ad | 1647 | } |
b56a3802 | 1648 | |
12558038 CG |
1649 | pmu_check_apic(); |
1650 | ||
33c6d6a7 | 1651 | /* sanity check that the hardware exists or is emulated */ |
4407204c | 1652 | if (!check_hw_exists()) |
004417a6 | 1653 | return 0; |
33c6d6a7 | 1654 | |
1123e3ad | 1655 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
faa28ae0 | 1656 | |
e97df763 PZ |
1657 | x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */ |
1658 | ||
c1d6f42f PZ |
1659 | for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next) |
1660 | quirk->func(); | |
3c44780b | 1661 | |
a1eac7ac RR |
1662 | if (!x86_pmu.intel_ctrl) |
1663 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; | |
241771ef | 1664 | |
cdd6c482 | 1665 | perf_events_lapic_init(); |
9c48f1c6 | 1666 | register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI"); |
1123e3ad | 1667 | |
63b14649 | 1668 | unconstrained = (struct event_constraint) |
948b1bb8 | 1669 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, |
9fac2cf3 | 1670 | 0, x86_pmu.num_counters, 0, 0); |
63b14649 | 1671 | |
641cc938 | 1672 | x86_pmu_format_group.attrs = x86_pmu.format_attrs; |
0c9d42ed | 1673 | |
f20093ee SE |
1674 | if (x86_pmu.event_attrs) |
1675 | x86_pmu_events_group.attrs = x86_pmu.event_attrs; | |
1676 | ||
a4747393 JO |
1677 | if (!x86_pmu.events_sysfs_show) |
1678 | x86_pmu_events_group.attrs = &empty_attrs; | |
8300daa2 JO |
1679 | else |
1680 | filter_events(x86_pmu_events_group.attrs); | |
a4747393 | 1681 | |
1a6461b1 AK |
1682 | if (x86_pmu.cpu_events) { |
1683 | struct attribute **tmp; | |
1684 | ||
1685 | tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events); | |
1686 | if (!WARN_ON(!tmp)) | |
1687 | x86_pmu_events_group.attrs = tmp; | |
1688 | } | |
1689 | ||
57c0c15b | 1690 | pr_info("... version: %d\n", x86_pmu.version); |
948b1bb8 RR |
1691 | pr_info("... bit width: %d\n", x86_pmu.cntval_bits); |
1692 | pr_info("... generic registers: %d\n", x86_pmu.num_counters); | |
1693 | pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); | |
57c0c15b | 1694 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
948b1bb8 | 1695 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed); |
d6dc0b4e | 1696 | pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl); |
3f6da390 | 1697 | |
2e80a82a | 1698 | perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); |
3f6da390 | 1699 | perf_cpu_notifier(x86_pmu_notifier); |
004417a6 PZ |
1700 | |
1701 | return 0; | |
241771ef | 1702 | } |
004417a6 | 1703 | early_initcall(init_hw_perf_events); |
621a01ea | 1704 | |
cdd6c482 | 1705 | static inline void x86_pmu_read(struct perf_event *event) |
ee06094f | 1706 | { |
cc2ad4ba | 1707 | x86_perf_event_update(event); |
ee06094f IM |
1708 | } |
1709 | ||
4d1c52b0 LM |
1710 | /* |
1711 | * Start group events scheduling transaction | |
1712 | * Set the flag to make pmu::enable() not perform the | |
1713 | * schedulability test, it will be performed at commit time | |
1714 | */ | |
51b0fe39 | 1715 | static void x86_pmu_start_txn(struct pmu *pmu) |
4d1c52b0 | 1716 | { |
33696fc0 | 1717 | perf_pmu_disable(pmu); |
0a3aee0d TH |
1718 | __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN); |
1719 | __this_cpu_write(cpu_hw_events.n_txn, 0); | |
4d1c52b0 LM |
1720 | } |
1721 | ||
1722 | /* | |
1723 | * Stop group events scheduling transaction | |
1724 | * Clear the flag and pmu::enable() will perform the | |
1725 | * schedulability test. | |
1726 | */ | |
51b0fe39 | 1727 | static void x86_pmu_cancel_txn(struct pmu *pmu) |
4d1c52b0 | 1728 | { |
0a3aee0d | 1729 | __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN); |
90151c35 | 1730 | /* |
c347a2f1 PZ |
1731 | * Truncate collected array by the number of events added in this |
1732 | * transaction. See x86_pmu_add() and x86_pmu_*_txn(). | |
90151c35 | 1733 | */ |
0a3aee0d TH |
1734 | __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn)); |
1735 | __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn)); | |
33696fc0 | 1736 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1737 | } |
1738 | ||
1739 | /* | |
1740 | * Commit group events scheduling transaction | |
1741 | * Perform the group schedulability test as a whole | |
1742 | * Return 0 if success | |
c347a2f1 PZ |
1743 | * |
1744 | * Does not cancel the transaction on failure; expects the caller to do this. | |
4d1c52b0 | 1745 | */ |
51b0fe39 | 1746 | static int x86_pmu_commit_txn(struct pmu *pmu) |
4d1c52b0 | 1747 | { |
89cbc767 | 1748 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
4d1c52b0 LM |
1749 | int assign[X86_PMC_IDX_MAX]; |
1750 | int n, ret; | |
1751 | ||
1752 | n = cpuc->n_events; | |
1753 | ||
1754 | if (!x86_pmu_initialized()) | |
1755 | return -EAGAIN; | |
1756 | ||
1757 | ret = x86_pmu.schedule_events(cpuc, n, assign); | |
1758 | if (ret) | |
1759 | return ret; | |
1760 | ||
1761 | /* | |
1762 | * copy new assignment, now we know it is possible | |
1763 | * will be used by hw_perf_enable() | |
1764 | */ | |
1765 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
1766 | ||
8d2cacbb | 1767 | cpuc->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1768 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1769 | return 0; |
1770 | } | |
cd8a38d3 SE |
1771 | /* |
1772 | * a fake_cpuc is used to validate event groups. Due to | |
1773 | * the extra reg logic, we need to also allocate a fake | |
1774 | * per_core and per_cpu structure. Otherwise, group events | |
1775 | * using extra reg may conflict without the kernel being | |
1776 | * able to catch this when the last event gets added to | |
1777 | * the group. | |
1778 | */ | |
1779 | static void free_fake_cpuc(struct cpu_hw_events *cpuc) | |
1780 | { | |
1781 | kfree(cpuc->shared_regs); | |
1782 | kfree(cpuc); | |
1783 | } | |
1784 | ||
1785 | static struct cpu_hw_events *allocate_fake_cpuc(void) | |
1786 | { | |
1787 | struct cpu_hw_events *cpuc; | |
1788 | int cpu = raw_smp_processor_id(); | |
1789 | ||
1790 | cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL); | |
1791 | if (!cpuc) | |
1792 | return ERR_PTR(-ENOMEM); | |
1793 | ||
1794 | /* only needed, if we have extra_regs */ | |
1795 | if (x86_pmu.extra_regs) { | |
1796 | cpuc->shared_regs = allocate_shared_regs(cpu); | |
1797 | if (!cpuc->shared_regs) | |
1798 | goto error; | |
1799 | } | |
b430f7c4 | 1800 | cpuc->is_fake = 1; |
cd8a38d3 SE |
1801 | return cpuc; |
1802 | error: | |
1803 | free_fake_cpuc(cpuc); | |
1804 | return ERR_PTR(-ENOMEM); | |
1805 | } | |
4d1c52b0 | 1806 | |
ca037701 PZ |
1807 | /* |
1808 | * validate that we can schedule this event | |
1809 | */ | |
1810 | static int validate_event(struct perf_event *event) | |
1811 | { | |
1812 | struct cpu_hw_events *fake_cpuc; | |
1813 | struct event_constraint *c; | |
1814 | int ret = 0; | |
1815 | ||
cd8a38d3 SE |
1816 | fake_cpuc = allocate_fake_cpuc(); |
1817 | if (IS_ERR(fake_cpuc)) | |
1818 | return PTR_ERR(fake_cpuc); | |
ca037701 | 1819 | |
79cba822 | 1820 | c = x86_pmu.get_event_constraints(fake_cpuc, -1, event); |
ca037701 PZ |
1821 | |
1822 | if (!c || !c->weight) | |
aa2bc1ad | 1823 | ret = -EINVAL; |
ca037701 PZ |
1824 | |
1825 | if (x86_pmu.put_event_constraints) | |
1826 | x86_pmu.put_event_constraints(fake_cpuc, event); | |
1827 | ||
cd8a38d3 | 1828 | free_fake_cpuc(fake_cpuc); |
ca037701 PZ |
1829 | |
1830 | return ret; | |
1831 | } | |
1832 | ||
1da53e02 SE |
1833 | /* |
1834 | * validate a single event group | |
1835 | * | |
1836 | * validation include: | |
184f412c IM |
1837 | * - check events are compatible which each other |
1838 | * - events do not compete for the same counter | |
1839 | * - number of events <= number of counters | |
1da53e02 SE |
1840 | * |
1841 | * validation ensures the group can be loaded onto the | |
1842 | * PMU if it was the only group available. | |
1843 | */ | |
fe9081cc PZ |
1844 | static int validate_group(struct perf_event *event) |
1845 | { | |
1da53e02 | 1846 | struct perf_event *leader = event->group_leader; |
502568d5 | 1847 | struct cpu_hw_events *fake_cpuc; |
aa2bc1ad | 1848 | int ret = -EINVAL, n; |
fe9081cc | 1849 | |
cd8a38d3 SE |
1850 | fake_cpuc = allocate_fake_cpuc(); |
1851 | if (IS_ERR(fake_cpuc)) | |
1852 | return PTR_ERR(fake_cpuc); | |
1da53e02 SE |
1853 | /* |
1854 | * the event is not yet connected with its | |
1855 | * siblings therefore we must first collect | |
1856 | * existing siblings, then add the new event | |
1857 | * before we can simulate the scheduling | |
1858 | */ | |
502568d5 | 1859 | n = collect_events(fake_cpuc, leader, true); |
1da53e02 | 1860 | if (n < 0) |
cd8a38d3 | 1861 | goto out; |
fe9081cc | 1862 | |
502568d5 PZ |
1863 | fake_cpuc->n_events = n; |
1864 | n = collect_events(fake_cpuc, event, false); | |
1da53e02 | 1865 | if (n < 0) |
cd8a38d3 | 1866 | goto out; |
fe9081cc | 1867 | |
502568d5 | 1868 | fake_cpuc->n_events = n; |
1da53e02 | 1869 | |
a072738e | 1870 | ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); |
502568d5 | 1871 | |
502568d5 | 1872 | out: |
cd8a38d3 | 1873 | free_fake_cpuc(fake_cpuc); |
502568d5 | 1874 | return ret; |
fe9081cc PZ |
1875 | } |
1876 | ||
dda99116 | 1877 | static int x86_pmu_event_init(struct perf_event *event) |
621a01ea | 1878 | { |
51b0fe39 | 1879 | struct pmu *tmp; |
621a01ea IM |
1880 | int err; |
1881 | ||
b0a873eb PZ |
1882 | switch (event->attr.type) { |
1883 | case PERF_TYPE_RAW: | |
1884 | case PERF_TYPE_HARDWARE: | |
1885 | case PERF_TYPE_HW_CACHE: | |
1886 | break; | |
1887 | ||
1888 | default: | |
1889 | return -ENOENT; | |
1890 | } | |
1891 | ||
1892 | err = __x86_pmu_event_init(event); | |
fe9081cc | 1893 | if (!err) { |
8113070d SE |
1894 | /* |
1895 | * we temporarily connect event to its pmu | |
1896 | * such that validate_group() can classify | |
1897 | * it as an x86 event using is_x86_event() | |
1898 | */ | |
1899 | tmp = event->pmu; | |
1900 | event->pmu = &pmu; | |
1901 | ||
fe9081cc PZ |
1902 | if (event->group_leader != event) |
1903 | err = validate_group(event); | |
ca037701 PZ |
1904 | else |
1905 | err = validate_event(event); | |
8113070d SE |
1906 | |
1907 | event->pmu = tmp; | |
fe9081cc | 1908 | } |
a1792cda | 1909 | if (err) { |
cdd6c482 IM |
1910 | if (event->destroy) |
1911 | event->destroy(event); | |
a1792cda | 1912 | } |
621a01ea | 1913 | |
7911d3f7 AL |
1914 | if (ACCESS_ONCE(x86_pmu.attr_rdpmc)) |
1915 | event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED; | |
1916 | ||
b0a873eb | 1917 | return err; |
621a01ea | 1918 | } |
d7d59fb3 | 1919 | |
7911d3f7 AL |
1920 | static void refresh_pce(void *ignored) |
1921 | { | |
1922 | if (current->mm) | |
1923 | load_mm_cr4(current->mm); | |
1924 | } | |
1925 | ||
1926 | static void x86_pmu_event_mapped(struct perf_event *event) | |
1927 | { | |
1928 | if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED)) | |
1929 | return; | |
1930 | ||
1931 | if (atomic_inc_return(¤t->mm->context.perf_rdpmc_allowed) == 1) | |
1932 | on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1); | |
1933 | } | |
1934 | ||
1935 | static void x86_pmu_event_unmapped(struct perf_event *event) | |
1936 | { | |
1937 | if (!current->mm) | |
1938 | return; | |
1939 | ||
1940 | if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED)) | |
1941 | return; | |
1942 | ||
1943 | if (atomic_dec_and_test(¤t->mm->context.perf_rdpmc_allowed)) | |
1944 | on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1); | |
1945 | } | |
1946 | ||
fe4a3308 PZ |
1947 | static int x86_pmu_event_idx(struct perf_event *event) |
1948 | { | |
1949 | int idx = event->hw.idx; | |
1950 | ||
7911d3f7 | 1951 | if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED)) |
c7206205 PZ |
1952 | return 0; |
1953 | ||
15c7ad51 RR |
1954 | if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) { |
1955 | idx -= INTEL_PMC_IDX_FIXED; | |
fe4a3308 PZ |
1956 | idx |= 1 << 30; |
1957 | } | |
1958 | ||
1959 | return idx + 1; | |
1960 | } | |
1961 | ||
0c9d42ed PZ |
1962 | static ssize_t get_attr_rdpmc(struct device *cdev, |
1963 | struct device_attribute *attr, | |
1964 | char *buf) | |
1965 | { | |
1966 | return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc); | |
1967 | } | |
1968 | ||
0c9d42ed PZ |
1969 | static ssize_t set_attr_rdpmc(struct device *cdev, |
1970 | struct device_attribute *attr, | |
1971 | const char *buf, size_t count) | |
1972 | { | |
e2b297fc SK |
1973 | unsigned long val; |
1974 | ssize_t ret; | |
1975 | ||
1976 | ret = kstrtoul(buf, 0, &val); | |
1977 | if (ret) | |
1978 | return ret; | |
e97df763 | 1979 | |
a6673429 AL |
1980 | if (val > 2) |
1981 | return -EINVAL; | |
1982 | ||
e97df763 PZ |
1983 | if (x86_pmu.attr_rdpmc_broken) |
1984 | return -ENOTSUPP; | |
0c9d42ed | 1985 | |
a6673429 AL |
1986 | if ((val == 2) != (x86_pmu.attr_rdpmc == 2)) { |
1987 | /* | |
1988 | * Changing into or out of always available, aka | |
1989 | * perf-event-bypassing mode. This path is extremely slow, | |
1990 | * but only root can trigger it, so it's okay. | |
1991 | */ | |
1992 | if (val == 2) | |
1993 | static_key_slow_inc(&rdpmc_always_available); | |
1994 | else | |
1995 | static_key_slow_dec(&rdpmc_always_available); | |
1996 | on_each_cpu(refresh_pce, NULL, 1); | |
1997 | } | |
1998 | ||
1999 | x86_pmu.attr_rdpmc = val; | |
2000 | ||
0c9d42ed PZ |
2001 | return count; |
2002 | } | |
2003 | ||
2004 | static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc); | |
2005 | ||
2006 | static struct attribute *x86_pmu_attrs[] = { | |
2007 | &dev_attr_rdpmc.attr, | |
2008 | NULL, | |
2009 | }; | |
2010 | ||
2011 | static struct attribute_group x86_pmu_attr_group = { | |
2012 | .attrs = x86_pmu_attrs, | |
2013 | }; | |
2014 | ||
2015 | static const struct attribute_group *x86_pmu_attr_groups[] = { | |
2016 | &x86_pmu_attr_group, | |
641cc938 | 2017 | &x86_pmu_format_group, |
a4747393 | 2018 | &x86_pmu_events_group, |
0c9d42ed PZ |
2019 | NULL, |
2020 | }; | |
2021 | ||
ba532500 | 2022 | static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) |
d010b332 | 2023 | { |
ba532500 YZ |
2024 | if (x86_pmu.sched_task) |
2025 | x86_pmu.sched_task(ctx, sched_in); | |
d010b332 SE |
2026 | } |
2027 | ||
c93dc84c PZ |
2028 | void perf_check_microcode(void) |
2029 | { | |
2030 | if (x86_pmu.check_microcode) | |
2031 | x86_pmu.check_microcode(); | |
2032 | } | |
2033 | EXPORT_SYMBOL_GPL(perf_check_microcode); | |
2034 | ||
b0a873eb | 2035 | static struct pmu pmu = { |
d010b332 SE |
2036 | .pmu_enable = x86_pmu_enable, |
2037 | .pmu_disable = x86_pmu_disable, | |
a4eaf7f1 | 2038 | |
c93dc84c | 2039 | .attr_groups = x86_pmu_attr_groups, |
0c9d42ed | 2040 | |
c93dc84c | 2041 | .event_init = x86_pmu_event_init, |
a4eaf7f1 | 2042 | |
7911d3f7 AL |
2043 | .event_mapped = x86_pmu_event_mapped, |
2044 | .event_unmapped = x86_pmu_event_unmapped, | |
2045 | ||
d010b332 SE |
2046 | .add = x86_pmu_add, |
2047 | .del = x86_pmu_del, | |
2048 | .start = x86_pmu_start, | |
2049 | .stop = x86_pmu_stop, | |
2050 | .read = x86_pmu_read, | |
a4eaf7f1 | 2051 | |
c93dc84c PZ |
2052 | .start_txn = x86_pmu_start_txn, |
2053 | .cancel_txn = x86_pmu_cancel_txn, | |
2054 | .commit_txn = x86_pmu_commit_txn, | |
fe4a3308 | 2055 | |
c93dc84c | 2056 | .event_idx = x86_pmu_event_idx, |
ba532500 | 2057 | .sched_task = x86_pmu_sched_task, |
e18bf526 | 2058 | .task_ctx_size = sizeof(struct x86_perf_task_context), |
b0a873eb PZ |
2059 | }; |
2060 | ||
c1317ec2 AL |
2061 | void arch_perf_update_userpage(struct perf_event *event, |
2062 | struct perf_event_mmap_page *userpg, u64 now) | |
e3f3541c | 2063 | { |
20d1c86a PZ |
2064 | struct cyc2ns_data *data; |
2065 | ||
fa731587 PZ |
2066 | userpg->cap_user_time = 0; |
2067 | userpg->cap_user_time_zero = 0; | |
7911d3f7 AL |
2068 | userpg->cap_user_rdpmc = |
2069 | !!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED); | |
c7206205 PZ |
2070 | userpg->pmc_width = x86_pmu.cntval_bits; |
2071 | ||
35af99e6 | 2072 | if (!sched_clock_stable()) |
e3f3541c PZ |
2073 | return; |
2074 | ||
20d1c86a PZ |
2075 | data = cyc2ns_read_begin(); |
2076 | ||
34f43927 PZ |
2077 | /* |
2078 | * Internal timekeeping for enabled/running/stopped times | |
2079 | * is always in the local_clock domain. | |
2080 | */ | |
fa731587 | 2081 | userpg->cap_user_time = 1; |
20d1c86a PZ |
2082 | userpg->time_mult = data->cyc2ns_mul; |
2083 | userpg->time_shift = data->cyc2ns_shift; | |
2084 | userpg->time_offset = data->cyc2ns_offset - now; | |
c73deb6a | 2085 | |
34f43927 PZ |
2086 | /* |
2087 | * cap_user_time_zero doesn't make sense when we're using a different | |
2088 | * time base for the records. | |
2089 | */ | |
2090 | if (event->clock == &local_clock) { | |
2091 | userpg->cap_user_time_zero = 1; | |
2092 | userpg->time_zero = data->cyc2ns_offset; | |
2093 | } | |
20d1c86a PZ |
2094 | |
2095 | cyc2ns_read_end(data); | |
e3f3541c PZ |
2096 | } |
2097 | ||
d7d59fb3 PZ |
2098 | /* |
2099 | * callchain support | |
2100 | */ | |
2101 | ||
d7d59fb3 PZ |
2102 | static int backtrace_stack(void *data, char *name) |
2103 | { | |
038e836e | 2104 | return 0; |
d7d59fb3 PZ |
2105 | } |
2106 | ||
2107 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
2108 | { | |
2109 | struct perf_callchain_entry *entry = data; | |
2110 | ||
70791ce9 | 2111 | perf_callchain_store(entry, addr); |
d7d59fb3 PZ |
2112 | } |
2113 | ||
2114 | static const struct stacktrace_ops backtrace_ops = { | |
d7d59fb3 PZ |
2115 | .stack = backtrace_stack, |
2116 | .address = backtrace_address, | |
06d65bda | 2117 | .walk_stack = print_context_stack_bp, |
d7d59fb3 PZ |
2118 | }; |
2119 | ||
56962b44 FW |
2120 | void |
2121 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 | 2122 | { |
927c7a9e FW |
2123 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
2124 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 2125 | return; |
927c7a9e FW |
2126 | } |
2127 | ||
70791ce9 | 2128 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 2129 | |
e8e999cf | 2130 | dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry); |
d7d59fb3 PZ |
2131 | } |
2132 | ||
bc6ca7b3 AS |
2133 | static inline int |
2134 | valid_user_frame(const void __user *fp, unsigned long size) | |
2135 | { | |
2136 | return (__range_not_ok(fp, size, TASK_SIZE) == 0); | |
2137 | } | |
2138 | ||
d07bdfd3 PZ |
2139 | static unsigned long get_segment_base(unsigned int segment) |
2140 | { | |
2141 | struct desc_struct *desc; | |
2142 | int idx = segment >> 3; | |
2143 | ||
2144 | if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) { | |
2145 | if (idx > LDT_ENTRIES) | |
2146 | return 0; | |
2147 | ||
2148 | if (idx > current->active_mm->context.size) | |
2149 | return 0; | |
2150 | ||
2151 | desc = current->active_mm->context.ldt; | |
2152 | } else { | |
2153 | if (idx > GDT_ENTRIES) | |
2154 | return 0; | |
2155 | ||
89cbc767 | 2156 | desc = raw_cpu_ptr(gdt_page.gdt); |
d07bdfd3 PZ |
2157 | } |
2158 | ||
2159 | return get_desc_base(desc + idx); | |
2160 | } | |
2161 | ||
257ef9d2 | 2162 | #ifdef CONFIG_COMPAT |
d1a797f3 PA |
2163 | |
2164 | #include <asm/compat.h> | |
2165 | ||
257ef9d2 TE |
2166 | static inline int |
2167 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
74193ef0 | 2168 | { |
257ef9d2 | 2169 | /* 32-bit process in 64-bit kernel. */ |
d07bdfd3 | 2170 | unsigned long ss_base, cs_base; |
257ef9d2 TE |
2171 | struct stack_frame_ia32 frame; |
2172 | const void __user *fp; | |
74193ef0 | 2173 | |
257ef9d2 TE |
2174 | if (!test_thread_flag(TIF_IA32)) |
2175 | return 0; | |
2176 | ||
d07bdfd3 PZ |
2177 | cs_base = get_segment_base(regs->cs); |
2178 | ss_base = get_segment_base(regs->ss); | |
2179 | ||
2180 | fp = compat_ptr(ss_base + regs->bp); | |
257ef9d2 TE |
2181 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
2182 | unsigned long bytes; | |
2183 | frame.next_frame = 0; | |
2184 | frame.return_address = 0; | |
2185 | ||
2186 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); | |
0a196848 | 2187 | if (bytes != 0) |
257ef9d2 | 2188 | break; |
74193ef0 | 2189 | |
bc6ca7b3 AS |
2190 | if (!valid_user_frame(fp, sizeof(frame))) |
2191 | break; | |
2192 | ||
d07bdfd3 PZ |
2193 | perf_callchain_store(entry, cs_base + frame.return_address); |
2194 | fp = compat_ptr(ss_base + frame.next_frame); | |
257ef9d2 TE |
2195 | } |
2196 | return 1; | |
d7d59fb3 | 2197 | } |
257ef9d2 TE |
2198 | #else |
2199 | static inline int | |
2200 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
2201 | { | |
2202 | return 0; | |
2203 | } | |
2204 | #endif | |
d7d59fb3 | 2205 | |
56962b44 FW |
2206 | void |
2207 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 PZ |
2208 | { |
2209 | struct stack_frame frame; | |
2210 | const void __user *fp; | |
2211 | ||
927c7a9e FW |
2212 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
2213 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 2214 | return; |
927c7a9e | 2215 | } |
5a6cec3a | 2216 | |
d07bdfd3 PZ |
2217 | /* |
2218 | * We don't know what to do with VM86 stacks.. ignore them for now. | |
2219 | */ | |
2220 | if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM)) | |
2221 | return; | |
2222 | ||
74193ef0 | 2223 | fp = (void __user *)regs->bp; |
d7d59fb3 | 2224 | |
70791ce9 | 2225 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 2226 | |
20afc60f AV |
2227 | if (!current->mm) |
2228 | return; | |
2229 | ||
257ef9d2 TE |
2230 | if (perf_callchain_user32(regs, entry)) |
2231 | return; | |
2232 | ||
f9188e02 | 2233 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
257ef9d2 | 2234 | unsigned long bytes; |
038e836e | 2235 | frame.next_frame = NULL; |
d7d59fb3 PZ |
2236 | frame.return_address = 0; |
2237 | ||
257ef9d2 | 2238 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); |
0a196848 | 2239 | if (bytes != 0) |
d7d59fb3 PZ |
2240 | break; |
2241 | ||
bc6ca7b3 AS |
2242 | if (!valid_user_frame(fp, sizeof(frame))) |
2243 | break; | |
2244 | ||
70791ce9 | 2245 | perf_callchain_store(entry, frame.return_address); |
038e836e | 2246 | fp = frame.next_frame; |
d7d59fb3 PZ |
2247 | } |
2248 | } | |
2249 | ||
d07bdfd3 PZ |
2250 | /* |
2251 | * Deal with code segment offsets for the various execution modes: | |
2252 | * | |
2253 | * VM86 - the good olde 16 bit days, where the linear address is | |
2254 | * 20 bits and we use regs->ip + 0x10 * regs->cs. | |
2255 | * | |
2256 | * IA32 - Where we need to look at GDT/LDT segment descriptor tables | |
2257 | * to figure out what the 32bit base address is. | |
2258 | * | |
2259 | * X32 - has TIF_X32 set, but is running in x86_64 | |
2260 | * | |
2261 | * X86_64 - CS,DS,SS,ES are all zero based. | |
2262 | */ | |
2263 | static unsigned long code_segment_base(struct pt_regs *regs) | |
39447b38 | 2264 | { |
383f3af3 AL |
2265 | /* |
2266 | * For IA32 we look at the GDT/LDT segment base to convert the | |
2267 | * effective IP to a linear address. | |
2268 | */ | |
2269 | ||
2270 | #ifdef CONFIG_X86_32 | |
d07bdfd3 PZ |
2271 | /* |
2272 | * If we are in VM86 mode, add the segment offset to convert to a | |
2273 | * linear address. | |
2274 | */ | |
2275 | if (regs->flags & X86_VM_MASK) | |
2276 | return 0x10 * regs->cs; | |
2277 | ||
55474c48 | 2278 | if (user_mode(regs) && regs->cs != __USER_CS) |
d07bdfd3 PZ |
2279 | return get_segment_base(regs->cs); |
2280 | #else | |
c56716af AL |
2281 | if (user_mode(regs) && !user_64bit_mode(regs) && |
2282 | regs->cs != __USER32_CS) | |
2283 | return get_segment_base(regs->cs); | |
d07bdfd3 PZ |
2284 | #endif |
2285 | return 0; | |
2286 | } | |
dcf46b94 | 2287 | |
d07bdfd3 PZ |
2288 | unsigned long perf_instruction_pointer(struct pt_regs *regs) |
2289 | { | |
39447b38 | 2290 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) |
d07bdfd3 | 2291 | return perf_guest_cbs->get_guest_ip(); |
dcf46b94 | 2292 | |
d07bdfd3 | 2293 | return regs->ip + code_segment_base(regs); |
39447b38 ZY |
2294 | } |
2295 | ||
2296 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
2297 | { | |
2298 | int misc = 0; | |
dcf46b94 | 2299 | |
39447b38 | 2300 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
dcf46b94 ZY |
2301 | if (perf_guest_cbs->is_user_mode()) |
2302 | misc |= PERF_RECORD_MISC_GUEST_USER; | |
2303 | else | |
2304 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; | |
2305 | } else { | |
d07bdfd3 | 2306 | if (user_mode(regs)) |
dcf46b94 ZY |
2307 | misc |= PERF_RECORD_MISC_USER; |
2308 | else | |
2309 | misc |= PERF_RECORD_MISC_KERNEL; | |
2310 | } | |
2311 | ||
39447b38 | 2312 | if (regs->flags & PERF_EFLAGS_EXACT) |
ab608344 | 2313 | misc |= PERF_RECORD_MISC_EXACT_IP; |
39447b38 ZY |
2314 | |
2315 | return misc; | |
2316 | } | |
b3d9468a GN |
2317 | |
2318 | void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) | |
2319 | { | |
2320 | cap->version = x86_pmu.version; | |
2321 | cap->num_counters_gp = x86_pmu.num_counters; | |
2322 | cap->num_counters_fixed = x86_pmu.num_counters_fixed; | |
2323 | cap->bit_width_gp = x86_pmu.cntval_bits; | |
2324 | cap->bit_width_fixed = x86_pmu.cntval_bits; | |
2325 | cap->events_mask = (unsigned int)x86_pmu.events_maskl; | |
2326 | cap->events_mask_len = x86_pmu.events_mask_len; | |
2327 | } | |
2328 | EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability); |