Commit | Line | Data |
---|---|---|
241771ef | 1 | /* |
cdd6c482 | 2 | * Performance events x86 architecture code |
241771ef | 3 | * |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
30dd568c | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
1da53e02 | 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
241771ef IM |
11 | * |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | ||
cdd6c482 | 15 | #include <linux/perf_event.h> |
241771ef IM |
16 | #include <linux/capability.h> |
17 | #include <linux/notifier.h> | |
18 | #include <linux/hardirq.h> | |
19 | #include <linux/kprobes.h> | |
4ac13294 | 20 | #include <linux/module.h> |
241771ef IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/sched.h> | |
d7d59fb3 | 23 | #include <linux/uaccess.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
30dd568c | 25 | #include <linux/cpu.h> |
272d30be | 26 | #include <linux/bitops.h> |
0c9d42ed | 27 | #include <linux/device.h> |
241771ef | 28 | |
241771ef | 29 | #include <asm/apic.h> |
d7d59fb3 | 30 | #include <asm/stacktrace.h> |
4e935e47 | 31 | #include <asm/nmi.h> |
69092624 | 32 | #include <asm/smp.h> |
c8e5910e | 33 | #include <asm/alternative.h> |
e3f3541c | 34 | #include <asm/timer.h> |
d07bdfd3 PZ |
35 | #include <asm/desc.h> |
36 | #include <asm/ldt.h> | |
241771ef | 37 | |
de0428a7 KW |
38 | #include "perf_event.h" |
39 | ||
de0428a7 | 40 | struct x86_pmu x86_pmu __read_mostly; |
efc9f05d | 41 | |
de0428a7 | 42 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
b0f3f28e PZ |
43 | .enabled = 1, |
44 | }; | |
241771ef | 45 | |
de0428a7 | 46 | u64 __read_mostly hw_cache_event_ids |
8326f44d IM |
47 | [PERF_COUNT_HW_CACHE_MAX] |
48 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
49 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
de0428a7 | 50 | u64 __read_mostly hw_cache_extra_regs |
e994d7d2 AK |
51 | [PERF_COUNT_HW_CACHE_MAX] |
52 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
53 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
8326f44d | 54 | |
ee06094f | 55 | /* |
cdd6c482 IM |
56 | * Propagate event elapsed time into the generic event. |
57 | * Can only be executed on the CPU where the event is active. | |
ee06094f IM |
58 | * Returns the delta events processed. |
59 | */ | |
de0428a7 | 60 | u64 x86_perf_event_update(struct perf_event *event) |
ee06094f | 61 | { |
cc2ad4ba | 62 | struct hw_perf_event *hwc = &event->hw; |
948b1bb8 | 63 | int shift = 64 - x86_pmu.cntval_bits; |
ec3232bd | 64 | u64 prev_raw_count, new_raw_count; |
cc2ad4ba | 65 | int idx = hwc->idx; |
ec3232bd | 66 | s64 delta; |
ee06094f | 67 | |
15c7ad51 | 68 | if (idx == INTEL_PMC_IDX_FIXED_BTS) |
30dd568c MM |
69 | return 0; |
70 | ||
ee06094f | 71 | /* |
cdd6c482 | 72 | * Careful: an NMI might modify the previous event value. |
ee06094f IM |
73 | * |
74 | * Our tactic to handle this is to first atomically read and | |
75 | * exchange a new raw count - then add that new-prev delta | |
cdd6c482 | 76 | * count to the generic event atomically: |
ee06094f IM |
77 | */ |
78 | again: | |
e7850595 | 79 | prev_raw_count = local64_read(&hwc->prev_count); |
c48b6053 | 80 | rdpmcl(hwc->event_base_rdpmc, new_raw_count); |
ee06094f | 81 | |
e7850595 | 82 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
ee06094f IM |
83 | new_raw_count) != prev_raw_count) |
84 | goto again; | |
85 | ||
86 | /* | |
87 | * Now we have the new raw value and have updated the prev | |
88 | * timestamp already. We can now calculate the elapsed delta | |
cdd6c482 | 89 | * (event-)time and add that to the generic event. |
ee06094f IM |
90 | * |
91 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 92 | * of the count. |
ee06094f | 93 | */ |
ec3232bd PZ |
94 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
95 | delta >>= shift; | |
ee06094f | 96 | |
e7850595 PZ |
97 | local64_add(delta, &event->count); |
98 | local64_sub(delta, &hwc->period_left); | |
4b7bfd0d RR |
99 | |
100 | return new_raw_count; | |
ee06094f IM |
101 | } |
102 | ||
a7e3ed1e AK |
103 | /* |
104 | * Find and validate any extra registers to set up. | |
105 | */ | |
106 | static int x86_pmu_extra_regs(u64 config, struct perf_event *event) | |
107 | { | |
efc9f05d | 108 | struct hw_perf_event_extra *reg; |
a7e3ed1e AK |
109 | struct extra_reg *er; |
110 | ||
efc9f05d | 111 | reg = &event->hw.extra_reg; |
a7e3ed1e AK |
112 | |
113 | if (!x86_pmu.extra_regs) | |
114 | return 0; | |
115 | ||
116 | for (er = x86_pmu.extra_regs; er->msr; er++) { | |
117 | if (er->event != (config & er->config_mask)) | |
118 | continue; | |
119 | if (event->attr.config1 & ~er->valid_mask) | |
120 | return -EINVAL; | |
efc9f05d SE |
121 | |
122 | reg->idx = er->idx; | |
123 | reg->config = event->attr.config1; | |
124 | reg->reg = er->msr; | |
a7e3ed1e AK |
125 | break; |
126 | } | |
127 | return 0; | |
128 | } | |
129 | ||
cdd6c482 | 130 | static atomic_t active_events; |
4e935e47 PZ |
131 | static DEFINE_MUTEX(pmc_reserve_mutex); |
132 | ||
b27ea29c RR |
133 | #ifdef CONFIG_X86_LOCAL_APIC |
134 | ||
4e935e47 PZ |
135 | static bool reserve_pmc_hardware(void) |
136 | { | |
137 | int i; | |
138 | ||
948b1bb8 | 139 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 140 | if (!reserve_perfctr_nmi(x86_pmu_event_addr(i))) |
4e935e47 PZ |
141 | goto perfctr_fail; |
142 | } | |
143 | ||
948b1bb8 | 144 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 145 | if (!reserve_evntsel_nmi(x86_pmu_config_addr(i))) |
4e935e47 PZ |
146 | goto eventsel_fail; |
147 | } | |
148 | ||
149 | return true; | |
150 | ||
151 | eventsel_fail: | |
152 | for (i--; i >= 0; i--) | |
41bf4989 | 153 | release_evntsel_nmi(x86_pmu_config_addr(i)); |
4e935e47 | 154 | |
948b1bb8 | 155 | i = x86_pmu.num_counters; |
4e935e47 PZ |
156 | |
157 | perfctr_fail: | |
158 | for (i--; i >= 0; i--) | |
41bf4989 | 159 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
4e935e47 | 160 | |
4e935e47 PZ |
161 | return false; |
162 | } | |
163 | ||
164 | static void release_pmc_hardware(void) | |
165 | { | |
166 | int i; | |
167 | ||
948b1bb8 | 168 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 RR |
169 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
170 | release_evntsel_nmi(x86_pmu_config_addr(i)); | |
4e935e47 | 171 | } |
4e935e47 PZ |
172 | } |
173 | ||
b27ea29c RR |
174 | #else |
175 | ||
176 | static bool reserve_pmc_hardware(void) { return true; } | |
177 | static void release_pmc_hardware(void) {} | |
178 | ||
179 | #endif | |
180 | ||
33c6d6a7 DZ |
181 | static bool check_hw_exists(void) |
182 | { | |
a5ebe0ba GD |
183 | u64 val, val_fail, val_new= ~0; |
184 | int i, reg, reg_fail, ret = 0; | |
185 | int bios_fail = 0; | |
33c6d6a7 | 186 | |
4407204c PZ |
187 | /* |
188 | * Check to see if the BIOS enabled any of the counters, if so | |
189 | * complain and bail. | |
190 | */ | |
191 | for (i = 0; i < x86_pmu.num_counters; i++) { | |
41bf4989 | 192 | reg = x86_pmu_config_addr(i); |
4407204c PZ |
193 | ret = rdmsrl_safe(reg, &val); |
194 | if (ret) | |
195 | goto msr_fail; | |
a5ebe0ba GD |
196 | if (val & ARCH_PERFMON_EVENTSEL_ENABLE) { |
197 | bios_fail = 1; | |
198 | val_fail = val; | |
199 | reg_fail = reg; | |
200 | } | |
4407204c PZ |
201 | } |
202 | ||
203 | if (x86_pmu.num_counters_fixed) { | |
204 | reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
205 | ret = rdmsrl_safe(reg, &val); | |
206 | if (ret) | |
207 | goto msr_fail; | |
208 | for (i = 0; i < x86_pmu.num_counters_fixed; i++) { | |
a5ebe0ba GD |
209 | if (val & (0x03 << i*4)) { |
210 | bios_fail = 1; | |
211 | val_fail = val; | |
212 | reg_fail = reg; | |
213 | } | |
4407204c PZ |
214 | } |
215 | } | |
216 | ||
217 | /* | |
bffd5fc2 AP |
218 | * Read the current value, change it and read it back to see if it |
219 | * matches, this is needed to detect certain hardware emulators | |
220 | * (qemu/kvm) that don't trap on the MSR access and always return 0s. | |
4407204c | 221 | */ |
f285f92f | 222 | reg = x86_pmu_event_addr(0); |
bffd5fc2 AP |
223 | if (rdmsrl_safe(reg, &val)) |
224 | goto msr_fail; | |
225 | val ^= 0xffffUL; | |
f285f92f RR |
226 | ret = wrmsrl_safe(reg, val); |
227 | ret |= rdmsrl_safe(reg, &val_new); | |
33c6d6a7 | 228 | if (ret || val != val_new) |
4407204c | 229 | goto msr_fail; |
33c6d6a7 | 230 | |
45daae57 IM |
231 | /* |
232 | * We still allow the PMU driver to operate: | |
233 | */ | |
a5ebe0ba GD |
234 | if (bios_fail) { |
235 | printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n"); | |
236 | printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg_fail, val_fail); | |
237 | } | |
45daae57 IM |
238 | |
239 | return true; | |
4407204c PZ |
240 | |
241 | msr_fail: | |
242 | printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n"); | |
f285f92f | 243 | printk(KERN_ERR "Failed to access perfctr msr (MSR %x is %Lx)\n", reg, val_new); |
45daae57 | 244 | |
4407204c | 245 | return false; |
33c6d6a7 DZ |
246 | } |
247 | ||
cdd6c482 | 248 | static void hw_perf_event_destroy(struct perf_event *event) |
4e935e47 | 249 | { |
cdd6c482 | 250 | if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) { |
4e935e47 | 251 | release_pmc_hardware(); |
ca037701 | 252 | release_ds_buffers(); |
4e935e47 PZ |
253 | mutex_unlock(&pmc_reserve_mutex); |
254 | } | |
255 | } | |
256 | ||
85cf9dba RR |
257 | static inline int x86_pmu_initialized(void) |
258 | { | |
259 | return x86_pmu.handle_irq != NULL; | |
260 | } | |
261 | ||
8326f44d | 262 | static inline int |
e994d7d2 | 263 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event) |
8326f44d | 264 | { |
e994d7d2 | 265 | struct perf_event_attr *attr = &event->attr; |
8326f44d IM |
266 | unsigned int cache_type, cache_op, cache_result; |
267 | u64 config, val; | |
268 | ||
269 | config = attr->config; | |
270 | ||
271 | cache_type = (config >> 0) & 0xff; | |
272 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
273 | return -EINVAL; | |
274 | ||
275 | cache_op = (config >> 8) & 0xff; | |
276 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
277 | return -EINVAL; | |
278 | ||
279 | cache_result = (config >> 16) & 0xff; | |
280 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
281 | return -EINVAL; | |
282 | ||
283 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; | |
284 | ||
285 | if (val == 0) | |
286 | return -ENOENT; | |
287 | ||
288 | if (val == -1) | |
289 | return -EINVAL; | |
290 | ||
291 | hwc->config |= val; | |
e994d7d2 AK |
292 | attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result]; |
293 | return x86_pmu_extra_regs(val, event); | |
8326f44d IM |
294 | } |
295 | ||
de0428a7 | 296 | int x86_setup_perfctr(struct perf_event *event) |
c1726f34 RR |
297 | { |
298 | struct perf_event_attr *attr = &event->attr; | |
299 | struct hw_perf_event *hwc = &event->hw; | |
300 | u64 config; | |
301 | ||
6c7e550f | 302 | if (!is_sampling_event(event)) { |
c1726f34 RR |
303 | hwc->sample_period = x86_pmu.max_period; |
304 | hwc->last_period = hwc->sample_period; | |
e7850595 | 305 | local64_set(&hwc->period_left, hwc->sample_period); |
c1726f34 RR |
306 | } else { |
307 | /* | |
308 | * If we have a PMU initialized but no APIC | |
309 | * interrupts, we cannot sample hardware | |
310 | * events (user-space has to fall back and | |
311 | * sample via a hrtimer based software event): | |
312 | */ | |
313 | if (!x86_pmu.apic) | |
314 | return -EOPNOTSUPP; | |
315 | } | |
316 | ||
317 | if (attr->type == PERF_TYPE_RAW) | |
ed13ec58 | 318 | return x86_pmu_extra_regs(event->attr.config, event); |
c1726f34 RR |
319 | |
320 | if (attr->type == PERF_TYPE_HW_CACHE) | |
e994d7d2 | 321 | return set_ext_hw_attr(hwc, event); |
c1726f34 RR |
322 | |
323 | if (attr->config >= x86_pmu.max_events) | |
324 | return -EINVAL; | |
325 | ||
326 | /* | |
327 | * The generic map: | |
328 | */ | |
329 | config = x86_pmu.event_map(attr->config); | |
330 | ||
331 | if (config == 0) | |
332 | return -ENOENT; | |
333 | ||
334 | if (config == -1LL) | |
335 | return -EINVAL; | |
336 | ||
337 | /* | |
338 | * Branch tracing: | |
339 | */ | |
18a073a3 PZ |
340 | if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS && |
341 | !attr->freq && hwc->sample_period == 1) { | |
c1726f34 | 342 | /* BTS is not supported by this architecture. */ |
6809b6ea | 343 | if (!x86_pmu.bts_active) |
c1726f34 RR |
344 | return -EOPNOTSUPP; |
345 | ||
346 | /* BTS is currently only allowed for user-mode. */ | |
347 | if (!attr->exclude_kernel) | |
348 | return -EOPNOTSUPP; | |
349 | } | |
350 | ||
351 | hwc->config |= config; | |
352 | ||
353 | return 0; | |
354 | } | |
4261e0e0 | 355 | |
ff3fb511 SE |
356 | /* |
357 | * check that branch_sample_type is compatible with | |
358 | * settings needed for precise_ip > 1 which implies | |
359 | * using the LBR to capture ALL taken branches at the | |
360 | * priv levels of the measurement | |
361 | */ | |
362 | static inline int precise_br_compat(struct perf_event *event) | |
363 | { | |
364 | u64 m = event->attr.branch_sample_type; | |
365 | u64 b = 0; | |
366 | ||
367 | /* must capture all branches */ | |
368 | if (!(m & PERF_SAMPLE_BRANCH_ANY)) | |
369 | return 0; | |
370 | ||
371 | m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER; | |
372 | ||
373 | if (!event->attr.exclude_user) | |
374 | b |= PERF_SAMPLE_BRANCH_USER; | |
375 | ||
376 | if (!event->attr.exclude_kernel) | |
377 | b |= PERF_SAMPLE_BRANCH_KERNEL; | |
378 | ||
379 | /* | |
380 | * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86 | |
381 | */ | |
382 | ||
383 | return m == b; | |
384 | } | |
385 | ||
de0428a7 | 386 | int x86_pmu_hw_config(struct perf_event *event) |
a072738e | 387 | { |
ab608344 PZ |
388 | if (event->attr.precise_ip) { |
389 | int precise = 0; | |
390 | ||
391 | /* Support for constant skid */ | |
c93dc84c | 392 | if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) { |
ab608344 PZ |
393 | precise++; |
394 | ||
5553be26 PZ |
395 | /* Support for IP fixup */ |
396 | if (x86_pmu.lbr_nr) | |
397 | precise++; | |
398 | } | |
ab608344 PZ |
399 | |
400 | if (event->attr.precise_ip > precise) | |
401 | return -EOPNOTSUPP; | |
ff3fb511 SE |
402 | /* |
403 | * check that PEBS LBR correction does not conflict with | |
404 | * whatever the user is asking with attr->branch_sample_type | |
405 | */ | |
406 | if (event->attr.precise_ip > 1) { | |
407 | u64 *br_type = &event->attr.branch_sample_type; | |
408 | ||
409 | if (has_branch_stack(event)) { | |
410 | if (!precise_br_compat(event)) | |
411 | return -EOPNOTSUPP; | |
412 | ||
413 | /* branch_sample_type is compatible */ | |
414 | ||
415 | } else { | |
416 | /* | |
417 | * user did not specify branch_sample_type | |
418 | * | |
419 | * For PEBS fixups, we capture all | |
420 | * the branches at the priv level of the | |
421 | * event. | |
422 | */ | |
423 | *br_type = PERF_SAMPLE_BRANCH_ANY; | |
424 | ||
425 | if (!event->attr.exclude_user) | |
426 | *br_type |= PERF_SAMPLE_BRANCH_USER; | |
427 | ||
428 | if (!event->attr.exclude_kernel) | |
429 | *br_type |= PERF_SAMPLE_BRANCH_KERNEL; | |
430 | } | |
431 | } | |
ab608344 PZ |
432 | } |
433 | ||
a072738e CG |
434 | /* |
435 | * Generate PMC IRQs: | |
436 | * (keep 'enabled' bit clear for now) | |
437 | */ | |
b4cdc5c2 | 438 | event->hw.config = ARCH_PERFMON_EVENTSEL_INT; |
a072738e CG |
439 | |
440 | /* | |
441 | * Count user and OS events unless requested not to | |
442 | */ | |
b4cdc5c2 PZ |
443 | if (!event->attr.exclude_user) |
444 | event->hw.config |= ARCH_PERFMON_EVENTSEL_USR; | |
445 | if (!event->attr.exclude_kernel) | |
446 | event->hw.config |= ARCH_PERFMON_EVENTSEL_OS; | |
a072738e | 447 | |
b4cdc5c2 PZ |
448 | if (event->attr.type == PERF_TYPE_RAW) |
449 | event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; | |
a072738e | 450 | |
9d0fcba6 | 451 | return x86_setup_perfctr(event); |
a098f448 RR |
452 | } |
453 | ||
241771ef | 454 | /* |
0d48696f | 455 | * Setup the hardware configuration for a given attr_type |
241771ef | 456 | */ |
b0a873eb | 457 | static int __x86_pmu_event_init(struct perf_event *event) |
241771ef | 458 | { |
4e935e47 | 459 | int err; |
241771ef | 460 | |
85cf9dba RR |
461 | if (!x86_pmu_initialized()) |
462 | return -ENODEV; | |
241771ef | 463 | |
4e935e47 | 464 | err = 0; |
cdd6c482 | 465 | if (!atomic_inc_not_zero(&active_events)) { |
4e935e47 | 466 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 467 | if (atomic_read(&active_events) == 0) { |
30dd568c MM |
468 | if (!reserve_pmc_hardware()) |
469 | err = -EBUSY; | |
f80c9e30 PZ |
470 | else |
471 | reserve_ds_buffers(); | |
30dd568c MM |
472 | } |
473 | if (!err) | |
cdd6c482 | 474 | atomic_inc(&active_events); |
4e935e47 PZ |
475 | mutex_unlock(&pmc_reserve_mutex); |
476 | } | |
477 | if (err) | |
478 | return err; | |
479 | ||
cdd6c482 | 480 | event->destroy = hw_perf_event_destroy; |
a1792cda | 481 | |
4261e0e0 RR |
482 | event->hw.idx = -1; |
483 | event->hw.last_cpu = -1; | |
484 | event->hw.last_tag = ~0ULL; | |
b690081d | 485 | |
efc9f05d SE |
486 | /* mark unused */ |
487 | event->hw.extra_reg.idx = EXTRA_REG_NONE; | |
b36817e8 SE |
488 | event->hw.branch_reg.idx = EXTRA_REG_NONE; |
489 | ||
9d0fcba6 | 490 | return x86_pmu.hw_config(event); |
4261e0e0 RR |
491 | } |
492 | ||
de0428a7 | 493 | void x86_pmu_disable_all(void) |
f87ad35d | 494 | { |
cdd6c482 | 495 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
9e35ad38 PZ |
496 | int idx; |
497 | ||
948b1bb8 | 498 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
b0f3f28e PZ |
499 | u64 val; |
500 | ||
43f6201a | 501 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 502 | continue; |
41bf4989 | 503 | rdmsrl(x86_pmu_config_addr(idx), val); |
bb1165d6 | 504 | if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) |
4295ee62 | 505 | continue; |
bb1165d6 | 506 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
41bf4989 | 507 | wrmsrl(x86_pmu_config_addr(idx), val); |
f87ad35d | 508 | } |
f87ad35d JSR |
509 | } |
510 | ||
a4eaf7f1 | 511 | static void x86_pmu_disable(struct pmu *pmu) |
b56a3802 | 512 | { |
1da53e02 SE |
513 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
514 | ||
85cf9dba | 515 | if (!x86_pmu_initialized()) |
9e35ad38 | 516 | return; |
1da53e02 | 517 | |
1a6e21f7 PZ |
518 | if (!cpuc->enabled) |
519 | return; | |
520 | ||
521 | cpuc->n_added = 0; | |
522 | cpuc->enabled = 0; | |
523 | barrier(); | |
1da53e02 SE |
524 | |
525 | x86_pmu.disable_all(); | |
b56a3802 | 526 | } |
241771ef | 527 | |
de0428a7 | 528 | void x86_pmu_enable_all(int added) |
f87ad35d | 529 | { |
cdd6c482 | 530 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
f87ad35d JSR |
531 | int idx; |
532 | ||
948b1bb8 | 533 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
d45dd923 | 534 | struct hw_perf_event *hwc = &cpuc->events[idx]->hw; |
b0f3f28e | 535 | |
43f6201a | 536 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 537 | continue; |
984b838c | 538 | |
d45dd923 | 539 | __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); |
f87ad35d JSR |
540 | } |
541 | } | |
542 | ||
51b0fe39 | 543 | static struct pmu pmu; |
1da53e02 SE |
544 | |
545 | static inline int is_x86_event(struct perf_event *event) | |
546 | { | |
547 | return event->pmu == &pmu; | |
548 | } | |
549 | ||
1e2ad28f RR |
550 | /* |
551 | * Event scheduler state: | |
552 | * | |
553 | * Assign events iterating over all events and counters, beginning | |
554 | * with events with least weights first. Keep the current iterator | |
555 | * state in struct sched_state. | |
556 | */ | |
557 | struct sched_state { | |
558 | int weight; | |
559 | int event; /* event index */ | |
560 | int counter; /* counter index */ | |
561 | int unassigned; /* number of events to be assigned left */ | |
562 | unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
563 | }; | |
564 | ||
bc1738f6 RR |
565 | /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */ |
566 | #define SCHED_STATES_MAX 2 | |
567 | ||
1e2ad28f RR |
568 | struct perf_sched { |
569 | int max_weight; | |
570 | int max_events; | |
43b45780 | 571 | struct perf_event **events; |
1e2ad28f | 572 | struct sched_state state; |
bc1738f6 RR |
573 | int saved_states; |
574 | struct sched_state saved[SCHED_STATES_MAX]; | |
1e2ad28f RR |
575 | }; |
576 | ||
577 | /* | |
578 | * Initialize interator that runs through all events and counters. | |
579 | */ | |
43b45780 | 580 | static void perf_sched_init(struct perf_sched *sched, struct perf_event **events, |
1e2ad28f RR |
581 | int num, int wmin, int wmax) |
582 | { | |
583 | int idx; | |
584 | ||
585 | memset(sched, 0, sizeof(*sched)); | |
586 | sched->max_events = num; | |
587 | sched->max_weight = wmax; | |
43b45780 | 588 | sched->events = events; |
1e2ad28f RR |
589 | |
590 | for (idx = 0; idx < num; idx++) { | |
43b45780 | 591 | if (events[idx]->hw.constraint->weight == wmin) |
1e2ad28f RR |
592 | break; |
593 | } | |
594 | ||
595 | sched->state.event = idx; /* start with min weight */ | |
596 | sched->state.weight = wmin; | |
597 | sched->state.unassigned = num; | |
598 | } | |
599 | ||
bc1738f6 RR |
600 | static void perf_sched_save_state(struct perf_sched *sched) |
601 | { | |
602 | if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX)) | |
603 | return; | |
604 | ||
605 | sched->saved[sched->saved_states] = sched->state; | |
606 | sched->saved_states++; | |
607 | } | |
608 | ||
609 | static bool perf_sched_restore_state(struct perf_sched *sched) | |
610 | { | |
611 | if (!sched->saved_states) | |
612 | return false; | |
613 | ||
614 | sched->saved_states--; | |
615 | sched->state = sched->saved[sched->saved_states]; | |
616 | ||
617 | /* continue with next counter: */ | |
618 | clear_bit(sched->state.counter++, sched->state.used); | |
619 | ||
620 | return true; | |
621 | } | |
622 | ||
1e2ad28f RR |
623 | /* |
624 | * Select a counter for the current event to schedule. Return true on | |
625 | * success. | |
626 | */ | |
bc1738f6 | 627 | static bool __perf_sched_find_counter(struct perf_sched *sched) |
1e2ad28f RR |
628 | { |
629 | struct event_constraint *c; | |
630 | int idx; | |
631 | ||
632 | if (!sched->state.unassigned) | |
633 | return false; | |
634 | ||
635 | if (sched->state.event >= sched->max_events) | |
636 | return false; | |
637 | ||
43b45780 | 638 | c = sched->events[sched->state.event]->hw.constraint; |
4defea85 | 639 | /* Prefer fixed purpose counters */ |
15c7ad51 RR |
640 | if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) { |
641 | idx = INTEL_PMC_IDX_FIXED; | |
307b1cd7 | 642 | for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) { |
4defea85 PZ |
643 | if (!__test_and_set_bit(idx, sched->state.used)) |
644 | goto done; | |
645 | } | |
646 | } | |
1e2ad28f RR |
647 | /* Grab the first unused counter starting with idx */ |
648 | idx = sched->state.counter; | |
15c7ad51 | 649 | for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) { |
1e2ad28f | 650 | if (!__test_and_set_bit(idx, sched->state.used)) |
4defea85 | 651 | goto done; |
1e2ad28f | 652 | } |
1e2ad28f | 653 | |
4defea85 PZ |
654 | return false; |
655 | ||
656 | done: | |
657 | sched->state.counter = idx; | |
1e2ad28f | 658 | |
bc1738f6 RR |
659 | if (c->overlap) |
660 | perf_sched_save_state(sched); | |
661 | ||
662 | return true; | |
663 | } | |
664 | ||
665 | static bool perf_sched_find_counter(struct perf_sched *sched) | |
666 | { | |
667 | while (!__perf_sched_find_counter(sched)) { | |
668 | if (!perf_sched_restore_state(sched)) | |
669 | return false; | |
670 | } | |
671 | ||
1e2ad28f RR |
672 | return true; |
673 | } | |
674 | ||
675 | /* | |
676 | * Go through all unassigned events and find the next one to schedule. | |
677 | * Take events with the least weight first. Return true on success. | |
678 | */ | |
679 | static bool perf_sched_next_event(struct perf_sched *sched) | |
680 | { | |
681 | struct event_constraint *c; | |
682 | ||
683 | if (!sched->state.unassigned || !--sched->state.unassigned) | |
684 | return false; | |
685 | ||
686 | do { | |
687 | /* next event */ | |
688 | sched->state.event++; | |
689 | if (sched->state.event >= sched->max_events) { | |
690 | /* next weight */ | |
691 | sched->state.event = 0; | |
692 | sched->state.weight++; | |
693 | if (sched->state.weight > sched->max_weight) | |
694 | return false; | |
695 | } | |
43b45780 | 696 | c = sched->events[sched->state.event]->hw.constraint; |
1e2ad28f RR |
697 | } while (c->weight != sched->state.weight); |
698 | ||
699 | sched->state.counter = 0; /* start with first counter */ | |
700 | ||
701 | return true; | |
702 | } | |
703 | ||
704 | /* | |
705 | * Assign a counter for each event. | |
706 | */ | |
43b45780 | 707 | int perf_assign_events(struct perf_event **events, int n, |
4b4969b1 | 708 | int wmin, int wmax, int *assign) |
1e2ad28f RR |
709 | { |
710 | struct perf_sched sched; | |
711 | ||
43b45780 | 712 | perf_sched_init(&sched, events, n, wmin, wmax); |
1e2ad28f RR |
713 | |
714 | do { | |
715 | if (!perf_sched_find_counter(&sched)) | |
716 | break; /* failed */ | |
717 | if (assign) | |
718 | assign[sched.state.event] = sched.state.counter; | |
719 | } while (perf_sched_next_event(&sched)); | |
720 | ||
721 | return sched.state.unassigned; | |
722 | } | |
723 | ||
de0428a7 | 724 | int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) |
1da53e02 | 725 | { |
43b45780 | 726 | struct event_constraint *c; |
1da53e02 | 727 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
1e2ad28f | 728 | int i, wmin, wmax, num = 0; |
1da53e02 SE |
729 | struct hw_perf_event *hwc; |
730 | ||
731 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
732 | ||
1e2ad28f | 733 | for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) { |
43b45780 | 734 | hwc = &cpuc->event_list[i]->hw; |
b622d644 | 735 | c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]); |
43b45780 AH |
736 | hwc->constraint = c; |
737 | ||
1e2ad28f RR |
738 | wmin = min(wmin, c->weight); |
739 | wmax = max(wmax, c->weight); | |
1da53e02 SE |
740 | } |
741 | ||
8113070d SE |
742 | /* |
743 | * fastpath, try to reuse previous register | |
744 | */ | |
c933c1a6 | 745 | for (i = 0; i < n; i++) { |
8113070d | 746 | hwc = &cpuc->event_list[i]->hw; |
43b45780 | 747 | c = hwc->constraint; |
8113070d SE |
748 | |
749 | /* never assigned */ | |
750 | if (hwc->idx == -1) | |
751 | break; | |
752 | ||
753 | /* constraint still honored */ | |
63b14649 | 754 | if (!test_bit(hwc->idx, c->idxmsk)) |
8113070d SE |
755 | break; |
756 | ||
757 | /* not already used */ | |
758 | if (test_bit(hwc->idx, used_mask)) | |
759 | break; | |
760 | ||
34538ee7 | 761 | __set_bit(hwc->idx, used_mask); |
8113070d SE |
762 | if (assign) |
763 | assign[i] = hwc->idx; | |
764 | } | |
8113070d | 765 | |
1e2ad28f RR |
766 | /* slow path */ |
767 | if (i != n) | |
43b45780 AH |
768 | num = perf_assign_events(cpuc->event_list, n, wmin, |
769 | wmax, assign); | |
8113070d | 770 | |
1da53e02 SE |
771 | /* |
772 | * scheduling failed or is just a simulation, | |
773 | * free resources if necessary | |
774 | */ | |
775 | if (!assign || num) { | |
776 | for (i = 0; i < n; i++) { | |
777 | if (x86_pmu.put_event_constraints) | |
778 | x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]); | |
779 | } | |
780 | } | |
aa2bc1ad | 781 | return num ? -EINVAL : 0; |
1da53e02 SE |
782 | } |
783 | ||
784 | /* | |
785 | * dogrp: true if must collect siblings events (group) | |
786 | * returns total number of events and error code | |
787 | */ | |
788 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) | |
789 | { | |
790 | struct perf_event *event; | |
791 | int n, max_count; | |
792 | ||
948b1bb8 | 793 | max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed; |
1da53e02 SE |
794 | |
795 | /* current number of events already accepted */ | |
796 | n = cpuc->n_events; | |
797 | ||
798 | if (is_x86_event(leader)) { | |
799 | if (n >= max_count) | |
aa2bc1ad | 800 | return -EINVAL; |
1da53e02 SE |
801 | cpuc->event_list[n] = leader; |
802 | n++; | |
803 | } | |
804 | if (!dogrp) | |
805 | return n; | |
806 | ||
807 | list_for_each_entry(event, &leader->sibling_list, group_entry) { | |
808 | if (!is_x86_event(event) || | |
8113070d | 809 | event->state <= PERF_EVENT_STATE_OFF) |
1da53e02 SE |
810 | continue; |
811 | ||
812 | if (n >= max_count) | |
aa2bc1ad | 813 | return -EINVAL; |
1da53e02 SE |
814 | |
815 | cpuc->event_list[n] = event; | |
816 | n++; | |
817 | } | |
818 | return n; | |
819 | } | |
820 | ||
1da53e02 | 821 | static inline void x86_assign_hw_event(struct perf_event *event, |
447a194b | 822 | struct cpu_hw_events *cpuc, int i) |
1da53e02 | 823 | { |
447a194b SE |
824 | struct hw_perf_event *hwc = &event->hw; |
825 | ||
826 | hwc->idx = cpuc->assign[i]; | |
827 | hwc->last_cpu = smp_processor_id(); | |
828 | hwc->last_tag = ++cpuc->tags[i]; | |
1da53e02 | 829 | |
15c7ad51 | 830 | if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) { |
1da53e02 SE |
831 | hwc->config_base = 0; |
832 | hwc->event_base = 0; | |
15c7ad51 | 833 | } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) { |
1da53e02 | 834 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
15c7ad51 RR |
835 | hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED); |
836 | hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30; | |
1da53e02 | 837 | } else { |
73d6e522 RR |
838 | hwc->config_base = x86_pmu_config_addr(hwc->idx); |
839 | hwc->event_base = x86_pmu_event_addr(hwc->idx); | |
0fbdad07 | 840 | hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx); |
1da53e02 SE |
841 | } |
842 | } | |
843 | ||
447a194b SE |
844 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
845 | struct cpu_hw_events *cpuc, | |
846 | int i) | |
847 | { | |
848 | return hwc->idx == cpuc->assign[i] && | |
849 | hwc->last_cpu == smp_processor_id() && | |
850 | hwc->last_tag == cpuc->tags[i]; | |
851 | } | |
852 | ||
a4eaf7f1 | 853 | static void x86_pmu_start(struct perf_event *event, int flags); |
2e841873 | 854 | |
a4eaf7f1 | 855 | static void x86_pmu_enable(struct pmu *pmu) |
ee06094f | 856 | { |
1da53e02 SE |
857 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
858 | struct perf_event *event; | |
859 | struct hw_perf_event *hwc; | |
11164cd4 | 860 | int i, added = cpuc->n_added; |
1da53e02 | 861 | |
85cf9dba | 862 | if (!x86_pmu_initialized()) |
2b9ff0db | 863 | return; |
1a6e21f7 PZ |
864 | |
865 | if (cpuc->enabled) | |
866 | return; | |
867 | ||
1da53e02 | 868 | if (cpuc->n_added) { |
19925ce7 | 869 | int n_running = cpuc->n_events - cpuc->n_added; |
1da53e02 SE |
870 | /* |
871 | * apply assignment obtained either from | |
872 | * hw_perf_group_sched_in() or x86_pmu_enable() | |
873 | * | |
874 | * step1: save events moving to new counters | |
875 | * step2: reprogram moved events into new counters | |
876 | */ | |
19925ce7 | 877 | for (i = 0; i < n_running; i++) { |
1da53e02 SE |
878 | event = cpuc->event_list[i]; |
879 | hwc = &event->hw; | |
880 | ||
447a194b SE |
881 | /* |
882 | * we can avoid reprogramming counter if: | |
883 | * - assigned same counter as last time | |
884 | * - running on same CPU as last time | |
885 | * - no other event has used the counter since | |
886 | */ | |
887 | if (hwc->idx == -1 || | |
888 | match_prev_assignment(hwc, cpuc, i)) | |
1da53e02 SE |
889 | continue; |
890 | ||
a4eaf7f1 PZ |
891 | /* |
892 | * Ensure we don't accidentally enable a stopped | |
893 | * counter simply because we rescheduled. | |
894 | */ | |
895 | if (hwc->state & PERF_HES_STOPPED) | |
896 | hwc->state |= PERF_HES_ARCH; | |
897 | ||
898 | x86_pmu_stop(event, PERF_EF_UPDATE); | |
1da53e02 SE |
899 | } |
900 | ||
901 | for (i = 0; i < cpuc->n_events; i++) { | |
1da53e02 SE |
902 | event = cpuc->event_list[i]; |
903 | hwc = &event->hw; | |
904 | ||
45e16a68 | 905 | if (!match_prev_assignment(hwc, cpuc, i)) |
447a194b | 906 | x86_assign_hw_event(event, cpuc, i); |
45e16a68 PZ |
907 | else if (i < n_running) |
908 | continue; | |
1da53e02 | 909 | |
a4eaf7f1 PZ |
910 | if (hwc->state & PERF_HES_ARCH) |
911 | continue; | |
912 | ||
913 | x86_pmu_start(event, PERF_EF_RELOAD); | |
1da53e02 SE |
914 | } |
915 | cpuc->n_added = 0; | |
916 | perf_events_lapic_init(); | |
917 | } | |
1a6e21f7 PZ |
918 | |
919 | cpuc->enabled = 1; | |
920 | barrier(); | |
921 | ||
11164cd4 | 922 | x86_pmu.enable_all(added); |
ee06094f | 923 | } |
ee06094f | 924 | |
245b2e70 | 925 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
241771ef | 926 | |
ee06094f IM |
927 | /* |
928 | * Set the next IRQ period, based on the hwc->period_left value. | |
cdd6c482 | 929 | * To be called with the event disabled in hw: |
ee06094f | 930 | */ |
de0428a7 | 931 | int x86_perf_event_set_period(struct perf_event *event) |
241771ef | 932 | { |
07088edb | 933 | struct hw_perf_event *hwc = &event->hw; |
e7850595 | 934 | s64 left = local64_read(&hwc->period_left); |
e4abb5d4 | 935 | s64 period = hwc->sample_period; |
7645a24c | 936 | int ret = 0, idx = hwc->idx; |
ee06094f | 937 | |
15c7ad51 | 938 | if (idx == INTEL_PMC_IDX_FIXED_BTS) |
30dd568c MM |
939 | return 0; |
940 | ||
ee06094f | 941 | /* |
af901ca1 | 942 | * If we are way outside a reasonable range then just skip forward: |
ee06094f IM |
943 | */ |
944 | if (unlikely(left <= -period)) { | |
945 | left = period; | |
e7850595 | 946 | local64_set(&hwc->period_left, left); |
9e350de3 | 947 | hwc->last_period = period; |
e4abb5d4 | 948 | ret = 1; |
ee06094f IM |
949 | } |
950 | ||
951 | if (unlikely(left <= 0)) { | |
952 | left += period; | |
e7850595 | 953 | local64_set(&hwc->period_left, left); |
9e350de3 | 954 | hwc->last_period = period; |
e4abb5d4 | 955 | ret = 1; |
ee06094f | 956 | } |
1c80f4b5 | 957 | /* |
dfc65094 | 958 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
1c80f4b5 IM |
959 | */ |
960 | if (unlikely(left < 2)) | |
961 | left = 2; | |
241771ef | 962 | |
e4abb5d4 PZ |
963 | if (left > x86_pmu.max_period) |
964 | left = x86_pmu.max_period; | |
965 | ||
245b2e70 | 966 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
ee06094f IM |
967 | |
968 | /* | |
cdd6c482 | 969 | * The hw event starts counting from this event offset, |
ee06094f IM |
970 | * mark it to be able to extra future deltas: |
971 | */ | |
e7850595 | 972 | local64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 973 | |
73d6e522 | 974 | wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac CG |
975 | |
976 | /* | |
977 | * Due to erratum on certan cpu we need | |
978 | * a second write to be sure the register | |
979 | * is updated properly | |
980 | */ | |
981 | if (x86_pmu.perfctr_second_write) { | |
73d6e522 | 982 | wrmsrl(hwc->event_base, |
948b1bb8 | 983 | (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac | 984 | } |
e4abb5d4 | 985 | |
cdd6c482 | 986 | perf_event_update_userpage(event); |
194002b2 | 987 | |
e4abb5d4 | 988 | return ret; |
2f18d1e8 IM |
989 | } |
990 | ||
de0428a7 | 991 | void x86_pmu_enable_event(struct perf_event *event) |
7c90cc45 | 992 | { |
0a3aee0d | 993 | if (__this_cpu_read(cpu_hw_events.enabled)) |
31fa58af RR |
994 | __x86_pmu_enable_event(&event->hw, |
995 | ARCH_PERFMON_EVENTSEL_ENABLE); | |
241771ef IM |
996 | } |
997 | ||
b690081d | 998 | /* |
a4eaf7f1 | 999 | * Add a single event to the PMU. |
1da53e02 SE |
1000 | * |
1001 | * The event is added to the group of enabled events | |
1002 | * but only if it can be scehduled with existing events. | |
fe9081cc | 1003 | */ |
a4eaf7f1 | 1004 | static int x86_pmu_add(struct perf_event *event, int flags) |
fe9081cc PZ |
1005 | { |
1006 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1da53e02 SE |
1007 | struct hw_perf_event *hwc; |
1008 | int assign[X86_PMC_IDX_MAX]; | |
1009 | int n, n0, ret; | |
fe9081cc | 1010 | |
1da53e02 | 1011 | hwc = &event->hw; |
fe9081cc | 1012 | |
33696fc0 | 1013 | perf_pmu_disable(event->pmu); |
1da53e02 | 1014 | n0 = cpuc->n_events; |
24cd7f54 PZ |
1015 | ret = n = collect_events(cpuc, event, false); |
1016 | if (ret < 0) | |
1017 | goto out; | |
53b441a5 | 1018 | |
a4eaf7f1 PZ |
1019 | hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; |
1020 | if (!(flags & PERF_EF_START)) | |
1021 | hwc->state |= PERF_HES_ARCH; | |
1022 | ||
4d1c52b0 LM |
1023 | /* |
1024 | * If group events scheduling transaction was started, | |
0d2eb44f | 1025 | * skip the schedulability test here, it will be performed |
a4eaf7f1 | 1026 | * at commit time (->commit_txn) as a whole |
4d1c52b0 | 1027 | */ |
8d2cacbb | 1028 | if (cpuc->group_flag & PERF_EVENT_TXN) |
24cd7f54 | 1029 | goto done_collect; |
4d1c52b0 | 1030 | |
a072738e | 1031 | ret = x86_pmu.schedule_events(cpuc, n, assign); |
1da53e02 | 1032 | if (ret) |
24cd7f54 | 1033 | goto out; |
1da53e02 SE |
1034 | /* |
1035 | * copy new assignment, now we know it is possible | |
1036 | * will be used by hw_perf_enable() | |
1037 | */ | |
1038 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
7e2ae347 | 1039 | |
24cd7f54 | 1040 | done_collect: |
1da53e02 | 1041 | cpuc->n_events = n; |
356e1f2e | 1042 | cpuc->n_added += n - n0; |
90151c35 | 1043 | cpuc->n_txn += n - n0; |
95cdd2e7 | 1044 | |
24cd7f54 PZ |
1045 | ret = 0; |
1046 | out: | |
33696fc0 | 1047 | perf_pmu_enable(event->pmu); |
24cd7f54 | 1048 | return ret; |
241771ef IM |
1049 | } |
1050 | ||
a4eaf7f1 | 1051 | static void x86_pmu_start(struct perf_event *event, int flags) |
d76a0812 | 1052 | { |
c08053e6 PZ |
1053 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
1054 | int idx = event->hw.idx; | |
1055 | ||
a4eaf7f1 PZ |
1056 | if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) |
1057 | return; | |
1058 | ||
1059 | if (WARN_ON_ONCE(idx == -1)) | |
1060 | return; | |
1061 | ||
1062 | if (flags & PERF_EF_RELOAD) { | |
1063 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
1064 | x86_perf_event_set_period(event); | |
1065 | } | |
1066 | ||
1067 | event->hw.state = 0; | |
d76a0812 | 1068 | |
c08053e6 PZ |
1069 | cpuc->events[idx] = event; |
1070 | __set_bit(idx, cpuc->active_mask); | |
63e6be6d | 1071 | __set_bit(idx, cpuc->running); |
aff3d91a | 1072 | x86_pmu.enable(event); |
c08053e6 | 1073 | perf_event_update_userpage(event); |
a78ac325 PZ |
1074 | } |
1075 | ||
cdd6c482 | 1076 | void perf_event_print_debug(void) |
241771ef | 1077 | { |
2f18d1e8 | 1078 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
ca037701 | 1079 | u64 pebs; |
cdd6c482 | 1080 | struct cpu_hw_events *cpuc; |
5bb9efe3 | 1081 | unsigned long flags; |
1e125676 IM |
1082 | int cpu, idx; |
1083 | ||
948b1bb8 | 1084 | if (!x86_pmu.num_counters) |
1e125676 | 1085 | return; |
241771ef | 1086 | |
5bb9efe3 | 1087 | local_irq_save(flags); |
241771ef IM |
1088 | |
1089 | cpu = smp_processor_id(); | |
cdd6c482 | 1090 | cpuc = &per_cpu(cpu_hw_events, cpu); |
241771ef | 1091 | |
faa28ae0 | 1092 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
1093 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
1094 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
1095 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
1096 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
ca037701 | 1097 | rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); |
a1ef58f4 JSR |
1098 | |
1099 | pr_info("\n"); | |
1100 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
1101 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
1102 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
1103 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
ca037701 | 1104 | pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); |
f87ad35d | 1105 | } |
7645a24c | 1106 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
241771ef | 1107 | |
948b1bb8 | 1108 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
41bf4989 RR |
1109 | rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl); |
1110 | rdmsrl(x86_pmu_event_addr(idx), pmc_count); | |
241771ef | 1111 | |
245b2e70 | 1112 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
241771ef | 1113 | |
a1ef58f4 | 1114 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 1115 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 1116 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 1117 | cpu, idx, pmc_count); |
a1ef58f4 | 1118 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 1119 | cpu, idx, prev_left); |
241771ef | 1120 | } |
948b1bb8 | 1121 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
2f18d1e8 IM |
1122 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
1123 | ||
a1ef58f4 | 1124 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
1125 | cpu, idx, pmc_count); |
1126 | } | |
5bb9efe3 | 1127 | local_irq_restore(flags); |
241771ef IM |
1128 | } |
1129 | ||
de0428a7 | 1130 | void x86_pmu_stop(struct perf_event *event, int flags) |
241771ef | 1131 | { |
d76a0812 | 1132 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
cdd6c482 | 1133 | struct hw_perf_event *hwc = &event->hw; |
241771ef | 1134 | |
a4eaf7f1 PZ |
1135 | if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) { |
1136 | x86_pmu.disable(event); | |
1137 | cpuc->events[hwc->idx] = NULL; | |
1138 | WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); | |
1139 | hwc->state |= PERF_HES_STOPPED; | |
1140 | } | |
30dd568c | 1141 | |
a4eaf7f1 PZ |
1142 | if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { |
1143 | /* | |
1144 | * Drain the remaining delta count out of a event | |
1145 | * that we are disabling: | |
1146 | */ | |
1147 | x86_perf_event_update(event); | |
1148 | hwc->state |= PERF_HES_UPTODATE; | |
1149 | } | |
2e841873 PZ |
1150 | } |
1151 | ||
a4eaf7f1 | 1152 | static void x86_pmu_del(struct perf_event *event, int flags) |
2e841873 PZ |
1153 | { |
1154 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1155 | int i; | |
1156 | ||
90151c35 SE |
1157 | /* |
1158 | * If we're called during a txn, we don't need to do anything. | |
1159 | * The events never got scheduled and ->cancel_txn will truncate | |
1160 | * the event_list. | |
1161 | */ | |
8d2cacbb | 1162 | if (cpuc->group_flag & PERF_EVENT_TXN) |
90151c35 SE |
1163 | return; |
1164 | ||
a4eaf7f1 | 1165 | x86_pmu_stop(event, PERF_EF_UPDATE); |
194002b2 | 1166 | |
1da53e02 SE |
1167 | for (i = 0; i < cpuc->n_events; i++) { |
1168 | if (event == cpuc->event_list[i]) { | |
1169 | ||
1170 | if (x86_pmu.put_event_constraints) | |
1171 | x86_pmu.put_event_constraints(cpuc, event); | |
1172 | ||
1173 | while (++i < cpuc->n_events) | |
1174 | cpuc->event_list[i-1] = cpuc->event_list[i]; | |
1175 | ||
1176 | --cpuc->n_events; | |
6c9687ab | 1177 | break; |
1da53e02 SE |
1178 | } |
1179 | } | |
cdd6c482 | 1180 | perf_event_update_userpage(event); |
241771ef IM |
1181 | } |
1182 | ||
de0428a7 | 1183 | int x86_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 1184 | { |
df1a132b | 1185 | struct perf_sample_data data; |
cdd6c482 IM |
1186 | struct cpu_hw_events *cpuc; |
1187 | struct perf_event *event; | |
11d1578f | 1188 | int idx, handled = 0; |
9029a5e3 IM |
1189 | u64 val; |
1190 | ||
cdd6c482 | 1191 | cpuc = &__get_cpu_var(cpu_hw_events); |
962bf7a6 | 1192 | |
2bce5dac DZ |
1193 | /* |
1194 | * Some chipsets need to unmask the LVTPC in a particular spot | |
1195 | * inside the nmi handler. As a result, the unmasking was pushed | |
1196 | * into all the nmi handlers. | |
1197 | * | |
1198 | * This generic handler doesn't seem to have any issues where the | |
1199 | * unmasking occurs so it was left at the top. | |
1200 | */ | |
1201 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
1202 | ||
948b1bb8 | 1203 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
63e6be6d RR |
1204 | if (!test_bit(idx, cpuc->active_mask)) { |
1205 | /* | |
1206 | * Though we deactivated the counter some cpus | |
1207 | * might still deliver spurious interrupts still | |
1208 | * in flight. Catch them: | |
1209 | */ | |
1210 | if (__test_and_clear_bit(idx, cpuc->running)) | |
1211 | handled++; | |
a29aa8a7 | 1212 | continue; |
63e6be6d | 1213 | } |
962bf7a6 | 1214 | |
cdd6c482 | 1215 | event = cpuc->events[idx]; |
a4016a79 | 1216 | |
cc2ad4ba | 1217 | val = x86_perf_event_update(event); |
948b1bb8 | 1218 | if (val & (1ULL << (x86_pmu.cntval_bits - 1))) |
48e22d56 | 1219 | continue; |
962bf7a6 | 1220 | |
9e350de3 | 1221 | /* |
cdd6c482 | 1222 | * event overflow |
9e350de3 | 1223 | */ |
4177c42a | 1224 | handled++; |
fd0d000b | 1225 | perf_sample_data_init(&data, 0, event->hw.last_period); |
9e350de3 | 1226 | |
07088edb | 1227 | if (!x86_perf_event_set_period(event)) |
e4abb5d4 PZ |
1228 | continue; |
1229 | ||
a8b0ca17 | 1230 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 1231 | x86_pmu_stop(event, 0); |
a29aa8a7 | 1232 | } |
962bf7a6 | 1233 | |
9e350de3 PZ |
1234 | if (handled) |
1235 | inc_irq_stat(apic_perf_irqs); | |
1236 | ||
a29aa8a7 RR |
1237 | return handled; |
1238 | } | |
39d81eab | 1239 | |
cdd6c482 | 1240 | void perf_events_lapic_init(void) |
241771ef | 1241 | { |
04da8a43 | 1242 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
241771ef | 1243 | return; |
85cf9dba | 1244 | |
241771ef | 1245 | /* |
c323d95f | 1246 | * Always use NMI for PMU |
241771ef | 1247 | */ |
c323d95f | 1248 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
241771ef IM |
1249 | } |
1250 | ||
1251 | static int __kprobes | |
9c48f1c6 | 1252 | perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs) |
241771ef | 1253 | { |
cdd6c482 | 1254 | if (!atomic_read(&active_events)) |
9c48f1c6 | 1255 | return NMI_DONE; |
4177c42a | 1256 | |
9c48f1c6 | 1257 | return x86_pmu.handle_irq(regs); |
241771ef IM |
1258 | } |
1259 | ||
de0428a7 KW |
1260 | struct event_constraint emptyconstraint; |
1261 | struct event_constraint unconstrained; | |
f87ad35d | 1262 | |
3f6da390 PZ |
1263 | static int __cpuinit |
1264 | x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) | |
1265 | { | |
1266 | unsigned int cpu = (long)hcpu; | |
7fdba1ca | 1267 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); |
b38b24ea | 1268 | int ret = NOTIFY_OK; |
3f6da390 PZ |
1269 | |
1270 | switch (action & ~CPU_TASKS_FROZEN) { | |
1271 | case CPU_UP_PREPARE: | |
7fdba1ca | 1272 | cpuc->kfree_on_online = NULL; |
3f6da390 | 1273 | if (x86_pmu.cpu_prepare) |
b38b24ea | 1274 | ret = x86_pmu.cpu_prepare(cpu); |
3f6da390 PZ |
1275 | break; |
1276 | ||
1277 | case CPU_STARTING: | |
0c9d42ed PZ |
1278 | if (x86_pmu.attr_rdpmc) |
1279 | set_in_cr4(X86_CR4_PCE); | |
3f6da390 PZ |
1280 | if (x86_pmu.cpu_starting) |
1281 | x86_pmu.cpu_starting(cpu); | |
1282 | break; | |
1283 | ||
7fdba1ca PZ |
1284 | case CPU_ONLINE: |
1285 | kfree(cpuc->kfree_on_online); | |
1286 | break; | |
1287 | ||
3f6da390 PZ |
1288 | case CPU_DYING: |
1289 | if (x86_pmu.cpu_dying) | |
1290 | x86_pmu.cpu_dying(cpu); | |
1291 | break; | |
1292 | ||
b38b24ea | 1293 | case CPU_UP_CANCELED: |
3f6da390 PZ |
1294 | case CPU_DEAD: |
1295 | if (x86_pmu.cpu_dead) | |
1296 | x86_pmu.cpu_dead(cpu); | |
1297 | break; | |
1298 | ||
1299 | default: | |
1300 | break; | |
1301 | } | |
1302 | ||
b38b24ea | 1303 | return ret; |
3f6da390 PZ |
1304 | } |
1305 | ||
12558038 CG |
1306 | static void __init pmu_check_apic(void) |
1307 | { | |
1308 | if (cpu_has_apic) | |
1309 | return; | |
1310 | ||
1311 | x86_pmu.apic = 0; | |
1312 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); | |
1313 | pr_info("no hardware sampling interrupt available.\n"); | |
1314 | } | |
1315 | ||
641cc938 JO |
1316 | static struct attribute_group x86_pmu_format_group = { |
1317 | .name = "format", | |
1318 | .attrs = NULL, | |
1319 | }; | |
1320 | ||
8300daa2 JO |
1321 | /* |
1322 | * Remove all undefined events (x86_pmu.event_map(id) == 0) | |
1323 | * out of events_attr attributes. | |
1324 | */ | |
1325 | static void __init filter_events(struct attribute **attrs) | |
1326 | { | |
3a54aaa0 SE |
1327 | struct device_attribute *d; |
1328 | struct perf_pmu_events_attr *pmu_attr; | |
8300daa2 JO |
1329 | int i, j; |
1330 | ||
1331 | for (i = 0; attrs[i]; i++) { | |
3a54aaa0 SE |
1332 | d = (struct device_attribute *)attrs[i]; |
1333 | pmu_attr = container_of(d, struct perf_pmu_events_attr, attr); | |
1334 | /* str trumps id */ | |
1335 | if (pmu_attr->event_str) | |
1336 | continue; | |
8300daa2 JO |
1337 | if (x86_pmu.event_map(i)) |
1338 | continue; | |
1339 | ||
1340 | for (j = i; attrs[j]; j++) | |
1341 | attrs[j] = attrs[j + 1]; | |
1342 | ||
1343 | /* Check the shifted attr. */ | |
1344 | i--; | |
1345 | } | |
1346 | } | |
1347 | ||
1a6461b1 AK |
1348 | /* Merge two pointer arrays */ |
1349 | static __init struct attribute **merge_attr(struct attribute **a, struct attribute **b) | |
1350 | { | |
1351 | struct attribute **new; | |
1352 | int j, i; | |
1353 | ||
1354 | for (j = 0; a[j]; j++) | |
1355 | ; | |
1356 | for (i = 0; b[i]; i++) | |
1357 | j++; | |
1358 | j++; | |
1359 | ||
1360 | new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL); | |
1361 | if (!new) | |
1362 | return NULL; | |
1363 | ||
1364 | j = 0; | |
1365 | for (i = 0; a[i]; i++) | |
1366 | new[j++] = a[i]; | |
1367 | for (i = 0; b[i]; i++) | |
1368 | new[j++] = b[i]; | |
1369 | new[j] = NULL; | |
1370 | ||
1371 | return new; | |
1372 | } | |
1373 | ||
f20093ee | 1374 | ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, |
a4747393 JO |
1375 | char *page) |
1376 | { | |
1377 | struct perf_pmu_events_attr *pmu_attr = \ | |
1378 | container_of(attr, struct perf_pmu_events_attr, attr); | |
a4747393 | 1379 | u64 config = x86_pmu.event_map(pmu_attr->id); |
a4747393 | 1380 | |
3a54aaa0 SE |
1381 | /* string trumps id */ |
1382 | if (pmu_attr->event_str) | |
1383 | return sprintf(page, "%s", pmu_attr->event_str); | |
a4747393 | 1384 | |
3a54aaa0 SE |
1385 | return x86_pmu.events_sysfs_show(page, config); |
1386 | } | |
a4747393 JO |
1387 | |
1388 | EVENT_ATTR(cpu-cycles, CPU_CYCLES ); | |
1389 | EVENT_ATTR(instructions, INSTRUCTIONS ); | |
1390 | EVENT_ATTR(cache-references, CACHE_REFERENCES ); | |
1391 | EVENT_ATTR(cache-misses, CACHE_MISSES ); | |
1392 | EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS ); | |
1393 | EVENT_ATTR(branch-misses, BRANCH_MISSES ); | |
1394 | EVENT_ATTR(bus-cycles, BUS_CYCLES ); | |
1395 | EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND ); | |
1396 | EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND ); | |
1397 | EVENT_ATTR(ref-cycles, REF_CPU_CYCLES ); | |
1398 | ||
1399 | static struct attribute *empty_attrs; | |
1400 | ||
95d18aa2 | 1401 | static struct attribute *events_attr[] = { |
a4747393 JO |
1402 | EVENT_PTR(CPU_CYCLES), |
1403 | EVENT_PTR(INSTRUCTIONS), | |
1404 | EVENT_PTR(CACHE_REFERENCES), | |
1405 | EVENT_PTR(CACHE_MISSES), | |
1406 | EVENT_PTR(BRANCH_INSTRUCTIONS), | |
1407 | EVENT_PTR(BRANCH_MISSES), | |
1408 | EVENT_PTR(BUS_CYCLES), | |
1409 | EVENT_PTR(STALLED_CYCLES_FRONTEND), | |
1410 | EVENT_PTR(STALLED_CYCLES_BACKEND), | |
1411 | EVENT_PTR(REF_CPU_CYCLES), | |
1412 | NULL, | |
1413 | }; | |
1414 | ||
1415 | static struct attribute_group x86_pmu_events_group = { | |
1416 | .name = "events", | |
1417 | .attrs = events_attr, | |
1418 | }; | |
1419 | ||
0bf79d44 | 1420 | ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event) |
43c032fe | 1421 | { |
43c032fe JO |
1422 | u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8; |
1423 | u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24; | |
1424 | bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE); | |
1425 | bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL); | |
1426 | bool any = (config & ARCH_PERFMON_EVENTSEL_ANY); | |
1427 | bool inv = (config & ARCH_PERFMON_EVENTSEL_INV); | |
1428 | ssize_t ret; | |
1429 | ||
1430 | /* | |
1431 | * We have whole page size to spend and just little data | |
1432 | * to write, so we can safely use sprintf. | |
1433 | */ | |
1434 | ret = sprintf(page, "event=0x%02llx", event); | |
1435 | ||
1436 | if (umask) | |
1437 | ret += sprintf(page + ret, ",umask=0x%02llx", umask); | |
1438 | ||
1439 | if (edge) | |
1440 | ret += sprintf(page + ret, ",edge"); | |
1441 | ||
1442 | if (pc) | |
1443 | ret += sprintf(page + ret, ",pc"); | |
1444 | ||
1445 | if (any) | |
1446 | ret += sprintf(page + ret, ",any"); | |
1447 | ||
1448 | if (inv) | |
1449 | ret += sprintf(page + ret, ",inv"); | |
1450 | ||
1451 | if (cmask) | |
1452 | ret += sprintf(page + ret, ",cmask=0x%02llx", cmask); | |
1453 | ||
1454 | ret += sprintf(page + ret, "\n"); | |
1455 | ||
1456 | return ret; | |
1457 | } | |
1458 | ||
dda99116 | 1459 | static int __init init_hw_perf_events(void) |
b56a3802 | 1460 | { |
c1d6f42f | 1461 | struct x86_pmu_quirk *quirk; |
72eae04d RR |
1462 | int err; |
1463 | ||
cdd6c482 | 1464 | pr_info("Performance Events: "); |
1123e3ad | 1465 | |
b56a3802 JSR |
1466 | switch (boot_cpu_data.x86_vendor) { |
1467 | case X86_VENDOR_INTEL: | |
72eae04d | 1468 | err = intel_pmu_init(); |
b56a3802 | 1469 | break; |
f87ad35d | 1470 | case X86_VENDOR_AMD: |
72eae04d | 1471 | err = amd_pmu_init(); |
f87ad35d | 1472 | break; |
4138960a | 1473 | default: |
004417a6 | 1474 | return 0; |
b56a3802 | 1475 | } |
1123e3ad | 1476 | if (err != 0) { |
cdd6c482 | 1477 | pr_cont("no PMU driver, software events only.\n"); |
004417a6 | 1478 | return 0; |
1123e3ad | 1479 | } |
b56a3802 | 1480 | |
12558038 CG |
1481 | pmu_check_apic(); |
1482 | ||
33c6d6a7 | 1483 | /* sanity check that the hardware exists or is emulated */ |
4407204c | 1484 | if (!check_hw_exists()) |
004417a6 | 1485 | return 0; |
33c6d6a7 | 1486 | |
1123e3ad | 1487 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
faa28ae0 | 1488 | |
c1d6f42f PZ |
1489 | for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next) |
1490 | quirk->func(); | |
3c44780b | 1491 | |
a1eac7ac RR |
1492 | if (!x86_pmu.intel_ctrl) |
1493 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; | |
241771ef | 1494 | |
cdd6c482 | 1495 | perf_events_lapic_init(); |
9c48f1c6 | 1496 | register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI"); |
1123e3ad | 1497 | |
63b14649 | 1498 | unconstrained = (struct event_constraint) |
948b1bb8 | 1499 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, |
9fac2cf3 | 1500 | 0, x86_pmu.num_counters, 0, 0); |
63b14649 | 1501 | |
0c9d42ed | 1502 | x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */ |
641cc938 | 1503 | x86_pmu_format_group.attrs = x86_pmu.format_attrs; |
0c9d42ed | 1504 | |
f20093ee SE |
1505 | if (x86_pmu.event_attrs) |
1506 | x86_pmu_events_group.attrs = x86_pmu.event_attrs; | |
1507 | ||
a4747393 JO |
1508 | if (!x86_pmu.events_sysfs_show) |
1509 | x86_pmu_events_group.attrs = &empty_attrs; | |
8300daa2 JO |
1510 | else |
1511 | filter_events(x86_pmu_events_group.attrs); | |
a4747393 | 1512 | |
1a6461b1 AK |
1513 | if (x86_pmu.cpu_events) { |
1514 | struct attribute **tmp; | |
1515 | ||
1516 | tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events); | |
1517 | if (!WARN_ON(!tmp)) | |
1518 | x86_pmu_events_group.attrs = tmp; | |
1519 | } | |
1520 | ||
57c0c15b | 1521 | pr_info("... version: %d\n", x86_pmu.version); |
948b1bb8 RR |
1522 | pr_info("... bit width: %d\n", x86_pmu.cntval_bits); |
1523 | pr_info("... generic registers: %d\n", x86_pmu.num_counters); | |
1524 | pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); | |
57c0c15b | 1525 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
948b1bb8 | 1526 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed); |
d6dc0b4e | 1527 | pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl); |
3f6da390 | 1528 | |
2e80a82a | 1529 | perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); |
3f6da390 | 1530 | perf_cpu_notifier(x86_pmu_notifier); |
004417a6 PZ |
1531 | |
1532 | return 0; | |
241771ef | 1533 | } |
004417a6 | 1534 | early_initcall(init_hw_perf_events); |
621a01ea | 1535 | |
cdd6c482 | 1536 | static inline void x86_pmu_read(struct perf_event *event) |
ee06094f | 1537 | { |
cc2ad4ba | 1538 | x86_perf_event_update(event); |
ee06094f IM |
1539 | } |
1540 | ||
4d1c52b0 LM |
1541 | /* |
1542 | * Start group events scheduling transaction | |
1543 | * Set the flag to make pmu::enable() not perform the | |
1544 | * schedulability test, it will be performed at commit time | |
1545 | */ | |
51b0fe39 | 1546 | static void x86_pmu_start_txn(struct pmu *pmu) |
4d1c52b0 | 1547 | { |
33696fc0 | 1548 | perf_pmu_disable(pmu); |
0a3aee0d TH |
1549 | __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN); |
1550 | __this_cpu_write(cpu_hw_events.n_txn, 0); | |
4d1c52b0 LM |
1551 | } |
1552 | ||
1553 | /* | |
1554 | * Stop group events scheduling transaction | |
1555 | * Clear the flag and pmu::enable() will perform the | |
1556 | * schedulability test. | |
1557 | */ | |
51b0fe39 | 1558 | static void x86_pmu_cancel_txn(struct pmu *pmu) |
4d1c52b0 | 1559 | { |
0a3aee0d | 1560 | __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN); |
90151c35 SE |
1561 | /* |
1562 | * Truncate the collected events. | |
1563 | */ | |
0a3aee0d TH |
1564 | __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn)); |
1565 | __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn)); | |
33696fc0 | 1566 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1567 | } |
1568 | ||
1569 | /* | |
1570 | * Commit group events scheduling transaction | |
1571 | * Perform the group schedulability test as a whole | |
1572 | * Return 0 if success | |
1573 | */ | |
51b0fe39 | 1574 | static int x86_pmu_commit_txn(struct pmu *pmu) |
4d1c52b0 LM |
1575 | { |
1576 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1577 | int assign[X86_PMC_IDX_MAX]; | |
1578 | int n, ret; | |
1579 | ||
1580 | n = cpuc->n_events; | |
1581 | ||
1582 | if (!x86_pmu_initialized()) | |
1583 | return -EAGAIN; | |
1584 | ||
1585 | ret = x86_pmu.schedule_events(cpuc, n, assign); | |
1586 | if (ret) | |
1587 | return ret; | |
1588 | ||
1589 | /* | |
1590 | * copy new assignment, now we know it is possible | |
1591 | * will be used by hw_perf_enable() | |
1592 | */ | |
1593 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
1594 | ||
8d2cacbb | 1595 | cpuc->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1596 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1597 | return 0; |
1598 | } | |
cd8a38d3 SE |
1599 | /* |
1600 | * a fake_cpuc is used to validate event groups. Due to | |
1601 | * the extra reg logic, we need to also allocate a fake | |
1602 | * per_core and per_cpu structure. Otherwise, group events | |
1603 | * using extra reg may conflict without the kernel being | |
1604 | * able to catch this when the last event gets added to | |
1605 | * the group. | |
1606 | */ | |
1607 | static void free_fake_cpuc(struct cpu_hw_events *cpuc) | |
1608 | { | |
1609 | kfree(cpuc->shared_regs); | |
1610 | kfree(cpuc); | |
1611 | } | |
1612 | ||
1613 | static struct cpu_hw_events *allocate_fake_cpuc(void) | |
1614 | { | |
1615 | struct cpu_hw_events *cpuc; | |
1616 | int cpu = raw_smp_processor_id(); | |
1617 | ||
1618 | cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL); | |
1619 | if (!cpuc) | |
1620 | return ERR_PTR(-ENOMEM); | |
1621 | ||
1622 | /* only needed, if we have extra_regs */ | |
1623 | if (x86_pmu.extra_regs) { | |
1624 | cpuc->shared_regs = allocate_shared_regs(cpu); | |
1625 | if (!cpuc->shared_regs) | |
1626 | goto error; | |
1627 | } | |
b430f7c4 | 1628 | cpuc->is_fake = 1; |
cd8a38d3 SE |
1629 | return cpuc; |
1630 | error: | |
1631 | free_fake_cpuc(cpuc); | |
1632 | return ERR_PTR(-ENOMEM); | |
1633 | } | |
4d1c52b0 | 1634 | |
ca037701 PZ |
1635 | /* |
1636 | * validate that we can schedule this event | |
1637 | */ | |
1638 | static int validate_event(struct perf_event *event) | |
1639 | { | |
1640 | struct cpu_hw_events *fake_cpuc; | |
1641 | struct event_constraint *c; | |
1642 | int ret = 0; | |
1643 | ||
cd8a38d3 SE |
1644 | fake_cpuc = allocate_fake_cpuc(); |
1645 | if (IS_ERR(fake_cpuc)) | |
1646 | return PTR_ERR(fake_cpuc); | |
ca037701 PZ |
1647 | |
1648 | c = x86_pmu.get_event_constraints(fake_cpuc, event); | |
1649 | ||
1650 | if (!c || !c->weight) | |
aa2bc1ad | 1651 | ret = -EINVAL; |
ca037701 PZ |
1652 | |
1653 | if (x86_pmu.put_event_constraints) | |
1654 | x86_pmu.put_event_constraints(fake_cpuc, event); | |
1655 | ||
cd8a38d3 | 1656 | free_fake_cpuc(fake_cpuc); |
ca037701 PZ |
1657 | |
1658 | return ret; | |
1659 | } | |
1660 | ||
1da53e02 SE |
1661 | /* |
1662 | * validate a single event group | |
1663 | * | |
1664 | * validation include: | |
184f412c IM |
1665 | * - check events are compatible which each other |
1666 | * - events do not compete for the same counter | |
1667 | * - number of events <= number of counters | |
1da53e02 SE |
1668 | * |
1669 | * validation ensures the group can be loaded onto the | |
1670 | * PMU if it was the only group available. | |
1671 | */ | |
fe9081cc PZ |
1672 | static int validate_group(struct perf_event *event) |
1673 | { | |
1da53e02 | 1674 | struct perf_event *leader = event->group_leader; |
502568d5 | 1675 | struct cpu_hw_events *fake_cpuc; |
aa2bc1ad | 1676 | int ret = -EINVAL, n; |
fe9081cc | 1677 | |
cd8a38d3 SE |
1678 | fake_cpuc = allocate_fake_cpuc(); |
1679 | if (IS_ERR(fake_cpuc)) | |
1680 | return PTR_ERR(fake_cpuc); | |
1da53e02 SE |
1681 | /* |
1682 | * the event is not yet connected with its | |
1683 | * siblings therefore we must first collect | |
1684 | * existing siblings, then add the new event | |
1685 | * before we can simulate the scheduling | |
1686 | */ | |
502568d5 | 1687 | n = collect_events(fake_cpuc, leader, true); |
1da53e02 | 1688 | if (n < 0) |
cd8a38d3 | 1689 | goto out; |
fe9081cc | 1690 | |
502568d5 PZ |
1691 | fake_cpuc->n_events = n; |
1692 | n = collect_events(fake_cpuc, event, false); | |
1da53e02 | 1693 | if (n < 0) |
cd8a38d3 | 1694 | goto out; |
fe9081cc | 1695 | |
502568d5 | 1696 | fake_cpuc->n_events = n; |
1da53e02 | 1697 | |
a072738e | 1698 | ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); |
502568d5 | 1699 | |
502568d5 | 1700 | out: |
cd8a38d3 | 1701 | free_fake_cpuc(fake_cpuc); |
502568d5 | 1702 | return ret; |
fe9081cc PZ |
1703 | } |
1704 | ||
dda99116 | 1705 | static int x86_pmu_event_init(struct perf_event *event) |
621a01ea | 1706 | { |
51b0fe39 | 1707 | struct pmu *tmp; |
621a01ea IM |
1708 | int err; |
1709 | ||
b0a873eb PZ |
1710 | switch (event->attr.type) { |
1711 | case PERF_TYPE_RAW: | |
1712 | case PERF_TYPE_HARDWARE: | |
1713 | case PERF_TYPE_HW_CACHE: | |
1714 | break; | |
1715 | ||
1716 | default: | |
1717 | return -ENOENT; | |
1718 | } | |
1719 | ||
1720 | err = __x86_pmu_event_init(event); | |
fe9081cc | 1721 | if (!err) { |
8113070d SE |
1722 | /* |
1723 | * we temporarily connect event to its pmu | |
1724 | * such that validate_group() can classify | |
1725 | * it as an x86 event using is_x86_event() | |
1726 | */ | |
1727 | tmp = event->pmu; | |
1728 | event->pmu = &pmu; | |
1729 | ||
fe9081cc PZ |
1730 | if (event->group_leader != event) |
1731 | err = validate_group(event); | |
ca037701 PZ |
1732 | else |
1733 | err = validate_event(event); | |
8113070d SE |
1734 | |
1735 | event->pmu = tmp; | |
fe9081cc | 1736 | } |
a1792cda | 1737 | if (err) { |
cdd6c482 IM |
1738 | if (event->destroy) |
1739 | event->destroy(event); | |
a1792cda | 1740 | } |
621a01ea | 1741 | |
b0a873eb | 1742 | return err; |
621a01ea | 1743 | } |
d7d59fb3 | 1744 | |
fe4a3308 PZ |
1745 | static int x86_pmu_event_idx(struct perf_event *event) |
1746 | { | |
1747 | int idx = event->hw.idx; | |
1748 | ||
c7206205 PZ |
1749 | if (!x86_pmu.attr_rdpmc) |
1750 | return 0; | |
1751 | ||
15c7ad51 RR |
1752 | if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) { |
1753 | idx -= INTEL_PMC_IDX_FIXED; | |
fe4a3308 PZ |
1754 | idx |= 1 << 30; |
1755 | } | |
1756 | ||
1757 | return idx + 1; | |
1758 | } | |
1759 | ||
0c9d42ed PZ |
1760 | static ssize_t get_attr_rdpmc(struct device *cdev, |
1761 | struct device_attribute *attr, | |
1762 | char *buf) | |
1763 | { | |
1764 | return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc); | |
1765 | } | |
1766 | ||
1767 | static void change_rdpmc(void *info) | |
1768 | { | |
1769 | bool enable = !!(unsigned long)info; | |
1770 | ||
1771 | if (enable) | |
1772 | set_in_cr4(X86_CR4_PCE); | |
1773 | else | |
1774 | clear_in_cr4(X86_CR4_PCE); | |
1775 | } | |
1776 | ||
1777 | static ssize_t set_attr_rdpmc(struct device *cdev, | |
1778 | struct device_attribute *attr, | |
1779 | const char *buf, size_t count) | |
1780 | { | |
e2b297fc SK |
1781 | unsigned long val; |
1782 | ssize_t ret; | |
1783 | ||
1784 | ret = kstrtoul(buf, 0, &val); | |
1785 | if (ret) | |
1786 | return ret; | |
0c9d42ed PZ |
1787 | |
1788 | if (!!val != !!x86_pmu.attr_rdpmc) { | |
1789 | x86_pmu.attr_rdpmc = !!val; | |
1790 | smp_call_function(change_rdpmc, (void *)val, 1); | |
1791 | } | |
1792 | ||
1793 | return count; | |
1794 | } | |
1795 | ||
1796 | static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc); | |
1797 | ||
1798 | static struct attribute *x86_pmu_attrs[] = { | |
1799 | &dev_attr_rdpmc.attr, | |
1800 | NULL, | |
1801 | }; | |
1802 | ||
1803 | static struct attribute_group x86_pmu_attr_group = { | |
1804 | .attrs = x86_pmu_attrs, | |
1805 | }; | |
1806 | ||
1807 | static const struct attribute_group *x86_pmu_attr_groups[] = { | |
1808 | &x86_pmu_attr_group, | |
641cc938 | 1809 | &x86_pmu_format_group, |
a4747393 | 1810 | &x86_pmu_events_group, |
0c9d42ed PZ |
1811 | NULL, |
1812 | }; | |
1813 | ||
d010b332 SE |
1814 | static void x86_pmu_flush_branch_stack(void) |
1815 | { | |
1816 | if (x86_pmu.flush_branch_stack) | |
1817 | x86_pmu.flush_branch_stack(); | |
1818 | } | |
1819 | ||
c93dc84c PZ |
1820 | void perf_check_microcode(void) |
1821 | { | |
1822 | if (x86_pmu.check_microcode) | |
1823 | x86_pmu.check_microcode(); | |
1824 | } | |
1825 | EXPORT_SYMBOL_GPL(perf_check_microcode); | |
1826 | ||
b0a873eb | 1827 | static struct pmu pmu = { |
d010b332 SE |
1828 | .pmu_enable = x86_pmu_enable, |
1829 | .pmu_disable = x86_pmu_disable, | |
a4eaf7f1 | 1830 | |
c93dc84c | 1831 | .attr_groups = x86_pmu_attr_groups, |
0c9d42ed | 1832 | |
c93dc84c | 1833 | .event_init = x86_pmu_event_init, |
a4eaf7f1 | 1834 | |
d010b332 SE |
1835 | .add = x86_pmu_add, |
1836 | .del = x86_pmu_del, | |
1837 | .start = x86_pmu_start, | |
1838 | .stop = x86_pmu_stop, | |
1839 | .read = x86_pmu_read, | |
a4eaf7f1 | 1840 | |
c93dc84c PZ |
1841 | .start_txn = x86_pmu_start_txn, |
1842 | .cancel_txn = x86_pmu_cancel_txn, | |
1843 | .commit_txn = x86_pmu_commit_txn, | |
fe4a3308 | 1844 | |
c93dc84c | 1845 | .event_idx = x86_pmu_event_idx, |
d010b332 | 1846 | .flush_branch_stack = x86_pmu_flush_branch_stack, |
b0a873eb PZ |
1847 | }; |
1848 | ||
c7206205 | 1849 | void arch_perf_update_userpage(struct perf_event_mmap_page *userpg, u64 now) |
e3f3541c | 1850 | { |
c7206205 PZ |
1851 | userpg->cap_usr_time = 0; |
1852 | userpg->cap_usr_rdpmc = x86_pmu.attr_rdpmc; | |
1853 | userpg->pmc_width = x86_pmu.cntval_bits; | |
1854 | ||
e3f3541c PZ |
1855 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
1856 | return; | |
1857 | ||
1858 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) | |
1859 | return; | |
1860 | ||
c7206205 | 1861 | userpg->cap_usr_time = 1; |
e3f3541c PZ |
1862 | userpg->time_mult = this_cpu_read(cyc2ns); |
1863 | userpg->time_shift = CYC2NS_SCALE_FACTOR; | |
1864 | userpg->time_offset = this_cpu_read(cyc2ns_offset) - now; | |
1865 | } | |
1866 | ||
d7d59fb3 PZ |
1867 | /* |
1868 | * callchain support | |
1869 | */ | |
1870 | ||
d7d59fb3 PZ |
1871 | static int backtrace_stack(void *data, char *name) |
1872 | { | |
038e836e | 1873 | return 0; |
d7d59fb3 PZ |
1874 | } |
1875 | ||
1876 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
1877 | { | |
1878 | struct perf_callchain_entry *entry = data; | |
1879 | ||
70791ce9 | 1880 | perf_callchain_store(entry, addr); |
d7d59fb3 PZ |
1881 | } |
1882 | ||
1883 | static const struct stacktrace_ops backtrace_ops = { | |
d7d59fb3 PZ |
1884 | .stack = backtrace_stack, |
1885 | .address = backtrace_address, | |
06d65bda | 1886 | .walk_stack = print_context_stack_bp, |
d7d59fb3 PZ |
1887 | }; |
1888 | ||
56962b44 FW |
1889 | void |
1890 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 | 1891 | { |
927c7a9e FW |
1892 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
1893 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 1894 | return; |
927c7a9e FW |
1895 | } |
1896 | ||
70791ce9 | 1897 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 1898 | |
e8e999cf | 1899 | dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry); |
d7d59fb3 PZ |
1900 | } |
1901 | ||
bc6ca7b3 AS |
1902 | static inline int |
1903 | valid_user_frame(const void __user *fp, unsigned long size) | |
1904 | { | |
1905 | return (__range_not_ok(fp, size, TASK_SIZE) == 0); | |
1906 | } | |
1907 | ||
d07bdfd3 PZ |
1908 | static unsigned long get_segment_base(unsigned int segment) |
1909 | { | |
1910 | struct desc_struct *desc; | |
1911 | int idx = segment >> 3; | |
1912 | ||
1913 | if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) { | |
1914 | if (idx > LDT_ENTRIES) | |
1915 | return 0; | |
1916 | ||
1917 | if (idx > current->active_mm->context.size) | |
1918 | return 0; | |
1919 | ||
1920 | desc = current->active_mm->context.ldt; | |
1921 | } else { | |
1922 | if (idx > GDT_ENTRIES) | |
1923 | return 0; | |
1924 | ||
1925 | desc = __this_cpu_ptr(&gdt_page.gdt[0]); | |
1926 | } | |
1927 | ||
1928 | return get_desc_base(desc + idx); | |
1929 | } | |
1930 | ||
257ef9d2 | 1931 | #ifdef CONFIG_COMPAT |
d1a797f3 PA |
1932 | |
1933 | #include <asm/compat.h> | |
1934 | ||
257ef9d2 TE |
1935 | static inline int |
1936 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
74193ef0 | 1937 | { |
257ef9d2 | 1938 | /* 32-bit process in 64-bit kernel. */ |
d07bdfd3 | 1939 | unsigned long ss_base, cs_base; |
257ef9d2 TE |
1940 | struct stack_frame_ia32 frame; |
1941 | const void __user *fp; | |
74193ef0 | 1942 | |
257ef9d2 TE |
1943 | if (!test_thread_flag(TIF_IA32)) |
1944 | return 0; | |
1945 | ||
d07bdfd3 PZ |
1946 | cs_base = get_segment_base(regs->cs); |
1947 | ss_base = get_segment_base(regs->ss); | |
1948 | ||
1949 | fp = compat_ptr(ss_base + regs->bp); | |
257ef9d2 TE |
1950 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
1951 | unsigned long bytes; | |
1952 | frame.next_frame = 0; | |
1953 | frame.return_address = 0; | |
1954 | ||
1955 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); | |
1956 | if (bytes != sizeof(frame)) | |
1957 | break; | |
74193ef0 | 1958 | |
bc6ca7b3 AS |
1959 | if (!valid_user_frame(fp, sizeof(frame))) |
1960 | break; | |
1961 | ||
d07bdfd3 PZ |
1962 | perf_callchain_store(entry, cs_base + frame.return_address); |
1963 | fp = compat_ptr(ss_base + frame.next_frame); | |
257ef9d2 TE |
1964 | } |
1965 | return 1; | |
d7d59fb3 | 1966 | } |
257ef9d2 TE |
1967 | #else |
1968 | static inline int | |
1969 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1970 | { | |
1971 | return 0; | |
1972 | } | |
1973 | #endif | |
d7d59fb3 | 1974 | |
56962b44 FW |
1975 | void |
1976 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 PZ |
1977 | { |
1978 | struct stack_frame frame; | |
1979 | const void __user *fp; | |
1980 | ||
927c7a9e FW |
1981 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
1982 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 1983 | return; |
927c7a9e | 1984 | } |
5a6cec3a | 1985 | |
d07bdfd3 PZ |
1986 | /* |
1987 | * We don't know what to do with VM86 stacks.. ignore them for now. | |
1988 | */ | |
1989 | if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM)) | |
1990 | return; | |
1991 | ||
74193ef0 | 1992 | fp = (void __user *)regs->bp; |
d7d59fb3 | 1993 | |
70791ce9 | 1994 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 1995 | |
20afc60f AV |
1996 | if (!current->mm) |
1997 | return; | |
1998 | ||
257ef9d2 TE |
1999 | if (perf_callchain_user32(regs, entry)) |
2000 | return; | |
2001 | ||
f9188e02 | 2002 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
257ef9d2 | 2003 | unsigned long bytes; |
038e836e | 2004 | frame.next_frame = NULL; |
d7d59fb3 PZ |
2005 | frame.return_address = 0; |
2006 | ||
257ef9d2 TE |
2007 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); |
2008 | if (bytes != sizeof(frame)) | |
d7d59fb3 PZ |
2009 | break; |
2010 | ||
bc6ca7b3 AS |
2011 | if (!valid_user_frame(fp, sizeof(frame))) |
2012 | break; | |
2013 | ||
70791ce9 | 2014 | perf_callchain_store(entry, frame.return_address); |
038e836e | 2015 | fp = frame.next_frame; |
d7d59fb3 PZ |
2016 | } |
2017 | } | |
2018 | ||
d07bdfd3 PZ |
2019 | /* |
2020 | * Deal with code segment offsets for the various execution modes: | |
2021 | * | |
2022 | * VM86 - the good olde 16 bit days, where the linear address is | |
2023 | * 20 bits and we use regs->ip + 0x10 * regs->cs. | |
2024 | * | |
2025 | * IA32 - Where we need to look at GDT/LDT segment descriptor tables | |
2026 | * to figure out what the 32bit base address is. | |
2027 | * | |
2028 | * X32 - has TIF_X32 set, but is running in x86_64 | |
2029 | * | |
2030 | * X86_64 - CS,DS,SS,ES are all zero based. | |
2031 | */ | |
2032 | static unsigned long code_segment_base(struct pt_regs *regs) | |
39447b38 | 2033 | { |
d07bdfd3 PZ |
2034 | /* |
2035 | * If we are in VM86 mode, add the segment offset to convert to a | |
2036 | * linear address. | |
2037 | */ | |
2038 | if (regs->flags & X86_VM_MASK) | |
2039 | return 0x10 * regs->cs; | |
2040 | ||
2041 | /* | |
2042 | * For IA32 we look at the GDT/LDT segment base to convert the | |
2043 | * effective IP to a linear address. | |
2044 | */ | |
2045 | #ifdef CONFIG_X86_32 | |
2046 | if (user_mode(regs) && regs->cs != __USER_CS) | |
2047 | return get_segment_base(regs->cs); | |
2048 | #else | |
2049 | if (test_thread_flag(TIF_IA32)) { | |
2050 | if (user_mode(regs) && regs->cs != __USER32_CS) | |
2051 | return get_segment_base(regs->cs); | |
2052 | } | |
2053 | #endif | |
2054 | return 0; | |
2055 | } | |
dcf46b94 | 2056 | |
d07bdfd3 PZ |
2057 | unsigned long perf_instruction_pointer(struct pt_regs *regs) |
2058 | { | |
39447b38 | 2059 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) |
d07bdfd3 | 2060 | return perf_guest_cbs->get_guest_ip(); |
dcf46b94 | 2061 | |
d07bdfd3 | 2062 | return regs->ip + code_segment_base(regs); |
39447b38 ZY |
2063 | } |
2064 | ||
2065 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
2066 | { | |
2067 | int misc = 0; | |
dcf46b94 | 2068 | |
39447b38 | 2069 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
dcf46b94 ZY |
2070 | if (perf_guest_cbs->is_user_mode()) |
2071 | misc |= PERF_RECORD_MISC_GUEST_USER; | |
2072 | else | |
2073 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; | |
2074 | } else { | |
d07bdfd3 | 2075 | if (user_mode(regs)) |
dcf46b94 ZY |
2076 | misc |= PERF_RECORD_MISC_USER; |
2077 | else | |
2078 | misc |= PERF_RECORD_MISC_KERNEL; | |
2079 | } | |
2080 | ||
39447b38 | 2081 | if (regs->flags & PERF_EFLAGS_EXACT) |
ab608344 | 2082 | misc |= PERF_RECORD_MISC_EXACT_IP; |
39447b38 ZY |
2083 | |
2084 | return misc; | |
2085 | } | |
b3d9468a GN |
2086 | |
2087 | void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) | |
2088 | { | |
2089 | cap->version = x86_pmu.version; | |
2090 | cap->num_counters_gp = x86_pmu.num_counters; | |
2091 | cap->num_counters_fixed = x86_pmu.num_counters_fixed; | |
2092 | cap->bit_width_gp = x86_pmu.cntval_bits; | |
2093 | cap->bit_width_fixed = x86_pmu.cntval_bits; | |
2094 | cap->events_mask = (unsigned int)x86_pmu.events_maskl; | |
2095 | cap->events_mask_len = x86_pmu.events_mask_len; | |
2096 | } | |
2097 | EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability); |