Commit | Line | Data |
---|---|---|
241771ef | 1 | /* |
cdd6c482 | 2 | * Performance events x86 architecture code |
241771ef | 3 | * |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
30dd568c | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
1da53e02 | 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
241771ef IM |
11 | * |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | ||
cdd6c482 | 15 | #include <linux/perf_event.h> |
241771ef IM |
16 | #include <linux/capability.h> |
17 | #include <linux/notifier.h> | |
18 | #include <linux/hardirq.h> | |
19 | #include <linux/kprobes.h> | |
4ac13294 | 20 | #include <linux/module.h> |
241771ef IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/sched.h> | |
d7d59fb3 | 23 | #include <linux/uaccess.h> |
74193ef0 | 24 | #include <linux/highmem.h> |
30dd568c | 25 | #include <linux/cpu.h> |
272d30be | 26 | #include <linux/bitops.h> |
241771ef | 27 | |
241771ef | 28 | #include <asm/apic.h> |
d7d59fb3 | 29 | #include <asm/stacktrace.h> |
4e935e47 | 30 | #include <asm/nmi.h> |
257ef9d2 | 31 | #include <asm/compat.h> |
241771ef | 32 | |
7645a24c PZ |
33 | #if 0 |
34 | #undef wrmsrl | |
35 | #define wrmsrl(msr, val) \ | |
36 | do { \ | |
37 | trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\ | |
38 | (unsigned long)(val)); \ | |
39 | native_write_msr((msr), (u32)((u64)(val)), \ | |
40 | (u32)((u64)(val) >> 32)); \ | |
41 | } while (0) | |
42 | #endif | |
43 | ||
ef21f683 PZ |
44 | /* |
45 | * best effort, GUP based copy_from_user() that assumes IRQ or NMI context | |
46 | */ | |
47 | static unsigned long | |
48 | copy_from_user_nmi(void *to, const void __user *from, unsigned long n) | |
49 | { | |
50 | unsigned long offset, addr = (unsigned long)from; | |
51 | int type = in_nmi() ? KM_NMI : KM_IRQ0; | |
52 | unsigned long size, len = 0; | |
53 | struct page *page; | |
54 | void *map; | |
55 | int ret; | |
56 | ||
57 | do { | |
58 | ret = __get_user_pages_fast(addr, 1, 0, &page); | |
59 | if (!ret) | |
60 | break; | |
61 | ||
62 | offset = addr & (PAGE_SIZE - 1); | |
63 | size = min(PAGE_SIZE - offset, n - len); | |
64 | ||
65 | map = kmap_atomic(page, type); | |
66 | memcpy(to, map+offset, size); | |
67 | kunmap_atomic(map, type); | |
68 | put_page(page); | |
69 | ||
70 | len += size; | |
71 | to += size; | |
72 | addr += size; | |
73 | ||
74 | } while (len < n); | |
75 | ||
76 | return len; | |
77 | } | |
78 | ||
1da53e02 | 79 | struct event_constraint { |
c91e0f5d PZ |
80 | union { |
81 | unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
b622d644 | 82 | u64 idxmsk64; |
c91e0f5d | 83 | }; |
b622d644 PZ |
84 | u64 code; |
85 | u64 cmask; | |
272d30be | 86 | int weight; |
1da53e02 SE |
87 | }; |
88 | ||
38331f62 SE |
89 | struct amd_nb { |
90 | int nb_id; /* NorthBridge id */ | |
91 | int refcnt; /* reference count */ | |
92 | struct perf_event *owners[X86_PMC_IDX_MAX]; | |
93 | struct event_constraint event_constraints[X86_PMC_IDX_MAX]; | |
94 | }; | |
95 | ||
caff2bef PZ |
96 | #define MAX_LBR_ENTRIES 16 |
97 | ||
cdd6c482 | 98 | struct cpu_hw_events { |
ca037701 PZ |
99 | /* |
100 | * Generic x86 PMC bits | |
101 | */ | |
1da53e02 | 102 | struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */ |
43f6201a | 103 | unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
b0f3f28e | 104 | int enabled; |
241771ef | 105 | |
1da53e02 SE |
106 | int n_events; |
107 | int n_added; | |
108 | int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ | |
447a194b | 109 | u64 tags[X86_PMC_IDX_MAX]; |
1da53e02 | 110 | struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */ |
ca037701 PZ |
111 | |
112 | /* | |
113 | * Intel DebugStore bits | |
114 | */ | |
115 | struct debug_store *ds; | |
116 | u64 pebs_enabled; | |
117 | ||
caff2bef PZ |
118 | /* |
119 | * Intel LBR bits | |
120 | */ | |
121 | int lbr_users; | |
122 | void *lbr_context; | |
123 | struct perf_branch_stack lbr_stack; | |
124 | struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES]; | |
125 | ||
ca037701 PZ |
126 | /* |
127 | * AMD specific bits | |
128 | */ | |
38331f62 | 129 | struct amd_nb *amd_nb; |
b690081d SE |
130 | }; |
131 | ||
fce877e3 | 132 | #define __EVENT_CONSTRAINT(c, n, m, w) {\ |
b622d644 | 133 | { .idxmsk64 = (n) }, \ |
c91e0f5d PZ |
134 | .code = (c), \ |
135 | .cmask = (m), \ | |
fce877e3 | 136 | .weight = (w), \ |
c91e0f5d | 137 | } |
b690081d | 138 | |
fce877e3 PZ |
139 | #define EVENT_CONSTRAINT(c, n, m) \ |
140 | __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n)) | |
141 | ||
ca037701 PZ |
142 | /* |
143 | * Constraint on the Event code. | |
144 | */ | |
ed8777fc | 145 | #define INTEL_EVENT_CONSTRAINT(c, n) \ |
a098f448 | 146 | EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT) |
8433be11 | 147 | |
ca037701 PZ |
148 | /* |
149 | * Constraint on the Event code + UMask + fixed-mask | |
a098f448 RR |
150 | * |
151 | * filter mask to validate fixed counter events. | |
152 | * the following filters disqualify for fixed counters: | |
153 | * - inv | |
154 | * - edge | |
155 | * - cnt-mask | |
156 | * The other filters are supported by fixed counters. | |
157 | * The any-thread option is supported starting with v3. | |
ca037701 | 158 | */ |
ed8777fc | 159 | #define FIXED_EVENT_CONSTRAINT(c, n) \ |
a098f448 | 160 | EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK) |
8433be11 | 161 | |
ca037701 PZ |
162 | /* |
163 | * Constraint on the Event code + UMask | |
164 | */ | |
165 | #define PEBS_EVENT_CONSTRAINT(c, n) \ | |
166 | EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK) | |
167 | ||
ed8777fc PZ |
168 | #define EVENT_CONSTRAINT_END \ |
169 | EVENT_CONSTRAINT(0, 0, 0) | |
170 | ||
171 | #define for_each_event_constraint(e, c) \ | |
172 | for ((e) = (c); (e)->cmask; (e)++) | |
b690081d | 173 | |
8db909a7 PZ |
174 | union perf_capabilities { |
175 | struct { | |
176 | u64 lbr_format : 6; | |
177 | u64 pebs_trap : 1; | |
178 | u64 pebs_arch_reg : 1; | |
179 | u64 pebs_format : 4; | |
180 | u64 smm_freeze : 1; | |
181 | }; | |
182 | u64 capabilities; | |
183 | }; | |
184 | ||
241771ef | 185 | /* |
5f4ec28f | 186 | * struct x86_pmu - generic x86 pmu |
241771ef | 187 | */ |
5f4ec28f | 188 | struct x86_pmu { |
ca037701 PZ |
189 | /* |
190 | * Generic x86 PMC bits | |
191 | */ | |
faa28ae0 RR |
192 | const char *name; |
193 | int version; | |
a3288106 | 194 | int (*handle_irq)(struct pt_regs *); |
9e35ad38 | 195 | void (*disable_all)(void); |
11164cd4 | 196 | void (*enable_all)(int added); |
aff3d91a PZ |
197 | void (*enable)(struct perf_event *); |
198 | void (*disable)(struct perf_event *); | |
a072738e CG |
199 | int (*hw_config)(struct perf_event_attr *attr, struct hw_perf_event *hwc); |
200 | int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign); | |
169e41eb JSR |
201 | unsigned eventsel; |
202 | unsigned perfctr; | |
b0f3f28e PZ |
203 | u64 (*event_map)(int); |
204 | u64 (*raw_event)(u64); | |
169e41eb | 205 | int max_events; |
948b1bb8 RR |
206 | int num_counters; |
207 | int num_counters_fixed; | |
208 | int cntval_bits; | |
209 | u64 cntval_mask; | |
04da8a43 | 210 | int apic; |
c619b8ff | 211 | u64 max_period; |
63b14649 PZ |
212 | struct event_constraint * |
213 | (*get_event_constraints)(struct cpu_hw_events *cpuc, | |
214 | struct perf_event *event); | |
215 | ||
c91e0f5d PZ |
216 | void (*put_event_constraints)(struct cpu_hw_events *cpuc, |
217 | struct perf_event *event); | |
63b14649 | 218 | struct event_constraint *event_constraints; |
3c44780b | 219 | void (*quirks)(void); |
3f6da390 | 220 | |
b38b24ea | 221 | int (*cpu_prepare)(int cpu); |
3f6da390 PZ |
222 | void (*cpu_starting)(int cpu); |
223 | void (*cpu_dying)(int cpu); | |
224 | void (*cpu_dead)(int cpu); | |
ca037701 PZ |
225 | |
226 | /* | |
227 | * Intel Arch Perfmon v2+ | |
228 | */ | |
8db909a7 PZ |
229 | u64 intel_ctrl; |
230 | union perf_capabilities intel_cap; | |
ca037701 PZ |
231 | |
232 | /* | |
233 | * Intel DebugStore bits | |
234 | */ | |
235 | int bts, pebs; | |
236 | int pebs_record_size; | |
237 | void (*drain_pebs)(struct pt_regs *regs); | |
238 | struct event_constraint *pebs_constraints; | |
caff2bef PZ |
239 | |
240 | /* | |
241 | * Intel LBR | |
242 | */ | |
243 | unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */ | |
244 | int lbr_nr; /* hardware stack size */ | |
b56a3802 JSR |
245 | }; |
246 | ||
4a06bd85 | 247 | static struct x86_pmu x86_pmu __read_mostly; |
b56a3802 | 248 | |
cdd6c482 | 249 | static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
b0f3f28e PZ |
250 | .enabled = 1, |
251 | }; | |
241771ef | 252 | |
07088edb | 253 | static int x86_perf_event_set_period(struct perf_event *event); |
b690081d | 254 | |
8326f44d | 255 | /* |
dfc65094 | 256 | * Generalized hw caching related hw_event table, filled |
8326f44d | 257 | * in on a per model basis. A value of 0 means |
dfc65094 IM |
258 | * 'not supported', -1 means 'hw_event makes no sense on |
259 | * this CPU', any other value means the raw hw_event | |
8326f44d IM |
260 | * ID. |
261 | */ | |
262 | ||
263 | #define C(x) PERF_COUNT_HW_CACHE_##x | |
264 | ||
265 | static u64 __read_mostly hw_cache_event_ids | |
266 | [PERF_COUNT_HW_CACHE_MAX] | |
267 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
268 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
269 | ||
ee06094f | 270 | /* |
cdd6c482 IM |
271 | * Propagate event elapsed time into the generic event. |
272 | * Can only be executed on the CPU where the event is active. | |
ee06094f IM |
273 | * Returns the delta events processed. |
274 | */ | |
4b7bfd0d | 275 | static u64 |
cc2ad4ba | 276 | x86_perf_event_update(struct perf_event *event) |
ee06094f | 277 | { |
cc2ad4ba | 278 | struct hw_perf_event *hwc = &event->hw; |
948b1bb8 | 279 | int shift = 64 - x86_pmu.cntval_bits; |
ec3232bd | 280 | u64 prev_raw_count, new_raw_count; |
cc2ad4ba | 281 | int idx = hwc->idx; |
ec3232bd | 282 | s64 delta; |
ee06094f | 283 | |
30dd568c MM |
284 | if (idx == X86_PMC_IDX_FIXED_BTS) |
285 | return 0; | |
286 | ||
ee06094f | 287 | /* |
cdd6c482 | 288 | * Careful: an NMI might modify the previous event value. |
ee06094f IM |
289 | * |
290 | * Our tactic to handle this is to first atomically read and | |
291 | * exchange a new raw count - then add that new-prev delta | |
cdd6c482 | 292 | * count to the generic event atomically: |
ee06094f IM |
293 | */ |
294 | again: | |
295 | prev_raw_count = atomic64_read(&hwc->prev_count); | |
cdd6c482 | 296 | rdmsrl(hwc->event_base + idx, new_raw_count); |
ee06094f IM |
297 | |
298 | if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count, | |
299 | new_raw_count) != prev_raw_count) | |
300 | goto again; | |
301 | ||
302 | /* | |
303 | * Now we have the new raw value and have updated the prev | |
304 | * timestamp already. We can now calculate the elapsed delta | |
cdd6c482 | 305 | * (event-)time and add that to the generic event. |
ee06094f IM |
306 | * |
307 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 308 | * of the count. |
ee06094f | 309 | */ |
ec3232bd PZ |
310 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
311 | delta >>= shift; | |
ee06094f | 312 | |
cdd6c482 | 313 | atomic64_add(delta, &event->count); |
ee06094f | 314 | atomic64_sub(delta, &hwc->period_left); |
4b7bfd0d RR |
315 | |
316 | return new_raw_count; | |
ee06094f IM |
317 | } |
318 | ||
cdd6c482 | 319 | static atomic_t active_events; |
4e935e47 PZ |
320 | static DEFINE_MUTEX(pmc_reserve_mutex); |
321 | ||
b27ea29c RR |
322 | #ifdef CONFIG_X86_LOCAL_APIC |
323 | ||
4e935e47 PZ |
324 | static bool reserve_pmc_hardware(void) |
325 | { | |
326 | int i; | |
327 | ||
328 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
329 | disable_lapic_nmi_watchdog(); | |
330 | ||
948b1bb8 | 331 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 | 332 | if (!reserve_perfctr_nmi(x86_pmu.perfctr + i)) |
4e935e47 PZ |
333 | goto perfctr_fail; |
334 | } | |
335 | ||
948b1bb8 | 336 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 | 337 | if (!reserve_evntsel_nmi(x86_pmu.eventsel + i)) |
4e935e47 PZ |
338 | goto eventsel_fail; |
339 | } | |
340 | ||
341 | return true; | |
342 | ||
343 | eventsel_fail: | |
344 | for (i--; i >= 0; i--) | |
4a06bd85 | 345 | release_evntsel_nmi(x86_pmu.eventsel + i); |
4e935e47 | 346 | |
948b1bb8 | 347 | i = x86_pmu.num_counters; |
4e935e47 PZ |
348 | |
349 | perfctr_fail: | |
350 | for (i--; i >= 0; i--) | |
4a06bd85 | 351 | release_perfctr_nmi(x86_pmu.perfctr + i); |
4e935e47 PZ |
352 | |
353 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
354 | enable_lapic_nmi_watchdog(); | |
355 | ||
356 | return false; | |
357 | } | |
358 | ||
359 | static void release_pmc_hardware(void) | |
360 | { | |
361 | int i; | |
362 | ||
948b1bb8 | 363 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 RR |
364 | release_perfctr_nmi(x86_pmu.perfctr + i); |
365 | release_evntsel_nmi(x86_pmu.eventsel + i); | |
4e935e47 PZ |
366 | } |
367 | ||
368 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
369 | enable_lapic_nmi_watchdog(); | |
370 | } | |
371 | ||
b27ea29c RR |
372 | #else |
373 | ||
374 | static bool reserve_pmc_hardware(void) { return true; } | |
375 | static void release_pmc_hardware(void) {} | |
376 | ||
377 | #endif | |
378 | ||
ca037701 PZ |
379 | static int reserve_ds_buffers(void); |
380 | static void release_ds_buffers(void); | |
30dd568c | 381 | |
cdd6c482 | 382 | static void hw_perf_event_destroy(struct perf_event *event) |
4e935e47 | 383 | { |
cdd6c482 | 384 | if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) { |
4e935e47 | 385 | release_pmc_hardware(); |
ca037701 | 386 | release_ds_buffers(); |
4e935e47 PZ |
387 | mutex_unlock(&pmc_reserve_mutex); |
388 | } | |
389 | } | |
390 | ||
85cf9dba RR |
391 | static inline int x86_pmu_initialized(void) |
392 | { | |
393 | return x86_pmu.handle_irq != NULL; | |
394 | } | |
395 | ||
8326f44d | 396 | static inline int |
cdd6c482 | 397 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr) |
8326f44d IM |
398 | { |
399 | unsigned int cache_type, cache_op, cache_result; | |
400 | u64 config, val; | |
401 | ||
402 | config = attr->config; | |
403 | ||
404 | cache_type = (config >> 0) & 0xff; | |
405 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
406 | return -EINVAL; | |
407 | ||
408 | cache_op = (config >> 8) & 0xff; | |
409 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
410 | return -EINVAL; | |
411 | ||
412 | cache_result = (config >> 16) & 0xff; | |
413 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
414 | return -EINVAL; | |
415 | ||
416 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; | |
417 | ||
418 | if (val == 0) | |
419 | return -ENOENT; | |
420 | ||
421 | if (val == -1) | |
422 | return -EINVAL; | |
423 | ||
424 | hwc->config |= val; | |
425 | ||
426 | return 0; | |
427 | } | |
428 | ||
a072738e CG |
429 | static int x86_hw_config(struct perf_event_attr *attr, struct hw_perf_event *hwc) |
430 | { | |
431 | /* | |
432 | * Generate PMC IRQs: | |
433 | * (keep 'enabled' bit clear for now) | |
434 | */ | |
435 | hwc->config = ARCH_PERFMON_EVENTSEL_INT; | |
436 | ||
437 | /* | |
438 | * Count user and OS events unless requested not to | |
439 | */ | |
440 | if (!attr->exclude_user) | |
441 | hwc->config |= ARCH_PERFMON_EVENTSEL_USR; | |
442 | if (!attr->exclude_kernel) | |
443 | hwc->config |= ARCH_PERFMON_EVENTSEL_OS; | |
444 | ||
445 | return 0; | |
446 | } | |
447 | ||
a098f448 RR |
448 | static u64 x86_pmu_raw_event(u64 hw_event) |
449 | { | |
450 | return hw_event & X86_RAW_EVENT_MASK; | |
451 | } | |
452 | ||
241771ef | 453 | /* |
0d48696f | 454 | * Setup the hardware configuration for a given attr_type |
241771ef | 455 | */ |
cdd6c482 | 456 | static int __hw_perf_event_init(struct perf_event *event) |
241771ef | 457 | { |
cdd6c482 IM |
458 | struct perf_event_attr *attr = &event->attr; |
459 | struct hw_perf_event *hwc = &event->hw; | |
9c74fb50 | 460 | u64 config; |
4e935e47 | 461 | int err; |
241771ef | 462 | |
85cf9dba RR |
463 | if (!x86_pmu_initialized()) |
464 | return -ENODEV; | |
241771ef | 465 | |
4e935e47 | 466 | err = 0; |
cdd6c482 | 467 | if (!atomic_inc_not_zero(&active_events)) { |
4e935e47 | 468 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 469 | if (atomic_read(&active_events) == 0) { |
30dd568c MM |
470 | if (!reserve_pmc_hardware()) |
471 | err = -EBUSY; | |
4b24a88b | 472 | else { |
ca037701 | 473 | err = reserve_ds_buffers(); |
4b24a88b SE |
474 | if (err) |
475 | release_pmc_hardware(); | |
476 | } | |
30dd568c MM |
477 | } |
478 | if (!err) | |
cdd6c482 | 479 | atomic_inc(&active_events); |
4e935e47 PZ |
480 | mutex_unlock(&pmc_reserve_mutex); |
481 | } | |
482 | if (err) | |
483 | return err; | |
484 | ||
cdd6c482 | 485 | event->destroy = hw_perf_event_destroy; |
a1792cda | 486 | |
b690081d | 487 | hwc->idx = -1; |
447a194b SE |
488 | hwc->last_cpu = -1; |
489 | hwc->last_tag = ~0ULL; | |
b690081d | 490 | |
a072738e | 491 | /* Processor specifics */ |
984763cb RR |
492 | err = x86_pmu.hw_config(attr, hwc); |
493 | if (err) | |
494 | return err; | |
0475f9ea | 495 | |
bd2b5b12 | 496 | if (!hwc->sample_period) { |
b23f3325 | 497 | hwc->sample_period = x86_pmu.max_period; |
9e350de3 | 498 | hwc->last_period = hwc->sample_period; |
bd2b5b12 | 499 | atomic64_set(&hwc->period_left, hwc->sample_period); |
04da8a43 IM |
500 | } else { |
501 | /* | |
502 | * If we have a PMU initialized but no APIC | |
503 | * interrupts, we cannot sample hardware | |
cdd6c482 IM |
504 | * events (user-space has to fall back and |
505 | * sample via a hrtimer based software event): | |
04da8a43 IM |
506 | */ |
507 | if (!x86_pmu.apic) | |
508 | return -EOPNOTSUPP; | |
bd2b5b12 | 509 | } |
d2517a49 | 510 | |
241771ef | 511 | /* |
dfc65094 | 512 | * Raw hw_event type provide the config in the hw_event structure |
241771ef | 513 | */ |
a21ca2ca IM |
514 | if (attr->type == PERF_TYPE_RAW) { |
515 | hwc->config |= x86_pmu.raw_event(attr->config); | |
320ebf09 PZ |
516 | if ((hwc->config & ARCH_PERFMON_EVENTSEL_ANY) && |
517 | perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN)) | |
518 | return -EACCES; | |
8326f44d | 519 | return 0; |
241771ef | 520 | } |
241771ef | 521 | |
8326f44d IM |
522 | if (attr->type == PERF_TYPE_HW_CACHE) |
523 | return set_ext_hw_attr(hwc, attr); | |
524 | ||
525 | if (attr->config >= x86_pmu.max_events) | |
526 | return -EINVAL; | |
9c74fb50 | 527 | |
8326f44d IM |
528 | /* |
529 | * The generic map: | |
530 | */ | |
9c74fb50 PZ |
531 | config = x86_pmu.event_map(attr->config); |
532 | ||
533 | if (config == 0) | |
534 | return -ENOENT; | |
535 | ||
536 | if (config == -1LL) | |
537 | return -EINVAL; | |
538 | ||
747b50aa | 539 | /* |
540 | * Branch tracing: | |
541 | */ | |
542 | if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) && | |
1653192f | 543 | (hwc->sample_period == 1)) { |
544 | /* BTS is not supported by this architecture. */ | |
ca037701 | 545 | if (!x86_pmu.bts) |
1653192f | 546 | return -EOPNOTSUPP; |
547 | ||
548 | /* BTS is currently only allowed for user-mode. */ | |
a072738e | 549 | if (!attr->exclude_kernel) |
1653192f | 550 | return -EOPNOTSUPP; |
551 | } | |
747b50aa | 552 | |
9c74fb50 | 553 | hwc->config |= config; |
4e935e47 | 554 | |
241771ef IM |
555 | return 0; |
556 | } | |
557 | ||
8c48e444 | 558 | static void x86_pmu_disable_all(void) |
f87ad35d | 559 | { |
cdd6c482 | 560 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
9e35ad38 PZ |
561 | int idx; |
562 | ||
948b1bb8 | 563 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
b0f3f28e PZ |
564 | u64 val; |
565 | ||
43f6201a | 566 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 567 | continue; |
8c48e444 | 568 | rdmsrl(x86_pmu.eventsel + idx, val); |
bb1165d6 | 569 | if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) |
4295ee62 | 570 | continue; |
bb1165d6 | 571 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
8c48e444 | 572 | wrmsrl(x86_pmu.eventsel + idx, val); |
f87ad35d | 573 | } |
f87ad35d JSR |
574 | } |
575 | ||
9e35ad38 | 576 | void hw_perf_disable(void) |
b56a3802 | 577 | { |
1da53e02 SE |
578 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
579 | ||
85cf9dba | 580 | if (!x86_pmu_initialized()) |
9e35ad38 | 581 | return; |
1da53e02 | 582 | |
1a6e21f7 PZ |
583 | if (!cpuc->enabled) |
584 | return; | |
585 | ||
586 | cpuc->n_added = 0; | |
587 | cpuc->enabled = 0; | |
588 | barrier(); | |
1da53e02 SE |
589 | |
590 | x86_pmu.disable_all(); | |
b56a3802 | 591 | } |
241771ef | 592 | |
11164cd4 | 593 | static void x86_pmu_enable_all(int added) |
f87ad35d | 594 | { |
cdd6c482 | 595 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
f87ad35d JSR |
596 | int idx; |
597 | ||
948b1bb8 | 598 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
cdd6c482 | 599 | struct perf_event *event = cpuc->events[idx]; |
4295ee62 | 600 | u64 val; |
b0f3f28e | 601 | |
43f6201a | 602 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 603 | continue; |
984b838c | 604 | |
cdd6c482 | 605 | val = event->hw.config; |
bb1165d6 | 606 | val |= ARCH_PERFMON_EVENTSEL_ENABLE; |
8c48e444 | 607 | wrmsrl(x86_pmu.eventsel + idx, val); |
f87ad35d JSR |
608 | } |
609 | } | |
610 | ||
1da53e02 SE |
611 | static const struct pmu pmu; |
612 | ||
613 | static inline int is_x86_event(struct perf_event *event) | |
614 | { | |
615 | return event->pmu == &pmu; | |
616 | } | |
617 | ||
618 | static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) | |
619 | { | |
63b14649 | 620 | struct event_constraint *c, *constraints[X86_PMC_IDX_MAX]; |
1da53e02 | 621 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
c933c1a6 | 622 | int i, j, w, wmax, num = 0; |
1da53e02 SE |
623 | struct hw_perf_event *hwc; |
624 | ||
625 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
626 | ||
627 | for (i = 0; i < n; i++) { | |
b622d644 PZ |
628 | c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]); |
629 | constraints[i] = c; | |
1da53e02 SE |
630 | } |
631 | ||
8113070d SE |
632 | /* |
633 | * fastpath, try to reuse previous register | |
634 | */ | |
c933c1a6 | 635 | for (i = 0; i < n; i++) { |
8113070d | 636 | hwc = &cpuc->event_list[i]->hw; |
81269a08 | 637 | c = constraints[i]; |
8113070d SE |
638 | |
639 | /* never assigned */ | |
640 | if (hwc->idx == -1) | |
641 | break; | |
642 | ||
643 | /* constraint still honored */ | |
63b14649 | 644 | if (!test_bit(hwc->idx, c->idxmsk)) |
8113070d SE |
645 | break; |
646 | ||
647 | /* not already used */ | |
648 | if (test_bit(hwc->idx, used_mask)) | |
649 | break; | |
650 | ||
34538ee7 | 651 | __set_bit(hwc->idx, used_mask); |
8113070d SE |
652 | if (assign) |
653 | assign[i] = hwc->idx; | |
654 | } | |
c933c1a6 | 655 | if (i == n) |
8113070d SE |
656 | goto done; |
657 | ||
658 | /* | |
659 | * begin slow path | |
660 | */ | |
661 | ||
662 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
663 | ||
1da53e02 SE |
664 | /* |
665 | * weight = number of possible counters | |
666 | * | |
667 | * 1 = most constrained, only works on one counter | |
668 | * wmax = least constrained, works on any counter | |
669 | * | |
670 | * assign events to counters starting with most | |
671 | * constrained events. | |
672 | */ | |
948b1bb8 | 673 | wmax = x86_pmu.num_counters; |
1da53e02 SE |
674 | |
675 | /* | |
676 | * when fixed event counters are present, | |
677 | * wmax is incremented by 1 to account | |
678 | * for one more choice | |
679 | */ | |
948b1bb8 | 680 | if (x86_pmu.num_counters_fixed) |
1da53e02 SE |
681 | wmax++; |
682 | ||
8113070d | 683 | for (w = 1, num = n; num && w <= wmax; w++) { |
1da53e02 | 684 | /* for each event */ |
8113070d | 685 | for (i = 0; num && i < n; i++) { |
81269a08 | 686 | c = constraints[i]; |
1da53e02 SE |
687 | hwc = &cpuc->event_list[i]->hw; |
688 | ||
272d30be | 689 | if (c->weight != w) |
1da53e02 SE |
690 | continue; |
691 | ||
984b3f57 | 692 | for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) { |
1da53e02 SE |
693 | if (!test_bit(j, used_mask)) |
694 | break; | |
695 | } | |
696 | ||
697 | if (j == X86_PMC_IDX_MAX) | |
698 | break; | |
1da53e02 | 699 | |
34538ee7 | 700 | __set_bit(j, used_mask); |
8113070d | 701 | |
1da53e02 SE |
702 | if (assign) |
703 | assign[i] = j; | |
704 | num--; | |
705 | } | |
706 | } | |
8113070d | 707 | done: |
1da53e02 SE |
708 | /* |
709 | * scheduling failed or is just a simulation, | |
710 | * free resources if necessary | |
711 | */ | |
712 | if (!assign || num) { | |
713 | for (i = 0; i < n; i++) { | |
714 | if (x86_pmu.put_event_constraints) | |
715 | x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]); | |
716 | } | |
717 | } | |
718 | return num ? -ENOSPC : 0; | |
719 | } | |
720 | ||
721 | /* | |
722 | * dogrp: true if must collect siblings events (group) | |
723 | * returns total number of events and error code | |
724 | */ | |
725 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) | |
726 | { | |
727 | struct perf_event *event; | |
728 | int n, max_count; | |
729 | ||
948b1bb8 | 730 | max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed; |
1da53e02 SE |
731 | |
732 | /* current number of events already accepted */ | |
733 | n = cpuc->n_events; | |
734 | ||
735 | if (is_x86_event(leader)) { | |
736 | if (n >= max_count) | |
737 | return -ENOSPC; | |
738 | cpuc->event_list[n] = leader; | |
739 | n++; | |
740 | } | |
741 | if (!dogrp) | |
742 | return n; | |
743 | ||
744 | list_for_each_entry(event, &leader->sibling_list, group_entry) { | |
745 | if (!is_x86_event(event) || | |
8113070d | 746 | event->state <= PERF_EVENT_STATE_OFF) |
1da53e02 SE |
747 | continue; |
748 | ||
749 | if (n >= max_count) | |
750 | return -ENOSPC; | |
751 | ||
752 | cpuc->event_list[n] = event; | |
753 | n++; | |
754 | } | |
755 | return n; | |
756 | } | |
757 | ||
1da53e02 | 758 | static inline void x86_assign_hw_event(struct perf_event *event, |
447a194b | 759 | struct cpu_hw_events *cpuc, int i) |
1da53e02 | 760 | { |
447a194b SE |
761 | struct hw_perf_event *hwc = &event->hw; |
762 | ||
763 | hwc->idx = cpuc->assign[i]; | |
764 | hwc->last_cpu = smp_processor_id(); | |
765 | hwc->last_tag = ++cpuc->tags[i]; | |
1da53e02 SE |
766 | |
767 | if (hwc->idx == X86_PMC_IDX_FIXED_BTS) { | |
768 | hwc->config_base = 0; | |
769 | hwc->event_base = 0; | |
770 | } else if (hwc->idx >= X86_PMC_IDX_FIXED) { | |
771 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
772 | /* | |
773 | * We set it so that event_base + idx in wrmsr/rdmsr maps to | |
774 | * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2: | |
775 | */ | |
776 | hwc->event_base = | |
777 | MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED; | |
778 | } else { | |
779 | hwc->config_base = x86_pmu.eventsel; | |
780 | hwc->event_base = x86_pmu.perfctr; | |
781 | } | |
782 | } | |
783 | ||
447a194b SE |
784 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
785 | struct cpu_hw_events *cpuc, | |
786 | int i) | |
787 | { | |
788 | return hwc->idx == cpuc->assign[i] && | |
789 | hwc->last_cpu == smp_processor_id() && | |
790 | hwc->last_tag == cpuc->tags[i]; | |
791 | } | |
792 | ||
c08053e6 | 793 | static int x86_pmu_start(struct perf_event *event); |
d76a0812 | 794 | static void x86_pmu_stop(struct perf_event *event); |
2e841873 | 795 | |
9e35ad38 | 796 | void hw_perf_enable(void) |
ee06094f | 797 | { |
1da53e02 SE |
798 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
799 | struct perf_event *event; | |
800 | struct hw_perf_event *hwc; | |
11164cd4 | 801 | int i, added = cpuc->n_added; |
1da53e02 | 802 | |
85cf9dba | 803 | if (!x86_pmu_initialized()) |
2b9ff0db | 804 | return; |
1a6e21f7 PZ |
805 | |
806 | if (cpuc->enabled) | |
807 | return; | |
808 | ||
1da53e02 | 809 | if (cpuc->n_added) { |
19925ce7 | 810 | int n_running = cpuc->n_events - cpuc->n_added; |
1da53e02 SE |
811 | /* |
812 | * apply assignment obtained either from | |
813 | * hw_perf_group_sched_in() or x86_pmu_enable() | |
814 | * | |
815 | * step1: save events moving to new counters | |
816 | * step2: reprogram moved events into new counters | |
817 | */ | |
19925ce7 | 818 | for (i = 0; i < n_running; i++) { |
1da53e02 SE |
819 | event = cpuc->event_list[i]; |
820 | hwc = &event->hw; | |
821 | ||
447a194b SE |
822 | /* |
823 | * we can avoid reprogramming counter if: | |
824 | * - assigned same counter as last time | |
825 | * - running on same CPU as last time | |
826 | * - no other event has used the counter since | |
827 | */ | |
828 | if (hwc->idx == -1 || | |
829 | match_prev_assignment(hwc, cpuc, i)) | |
1da53e02 SE |
830 | continue; |
831 | ||
d76a0812 | 832 | x86_pmu_stop(event); |
1da53e02 SE |
833 | } |
834 | ||
835 | for (i = 0; i < cpuc->n_events; i++) { | |
1da53e02 SE |
836 | event = cpuc->event_list[i]; |
837 | hwc = &event->hw; | |
838 | ||
45e16a68 | 839 | if (!match_prev_assignment(hwc, cpuc, i)) |
447a194b | 840 | x86_assign_hw_event(event, cpuc, i); |
45e16a68 PZ |
841 | else if (i < n_running) |
842 | continue; | |
1da53e02 | 843 | |
c08053e6 | 844 | x86_pmu_start(event); |
1da53e02 SE |
845 | } |
846 | cpuc->n_added = 0; | |
847 | perf_events_lapic_init(); | |
848 | } | |
1a6e21f7 PZ |
849 | |
850 | cpuc->enabled = 1; | |
851 | barrier(); | |
852 | ||
11164cd4 | 853 | x86_pmu.enable_all(added); |
ee06094f | 854 | } |
ee06094f | 855 | |
aff3d91a | 856 | static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc) |
b0f3f28e | 857 | { |
7645a24c | 858 | wrmsrl(hwc->config_base + hwc->idx, |
bb1165d6 | 859 | hwc->config | ARCH_PERFMON_EVENTSEL_ENABLE); |
b0f3f28e PZ |
860 | } |
861 | ||
aff3d91a | 862 | static inline void x86_pmu_disable_event(struct perf_event *event) |
b0f3f28e | 863 | { |
aff3d91a | 864 | struct hw_perf_event *hwc = &event->hw; |
7645a24c PZ |
865 | |
866 | wrmsrl(hwc->config_base + hwc->idx, hwc->config); | |
b0f3f28e PZ |
867 | } |
868 | ||
245b2e70 | 869 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
241771ef | 870 | |
ee06094f IM |
871 | /* |
872 | * Set the next IRQ period, based on the hwc->period_left value. | |
cdd6c482 | 873 | * To be called with the event disabled in hw: |
ee06094f | 874 | */ |
e4abb5d4 | 875 | static int |
07088edb | 876 | x86_perf_event_set_period(struct perf_event *event) |
241771ef | 877 | { |
07088edb | 878 | struct hw_perf_event *hwc = &event->hw; |
2f18d1e8 | 879 | s64 left = atomic64_read(&hwc->period_left); |
e4abb5d4 | 880 | s64 period = hwc->sample_period; |
7645a24c | 881 | int ret = 0, idx = hwc->idx; |
ee06094f | 882 | |
30dd568c MM |
883 | if (idx == X86_PMC_IDX_FIXED_BTS) |
884 | return 0; | |
885 | ||
ee06094f | 886 | /* |
af901ca1 | 887 | * If we are way outside a reasonable range then just skip forward: |
ee06094f IM |
888 | */ |
889 | if (unlikely(left <= -period)) { | |
890 | left = period; | |
891 | atomic64_set(&hwc->period_left, left); | |
9e350de3 | 892 | hwc->last_period = period; |
e4abb5d4 | 893 | ret = 1; |
ee06094f IM |
894 | } |
895 | ||
896 | if (unlikely(left <= 0)) { | |
897 | left += period; | |
898 | atomic64_set(&hwc->period_left, left); | |
9e350de3 | 899 | hwc->last_period = period; |
e4abb5d4 | 900 | ret = 1; |
ee06094f | 901 | } |
1c80f4b5 | 902 | /* |
dfc65094 | 903 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
1c80f4b5 IM |
904 | */ |
905 | if (unlikely(left < 2)) | |
906 | left = 2; | |
241771ef | 907 | |
e4abb5d4 PZ |
908 | if (left > x86_pmu.max_period) |
909 | left = x86_pmu.max_period; | |
910 | ||
245b2e70 | 911 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
ee06094f IM |
912 | |
913 | /* | |
cdd6c482 | 914 | * The hw event starts counting from this event offset, |
ee06094f IM |
915 | * mark it to be able to extra future deltas: |
916 | */ | |
2f18d1e8 | 917 | atomic64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 918 | |
7645a24c | 919 | wrmsrl(hwc->event_base + idx, |
948b1bb8 | 920 | (u64)(-left) & x86_pmu.cntval_mask); |
e4abb5d4 | 921 | |
cdd6c482 | 922 | perf_event_update_userpage(event); |
194002b2 | 923 | |
e4abb5d4 | 924 | return ret; |
2f18d1e8 IM |
925 | } |
926 | ||
aff3d91a | 927 | static void x86_pmu_enable_event(struct perf_event *event) |
7c90cc45 | 928 | { |
cdd6c482 | 929 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
7c90cc45 | 930 | if (cpuc->enabled) |
aff3d91a | 931 | __x86_pmu_enable_event(&event->hw); |
241771ef IM |
932 | } |
933 | ||
b690081d | 934 | /* |
1da53e02 SE |
935 | * activate a single event |
936 | * | |
937 | * The event is added to the group of enabled events | |
938 | * but only if it can be scehduled with existing events. | |
939 | * | |
940 | * Called with PMU disabled. If successful and return value 1, | |
941 | * then guaranteed to call perf_enable() and hw_perf_enable() | |
fe9081cc PZ |
942 | */ |
943 | static int x86_pmu_enable(struct perf_event *event) | |
944 | { | |
945 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1da53e02 SE |
946 | struct hw_perf_event *hwc; |
947 | int assign[X86_PMC_IDX_MAX]; | |
948 | int n, n0, ret; | |
fe9081cc | 949 | |
1da53e02 | 950 | hwc = &event->hw; |
fe9081cc | 951 | |
1da53e02 SE |
952 | n0 = cpuc->n_events; |
953 | n = collect_events(cpuc, event, false); | |
954 | if (n < 0) | |
955 | return n; | |
53b441a5 | 956 | |
a072738e | 957 | ret = x86_pmu.schedule_events(cpuc, n, assign); |
1da53e02 SE |
958 | if (ret) |
959 | return ret; | |
960 | /* | |
961 | * copy new assignment, now we know it is possible | |
962 | * will be used by hw_perf_enable() | |
963 | */ | |
964 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
7e2ae347 | 965 | |
1da53e02 | 966 | cpuc->n_events = n; |
356e1f2e | 967 | cpuc->n_added += n - n0; |
95cdd2e7 IM |
968 | |
969 | return 0; | |
241771ef IM |
970 | } |
971 | ||
d76a0812 SE |
972 | static int x86_pmu_start(struct perf_event *event) |
973 | { | |
c08053e6 PZ |
974 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
975 | int idx = event->hw.idx; | |
976 | ||
977 | if (idx == -1) | |
d76a0812 SE |
978 | return -EAGAIN; |
979 | ||
07088edb | 980 | x86_perf_event_set_period(event); |
c08053e6 PZ |
981 | cpuc->events[idx] = event; |
982 | __set_bit(idx, cpuc->active_mask); | |
aff3d91a | 983 | x86_pmu.enable(event); |
c08053e6 | 984 | perf_event_update_userpage(event); |
d76a0812 SE |
985 | |
986 | return 0; | |
987 | } | |
988 | ||
cdd6c482 | 989 | static void x86_pmu_unthrottle(struct perf_event *event) |
a78ac325 | 990 | { |
71e2d282 PZ |
991 | int ret = x86_pmu_start(event); |
992 | WARN_ON_ONCE(ret); | |
a78ac325 PZ |
993 | } |
994 | ||
cdd6c482 | 995 | void perf_event_print_debug(void) |
241771ef | 996 | { |
2f18d1e8 | 997 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
ca037701 | 998 | u64 pebs; |
cdd6c482 | 999 | struct cpu_hw_events *cpuc; |
5bb9efe3 | 1000 | unsigned long flags; |
1e125676 IM |
1001 | int cpu, idx; |
1002 | ||
948b1bb8 | 1003 | if (!x86_pmu.num_counters) |
1e125676 | 1004 | return; |
241771ef | 1005 | |
5bb9efe3 | 1006 | local_irq_save(flags); |
241771ef IM |
1007 | |
1008 | cpu = smp_processor_id(); | |
cdd6c482 | 1009 | cpuc = &per_cpu(cpu_hw_events, cpu); |
241771ef | 1010 | |
faa28ae0 | 1011 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
1012 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
1013 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
1014 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
1015 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
ca037701 | 1016 | rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); |
a1ef58f4 JSR |
1017 | |
1018 | pr_info("\n"); | |
1019 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
1020 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
1021 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
1022 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
ca037701 | 1023 | pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); |
f87ad35d | 1024 | } |
7645a24c | 1025 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
241771ef | 1026 | |
948b1bb8 | 1027 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
4a06bd85 RR |
1028 | rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl); |
1029 | rdmsrl(x86_pmu.perfctr + idx, pmc_count); | |
241771ef | 1030 | |
245b2e70 | 1031 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
241771ef | 1032 | |
a1ef58f4 | 1033 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 1034 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 1035 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 1036 | cpu, idx, pmc_count); |
a1ef58f4 | 1037 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 1038 | cpu, idx, prev_left); |
241771ef | 1039 | } |
948b1bb8 | 1040 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
2f18d1e8 IM |
1041 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
1042 | ||
a1ef58f4 | 1043 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
1044 | cpu, idx, pmc_count); |
1045 | } | |
5bb9efe3 | 1046 | local_irq_restore(flags); |
241771ef IM |
1047 | } |
1048 | ||
d76a0812 | 1049 | static void x86_pmu_stop(struct perf_event *event) |
241771ef | 1050 | { |
d76a0812 | 1051 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
cdd6c482 | 1052 | struct hw_perf_event *hwc = &event->hw; |
2e841873 | 1053 | int idx = hwc->idx; |
241771ef | 1054 | |
71e2d282 PZ |
1055 | if (!__test_and_clear_bit(idx, cpuc->active_mask)) |
1056 | return; | |
1057 | ||
aff3d91a | 1058 | x86_pmu.disable(event); |
241771ef | 1059 | |
ee06094f | 1060 | /* |
cdd6c482 | 1061 | * Drain the remaining delta count out of a event |
ee06094f IM |
1062 | * that we are disabling: |
1063 | */ | |
cc2ad4ba | 1064 | x86_perf_event_update(event); |
30dd568c | 1065 | |
cdd6c482 | 1066 | cpuc->events[idx] = NULL; |
2e841873 PZ |
1067 | } |
1068 | ||
1069 | static void x86_pmu_disable(struct perf_event *event) | |
1070 | { | |
1071 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1072 | int i; | |
1073 | ||
d76a0812 | 1074 | x86_pmu_stop(event); |
194002b2 | 1075 | |
1da53e02 SE |
1076 | for (i = 0; i < cpuc->n_events; i++) { |
1077 | if (event == cpuc->event_list[i]) { | |
1078 | ||
1079 | if (x86_pmu.put_event_constraints) | |
1080 | x86_pmu.put_event_constraints(cpuc, event); | |
1081 | ||
1082 | while (++i < cpuc->n_events) | |
1083 | cpuc->event_list[i-1] = cpuc->event_list[i]; | |
1084 | ||
1085 | --cpuc->n_events; | |
6c9687ab | 1086 | break; |
1da53e02 SE |
1087 | } |
1088 | } | |
cdd6c482 | 1089 | perf_event_update_userpage(event); |
241771ef IM |
1090 | } |
1091 | ||
8c48e444 | 1092 | static int x86_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 1093 | { |
df1a132b | 1094 | struct perf_sample_data data; |
cdd6c482 IM |
1095 | struct cpu_hw_events *cpuc; |
1096 | struct perf_event *event; | |
1097 | struct hw_perf_event *hwc; | |
11d1578f | 1098 | int idx, handled = 0; |
9029a5e3 IM |
1099 | u64 val; |
1100 | ||
dc1d628a | 1101 | perf_sample_data_init(&data, 0); |
df1a132b | 1102 | |
cdd6c482 | 1103 | cpuc = &__get_cpu_var(cpu_hw_events); |
962bf7a6 | 1104 | |
948b1bb8 | 1105 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
43f6201a | 1106 | if (!test_bit(idx, cpuc->active_mask)) |
a29aa8a7 | 1107 | continue; |
962bf7a6 | 1108 | |
cdd6c482 IM |
1109 | event = cpuc->events[idx]; |
1110 | hwc = &event->hw; | |
a4016a79 | 1111 | |
cc2ad4ba | 1112 | val = x86_perf_event_update(event); |
948b1bb8 | 1113 | if (val & (1ULL << (x86_pmu.cntval_bits - 1))) |
48e22d56 | 1114 | continue; |
962bf7a6 | 1115 | |
9e350de3 | 1116 | /* |
cdd6c482 | 1117 | * event overflow |
9e350de3 PZ |
1118 | */ |
1119 | handled = 1; | |
cdd6c482 | 1120 | data.period = event->hw.last_period; |
9e350de3 | 1121 | |
07088edb | 1122 | if (!x86_perf_event_set_period(event)) |
e4abb5d4 PZ |
1123 | continue; |
1124 | ||
cdd6c482 | 1125 | if (perf_event_overflow(event, 1, &data, regs)) |
71e2d282 | 1126 | x86_pmu_stop(event); |
a29aa8a7 | 1127 | } |
962bf7a6 | 1128 | |
9e350de3 PZ |
1129 | if (handled) |
1130 | inc_irq_stat(apic_perf_irqs); | |
1131 | ||
a29aa8a7 RR |
1132 | return handled; |
1133 | } | |
39d81eab | 1134 | |
b6276f35 PZ |
1135 | void smp_perf_pending_interrupt(struct pt_regs *regs) |
1136 | { | |
1137 | irq_enter(); | |
1138 | ack_APIC_irq(); | |
1139 | inc_irq_stat(apic_pending_irqs); | |
cdd6c482 | 1140 | perf_event_do_pending(); |
b6276f35 PZ |
1141 | irq_exit(); |
1142 | } | |
1143 | ||
cdd6c482 | 1144 | void set_perf_event_pending(void) |
b6276f35 | 1145 | { |
04da8a43 | 1146 | #ifdef CONFIG_X86_LOCAL_APIC |
7d428966 PZ |
1147 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
1148 | return; | |
1149 | ||
b6276f35 | 1150 | apic->send_IPI_self(LOCAL_PENDING_VECTOR); |
04da8a43 | 1151 | #endif |
b6276f35 PZ |
1152 | } |
1153 | ||
cdd6c482 | 1154 | void perf_events_lapic_init(void) |
241771ef | 1155 | { |
04da8a43 | 1156 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
241771ef | 1157 | return; |
85cf9dba | 1158 | |
241771ef | 1159 | /* |
c323d95f | 1160 | * Always use NMI for PMU |
241771ef | 1161 | */ |
c323d95f | 1162 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
241771ef IM |
1163 | } |
1164 | ||
1165 | static int __kprobes | |
cdd6c482 | 1166 | perf_event_nmi_handler(struct notifier_block *self, |
241771ef IM |
1167 | unsigned long cmd, void *__args) |
1168 | { | |
1169 | struct die_args *args = __args; | |
1170 | struct pt_regs *regs; | |
b0f3f28e | 1171 | |
cdd6c482 | 1172 | if (!atomic_read(&active_events)) |
63a809a2 PZ |
1173 | return NOTIFY_DONE; |
1174 | ||
b0f3f28e PZ |
1175 | switch (cmd) { |
1176 | case DIE_NMI: | |
1177 | case DIE_NMI_IPI: | |
1178 | break; | |
241771ef | 1179 | |
b0f3f28e | 1180 | default: |
241771ef | 1181 | return NOTIFY_DONE; |
b0f3f28e | 1182 | } |
241771ef IM |
1183 | |
1184 | regs = args->regs; | |
1185 | ||
1186 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
a4016a79 PZ |
1187 | /* |
1188 | * Can't rely on the handled return value to say it was our NMI, two | |
cdd6c482 | 1189 | * events could trigger 'simultaneously' raising two back-to-back NMIs. |
a4016a79 PZ |
1190 | * |
1191 | * If the first NMI handles both, the latter will be empty and daze | |
1192 | * the CPU. | |
1193 | */ | |
a3288106 | 1194 | x86_pmu.handle_irq(regs); |
241771ef | 1195 | |
a4016a79 | 1196 | return NOTIFY_STOP; |
241771ef IM |
1197 | } |
1198 | ||
f22f54f4 PZ |
1199 | static __read_mostly struct notifier_block perf_event_nmi_notifier = { |
1200 | .notifier_call = perf_event_nmi_handler, | |
1201 | .next = NULL, | |
1202 | .priority = 1 | |
1203 | }; | |
1204 | ||
63b14649 | 1205 | static struct event_constraint unconstrained; |
38331f62 | 1206 | static struct event_constraint emptyconstraint; |
63b14649 | 1207 | |
63b14649 | 1208 | static struct event_constraint * |
f22f54f4 | 1209 | x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event) |
1da53e02 | 1210 | { |
63b14649 | 1211 | struct event_constraint *c; |
1da53e02 | 1212 | |
1da53e02 SE |
1213 | if (x86_pmu.event_constraints) { |
1214 | for_each_event_constraint(c, x86_pmu.event_constraints) { | |
63b14649 PZ |
1215 | if ((event->hw.config & c->cmask) == c->code) |
1216 | return c; | |
1da53e02 SE |
1217 | } |
1218 | } | |
63b14649 PZ |
1219 | |
1220 | return &unconstrained; | |
1da53e02 SE |
1221 | } |
1222 | ||
1da53e02 | 1223 | static int x86_event_sched_in(struct perf_event *event, |
6e37738a | 1224 | struct perf_cpu_context *cpuctx) |
1da53e02 SE |
1225 | { |
1226 | int ret = 0; | |
1227 | ||
1228 | event->state = PERF_EVENT_STATE_ACTIVE; | |
6e37738a | 1229 | event->oncpu = smp_processor_id(); |
1da53e02 SE |
1230 | event->tstamp_running += event->ctx->time - event->tstamp_stopped; |
1231 | ||
1232 | if (!is_x86_event(event)) | |
1233 | ret = event->pmu->enable(event); | |
1234 | ||
1235 | if (!ret && !is_software_event(event)) | |
1236 | cpuctx->active_oncpu++; | |
1237 | ||
1238 | if (!ret && event->attr.exclusive) | |
1239 | cpuctx->exclusive = 1; | |
1240 | ||
1241 | return ret; | |
1242 | } | |
1243 | ||
1244 | static void x86_event_sched_out(struct perf_event *event, | |
6e37738a | 1245 | struct perf_cpu_context *cpuctx) |
1da53e02 SE |
1246 | { |
1247 | event->state = PERF_EVENT_STATE_INACTIVE; | |
1248 | event->oncpu = -1; | |
1249 | ||
1250 | if (!is_x86_event(event)) | |
1251 | event->pmu->disable(event); | |
1252 | ||
1253 | event->tstamp_running -= event->ctx->time - event->tstamp_stopped; | |
1254 | ||
1255 | if (!is_software_event(event)) | |
1256 | cpuctx->active_oncpu--; | |
1257 | ||
1258 | if (event->attr.exclusive || !cpuctx->active_oncpu) | |
1259 | cpuctx->exclusive = 0; | |
1260 | } | |
1261 | ||
1262 | /* | |
1263 | * Called to enable a whole group of events. | |
1264 | * Returns 1 if the group was enabled, or -EAGAIN if it could not be. | |
1265 | * Assumes the caller has disabled interrupts and has | |
1266 | * frozen the PMU with hw_perf_save_disable. | |
1267 | * | |
1268 | * called with PMU disabled. If successful and return value 1, | |
1269 | * then guaranteed to call perf_enable() and hw_perf_enable() | |
1270 | */ | |
1271 | int hw_perf_group_sched_in(struct perf_event *leader, | |
1272 | struct perf_cpu_context *cpuctx, | |
6e37738a | 1273 | struct perf_event_context *ctx) |
1da53e02 | 1274 | { |
6e37738a | 1275 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
1da53e02 SE |
1276 | struct perf_event *sub; |
1277 | int assign[X86_PMC_IDX_MAX]; | |
1278 | int n0, n1, ret; | |
1279 | ||
0b861225 CG |
1280 | if (!x86_pmu_initialized()) |
1281 | return 0; | |
1282 | ||
1da53e02 SE |
1283 | /* n0 = total number of events */ |
1284 | n0 = collect_events(cpuc, leader, true); | |
1285 | if (n0 < 0) | |
1286 | return n0; | |
1287 | ||
a072738e | 1288 | ret = x86_pmu.schedule_events(cpuc, n0, assign); |
1da53e02 SE |
1289 | if (ret) |
1290 | return ret; | |
1291 | ||
6e37738a | 1292 | ret = x86_event_sched_in(leader, cpuctx); |
1da53e02 SE |
1293 | if (ret) |
1294 | return ret; | |
1295 | ||
1296 | n1 = 1; | |
1297 | list_for_each_entry(sub, &leader->sibling_list, group_entry) { | |
8113070d | 1298 | if (sub->state > PERF_EVENT_STATE_OFF) { |
6e37738a | 1299 | ret = x86_event_sched_in(sub, cpuctx); |
1da53e02 SE |
1300 | if (ret) |
1301 | goto undo; | |
1302 | ++n1; | |
1303 | } | |
1304 | } | |
1305 | /* | |
1306 | * copy new assignment, now we know it is possible | |
1307 | * will be used by hw_perf_enable() | |
1308 | */ | |
1309 | memcpy(cpuc->assign, assign, n0*sizeof(int)); | |
1310 | ||
1311 | cpuc->n_events = n0; | |
356e1f2e | 1312 | cpuc->n_added += n1; |
1da53e02 SE |
1313 | ctx->nr_active += n1; |
1314 | ||
1315 | /* | |
1316 | * 1 means successful and events are active | |
1317 | * This is not quite true because we defer | |
1318 | * actual activation until hw_perf_enable() but | |
1319 | * this way we* ensure caller won't try to enable | |
1320 | * individual events | |
1321 | */ | |
1322 | return 1; | |
1323 | undo: | |
6e37738a | 1324 | x86_event_sched_out(leader, cpuctx); |
1da53e02 SE |
1325 | n0 = 1; |
1326 | list_for_each_entry(sub, &leader->sibling_list, group_entry) { | |
1327 | if (sub->state == PERF_EVENT_STATE_ACTIVE) { | |
6e37738a | 1328 | x86_event_sched_out(sub, cpuctx); |
1da53e02 SE |
1329 | if (++n0 == n1) |
1330 | break; | |
1331 | } | |
1332 | } | |
1333 | return ret; | |
1334 | } | |
1335 | ||
f22f54f4 PZ |
1336 | #include "perf_event_amd.c" |
1337 | #include "perf_event_p6.c" | |
a072738e | 1338 | #include "perf_event_p4.c" |
caff2bef | 1339 | #include "perf_event_intel_lbr.c" |
ca037701 | 1340 | #include "perf_event_intel_ds.c" |
f22f54f4 | 1341 | #include "perf_event_intel.c" |
f87ad35d | 1342 | |
3f6da390 PZ |
1343 | static int __cpuinit |
1344 | x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) | |
1345 | { | |
1346 | unsigned int cpu = (long)hcpu; | |
b38b24ea | 1347 | int ret = NOTIFY_OK; |
3f6da390 PZ |
1348 | |
1349 | switch (action & ~CPU_TASKS_FROZEN) { | |
1350 | case CPU_UP_PREPARE: | |
1351 | if (x86_pmu.cpu_prepare) | |
b38b24ea | 1352 | ret = x86_pmu.cpu_prepare(cpu); |
3f6da390 PZ |
1353 | break; |
1354 | ||
1355 | case CPU_STARTING: | |
1356 | if (x86_pmu.cpu_starting) | |
1357 | x86_pmu.cpu_starting(cpu); | |
1358 | break; | |
1359 | ||
1360 | case CPU_DYING: | |
1361 | if (x86_pmu.cpu_dying) | |
1362 | x86_pmu.cpu_dying(cpu); | |
1363 | break; | |
1364 | ||
b38b24ea | 1365 | case CPU_UP_CANCELED: |
3f6da390 PZ |
1366 | case CPU_DEAD: |
1367 | if (x86_pmu.cpu_dead) | |
1368 | x86_pmu.cpu_dead(cpu); | |
1369 | break; | |
1370 | ||
1371 | default: | |
1372 | break; | |
1373 | } | |
1374 | ||
b38b24ea | 1375 | return ret; |
3f6da390 PZ |
1376 | } |
1377 | ||
12558038 CG |
1378 | static void __init pmu_check_apic(void) |
1379 | { | |
1380 | if (cpu_has_apic) | |
1381 | return; | |
1382 | ||
1383 | x86_pmu.apic = 0; | |
1384 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); | |
1385 | pr_info("no hardware sampling interrupt available.\n"); | |
1386 | } | |
1387 | ||
cdd6c482 | 1388 | void __init init_hw_perf_events(void) |
b56a3802 | 1389 | { |
b622d644 | 1390 | struct event_constraint *c; |
72eae04d RR |
1391 | int err; |
1392 | ||
cdd6c482 | 1393 | pr_info("Performance Events: "); |
1123e3ad | 1394 | |
b56a3802 JSR |
1395 | switch (boot_cpu_data.x86_vendor) { |
1396 | case X86_VENDOR_INTEL: | |
72eae04d | 1397 | err = intel_pmu_init(); |
b56a3802 | 1398 | break; |
f87ad35d | 1399 | case X86_VENDOR_AMD: |
72eae04d | 1400 | err = amd_pmu_init(); |
f87ad35d | 1401 | break; |
4138960a RR |
1402 | default: |
1403 | return; | |
b56a3802 | 1404 | } |
1123e3ad | 1405 | if (err != 0) { |
cdd6c482 | 1406 | pr_cont("no PMU driver, software events only.\n"); |
b56a3802 | 1407 | return; |
1123e3ad | 1408 | } |
b56a3802 | 1409 | |
12558038 CG |
1410 | pmu_check_apic(); |
1411 | ||
1123e3ad | 1412 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
faa28ae0 | 1413 | |
3c44780b PZ |
1414 | if (x86_pmu.quirks) |
1415 | x86_pmu.quirks(); | |
1416 | ||
948b1bb8 | 1417 | if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) { |
cdd6c482 | 1418 | WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", |
948b1bb8 RR |
1419 | x86_pmu.num_counters, X86_PMC_MAX_GENERIC); |
1420 | x86_pmu.num_counters = X86_PMC_MAX_GENERIC; | |
241771ef | 1421 | } |
948b1bb8 RR |
1422 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; |
1423 | perf_max_events = x86_pmu.num_counters; | |
241771ef | 1424 | |
948b1bb8 | 1425 | if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) { |
cdd6c482 | 1426 | WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", |
948b1bb8 RR |
1427 | x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED); |
1428 | x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED; | |
703e937c | 1429 | } |
862a1a5f | 1430 | |
d6dc0b4e | 1431 | x86_pmu.intel_ctrl |= |
948b1bb8 | 1432 | ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED; |
241771ef | 1433 | |
cdd6c482 IM |
1434 | perf_events_lapic_init(); |
1435 | register_die_notifier(&perf_event_nmi_notifier); | |
1123e3ad | 1436 | |
63b14649 | 1437 | unconstrained = (struct event_constraint) |
948b1bb8 RR |
1438 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, |
1439 | 0, x86_pmu.num_counters); | |
63b14649 | 1440 | |
b622d644 PZ |
1441 | if (x86_pmu.event_constraints) { |
1442 | for_each_event_constraint(c, x86_pmu.event_constraints) { | |
a098f448 | 1443 | if (c->cmask != X86_RAW_EVENT_MASK) |
b622d644 PZ |
1444 | continue; |
1445 | ||
948b1bb8 RR |
1446 | c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; |
1447 | c->weight += x86_pmu.num_counters; | |
b622d644 PZ |
1448 | } |
1449 | } | |
1450 | ||
57c0c15b | 1451 | pr_info("... version: %d\n", x86_pmu.version); |
948b1bb8 RR |
1452 | pr_info("... bit width: %d\n", x86_pmu.cntval_bits); |
1453 | pr_info("... generic registers: %d\n", x86_pmu.num_counters); | |
1454 | pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); | |
57c0c15b | 1455 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
948b1bb8 | 1456 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed); |
d6dc0b4e | 1457 | pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl); |
3f6da390 PZ |
1458 | |
1459 | perf_cpu_notifier(x86_pmu_notifier); | |
241771ef | 1460 | } |
621a01ea | 1461 | |
cdd6c482 | 1462 | static inline void x86_pmu_read(struct perf_event *event) |
ee06094f | 1463 | { |
cc2ad4ba | 1464 | x86_perf_event_update(event); |
ee06094f IM |
1465 | } |
1466 | ||
4aeb0b42 RR |
1467 | static const struct pmu pmu = { |
1468 | .enable = x86_pmu_enable, | |
1469 | .disable = x86_pmu_disable, | |
d76a0812 SE |
1470 | .start = x86_pmu_start, |
1471 | .stop = x86_pmu_stop, | |
4aeb0b42 | 1472 | .read = x86_pmu_read, |
a78ac325 | 1473 | .unthrottle = x86_pmu_unthrottle, |
621a01ea IM |
1474 | }; |
1475 | ||
ca037701 PZ |
1476 | /* |
1477 | * validate that we can schedule this event | |
1478 | */ | |
1479 | static int validate_event(struct perf_event *event) | |
1480 | { | |
1481 | struct cpu_hw_events *fake_cpuc; | |
1482 | struct event_constraint *c; | |
1483 | int ret = 0; | |
1484 | ||
1485 | fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO); | |
1486 | if (!fake_cpuc) | |
1487 | return -ENOMEM; | |
1488 | ||
1489 | c = x86_pmu.get_event_constraints(fake_cpuc, event); | |
1490 | ||
1491 | if (!c || !c->weight) | |
1492 | ret = -ENOSPC; | |
1493 | ||
1494 | if (x86_pmu.put_event_constraints) | |
1495 | x86_pmu.put_event_constraints(fake_cpuc, event); | |
1496 | ||
1497 | kfree(fake_cpuc); | |
1498 | ||
1499 | return ret; | |
1500 | } | |
1501 | ||
1da53e02 SE |
1502 | /* |
1503 | * validate a single event group | |
1504 | * | |
1505 | * validation include: | |
184f412c IM |
1506 | * - check events are compatible which each other |
1507 | * - events do not compete for the same counter | |
1508 | * - number of events <= number of counters | |
1da53e02 SE |
1509 | * |
1510 | * validation ensures the group can be loaded onto the | |
1511 | * PMU if it was the only group available. | |
1512 | */ | |
fe9081cc PZ |
1513 | static int validate_group(struct perf_event *event) |
1514 | { | |
1da53e02 | 1515 | struct perf_event *leader = event->group_leader; |
502568d5 PZ |
1516 | struct cpu_hw_events *fake_cpuc; |
1517 | int ret, n; | |
fe9081cc | 1518 | |
502568d5 PZ |
1519 | ret = -ENOMEM; |
1520 | fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO); | |
1521 | if (!fake_cpuc) | |
1522 | goto out; | |
fe9081cc | 1523 | |
1da53e02 SE |
1524 | /* |
1525 | * the event is not yet connected with its | |
1526 | * siblings therefore we must first collect | |
1527 | * existing siblings, then add the new event | |
1528 | * before we can simulate the scheduling | |
1529 | */ | |
502568d5 PZ |
1530 | ret = -ENOSPC; |
1531 | n = collect_events(fake_cpuc, leader, true); | |
1da53e02 | 1532 | if (n < 0) |
502568d5 | 1533 | goto out_free; |
fe9081cc | 1534 | |
502568d5 PZ |
1535 | fake_cpuc->n_events = n; |
1536 | n = collect_events(fake_cpuc, event, false); | |
1da53e02 | 1537 | if (n < 0) |
502568d5 | 1538 | goto out_free; |
fe9081cc | 1539 | |
502568d5 | 1540 | fake_cpuc->n_events = n; |
1da53e02 | 1541 | |
a072738e | 1542 | ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); |
502568d5 PZ |
1543 | |
1544 | out_free: | |
1545 | kfree(fake_cpuc); | |
1546 | out: | |
1547 | return ret; | |
fe9081cc PZ |
1548 | } |
1549 | ||
cdd6c482 | 1550 | const struct pmu *hw_perf_event_init(struct perf_event *event) |
621a01ea | 1551 | { |
8113070d | 1552 | const struct pmu *tmp; |
621a01ea IM |
1553 | int err; |
1554 | ||
cdd6c482 | 1555 | err = __hw_perf_event_init(event); |
fe9081cc | 1556 | if (!err) { |
8113070d SE |
1557 | /* |
1558 | * we temporarily connect event to its pmu | |
1559 | * such that validate_group() can classify | |
1560 | * it as an x86 event using is_x86_event() | |
1561 | */ | |
1562 | tmp = event->pmu; | |
1563 | event->pmu = &pmu; | |
1564 | ||
fe9081cc PZ |
1565 | if (event->group_leader != event) |
1566 | err = validate_group(event); | |
ca037701 PZ |
1567 | else |
1568 | err = validate_event(event); | |
8113070d SE |
1569 | |
1570 | event->pmu = tmp; | |
fe9081cc | 1571 | } |
a1792cda | 1572 | if (err) { |
cdd6c482 IM |
1573 | if (event->destroy) |
1574 | event->destroy(event); | |
9ea98e19 | 1575 | return ERR_PTR(err); |
a1792cda | 1576 | } |
621a01ea | 1577 | |
4aeb0b42 | 1578 | return &pmu; |
621a01ea | 1579 | } |
d7d59fb3 PZ |
1580 | |
1581 | /* | |
1582 | * callchain support | |
1583 | */ | |
1584 | ||
1585 | static inline | |
f9188e02 | 1586 | void callchain_store(struct perf_callchain_entry *entry, u64 ip) |
d7d59fb3 | 1587 | { |
f9188e02 | 1588 | if (entry->nr < PERF_MAX_STACK_DEPTH) |
d7d59fb3 PZ |
1589 | entry->ip[entry->nr++] = ip; |
1590 | } | |
1591 | ||
245b2e70 TH |
1592 | static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry); |
1593 | static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry); | |
d7d59fb3 PZ |
1594 | |
1595 | ||
1596 | static void | |
1597 | backtrace_warning_symbol(void *data, char *msg, unsigned long symbol) | |
1598 | { | |
1599 | /* Ignore warnings */ | |
1600 | } | |
1601 | ||
1602 | static void backtrace_warning(void *data, char *msg) | |
1603 | { | |
1604 | /* Ignore warnings */ | |
1605 | } | |
1606 | ||
1607 | static int backtrace_stack(void *data, char *name) | |
1608 | { | |
038e836e | 1609 | return 0; |
d7d59fb3 PZ |
1610 | } |
1611 | ||
1612 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
1613 | { | |
1614 | struct perf_callchain_entry *entry = data; | |
1615 | ||
1616 | if (reliable) | |
1617 | callchain_store(entry, addr); | |
1618 | } | |
1619 | ||
1620 | static const struct stacktrace_ops backtrace_ops = { | |
1621 | .warning = backtrace_warning, | |
1622 | .warning_symbol = backtrace_warning_symbol, | |
1623 | .stack = backtrace_stack, | |
1624 | .address = backtrace_address, | |
06d65bda | 1625 | .walk_stack = print_context_stack_bp, |
d7d59fb3 PZ |
1626 | }; |
1627 | ||
038e836e IM |
1628 | #include "../dumpstack.h" |
1629 | ||
d7d59fb3 PZ |
1630 | static void |
1631 | perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1632 | { | |
f9188e02 | 1633 | callchain_store(entry, PERF_CONTEXT_KERNEL); |
038e836e | 1634 | callchain_store(entry, regs->ip); |
d7d59fb3 | 1635 | |
48b5ba9c | 1636 | dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry); |
d7d59fb3 PZ |
1637 | } |
1638 | ||
257ef9d2 TE |
1639 | #ifdef CONFIG_COMPAT |
1640 | static inline int | |
1641 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
74193ef0 | 1642 | { |
257ef9d2 TE |
1643 | /* 32-bit process in 64-bit kernel. */ |
1644 | struct stack_frame_ia32 frame; | |
1645 | const void __user *fp; | |
74193ef0 | 1646 | |
257ef9d2 TE |
1647 | if (!test_thread_flag(TIF_IA32)) |
1648 | return 0; | |
1649 | ||
1650 | fp = compat_ptr(regs->bp); | |
1651 | while (entry->nr < PERF_MAX_STACK_DEPTH) { | |
1652 | unsigned long bytes; | |
1653 | frame.next_frame = 0; | |
1654 | frame.return_address = 0; | |
1655 | ||
1656 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); | |
1657 | if (bytes != sizeof(frame)) | |
1658 | break; | |
74193ef0 | 1659 | |
257ef9d2 TE |
1660 | if (fp < compat_ptr(regs->sp)) |
1661 | break; | |
74193ef0 | 1662 | |
257ef9d2 TE |
1663 | callchain_store(entry, frame.return_address); |
1664 | fp = compat_ptr(frame.next_frame); | |
1665 | } | |
1666 | return 1; | |
d7d59fb3 | 1667 | } |
257ef9d2 TE |
1668 | #else |
1669 | static inline int | |
1670 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1671 | { | |
1672 | return 0; | |
1673 | } | |
1674 | #endif | |
d7d59fb3 PZ |
1675 | |
1676 | static void | |
1677 | perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1678 | { | |
1679 | struct stack_frame frame; | |
1680 | const void __user *fp; | |
1681 | ||
5a6cec3a IM |
1682 | if (!user_mode(regs)) |
1683 | regs = task_pt_regs(current); | |
1684 | ||
74193ef0 | 1685 | fp = (void __user *)regs->bp; |
d7d59fb3 | 1686 | |
f9188e02 | 1687 | callchain_store(entry, PERF_CONTEXT_USER); |
d7d59fb3 PZ |
1688 | callchain_store(entry, regs->ip); |
1689 | ||
257ef9d2 TE |
1690 | if (perf_callchain_user32(regs, entry)) |
1691 | return; | |
1692 | ||
f9188e02 | 1693 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
257ef9d2 | 1694 | unsigned long bytes; |
038e836e | 1695 | frame.next_frame = NULL; |
d7d59fb3 PZ |
1696 | frame.return_address = 0; |
1697 | ||
257ef9d2 TE |
1698 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); |
1699 | if (bytes != sizeof(frame)) | |
d7d59fb3 PZ |
1700 | break; |
1701 | ||
5a6cec3a | 1702 | if ((unsigned long)fp < regs->sp) |
d7d59fb3 PZ |
1703 | break; |
1704 | ||
1705 | callchain_store(entry, frame.return_address); | |
038e836e | 1706 | fp = frame.next_frame; |
d7d59fb3 PZ |
1707 | } |
1708 | } | |
1709 | ||
1710 | static void | |
1711 | perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1712 | { | |
1713 | int is_user; | |
1714 | ||
1715 | if (!regs) | |
1716 | return; | |
1717 | ||
1718 | is_user = user_mode(regs); | |
1719 | ||
d7d59fb3 PZ |
1720 | if (is_user && current->state != TASK_RUNNING) |
1721 | return; | |
1722 | ||
1723 | if (!is_user) | |
1724 | perf_callchain_kernel(regs, entry); | |
1725 | ||
1726 | if (current->mm) | |
1727 | perf_callchain_user(regs, entry); | |
1728 | } | |
1729 | ||
1730 | struct perf_callchain_entry *perf_callchain(struct pt_regs *regs) | |
1731 | { | |
1732 | struct perf_callchain_entry *entry; | |
1733 | ||
1734 | if (in_nmi()) | |
245b2e70 | 1735 | entry = &__get_cpu_var(pmc_nmi_entry); |
d7d59fb3 | 1736 | else |
245b2e70 | 1737 | entry = &__get_cpu_var(pmc_irq_entry); |
d7d59fb3 PZ |
1738 | |
1739 | entry->nr = 0; | |
1740 | ||
1741 | perf_do_callchain(regs, entry); | |
1742 | ||
1743 | return entry; | |
1744 | } | |
5331d7b8 FW |
1745 | |
1746 | void perf_arch_fetch_caller_regs(struct pt_regs *regs, unsigned long ip, int skip) | |
1747 | { | |
1748 | regs->ip = ip; | |
1749 | /* | |
1750 | * perf_arch_fetch_caller_regs adds another call, we need to increment | |
1751 | * the skip level | |
1752 | */ | |
1753 | regs->bp = rewind_frame_pointer(skip + 1); | |
1754 | regs->cs = __KERNEL_CS; | |
1755 | local_save_flags(regs->flags); | |
1756 | } |