Commit | Line | Data |
---|---|---|
241771ef | 1 | /* |
cdd6c482 | 2 | * Performance events x86 architecture code |
241771ef | 3 | * |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
30dd568c | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
1da53e02 | 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
241771ef IM |
11 | * |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | ||
cdd6c482 | 15 | #include <linux/perf_event.h> |
241771ef IM |
16 | #include <linux/capability.h> |
17 | #include <linux/notifier.h> | |
18 | #include <linux/hardirq.h> | |
19 | #include <linux/kprobes.h> | |
4ac13294 | 20 | #include <linux/module.h> |
241771ef IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/sched.h> | |
d7d59fb3 | 23 | #include <linux/uaccess.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
74193ef0 | 25 | #include <linux/highmem.h> |
30dd568c | 26 | #include <linux/cpu.h> |
272d30be | 27 | #include <linux/bitops.h> |
241771ef | 28 | |
241771ef | 29 | #include <asm/apic.h> |
d7d59fb3 | 30 | #include <asm/stacktrace.h> |
4e935e47 | 31 | #include <asm/nmi.h> |
257ef9d2 | 32 | #include <asm/compat.h> |
241771ef | 33 | |
7645a24c PZ |
34 | #if 0 |
35 | #undef wrmsrl | |
36 | #define wrmsrl(msr, val) \ | |
37 | do { \ | |
38 | trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\ | |
39 | (unsigned long)(val)); \ | |
40 | native_write_msr((msr), (u32)((u64)(val)), \ | |
41 | (u32)((u64)(val) >> 32)); \ | |
42 | } while (0) | |
43 | #endif | |
44 | ||
ef21f683 PZ |
45 | /* |
46 | * best effort, GUP based copy_from_user() that assumes IRQ or NMI context | |
47 | */ | |
48 | static unsigned long | |
49 | copy_from_user_nmi(void *to, const void __user *from, unsigned long n) | |
50 | { | |
51 | unsigned long offset, addr = (unsigned long)from; | |
ef21f683 PZ |
52 | unsigned long size, len = 0; |
53 | struct page *page; | |
54 | void *map; | |
55 | int ret; | |
56 | ||
57 | do { | |
58 | ret = __get_user_pages_fast(addr, 1, 0, &page); | |
59 | if (!ret) | |
60 | break; | |
61 | ||
62 | offset = addr & (PAGE_SIZE - 1); | |
63 | size = min(PAGE_SIZE - offset, n - len); | |
64 | ||
7a837d1b | 65 | map = kmap_atomic(page); |
ef21f683 | 66 | memcpy(to, map+offset, size); |
7a837d1b | 67 | kunmap_atomic(map); |
ef21f683 PZ |
68 | put_page(page); |
69 | ||
70 | len += size; | |
71 | to += size; | |
72 | addr += size; | |
73 | ||
74 | } while (len < n); | |
75 | ||
76 | return len; | |
77 | } | |
78 | ||
1da53e02 | 79 | struct event_constraint { |
c91e0f5d PZ |
80 | union { |
81 | unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
b622d644 | 82 | u64 idxmsk64; |
c91e0f5d | 83 | }; |
b622d644 PZ |
84 | u64 code; |
85 | u64 cmask; | |
272d30be | 86 | int weight; |
1da53e02 SE |
87 | }; |
88 | ||
38331f62 SE |
89 | struct amd_nb { |
90 | int nb_id; /* NorthBridge id */ | |
91 | int refcnt; /* reference count */ | |
92 | struct perf_event *owners[X86_PMC_IDX_MAX]; | |
93 | struct event_constraint event_constraints[X86_PMC_IDX_MAX]; | |
94 | }; | |
95 | ||
caff2bef PZ |
96 | #define MAX_LBR_ENTRIES 16 |
97 | ||
cdd6c482 | 98 | struct cpu_hw_events { |
ca037701 PZ |
99 | /* |
100 | * Generic x86 PMC bits | |
101 | */ | |
1da53e02 | 102 | struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */ |
43f6201a | 103 | unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
63e6be6d | 104 | unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
b0f3f28e | 105 | int enabled; |
241771ef | 106 | |
1da53e02 SE |
107 | int n_events; |
108 | int n_added; | |
90151c35 | 109 | int n_txn; |
1da53e02 | 110 | int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ |
447a194b | 111 | u64 tags[X86_PMC_IDX_MAX]; |
1da53e02 | 112 | struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */ |
ca037701 | 113 | |
4d1c52b0 LM |
114 | unsigned int group_flag; |
115 | ||
ca037701 PZ |
116 | /* |
117 | * Intel DebugStore bits | |
118 | */ | |
119 | struct debug_store *ds; | |
120 | u64 pebs_enabled; | |
121 | ||
caff2bef PZ |
122 | /* |
123 | * Intel LBR bits | |
124 | */ | |
125 | int lbr_users; | |
126 | void *lbr_context; | |
127 | struct perf_branch_stack lbr_stack; | |
128 | struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES]; | |
129 | ||
ca037701 PZ |
130 | /* |
131 | * AMD specific bits | |
132 | */ | |
38331f62 | 133 | struct amd_nb *amd_nb; |
b690081d SE |
134 | }; |
135 | ||
fce877e3 | 136 | #define __EVENT_CONSTRAINT(c, n, m, w) {\ |
b622d644 | 137 | { .idxmsk64 = (n) }, \ |
c91e0f5d PZ |
138 | .code = (c), \ |
139 | .cmask = (m), \ | |
fce877e3 | 140 | .weight = (w), \ |
c91e0f5d | 141 | } |
b690081d | 142 | |
fce877e3 PZ |
143 | #define EVENT_CONSTRAINT(c, n, m) \ |
144 | __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n)) | |
145 | ||
ca037701 PZ |
146 | /* |
147 | * Constraint on the Event code. | |
148 | */ | |
ed8777fc | 149 | #define INTEL_EVENT_CONSTRAINT(c, n) \ |
a098f448 | 150 | EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT) |
8433be11 | 151 | |
ca037701 PZ |
152 | /* |
153 | * Constraint on the Event code + UMask + fixed-mask | |
a098f448 RR |
154 | * |
155 | * filter mask to validate fixed counter events. | |
156 | * the following filters disqualify for fixed counters: | |
157 | * - inv | |
158 | * - edge | |
159 | * - cnt-mask | |
160 | * The other filters are supported by fixed counters. | |
161 | * The any-thread option is supported starting with v3. | |
ca037701 | 162 | */ |
ed8777fc | 163 | #define FIXED_EVENT_CONSTRAINT(c, n) \ |
a098f448 | 164 | EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK) |
8433be11 | 165 | |
ca037701 PZ |
166 | /* |
167 | * Constraint on the Event code + UMask | |
168 | */ | |
169 | #define PEBS_EVENT_CONSTRAINT(c, n) \ | |
170 | EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK) | |
171 | ||
ed8777fc PZ |
172 | #define EVENT_CONSTRAINT_END \ |
173 | EVENT_CONSTRAINT(0, 0, 0) | |
174 | ||
175 | #define for_each_event_constraint(e, c) \ | |
a1f2b70a | 176 | for ((e) = (c); (e)->weight; (e)++) |
b690081d | 177 | |
8db909a7 PZ |
178 | union perf_capabilities { |
179 | struct { | |
180 | u64 lbr_format : 6; | |
181 | u64 pebs_trap : 1; | |
182 | u64 pebs_arch_reg : 1; | |
183 | u64 pebs_format : 4; | |
184 | u64 smm_freeze : 1; | |
185 | }; | |
186 | u64 capabilities; | |
187 | }; | |
188 | ||
241771ef | 189 | /* |
5f4ec28f | 190 | * struct x86_pmu - generic x86 pmu |
241771ef | 191 | */ |
5f4ec28f | 192 | struct x86_pmu { |
ca037701 PZ |
193 | /* |
194 | * Generic x86 PMC bits | |
195 | */ | |
faa28ae0 RR |
196 | const char *name; |
197 | int version; | |
a3288106 | 198 | int (*handle_irq)(struct pt_regs *); |
9e35ad38 | 199 | void (*disable_all)(void); |
11164cd4 | 200 | void (*enable_all)(int added); |
aff3d91a PZ |
201 | void (*enable)(struct perf_event *); |
202 | void (*disable)(struct perf_event *); | |
b4cdc5c2 | 203 | int (*hw_config)(struct perf_event *event); |
a072738e | 204 | int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign); |
169e41eb JSR |
205 | unsigned eventsel; |
206 | unsigned perfctr; | |
b0f3f28e | 207 | u64 (*event_map)(int); |
169e41eb | 208 | int max_events; |
948b1bb8 RR |
209 | int num_counters; |
210 | int num_counters_fixed; | |
211 | int cntval_bits; | |
212 | u64 cntval_mask; | |
04da8a43 | 213 | int apic; |
c619b8ff | 214 | u64 max_period; |
63b14649 PZ |
215 | struct event_constraint * |
216 | (*get_event_constraints)(struct cpu_hw_events *cpuc, | |
217 | struct perf_event *event); | |
218 | ||
c91e0f5d PZ |
219 | void (*put_event_constraints)(struct cpu_hw_events *cpuc, |
220 | struct perf_event *event); | |
63b14649 | 221 | struct event_constraint *event_constraints; |
3c44780b | 222 | void (*quirks)(void); |
68aa00ac | 223 | int perfctr_second_write; |
3f6da390 | 224 | |
b38b24ea | 225 | int (*cpu_prepare)(int cpu); |
3f6da390 PZ |
226 | void (*cpu_starting)(int cpu); |
227 | void (*cpu_dying)(int cpu); | |
228 | void (*cpu_dead)(int cpu); | |
ca037701 PZ |
229 | |
230 | /* | |
231 | * Intel Arch Perfmon v2+ | |
232 | */ | |
8db909a7 PZ |
233 | u64 intel_ctrl; |
234 | union perf_capabilities intel_cap; | |
ca037701 PZ |
235 | |
236 | /* | |
237 | * Intel DebugStore bits | |
238 | */ | |
239 | int bts, pebs; | |
6809b6ea | 240 | int bts_active, pebs_active; |
ca037701 PZ |
241 | int pebs_record_size; |
242 | void (*drain_pebs)(struct pt_regs *regs); | |
243 | struct event_constraint *pebs_constraints; | |
caff2bef PZ |
244 | |
245 | /* | |
246 | * Intel LBR | |
247 | */ | |
248 | unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */ | |
249 | int lbr_nr; /* hardware stack size */ | |
b56a3802 JSR |
250 | }; |
251 | ||
4a06bd85 | 252 | static struct x86_pmu x86_pmu __read_mostly; |
b56a3802 | 253 | |
cdd6c482 | 254 | static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
b0f3f28e PZ |
255 | .enabled = 1, |
256 | }; | |
241771ef | 257 | |
07088edb | 258 | static int x86_perf_event_set_period(struct perf_event *event); |
b690081d | 259 | |
8326f44d | 260 | /* |
dfc65094 | 261 | * Generalized hw caching related hw_event table, filled |
8326f44d | 262 | * in on a per model basis. A value of 0 means |
dfc65094 IM |
263 | * 'not supported', -1 means 'hw_event makes no sense on |
264 | * this CPU', any other value means the raw hw_event | |
8326f44d IM |
265 | * ID. |
266 | */ | |
267 | ||
268 | #define C(x) PERF_COUNT_HW_CACHE_##x | |
269 | ||
270 | static u64 __read_mostly hw_cache_event_ids | |
271 | [PERF_COUNT_HW_CACHE_MAX] | |
272 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
273 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
274 | ||
ee06094f | 275 | /* |
cdd6c482 IM |
276 | * Propagate event elapsed time into the generic event. |
277 | * Can only be executed on the CPU where the event is active. | |
ee06094f IM |
278 | * Returns the delta events processed. |
279 | */ | |
4b7bfd0d | 280 | static u64 |
cc2ad4ba | 281 | x86_perf_event_update(struct perf_event *event) |
ee06094f | 282 | { |
cc2ad4ba | 283 | struct hw_perf_event *hwc = &event->hw; |
948b1bb8 | 284 | int shift = 64 - x86_pmu.cntval_bits; |
ec3232bd | 285 | u64 prev_raw_count, new_raw_count; |
cc2ad4ba | 286 | int idx = hwc->idx; |
ec3232bd | 287 | s64 delta; |
ee06094f | 288 | |
30dd568c MM |
289 | if (idx == X86_PMC_IDX_FIXED_BTS) |
290 | return 0; | |
291 | ||
ee06094f | 292 | /* |
cdd6c482 | 293 | * Careful: an NMI might modify the previous event value. |
ee06094f IM |
294 | * |
295 | * Our tactic to handle this is to first atomically read and | |
296 | * exchange a new raw count - then add that new-prev delta | |
cdd6c482 | 297 | * count to the generic event atomically: |
ee06094f IM |
298 | */ |
299 | again: | |
e7850595 | 300 | prev_raw_count = local64_read(&hwc->prev_count); |
cdd6c482 | 301 | rdmsrl(hwc->event_base + idx, new_raw_count); |
ee06094f | 302 | |
e7850595 | 303 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
ee06094f IM |
304 | new_raw_count) != prev_raw_count) |
305 | goto again; | |
306 | ||
307 | /* | |
308 | * Now we have the new raw value and have updated the prev | |
309 | * timestamp already. We can now calculate the elapsed delta | |
cdd6c482 | 310 | * (event-)time and add that to the generic event. |
ee06094f IM |
311 | * |
312 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 313 | * of the count. |
ee06094f | 314 | */ |
ec3232bd PZ |
315 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
316 | delta >>= shift; | |
ee06094f | 317 | |
e7850595 PZ |
318 | local64_add(delta, &event->count); |
319 | local64_sub(delta, &hwc->period_left); | |
4b7bfd0d RR |
320 | |
321 | return new_raw_count; | |
ee06094f IM |
322 | } |
323 | ||
cdd6c482 | 324 | static atomic_t active_events; |
4e935e47 PZ |
325 | static DEFINE_MUTEX(pmc_reserve_mutex); |
326 | ||
b27ea29c RR |
327 | #ifdef CONFIG_X86_LOCAL_APIC |
328 | ||
4e935e47 PZ |
329 | static bool reserve_pmc_hardware(void) |
330 | { | |
331 | int i; | |
332 | ||
948b1bb8 | 333 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 | 334 | if (!reserve_perfctr_nmi(x86_pmu.perfctr + i)) |
4e935e47 PZ |
335 | goto perfctr_fail; |
336 | } | |
337 | ||
948b1bb8 | 338 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 | 339 | if (!reserve_evntsel_nmi(x86_pmu.eventsel + i)) |
4e935e47 PZ |
340 | goto eventsel_fail; |
341 | } | |
342 | ||
343 | return true; | |
344 | ||
345 | eventsel_fail: | |
346 | for (i--; i >= 0; i--) | |
4a06bd85 | 347 | release_evntsel_nmi(x86_pmu.eventsel + i); |
4e935e47 | 348 | |
948b1bb8 | 349 | i = x86_pmu.num_counters; |
4e935e47 PZ |
350 | |
351 | perfctr_fail: | |
352 | for (i--; i >= 0; i--) | |
4a06bd85 | 353 | release_perfctr_nmi(x86_pmu.perfctr + i); |
4e935e47 | 354 | |
4e935e47 PZ |
355 | return false; |
356 | } | |
357 | ||
358 | static void release_pmc_hardware(void) | |
359 | { | |
360 | int i; | |
361 | ||
948b1bb8 | 362 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 RR |
363 | release_perfctr_nmi(x86_pmu.perfctr + i); |
364 | release_evntsel_nmi(x86_pmu.eventsel + i); | |
4e935e47 | 365 | } |
4e935e47 PZ |
366 | } |
367 | ||
b27ea29c RR |
368 | #else |
369 | ||
370 | static bool reserve_pmc_hardware(void) { return true; } | |
371 | static void release_pmc_hardware(void) {} | |
372 | ||
373 | #endif | |
374 | ||
33c6d6a7 DZ |
375 | static bool check_hw_exists(void) |
376 | { | |
377 | u64 val, val_new = 0; | |
4407204c | 378 | int i, reg, ret = 0; |
33c6d6a7 | 379 | |
4407204c PZ |
380 | /* |
381 | * Check to see if the BIOS enabled any of the counters, if so | |
382 | * complain and bail. | |
383 | */ | |
384 | for (i = 0; i < x86_pmu.num_counters; i++) { | |
385 | reg = x86_pmu.eventsel + i; | |
386 | ret = rdmsrl_safe(reg, &val); | |
387 | if (ret) | |
388 | goto msr_fail; | |
389 | if (val & ARCH_PERFMON_EVENTSEL_ENABLE) | |
390 | goto bios_fail; | |
391 | } | |
392 | ||
393 | if (x86_pmu.num_counters_fixed) { | |
394 | reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
395 | ret = rdmsrl_safe(reg, &val); | |
396 | if (ret) | |
397 | goto msr_fail; | |
398 | for (i = 0; i < x86_pmu.num_counters_fixed; i++) { | |
399 | if (val & (0x03 << i*4)) | |
400 | goto bios_fail; | |
401 | } | |
402 | } | |
403 | ||
404 | /* | |
405 | * Now write a value and read it back to see if it matches, | |
406 | * this is needed to detect certain hardware emulators (qemu/kvm) | |
407 | * that don't trap on the MSR access and always return 0s. | |
408 | */ | |
33c6d6a7 | 409 | val = 0xabcdUL; |
4407204c | 410 | ret = checking_wrmsrl(x86_pmu.perfctr, val); |
33c6d6a7 DZ |
411 | ret |= rdmsrl_safe(x86_pmu.perfctr, &val_new); |
412 | if (ret || val != val_new) | |
4407204c | 413 | goto msr_fail; |
33c6d6a7 DZ |
414 | |
415 | return true; | |
4407204c PZ |
416 | |
417 | bios_fail: | |
418 | printk(KERN_CONT "Broken BIOS detected, using software events only.\n"); | |
419 | printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg, val); | |
420 | return false; | |
421 | ||
422 | msr_fail: | |
423 | printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n"); | |
424 | return false; | |
33c6d6a7 DZ |
425 | } |
426 | ||
f80c9e30 | 427 | static void reserve_ds_buffers(void); |
ca037701 | 428 | static void release_ds_buffers(void); |
30dd568c | 429 | |
cdd6c482 | 430 | static void hw_perf_event_destroy(struct perf_event *event) |
4e935e47 | 431 | { |
cdd6c482 | 432 | if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) { |
4e935e47 | 433 | release_pmc_hardware(); |
ca037701 | 434 | release_ds_buffers(); |
4e935e47 PZ |
435 | mutex_unlock(&pmc_reserve_mutex); |
436 | } | |
437 | } | |
438 | ||
85cf9dba RR |
439 | static inline int x86_pmu_initialized(void) |
440 | { | |
441 | return x86_pmu.handle_irq != NULL; | |
442 | } | |
443 | ||
8326f44d | 444 | static inline int |
cdd6c482 | 445 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr) |
8326f44d IM |
446 | { |
447 | unsigned int cache_type, cache_op, cache_result; | |
448 | u64 config, val; | |
449 | ||
450 | config = attr->config; | |
451 | ||
452 | cache_type = (config >> 0) & 0xff; | |
453 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
454 | return -EINVAL; | |
455 | ||
456 | cache_op = (config >> 8) & 0xff; | |
457 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
458 | return -EINVAL; | |
459 | ||
460 | cache_result = (config >> 16) & 0xff; | |
461 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
462 | return -EINVAL; | |
463 | ||
464 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; | |
465 | ||
466 | if (val == 0) | |
467 | return -ENOENT; | |
468 | ||
469 | if (val == -1) | |
470 | return -EINVAL; | |
471 | ||
472 | hwc->config |= val; | |
473 | ||
474 | return 0; | |
475 | } | |
476 | ||
c1726f34 RR |
477 | static int x86_setup_perfctr(struct perf_event *event) |
478 | { | |
479 | struct perf_event_attr *attr = &event->attr; | |
480 | struct hw_perf_event *hwc = &event->hw; | |
481 | u64 config; | |
482 | ||
6c7e550f | 483 | if (!is_sampling_event(event)) { |
c1726f34 RR |
484 | hwc->sample_period = x86_pmu.max_period; |
485 | hwc->last_period = hwc->sample_period; | |
e7850595 | 486 | local64_set(&hwc->period_left, hwc->sample_period); |
c1726f34 RR |
487 | } else { |
488 | /* | |
489 | * If we have a PMU initialized but no APIC | |
490 | * interrupts, we cannot sample hardware | |
491 | * events (user-space has to fall back and | |
492 | * sample via a hrtimer based software event): | |
493 | */ | |
494 | if (!x86_pmu.apic) | |
495 | return -EOPNOTSUPP; | |
496 | } | |
497 | ||
498 | if (attr->type == PERF_TYPE_RAW) | |
499 | return 0; | |
500 | ||
501 | if (attr->type == PERF_TYPE_HW_CACHE) | |
502 | return set_ext_hw_attr(hwc, attr); | |
503 | ||
504 | if (attr->config >= x86_pmu.max_events) | |
505 | return -EINVAL; | |
506 | ||
507 | /* | |
508 | * The generic map: | |
509 | */ | |
510 | config = x86_pmu.event_map(attr->config); | |
511 | ||
512 | if (config == 0) | |
513 | return -ENOENT; | |
514 | ||
515 | if (config == -1LL) | |
516 | return -EINVAL; | |
517 | ||
518 | /* | |
519 | * Branch tracing: | |
520 | */ | |
521 | if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) && | |
522 | (hwc->sample_period == 1)) { | |
523 | /* BTS is not supported by this architecture. */ | |
6809b6ea | 524 | if (!x86_pmu.bts_active) |
c1726f34 RR |
525 | return -EOPNOTSUPP; |
526 | ||
527 | /* BTS is currently only allowed for user-mode. */ | |
528 | if (!attr->exclude_kernel) | |
529 | return -EOPNOTSUPP; | |
530 | } | |
531 | ||
532 | hwc->config |= config; | |
533 | ||
534 | return 0; | |
535 | } | |
4261e0e0 | 536 | |
b4cdc5c2 | 537 | static int x86_pmu_hw_config(struct perf_event *event) |
a072738e | 538 | { |
ab608344 PZ |
539 | if (event->attr.precise_ip) { |
540 | int precise = 0; | |
541 | ||
542 | /* Support for constant skid */ | |
6809b6ea | 543 | if (x86_pmu.pebs_active) { |
ab608344 PZ |
544 | precise++; |
545 | ||
5553be26 PZ |
546 | /* Support for IP fixup */ |
547 | if (x86_pmu.lbr_nr) | |
548 | precise++; | |
549 | } | |
ab608344 PZ |
550 | |
551 | if (event->attr.precise_ip > precise) | |
552 | return -EOPNOTSUPP; | |
553 | } | |
554 | ||
a072738e CG |
555 | /* |
556 | * Generate PMC IRQs: | |
557 | * (keep 'enabled' bit clear for now) | |
558 | */ | |
b4cdc5c2 | 559 | event->hw.config = ARCH_PERFMON_EVENTSEL_INT; |
a072738e CG |
560 | |
561 | /* | |
562 | * Count user and OS events unless requested not to | |
563 | */ | |
b4cdc5c2 PZ |
564 | if (!event->attr.exclude_user) |
565 | event->hw.config |= ARCH_PERFMON_EVENTSEL_USR; | |
566 | if (!event->attr.exclude_kernel) | |
567 | event->hw.config |= ARCH_PERFMON_EVENTSEL_OS; | |
a072738e | 568 | |
b4cdc5c2 PZ |
569 | if (event->attr.type == PERF_TYPE_RAW) |
570 | event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; | |
a072738e | 571 | |
9d0fcba6 | 572 | return x86_setup_perfctr(event); |
a098f448 RR |
573 | } |
574 | ||
241771ef | 575 | /* |
0d48696f | 576 | * Setup the hardware configuration for a given attr_type |
241771ef | 577 | */ |
b0a873eb | 578 | static int __x86_pmu_event_init(struct perf_event *event) |
241771ef | 579 | { |
4e935e47 | 580 | int err; |
241771ef | 581 | |
85cf9dba RR |
582 | if (!x86_pmu_initialized()) |
583 | return -ENODEV; | |
241771ef | 584 | |
4e935e47 | 585 | err = 0; |
cdd6c482 | 586 | if (!atomic_inc_not_zero(&active_events)) { |
4e935e47 | 587 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 588 | if (atomic_read(&active_events) == 0) { |
30dd568c MM |
589 | if (!reserve_pmc_hardware()) |
590 | err = -EBUSY; | |
f80c9e30 PZ |
591 | else |
592 | reserve_ds_buffers(); | |
30dd568c MM |
593 | } |
594 | if (!err) | |
cdd6c482 | 595 | atomic_inc(&active_events); |
4e935e47 PZ |
596 | mutex_unlock(&pmc_reserve_mutex); |
597 | } | |
598 | if (err) | |
599 | return err; | |
600 | ||
cdd6c482 | 601 | event->destroy = hw_perf_event_destroy; |
a1792cda | 602 | |
4261e0e0 RR |
603 | event->hw.idx = -1; |
604 | event->hw.last_cpu = -1; | |
605 | event->hw.last_tag = ~0ULL; | |
b690081d | 606 | |
9d0fcba6 | 607 | return x86_pmu.hw_config(event); |
4261e0e0 RR |
608 | } |
609 | ||
8c48e444 | 610 | static void x86_pmu_disable_all(void) |
f87ad35d | 611 | { |
cdd6c482 | 612 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
9e35ad38 PZ |
613 | int idx; |
614 | ||
948b1bb8 | 615 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
b0f3f28e PZ |
616 | u64 val; |
617 | ||
43f6201a | 618 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 619 | continue; |
8c48e444 | 620 | rdmsrl(x86_pmu.eventsel + idx, val); |
bb1165d6 | 621 | if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) |
4295ee62 | 622 | continue; |
bb1165d6 | 623 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
8c48e444 | 624 | wrmsrl(x86_pmu.eventsel + idx, val); |
f87ad35d | 625 | } |
f87ad35d JSR |
626 | } |
627 | ||
a4eaf7f1 | 628 | static void x86_pmu_disable(struct pmu *pmu) |
b56a3802 | 629 | { |
1da53e02 SE |
630 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
631 | ||
85cf9dba | 632 | if (!x86_pmu_initialized()) |
9e35ad38 | 633 | return; |
1da53e02 | 634 | |
1a6e21f7 PZ |
635 | if (!cpuc->enabled) |
636 | return; | |
637 | ||
638 | cpuc->n_added = 0; | |
639 | cpuc->enabled = 0; | |
640 | barrier(); | |
1da53e02 SE |
641 | |
642 | x86_pmu.disable_all(); | |
b56a3802 | 643 | } |
241771ef | 644 | |
11164cd4 | 645 | static void x86_pmu_enable_all(int added) |
f87ad35d | 646 | { |
cdd6c482 | 647 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
f87ad35d JSR |
648 | int idx; |
649 | ||
948b1bb8 | 650 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
cdd6c482 | 651 | struct perf_event *event = cpuc->events[idx]; |
4295ee62 | 652 | u64 val; |
b0f3f28e | 653 | |
43f6201a | 654 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 655 | continue; |
984b838c | 656 | |
cdd6c482 | 657 | val = event->hw.config; |
bb1165d6 | 658 | val |= ARCH_PERFMON_EVENTSEL_ENABLE; |
8c48e444 | 659 | wrmsrl(x86_pmu.eventsel + idx, val); |
f87ad35d JSR |
660 | } |
661 | } | |
662 | ||
51b0fe39 | 663 | static struct pmu pmu; |
1da53e02 SE |
664 | |
665 | static inline int is_x86_event(struct perf_event *event) | |
666 | { | |
667 | return event->pmu == &pmu; | |
668 | } | |
669 | ||
670 | static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) | |
671 | { | |
63b14649 | 672 | struct event_constraint *c, *constraints[X86_PMC_IDX_MAX]; |
1da53e02 | 673 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
c933c1a6 | 674 | int i, j, w, wmax, num = 0; |
1da53e02 SE |
675 | struct hw_perf_event *hwc; |
676 | ||
677 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
678 | ||
679 | for (i = 0; i < n; i++) { | |
b622d644 PZ |
680 | c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]); |
681 | constraints[i] = c; | |
1da53e02 SE |
682 | } |
683 | ||
8113070d SE |
684 | /* |
685 | * fastpath, try to reuse previous register | |
686 | */ | |
c933c1a6 | 687 | for (i = 0; i < n; i++) { |
8113070d | 688 | hwc = &cpuc->event_list[i]->hw; |
81269a08 | 689 | c = constraints[i]; |
8113070d SE |
690 | |
691 | /* never assigned */ | |
692 | if (hwc->idx == -1) | |
693 | break; | |
694 | ||
695 | /* constraint still honored */ | |
63b14649 | 696 | if (!test_bit(hwc->idx, c->idxmsk)) |
8113070d SE |
697 | break; |
698 | ||
699 | /* not already used */ | |
700 | if (test_bit(hwc->idx, used_mask)) | |
701 | break; | |
702 | ||
34538ee7 | 703 | __set_bit(hwc->idx, used_mask); |
8113070d SE |
704 | if (assign) |
705 | assign[i] = hwc->idx; | |
706 | } | |
c933c1a6 | 707 | if (i == n) |
8113070d SE |
708 | goto done; |
709 | ||
710 | /* | |
711 | * begin slow path | |
712 | */ | |
713 | ||
714 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
715 | ||
1da53e02 SE |
716 | /* |
717 | * weight = number of possible counters | |
718 | * | |
719 | * 1 = most constrained, only works on one counter | |
720 | * wmax = least constrained, works on any counter | |
721 | * | |
722 | * assign events to counters starting with most | |
723 | * constrained events. | |
724 | */ | |
948b1bb8 | 725 | wmax = x86_pmu.num_counters; |
1da53e02 SE |
726 | |
727 | /* | |
728 | * when fixed event counters are present, | |
729 | * wmax is incremented by 1 to account | |
730 | * for one more choice | |
731 | */ | |
948b1bb8 | 732 | if (x86_pmu.num_counters_fixed) |
1da53e02 SE |
733 | wmax++; |
734 | ||
8113070d | 735 | for (w = 1, num = n; num && w <= wmax; w++) { |
1da53e02 | 736 | /* for each event */ |
8113070d | 737 | for (i = 0; num && i < n; i++) { |
81269a08 | 738 | c = constraints[i]; |
1da53e02 SE |
739 | hwc = &cpuc->event_list[i]->hw; |
740 | ||
272d30be | 741 | if (c->weight != w) |
1da53e02 SE |
742 | continue; |
743 | ||
984b3f57 | 744 | for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) { |
1da53e02 SE |
745 | if (!test_bit(j, used_mask)) |
746 | break; | |
747 | } | |
748 | ||
749 | if (j == X86_PMC_IDX_MAX) | |
750 | break; | |
1da53e02 | 751 | |
34538ee7 | 752 | __set_bit(j, used_mask); |
8113070d | 753 | |
1da53e02 SE |
754 | if (assign) |
755 | assign[i] = j; | |
756 | num--; | |
757 | } | |
758 | } | |
8113070d | 759 | done: |
1da53e02 SE |
760 | /* |
761 | * scheduling failed or is just a simulation, | |
762 | * free resources if necessary | |
763 | */ | |
764 | if (!assign || num) { | |
765 | for (i = 0; i < n; i++) { | |
766 | if (x86_pmu.put_event_constraints) | |
767 | x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]); | |
768 | } | |
769 | } | |
770 | return num ? -ENOSPC : 0; | |
771 | } | |
772 | ||
773 | /* | |
774 | * dogrp: true if must collect siblings events (group) | |
775 | * returns total number of events and error code | |
776 | */ | |
777 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) | |
778 | { | |
779 | struct perf_event *event; | |
780 | int n, max_count; | |
781 | ||
948b1bb8 | 782 | max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed; |
1da53e02 SE |
783 | |
784 | /* current number of events already accepted */ | |
785 | n = cpuc->n_events; | |
786 | ||
787 | if (is_x86_event(leader)) { | |
788 | if (n >= max_count) | |
789 | return -ENOSPC; | |
790 | cpuc->event_list[n] = leader; | |
791 | n++; | |
792 | } | |
793 | if (!dogrp) | |
794 | return n; | |
795 | ||
796 | list_for_each_entry(event, &leader->sibling_list, group_entry) { | |
797 | if (!is_x86_event(event) || | |
8113070d | 798 | event->state <= PERF_EVENT_STATE_OFF) |
1da53e02 SE |
799 | continue; |
800 | ||
801 | if (n >= max_count) | |
802 | return -ENOSPC; | |
803 | ||
804 | cpuc->event_list[n] = event; | |
805 | n++; | |
806 | } | |
807 | return n; | |
808 | } | |
809 | ||
1da53e02 | 810 | static inline void x86_assign_hw_event(struct perf_event *event, |
447a194b | 811 | struct cpu_hw_events *cpuc, int i) |
1da53e02 | 812 | { |
447a194b SE |
813 | struct hw_perf_event *hwc = &event->hw; |
814 | ||
815 | hwc->idx = cpuc->assign[i]; | |
816 | hwc->last_cpu = smp_processor_id(); | |
817 | hwc->last_tag = ++cpuc->tags[i]; | |
1da53e02 SE |
818 | |
819 | if (hwc->idx == X86_PMC_IDX_FIXED_BTS) { | |
820 | hwc->config_base = 0; | |
821 | hwc->event_base = 0; | |
822 | } else if (hwc->idx >= X86_PMC_IDX_FIXED) { | |
823 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
824 | /* | |
825 | * We set it so that event_base + idx in wrmsr/rdmsr maps to | |
826 | * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2: | |
827 | */ | |
828 | hwc->event_base = | |
829 | MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED; | |
830 | } else { | |
831 | hwc->config_base = x86_pmu.eventsel; | |
832 | hwc->event_base = x86_pmu.perfctr; | |
833 | } | |
834 | } | |
835 | ||
447a194b SE |
836 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
837 | struct cpu_hw_events *cpuc, | |
838 | int i) | |
839 | { | |
840 | return hwc->idx == cpuc->assign[i] && | |
841 | hwc->last_cpu == smp_processor_id() && | |
842 | hwc->last_tag == cpuc->tags[i]; | |
843 | } | |
844 | ||
a4eaf7f1 PZ |
845 | static void x86_pmu_start(struct perf_event *event, int flags); |
846 | static void x86_pmu_stop(struct perf_event *event, int flags); | |
2e841873 | 847 | |
a4eaf7f1 | 848 | static void x86_pmu_enable(struct pmu *pmu) |
ee06094f | 849 | { |
1da53e02 SE |
850 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
851 | struct perf_event *event; | |
852 | struct hw_perf_event *hwc; | |
11164cd4 | 853 | int i, added = cpuc->n_added; |
1da53e02 | 854 | |
85cf9dba | 855 | if (!x86_pmu_initialized()) |
2b9ff0db | 856 | return; |
1a6e21f7 PZ |
857 | |
858 | if (cpuc->enabled) | |
859 | return; | |
860 | ||
1da53e02 | 861 | if (cpuc->n_added) { |
19925ce7 | 862 | int n_running = cpuc->n_events - cpuc->n_added; |
1da53e02 SE |
863 | /* |
864 | * apply assignment obtained either from | |
865 | * hw_perf_group_sched_in() or x86_pmu_enable() | |
866 | * | |
867 | * step1: save events moving to new counters | |
868 | * step2: reprogram moved events into new counters | |
869 | */ | |
19925ce7 | 870 | for (i = 0; i < n_running; i++) { |
1da53e02 SE |
871 | event = cpuc->event_list[i]; |
872 | hwc = &event->hw; | |
873 | ||
447a194b SE |
874 | /* |
875 | * we can avoid reprogramming counter if: | |
876 | * - assigned same counter as last time | |
877 | * - running on same CPU as last time | |
878 | * - no other event has used the counter since | |
879 | */ | |
880 | if (hwc->idx == -1 || | |
881 | match_prev_assignment(hwc, cpuc, i)) | |
1da53e02 SE |
882 | continue; |
883 | ||
a4eaf7f1 PZ |
884 | /* |
885 | * Ensure we don't accidentally enable a stopped | |
886 | * counter simply because we rescheduled. | |
887 | */ | |
888 | if (hwc->state & PERF_HES_STOPPED) | |
889 | hwc->state |= PERF_HES_ARCH; | |
890 | ||
891 | x86_pmu_stop(event, PERF_EF_UPDATE); | |
1da53e02 SE |
892 | } |
893 | ||
894 | for (i = 0; i < cpuc->n_events; i++) { | |
1da53e02 SE |
895 | event = cpuc->event_list[i]; |
896 | hwc = &event->hw; | |
897 | ||
45e16a68 | 898 | if (!match_prev_assignment(hwc, cpuc, i)) |
447a194b | 899 | x86_assign_hw_event(event, cpuc, i); |
45e16a68 PZ |
900 | else if (i < n_running) |
901 | continue; | |
1da53e02 | 902 | |
a4eaf7f1 PZ |
903 | if (hwc->state & PERF_HES_ARCH) |
904 | continue; | |
905 | ||
906 | x86_pmu_start(event, PERF_EF_RELOAD); | |
1da53e02 SE |
907 | } |
908 | cpuc->n_added = 0; | |
909 | perf_events_lapic_init(); | |
910 | } | |
1a6e21f7 PZ |
911 | |
912 | cpuc->enabled = 1; | |
913 | barrier(); | |
914 | ||
11164cd4 | 915 | x86_pmu.enable_all(added); |
ee06094f | 916 | } |
ee06094f | 917 | |
31fa58af RR |
918 | static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, |
919 | u64 enable_mask) | |
b0f3f28e | 920 | { |
31fa58af | 921 | wrmsrl(hwc->config_base + hwc->idx, hwc->config | enable_mask); |
b0f3f28e PZ |
922 | } |
923 | ||
aff3d91a | 924 | static inline void x86_pmu_disable_event(struct perf_event *event) |
b0f3f28e | 925 | { |
aff3d91a | 926 | struct hw_perf_event *hwc = &event->hw; |
7645a24c PZ |
927 | |
928 | wrmsrl(hwc->config_base + hwc->idx, hwc->config); | |
b0f3f28e PZ |
929 | } |
930 | ||
245b2e70 | 931 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
241771ef | 932 | |
ee06094f IM |
933 | /* |
934 | * Set the next IRQ period, based on the hwc->period_left value. | |
cdd6c482 | 935 | * To be called with the event disabled in hw: |
ee06094f | 936 | */ |
e4abb5d4 | 937 | static int |
07088edb | 938 | x86_perf_event_set_period(struct perf_event *event) |
241771ef | 939 | { |
07088edb | 940 | struct hw_perf_event *hwc = &event->hw; |
e7850595 | 941 | s64 left = local64_read(&hwc->period_left); |
e4abb5d4 | 942 | s64 period = hwc->sample_period; |
7645a24c | 943 | int ret = 0, idx = hwc->idx; |
ee06094f | 944 | |
30dd568c MM |
945 | if (idx == X86_PMC_IDX_FIXED_BTS) |
946 | return 0; | |
947 | ||
ee06094f | 948 | /* |
af901ca1 | 949 | * If we are way outside a reasonable range then just skip forward: |
ee06094f IM |
950 | */ |
951 | if (unlikely(left <= -period)) { | |
952 | left = period; | |
e7850595 | 953 | local64_set(&hwc->period_left, left); |
9e350de3 | 954 | hwc->last_period = period; |
e4abb5d4 | 955 | ret = 1; |
ee06094f IM |
956 | } |
957 | ||
958 | if (unlikely(left <= 0)) { | |
959 | left += period; | |
e7850595 | 960 | local64_set(&hwc->period_left, left); |
9e350de3 | 961 | hwc->last_period = period; |
e4abb5d4 | 962 | ret = 1; |
ee06094f | 963 | } |
1c80f4b5 | 964 | /* |
dfc65094 | 965 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
1c80f4b5 IM |
966 | */ |
967 | if (unlikely(left < 2)) | |
968 | left = 2; | |
241771ef | 969 | |
e4abb5d4 PZ |
970 | if (left > x86_pmu.max_period) |
971 | left = x86_pmu.max_period; | |
972 | ||
245b2e70 | 973 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
ee06094f IM |
974 | |
975 | /* | |
cdd6c482 | 976 | * The hw event starts counting from this event offset, |
ee06094f IM |
977 | * mark it to be able to extra future deltas: |
978 | */ | |
e7850595 | 979 | local64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 980 | |
68aa00ac CG |
981 | wrmsrl(hwc->event_base + idx, (u64)(-left) & x86_pmu.cntval_mask); |
982 | ||
983 | /* | |
984 | * Due to erratum on certan cpu we need | |
985 | * a second write to be sure the register | |
986 | * is updated properly | |
987 | */ | |
988 | if (x86_pmu.perfctr_second_write) { | |
989 | wrmsrl(hwc->event_base + idx, | |
948b1bb8 | 990 | (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac | 991 | } |
e4abb5d4 | 992 | |
cdd6c482 | 993 | perf_event_update_userpage(event); |
194002b2 | 994 | |
e4abb5d4 | 995 | return ret; |
2f18d1e8 IM |
996 | } |
997 | ||
aff3d91a | 998 | static void x86_pmu_enable_event(struct perf_event *event) |
7c90cc45 | 999 | { |
cdd6c482 | 1000 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
7c90cc45 | 1001 | if (cpuc->enabled) |
31fa58af RR |
1002 | __x86_pmu_enable_event(&event->hw, |
1003 | ARCH_PERFMON_EVENTSEL_ENABLE); | |
241771ef IM |
1004 | } |
1005 | ||
b690081d | 1006 | /* |
a4eaf7f1 | 1007 | * Add a single event to the PMU. |
1da53e02 SE |
1008 | * |
1009 | * The event is added to the group of enabled events | |
1010 | * but only if it can be scehduled with existing events. | |
fe9081cc | 1011 | */ |
a4eaf7f1 | 1012 | static int x86_pmu_add(struct perf_event *event, int flags) |
fe9081cc PZ |
1013 | { |
1014 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1da53e02 SE |
1015 | struct hw_perf_event *hwc; |
1016 | int assign[X86_PMC_IDX_MAX]; | |
1017 | int n, n0, ret; | |
fe9081cc | 1018 | |
1da53e02 | 1019 | hwc = &event->hw; |
fe9081cc | 1020 | |
33696fc0 | 1021 | perf_pmu_disable(event->pmu); |
1da53e02 | 1022 | n0 = cpuc->n_events; |
24cd7f54 PZ |
1023 | ret = n = collect_events(cpuc, event, false); |
1024 | if (ret < 0) | |
1025 | goto out; | |
53b441a5 | 1026 | |
a4eaf7f1 PZ |
1027 | hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; |
1028 | if (!(flags & PERF_EF_START)) | |
1029 | hwc->state |= PERF_HES_ARCH; | |
1030 | ||
4d1c52b0 LM |
1031 | /* |
1032 | * If group events scheduling transaction was started, | |
1033 | * skip the schedulability test here, it will be peformed | |
a4eaf7f1 | 1034 | * at commit time (->commit_txn) as a whole |
4d1c52b0 | 1035 | */ |
8d2cacbb | 1036 | if (cpuc->group_flag & PERF_EVENT_TXN) |
24cd7f54 | 1037 | goto done_collect; |
4d1c52b0 | 1038 | |
a072738e | 1039 | ret = x86_pmu.schedule_events(cpuc, n, assign); |
1da53e02 | 1040 | if (ret) |
24cd7f54 | 1041 | goto out; |
1da53e02 SE |
1042 | /* |
1043 | * copy new assignment, now we know it is possible | |
1044 | * will be used by hw_perf_enable() | |
1045 | */ | |
1046 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
7e2ae347 | 1047 | |
24cd7f54 | 1048 | done_collect: |
1da53e02 | 1049 | cpuc->n_events = n; |
356e1f2e | 1050 | cpuc->n_added += n - n0; |
90151c35 | 1051 | cpuc->n_txn += n - n0; |
95cdd2e7 | 1052 | |
24cd7f54 PZ |
1053 | ret = 0; |
1054 | out: | |
33696fc0 | 1055 | perf_pmu_enable(event->pmu); |
24cd7f54 | 1056 | return ret; |
241771ef IM |
1057 | } |
1058 | ||
a4eaf7f1 | 1059 | static void x86_pmu_start(struct perf_event *event, int flags) |
d76a0812 | 1060 | { |
c08053e6 PZ |
1061 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
1062 | int idx = event->hw.idx; | |
1063 | ||
a4eaf7f1 PZ |
1064 | if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) |
1065 | return; | |
1066 | ||
1067 | if (WARN_ON_ONCE(idx == -1)) | |
1068 | return; | |
1069 | ||
1070 | if (flags & PERF_EF_RELOAD) { | |
1071 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
1072 | x86_perf_event_set_period(event); | |
1073 | } | |
1074 | ||
1075 | event->hw.state = 0; | |
d76a0812 | 1076 | |
c08053e6 PZ |
1077 | cpuc->events[idx] = event; |
1078 | __set_bit(idx, cpuc->active_mask); | |
63e6be6d | 1079 | __set_bit(idx, cpuc->running); |
aff3d91a | 1080 | x86_pmu.enable(event); |
c08053e6 | 1081 | perf_event_update_userpage(event); |
a78ac325 PZ |
1082 | } |
1083 | ||
cdd6c482 | 1084 | void perf_event_print_debug(void) |
241771ef | 1085 | { |
2f18d1e8 | 1086 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
ca037701 | 1087 | u64 pebs; |
cdd6c482 | 1088 | struct cpu_hw_events *cpuc; |
5bb9efe3 | 1089 | unsigned long flags; |
1e125676 IM |
1090 | int cpu, idx; |
1091 | ||
948b1bb8 | 1092 | if (!x86_pmu.num_counters) |
1e125676 | 1093 | return; |
241771ef | 1094 | |
5bb9efe3 | 1095 | local_irq_save(flags); |
241771ef IM |
1096 | |
1097 | cpu = smp_processor_id(); | |
cdd6c482 | 1098 | cpuc = &per_cpu(cpu_hw_events, cpu); |
241771ef | 1099 | |
faa28ae0 | 1100 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
1101 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
1102 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
1103 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
1104 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
ca037701 | 1105 | rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); |
a1ef58f4 JSR |
1106 | |
1107 | pr_info("\n"); | |
1108 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
1109 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
1110 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
1111 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
ca037701 | 1112 | pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); |
f87ad35d | 1113 | } |
7645a24c | 1114 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
241771ef | 1115 | |
948b1bb8 | 1116 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
4a06bd85 RR |
1117 | rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl); |
1118 | rdmsrl(x86_pmu.perfctr + idx, pmc_count); | |
241771ef | 1119 | |
245b2e70 | 1120 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
241771ef | 1121 | |
a1ef58f4 | 1122 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 1123 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 1124 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 1125 | cpu, idx, pmc_count); |
a1ef58f4 | 1126 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 1127 | cpu, idx, prev_left); |
241771ef | 1128 | } |
948b1bb8 | 1129 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
2f18d1e8 IM |
1130 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
1131 | ||
a1ef58f4 | 1132 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
1133 | cpu, idx, pmc_count); |
1134 | } | |
5bb9efe3 | 1135 | local_irq_restore(flags); |
241771ef IM |
1136 | } |
1137 | ||
a4eaf7f1 | 1138 | static void x86_pmu_stop(struct perf_event *event, int flags) |
241771ef | 1139 | { |
d76a0812 | 1140 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
cdd6c482 | 1141 | struct hw_perf_event *hwc = &event->hw; |
241771ef | 1142 | |
a4eaf7f1 PZ |
1143 | if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) { |
1144 | x86_pmu.disable(event); | |
1145 | cpuc->events[hwc->idx] = NULL; | |
1146 | WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); | |
1147 | hwc->state |= PERF_HES_STOPPED; | |
1148 | } | |
30dd568c | 1149 | |
a4eaf7f1 PZ |
1150 | if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { |
1151 | /* | |
1152 | * Drain the remaining delta count out of a event | |
1153 | * that we are disabling: | |
1154 | */ | |
1155 | x86_perf_event_update(event); | |
1156 | hwc->state |= PERF_HES_UPTODATE; | |
1157 | } | |
2e841873 PZ |
1158 | } |
1159 | ||
a4eaf7f1 | 1160 | static void x86_pmu_del(struct perf_event *event, int flags) |
2e841873 PZ |
1161 | { |
1162 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1163 | int i; | |
1164 | ||
90151c35 SE |
1165 | /* |
1166 | * If we're called during a txn, we don't need to do anything. | |
1167 | * The events never got scheduled and ->cancel_txn will truncate | |
1168 | * the event_list. | |
1169 | */ | |
8d2cacbb | 1170 | if (cpuc->group_flag & PERF_EVENT_TXN) |
90151c35 SE |
1171 | return; |
1172 | ||
a4eaf7f1 | 1173 | x86_pmu_stop(event, PERF_EF_UPDATE); |
194002b2 | 1174 | |
1da53e02 SE |
1175 | for (i = 0; i < cpuc->n_events; i++) { |
1176 | if (event == cpuc->event_list[i]) { | |
1177 | ||
1178 | if (x86_pmu.put_event_constraints) | |
1179 | x86_pmu.put_event_constraints(cpuc, event); | |
1180 | ||
1181 | while (++i < cpuc->n_events) | |
1182 | cpuc->event_list[i-1] = cpuc->event_list[i]; | |
1183 | ||
1184 | --cpuc->n_events; | |
6c9687ab | 1185 | break; |
1da53e02 SE |
1186 | } |
1187 | } | |
cdd6c482 | 1188 | perf_event_update_userpage(event); |
241771ef IM |
1189 | } |
1190 | ||
8c48e444 | 1191 | static int x86_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 1192 | { |
df1a132b | 1193 | struct perf_sample_data data; |
cdd6c482 IM |
1194 | struct cpu_hw_events *cpuc; |
1195 | struct perf_event *event; | |
11d1578f | 1196 | int idx, handled = 0; |
9029a5e3 IM |
1197 | u64 val; |
1198 | ||
dc1d628a | 1199 | perf_sample_data_init(&data, 0); |
df1a132b | 1200 | |
cdd6c482 | 1201 | cpuc = &__get_cpu_var(cpu_hw_events); |
962bf7a6 | 1202 | |
948b1bb8 | 1203 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
63e6be6d RR |
1204 | if (!test_bit(idx, cpuc->active_mask)) { |
1205 | /* | |
1206 | * Though we deactivated the counter some cpus | |
1207 | * might still deliver spurious interrupts still | |
1208 | * in flight. Catch them: | |
1209 | */ | |
1210 | if (__test_and_clear_bit(idx, cpuc->running)) | |
1211 | handled++; | |
a29aa8a7 | 1212 | continue; |
63e6be6d | 1213 | } |
962bf7a6 | 1214 | |
cdd6c482 | 1215 | event = cpuc->events[idx]; |
a4016a79 | 1216 | |
cc2ad4ba | 1217 | val = x86_perf_event_update(event); |
948b1bb8 | 1218 | if (val & (1ULL << (x86_pmu.cntval_bits - 1))) |
48e22d56 | 1219 | continue; |
962bf7a6 | 1220 | |
9e350de3 | 1221 | /* |
cdd6c482 | 1222 | * event overflow |
9e350de3 | 1223 | */ |
4177c42a | 1224 | handled++; |
cdd6c482 | 1225 | data.period = event->hw.last_period; |
9e350de3 | 1226 | |
07088edb | 1227 | if (!x86_perf_event_set_period(event)) |
e4abb5d4 PZ |
1228 | continue; |
1229 | ||
cdd6c482 | 1230 | if (perf_event_overflow(event, 1, &data, regs)) |
a4eaf7f1 | 1231 | x86_pmu_stop(event, 0); |
a29aa8a7 | 1232 | } |
962bf7a6 | 1233 | |
9e350de3 PZ |
1234 | if (handled) |
1235 | inc_irq_stat(apic_perf_irqs); | |
1236 | ||
a29aa8a7 RR |
1237 | return handled; |
1238 | } | |
39d81eab | 1239 | |
cdd6c482 | 1240 | void perf_events_lapic_init(void) |
241771ef | 1241 | { |
04da8a43 | 1242 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
241771ef | 1243 | return; |
85cf9dba | 1244 | |
241771ef | 1245 | /* |
c323d95f | 1246 | * Always use NMI for PMU |
241771ef | 1247 | */ |
c323d95f | 1248 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
241771ef IM |
1249 | } |
1250 | ||
4177c42a RR |
1251 | struct pmu_nmi_state { |
1252 | unsigned int marked; | |
1253 | int handled; | |
1254 | }; | |
1255 | ||
1256 | static DEFINE_PER_CPU(struct pmu_nmi_state, pmu_nmi); | |
1257 | ||
241771ef | 1258 | static int __kprobes |
cdd6c482 | 1259 | perf_event_nmi_handler(struct notifier_block *self, |
241771ef IM |
1260 | unsigned long cmd, void *__args) |
1261 | { | |
1262 | struct die_args *args = __args; | |
4177c42a RR |
1263 | unsigned int this_nmi; |
1264 | int handled; | |
b0f3f28e | 1265 | |
cdd6c482 | 1266 | if (!atomic_read(&active_events)) |
63a809a2 PZ |
1267 | return NOTIFY_DONE; |
1268 | ||
b0f3f28e PZ |
1269 | switch (cmd) { |
1270 | case DIE_NMI: | |
1271 | case DIE_NMI_IPI: | |
1272 | break; | |
4177c42a RR |
1273 | case DIE_NMIUNKNOWN: |
1274 | this_nmi = percpu_read(irq_stat.__nmi_count); | |
1275 | if (this_nmi != __get_cpu_var(pmu_nmi).marked) | |
1276 | /* let the kernel handle the unknown nmi */ | |
1277 | return NOTIFY_DONE; | |
1278 | /* | |
1279 | * This one is a PMU back-to-back nmi. Two events | |
1280 | * trigger 'simultaneously' raising two back-to-back | |
1281 | * NMIs. If the first NMI handles both, the latter | |
1282 | * will be empty and daze the CPU. So, we drop it to | |
1283 | * avoid false-positive 'unknown nmi' messages. | |
1284 | */ | |
1285 | return NOTIFY_STOP; | |
b0f3f28e | 1286 | default: |
241771ef | 1287 | return NOTIFY_DONE; |
b0f3f28e | 1288 | } |
241771ef | 1289 | |
241771ef | 1290 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
4177c42a RR |
1291 | |
1292 | handled = x86_pmu.handle_irq(args->regs); | |
1293 | if (!handled) | |
1294 | return NOTIFY_DONE; | |
1295 | ||
1296 | this_nmi = percpu_read(irq_stat.__nmi_count); | |
1297 | if ((handled > 1) || | |
1298 | /* the next nmi could be a back-to-back nmi */ | |
1299 | ((__get_cpu_var(pmu_nmi).marked == this_nmi) && | |
1300 | (__get_cpu_var(pmu_nmi).handled > 1))) { | |
1301 | /* | |
1302 | * We could have two subsequent back-to-back nmis: The | |
1303 | * first handles more than one counter, the 2nd | |
1304 | * handles only one counter and the 3rd handles no | |
1305 | * counter. | |
1306 | * | |
1307 | * This is the 2nd nmi because the previous was | |
1308 | * handling more than one counter. We will mark the | |
1309 | * next (3rd) and then drop it if unhandled. | |
1310 | */ | |
1311 | __get_cpu_var(pmu_nmi).marked = this_nmi + 1; | |
1312 | __get_cpu_var(pmu_nmi).handled = handled; | |
1313 | } | |
241771ef | 1314 | |
a4016a79 | 1315 | return NOTIFY_STOP; |
241771ef IM |
1316 | } |
1317 | ||
f22f54f4 PZ |
1318 | static __read_mostly struct notifier_block perf_event_nmi_notifier = { |
1319 | .notifier_call = perf_event_nmi_handler, | |
1320 | .next = NULL, | |
1321 | .priority = 1 | |
1322 | }; | |
1323 | ||
63b14649 | 1324 | static struct event_constraint unconstrained; |
38331f62 | 1325 | static struct event_constraint emptyconstraint; |
63b14649 | 1326 | |
63b14649 | 1327 | static struct event_constraint * |
f22f54f4 | 1328 | x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event) |
1da53e02 | 1329 | { |
63b14649 | 1330 | struct event_constraint *c; |
1da53e02 | 1331 | |
1da53e02 SE |
1332 | if (x86_pmu.event_constraints) { |
1333 | for_each_event_constraint(c, x86_pmu.event_constraints) { | |
63b14649 PZ |
1334 | if ((event->hw.config & c->cmask) == c->code) |
1335 | return c; | |
1da53e02 SE |
1336 | } |
1337 | } | |
63b14649 PZ |
1338 | |
1339 | return &unconstrained; | |
1da53e02 SE |
1340 | } |
1341 | ||
f22f54f4 PZ |
1342 | #include "perf_event_amd.c" |
1343 | #include "perf_event_p6.c" | |
a072738e | 1344 | #include "perf_event_p4.c" |
caff2bef | 1345 | #include "perf_event_intel_lbr.c" |
ca037701 | 1346 | #include "perf_event_intel_ds.c" |
f22f54f4 | 1347 | #include "perf_event_intel.c" |
f87ad35d | 1348 | |
3f6da390 PZ |
1349 | static int __cpuinit |
1350 | x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) | |
1351 | { | |
1352 | unsigned int cpu = (long)hcpu; | |
b38b24ea | 1353 | int ret = NOTIFY_OK; |
3f6da390 PZ |
1354 | |
1355 | switch (action & ~CPU_TASKS_FROZEN) { | |
1356 | case CPU_UP_PREPARE: | |
1357 | if (x86_pmu.cpu_prepare) | |
b38b24ea | 1358 | ret = x86_pmu.cpu_prepare(cpu); |
3f6da390 PZ |
1359 | break; |
1360 | ||
1361 | case CPU_STARTING: | |
1362 | if (x86_pmu.cpu_starting) | |
1363 | x86_pmu.cpu_starting(cpu); | |
1364 | break; | |
1365 | ||
1366 | case CPU_DYING: | |
1367 | if (x86_pmu.cpu_dying) | |
1368 | x86_pmu.cpu_dying(cpu); | |
1369 | break; | |
1370 | ||
b38b24ea | 1371 | case CPU_UP_CANCELED: |
3f6da390 PZ |
1372 | case CPU_DEAD: |
1373 | if (x86_pmu.cpu_dead) | |
1374 | x86_pmu.cpu_dead(cpu); | |
1375 | break; | |
1376 | ||
1377 | default: | |
1378 | break; | |
1379 | } | |
1380 | ||
b38b24ea | 1381 | return ret; |
3f6da390 PZ |
1382 | } |
1383 | ||
12558038 CG |
1384 | static void __init pmu_check_apic(void) |
1385 | { | |
1386 | if (cpu_has_apic) | |
1387 | return; | |
1388 | ||
1389 | x86_pmu.apic = 0; | |
1390 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); | |
1391 | pr_info("no hardware sampling interrupt available.\n"); | |
1392 | } | |
1393 | ||
004417a6 | 1394 | int __init init_hw_perf_events(void) |
b56a3802 | 1395 | { |
b622d644 | 1396 | struct event_constraint *c; |
72eae04d RR |
1397 | int err; |
1398 | ||
cdd6c482 | 1399 | pr_info("Performance Events: "); |
1123e3ad | 1400 | |
b56a3802 JSR |
1401 | switch (boot_cpu_data.x86_vendor) { |
1402 | case X86_VENDOR_INTEL: | |
72eae04d | 1403 | err = intel_pmu_init(); |
b56a3802 | 1404 | break; |
f87ad35d | 1405 | case X86_VENDOR_AMD: |
72eae04d | 1406 | err = amd_pmu_init(); |
f87ad35d | 1407 | break; |
4138960a | 1408 | default: |
004417a6 | 1409 | return 0; |
b56a3802 | 1410 | } |
1123e3ad | 1411 | if (err != 0) { |
cdd6c482 | 1412 | pr_cont("no PMU driver, software events only.\n"); |
004417a6 | 1413 | return 0; |
1123e3ad | 1414 | } |
b56a3802 | 1415 | |
12558038 CG |
1416 | pmu_check_apic(); |
1417 | ||
33c6d6a7 | 1418 | /* sanity check that the hardware exists or is emulated */ |
4407204c | 1419 | if (!check_hw_exists()) |
004417a6 | 1420 | return 0; |
33c6d6a7 | 1421 | |
1123e3ad | 1422 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
faa28ae0 | 1423 | |
3c44780b PZ |
1424 | if (x86_pmu.quirks) |
1425 | x86_pmu.quirks(); | |
1426 | ||
948b1bb8 | 1427 | if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) { |
cdd6c482 | 1428 | WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", |
948b1bb8 RR |
1429 | x86_pmu.num_counters, X86_PMC_MAX_GENERIC); |
1430 | x86_pmu.num_counters = X86_PMC_MAX_GENERIC; | |
241771ef | 1431 | } |
948b1bb8 | 1432 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; |
241771ef | 1433 | |
948b1bb8 | 1434 | if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) { |
cdd6c482 | 1435 | WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", |
948b1bb8 RR |
1436 | x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED); |
1437 | x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED; | |
703e937c | 1438 | } |
862a1a5f | 1439 | |
d6dc0b4e | 1440 | x86_pmu.intel_ctrl |= |
948b1bb8 | 1441 | ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED; |
241771ef | 1442 | |
cdd6c482 IM |
1443 | perf_events_lapic_init(); |
1444 | register_die_notifier(&perf_event_nmi_notifier); | |
1123e3ad | 1445 | |
63b14649 | 1446 | unconstrained = (struct event_constraint) |
948b1bb8 RR |
1447 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, |
1448 | 0, x86_pmu.num_counters); | |
63b14649 | 1449 | |
b622d644 PZ |
1450 | if (x86_pmu.event_constraints) { |
1451 | for_each_event_constraint(c, x86_pmu.event_constraints) { | |
a098f448 | 1452 | if (c->cmask != X86_RAW_EVENT_MASK) |
b622d644 PZ |
1453 | continue; |
1454 | ||
948b1bb8 RR |
1455 | c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; |
1456 | c->weight += x86_pmu.num_counters; | |
b622d644 PZ |
1457 | } |
1458 | } | |
1459 | ||
57c0c15b | 1460 | pr_info("... version: %d\n", x86_pmu.version); |
948b1bb8 RR |
1461 | pr_info("... bit width: %d\n", x86_pmu.cntval_bits); |
1462 | pr_info("... generic registers: %d\n", x86_pmu.num_counters); | |
1463 | pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); | |
57c0c15b | 1464 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
948b1bb8 | 1465 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed); |
d6dc0b4e | 1466 | pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl); |
3f6da390 | 1467 | |
2e80a82a | 1468 | perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); |
3f6da390 | 1469 | perf_cpu_notifier(x86_pmu_notifier); |
004417a6 PZ |
1470 | |
1471 | return 0; | |
241771ef | 1472 | } |
004417a6 | 1473 | early_initcall(init_hw_perf_events); |
621a01ea | 1474 | |
cdd6c482 | 1475 | static inline void x86_pmu_read(struct perf_event *event) |
ee06094f | 1476 | { |
cc2ad4ba | 1477 | x86_perf_event_update(event); |
ee06094f IM |
1478 | } |
1479 | ||
4d1c52b0 LM |
1480 | /* |
1481 | * Start group events scheduling transaction | |
1482 | * Set the flag to make pmu::enable() not perform the | |
1483 | * schedulability test, it will be performed at commit time | |
1484 | */ | |
51b0fe39 | 1485 | static void x86_pmu_start_txn(struct pmu *pmu) |
4d1c52b0 LM |
1486 | { |
1487 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1488 | ||
33696fc0 | 1489 | perf_pmu_disable(pmu); |
8d2cacbb | 1490 | cpuc->group_flag |= PERF_EVENT_TXN; |
90151c35 | 1491 | cpuc->n_txn = 0; |
4d1c52b0 LM |
1492 | } |
1493 | ||
1494 | /* | |
1495 | * Stop group events scheduling transaction | |
1496 | * Clear the flag and pmu::enable() will perform the | |
1497 | * schedulability test. | |
1498 | */ | |
51b0fe39 | 1499 | static void x86_pmu_cancel_txn(struct pmu *pmu) |
4d1c52b0 LM |
1500 | { |
1501 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1502 | ||
8d2cacbb | 1503 | cpuc->group_flag &= ~PERF_EVENT_TXN; |
90151c35 SE |
1504 | /* |
1505 | * Truncate the collected events. | |
1506 | */ | |
1507 | cpuc->n_added -= cpuc->n_txn; | |
1508 | cpuc->n_events -= cpuc->n_txn; | |
33696fc0 | 1509 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1510 | } |
1511 | ||
1512 | /* | |
1513 | * Commit group events scheduling transaction | |
1514 | * Perform the group schedulability test as a whole | |
1515 | * Return 0 if success | |
1516 | */ | |
51b0fe39 | 1517 | static int x86_pmu_commit_txn(struct pmu *pmu) |
4d1c52b0 LM |
1518 | { |
1519 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1520 | int assign[X86_PMC_IDX_MAX]; | |
1521 | int n, ret; | |
1522 | ||
1523 | n = cpuc->n_events; | |
1524 | ||
1525 | if (!x86_pmu_initialized()) | |
1526 | return -EAGAIN; | |
1527 | ||
1528 | ret = x86_pmu.schedule_events(cpuc, n, assign); | |
1529 | if (ret) | |
1530 | return ret; | |
1531 | ||
1532 | /* | |
1533 | * copy new assignment, now we know it is possible | |
1534 | * will be used by hw_perf_enable() | |
1535 | */ | |
1536 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
1537 | ||
8d2cacbb | 1538 | cpuc->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1539 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1540 | return 0; |
1541 | } | |
1542 | ||
ca037701 PZ |
1543 | /* |
1544 | * validate that we can schedule this event | |
1545 | */ | |
1546 | static int validate_event(struct perf_event *event) | |
1547 | { | |
1548 | struct cpu_hw_events *fake_cpuc; | |
1549 | struct event_constraint *c; | |
1550 | int ret = 0; | |
1551 | ||
1552 | fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO); | |
1553 | if (!fake_cpuc) | |
1554 | return -ENOMEM; | |
1555 | ||
1556 | c = x86_pmu.get_event_constraints(fake_cpuc, event); | |
1557 | ||
1558 | if (!c || !c->weight) | |
1559 | ret = -ENOSPC; | |
1560 | ||
1561 | if (x86_pmu.put_event_constraints) | |
1562 | x86_pmu.put_event_constraints(fake_cpuc, event); | |
1563 | ||
1564 | kfree(fake_cpuc); | |
1565 | ||
1566 | return ret; | |
1567 | } | |
1568 | ||
1da53e02 SE |
1569 | /* |
1570 | * validate a single event group | |
1571 | * | |
1572 | * validation include: | |
184f412c IM |
1573 | * - check events are compatible which each other |
1574 | * - events do not compete for the same counter | |
1575 | * - number of events <= number of counters | |
1da53e02 SE |
1576 | * |
1577 | * validation ensures the group can be loaded onto the | |
1578 | * PMU if it was the only group available. | |
1579 | */ | |
fe9081cc PZ |
1580 | static int validate_group(struct perf_event *event) |
1581 | { | |
1da53e02 | 1582 | struct perf_event *leader = event->group_leader; |
502568d5 PZ |
1583 | struct cpu_hw_events *fake_cpuc; |
1584 | int ret, n; | |
fe9081cc | 1585 | |
502568d5 PZ |
1586 | ret = -ENOMEM; |
1587 | fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO); | |
1588 | if (!fake_cpuc) | |
1589 | goto out; | |
fe9081cc | 1590 | |
1da53e02 SE |
1591 | /* |
1592 | * the event is not yet connected with its | |
1593 | * siblings therefore we must first collect | |
1594 | * existing siblings, then add the new event | |
1595 | * before we can simulate the scheduling | |
1596 | */ | |
502568d5 PZ |
1597 | ret = -ENOSPC; |
1598 | n = collect_events(fake_cpuc, leader, true); | |
1da53e02 | 1599 | if (n < 0) |
502568d5 | 1600 | goto out_free; |
fe9081cc | 1601 | |
502568d5 PZ |
1602 | fake_cpuc->n_events = n; |
1603 | n = collect_events(fake_cpuc, event, false); | |
1da53e02 | 1604 | if (n < 0) |
502568d5 | 1605 | goto out_free; |
fe9081cc | 1606 | |
502568d5 | 1607 | fake_cpuc->n_events = n; |
1da53e02 | 1608 | |
a072738e | 1609 | ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); |
502568d5 PZ |
1610 | |
1611 | out_free: | |
1612 | kfree(fake_cpuc); | |
1613 | out: | |
1614 | return ret; | |
fe9081cc PZ |
1615 | } |
1616 | ||
b0a873eb | 1617 | int x86_pmu_event_init(struct perf_event *event) |
621a01ea | 1618 | { |
51b0fe39 | 1619 | struct pmu *tmp; |
621a01ea IM |
1620 | int err; |
1621 | ||
b0a873eb PZ |
1622 | switch (event->attr.type) { |
1623 | case PERF_TYPE_RAW: | |
1624 | case PERF_TYPE_HARDWARE: | |
1625 | case PERF_TYPE_HW_CACHE: | |
1626 | break; | |
1627 | ||
1628 | default: | |
1629 | return -ENOENT; | |
1630 | } | |
1631 | ||
1632 | err = __x86_pmu_event_init(event); | |
fe9081cc | 1633 | if (!err) { |
8113070d SE |
1634 | /* |
1635 | * we temporarily connect event to its pmu | |
1636 | * such that validate_group() can classify | |
1637 | * it as an x86 event using is_x86_event() | |
1638 | */ | |
1639 | tmp = event->pmu; | |
1640 | event->pmu = &pmu; | |
1641 | ||
fe9081cc PZ |
1642 | if (event->group_leader != event) |
1643 | err = validate_group(event); | |
ca037701 PZ |
1644 | else |
1645 | err = validate_event(event); | |
8113070d SE |
1646 | |
1647 | event->pmu = tmp; | |
fe9081cc | 1648 | } |
a1792cda | 1649 | if (err) { |
cdd6c482 IM |
1650 | if (event->destroy) |
1651 | event->destroy(event); | |
a1792cda | 1652 | } |
621a01ea | 1653 | |
b0a873eb | 1654 | return err; |
621a01ea | 1655 | } |
d7d59fb3 | 1656 | |
b0a873eb | 1657 | static struct pmu pmu = { |
a4eaf7f1 PZ |
1658 | .pmu_enable = x86_pmu_enable, |
1659 | .pmu_disable = x86_pmu_disable, | |
1660 | ||
b0a873eb | 1661 | .event_init = x86_pmu_event_init, |
a4eaf7f1 PZ |
1662 | |
1663 | .add = x86_pmu_add, | |
1664 | .del = x86_pmu_del, | |
b0a873eb PZ |
1665 | .start = x86_pmu_start, |
1666 | .stop = x86_pmu_stop, | |
1667 | .read = x86_pmu_read, | |
a4eaf7f1 | 1668 | |
b0a873eb PZ |
1669 | .start_txn = x86_pmu_start_txn, |
1670 | .cancel_txn = x86_pmu_cancel_txn, | |
1671 | .commit_txn = x86_pmu_commit_txn, | |
1672 | }; | |
1673 | ||
d7d59fb3 PZ |
1674 | /* |
1675 | * callchain support | |
1676 | */ | |
1677 | ||
d7d59fb3 PZ |
1678 | static void |
1679 | backtrace_warning_symbol(void *data, char *msg, unsigned long symbol) | |
1680 | { | |
1681 | /* Ignore warnings */ | |
1682 | } | |
1683 | ||
1684 | static void backtrace_warning(void *data, char *msg) | |
1685 | { | |
1686 | /* Ignore warnings */ | |
1687 | } | |
1688 | ||
1689 | static int backtrace_stack(void *data, char *name) | |
1690 | { | |
038e836e | 1691 | return 0; |
d7d59fb3 PZ |
1692 | } |
1693 | ||
1694 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
1695 | { | |
1696 | struct perf_callchain_entry *entry = data; | |
1697 | ||
70791ce9 | 1698 | perf_callchain_store(entry, addr); |
d7d59fb3 PZ |
1699 | } |
1700 | ||
1701 | static const struct stacktrace_ops backtrace_ops = { | |
1702 | .warning = backtrace_warning, | |
1703 | .warning_symbol = backtrace_warning_symbol, | |
1704 | .stack = backtrace_stack, | |
1705 | .address = backtrace_address, | |
06d65bda | 1706 | .walk_stack = print_context_stack_bp, |
d7d59fb3 PZ |
1707 | }; |
1708 | ||
56962b44 FW |
1709 | void |
1710 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 | 1711 | { |
927c7a9e FW |
1712 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
1713 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 1714 | return; |
927c7a9e FW |
1715 | } |
1716 | ||
70791ce9 | 1717 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 1718 | |
9c0729dc | 1719 | dump_trace(NULL, regs, NULL, &backtrace_ops, entry); |
d7d59fb3 PZ |
1720 | } |
1721 | ||
257ef9d2 TE |
1722 | #ifdef CONFIG_COMPAT |
1723 | static inline int | |
1724 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
74193ef0 | 1725 | { |
257ef9d2 TE |
1726 | /* 32-bit process in 64-bit kernel. */ |
1727 | struct stack_frame_ia32 frame; | |
1728 | const void __user *fp; | |
74193ef0 | 1729 | |
257ef9d2 TE |
1730 | if (!test_thread_flag(TIF_IA32)) |
1731 | return 0; | |
1732 | ||
1733 | fp = compat_ptr(regs->bp); | |
1734 | while (entry->nr < PERF_MAX_STACK_DEPTH) { | |
1735 | unsigned long bytes; | |
1736 | frame.next_frame = 0; | |
1737 | frame.return_address = 0; | |
1738 | ||
1739 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); | |
1740 | if (bytes != sizeof(frame)) | |
1741 | break; | |
74193ef0 | 1742 | |
257ef9d2 TE |
1743 | if (fp < compat_ptr(regs->sp)) |
1744 | break; | |
74193ef0 | 1745 | |
70791ce9 | 1746 | perf_callchain_store(entry, frame.return_address); |
257ef9d2 TE |
1747 | fp = compat_ptr(frame.next_frame); |
1748 | } | |
1749 | return 1; | |
d7d59fb3 | 1750 | } |
257ef9d2 TE |
1751 | #else |
1752 | static inline int | |
1753 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1754 | { | |
1755 | return 0; | |
1756 | } | |
1757 | #endif | |
d7d59fb3 | 1758 | |
56962b44 FW |
1759 | void |
1760 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 PZ |
1761 | { |
1762 | struct stack_frame frame; | |
1763 | const void __user *fp; | |
1764 | ||
927c7a9e FW |
1765 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
1766 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 1767 | return; |
927c7a9e | 1768 | } |
5a6cec3a | 1769 | |
74193ef0 | 1770 | fp = (void __user *)regs->bp; |
d7d59fb3 | 1771 | |
70791ce9 | 1772 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 1773 | |
257ef9d2 TE |
1774 | if (perf_callchain_user32(regs, entry)) |
1775 | return; | |
1776 | ||
f9188e02 | 1777 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
257ef9d2 | 1778 | unsigned long bytes; |
038e836e | 1779 | frame.next_frame = NULL; |
d7d59fb3 PZ |
1780 | frame.return_address = 0; |
1781 | ||
257ef9d2 TE |
1782 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); |
1783 | if (bytes != sizeof(frame)) | |
d7d59fb3 PZ |
1784 | break; |
1785 | ||
5a6cec3a | 1786 | if ((unsigned long)fp < regs->sp) |
d7d59fb3 PZ |
1787 | break; |
1788 | ||
70791ce9 | 1789 | perf_callchain_store(entry, frame.return_address); |
038e836e | 1790 | fp = frame.next_frame; |
d7d59fb3 PZ |
1791 | } |
1792 | } | |
1793 | ||
39447b38 ZY |
1794 | unsigned long perf_instruction_pointer(struct pt_regs *regs) |
1795 | { | |
1796 | unsigned long ip; | |
dcf46b94 | 1797 | |
39447b38 ZY |
1798 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) |
1799 | ip = perf_guest_cbs->get_guest_ip(); | |
1800 | else | |
1801 | ip = instruction_pointer(regs); | |
dcf46b94 | 1802 | |
39447b38 ZY |
1803 | return ip; |
1804 | } | |
1805 | ||
1806 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
1807 | { | |
1808 | int misc = 0; | |
dcf46b94 | 1809 | |
39447b38 | 1810 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
dcf46b94 ZY |
1811 | if (perf_guest_cbs->is_user_mode()) |
1812 | misc |= PERF_RECORD_MISC_GUEST_USER; | |
1813 | else | |
1814 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; | |
1815 | } else { | |
1816 | if (user_mode(regs)) | |
1817 | misc |= PERF_RECORD_MISC_USER; | |
1818 | else | |
1819 | misc |= PERF_RECORD_MISC_KERNEL; | |
1820 | } | |
1821 | ||
39447b38 | 1822 | if (regs->flags & PERF_EFLAGS_EXACT) |
ab608344 | 1823 | misc |= PERF_RECORD_MISC_EXACT_IP; |
39447b38 ZY |
1824 | |
1825 | return misc; | |
1826 | } |