Commit | Line | Data |
---|---|---|
241771ef IM |
1 | /* |
2 | * Performance counter x86 architecture code | |
3 | * | |
4 | * Copyright(C) 2008 Thomas Gleixner <tglx@linutronix.de> | |
5 | * Copyright(C) 2008 Red Hat, Inc., Ingo Molnar | |
b56a3802 | 6 | * Copyright(C) 2009 Jaswinder Singh Rajput |
39d81eab | 7 | * Copyright(C) 2009 Advanced Micro Devices, Inc., Robert Richter |
241771ef IM |
8 | * |
9 | * For licencing details see kernel-base/COPYING | |
10 | */ | |
11 | ||
12 | #include <linux/perf_counter.h> | |
13 | #include <linux/capability.h> | |
14 | #include <linux/notifier.h> | |
15 | #include <linux/hardirq.h> | |
16 | #include <linux/kprobes.h> | |
4ac13294 | 17 | #include <linux/module.h> |
241771ef IM |
18 | #include <linux/kdebug.h> |
19 | #include <linux/sched.h> | |
d7d59fb3 | 20 | #include <linux/uaccess.h> |
241771ef | 21 | |
241771ef | 22 | #include <asm/apic.h> |
d7d59fb3 | 23 | #include <asm/stacktrace.h> |
4e935e47 | 24 | #include <asm/nmi.h> |
241771ef IM |
25 | |
26 | static bool perf_counters_initialized __read_mostly; | |
862a1a5f | 27 | static u64 perf_counter_mask __read_mostly; |
703e937c | 28 | |
241771ef | 29 | struct cpu_hw_counters { |
862a1a5f IM |
30 | struct perf_counter *counters[X86_PMC_IDX_MAX]; |
31 | unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
93904966 | 32 | unsigned long active[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
4b39fd96 | 33 | unsigned long interrupts; |
b0f3f28e | 34 | u64 throttle_ctrl; |
b0f3f28e | 35 | int enabled; |
241771ef IM |
36 | }; |
37 | ||
38 | /* | |
5f4ec28f | 39 | * struct x86_pmu - generic x86 pmu |
241771ef | 40 | */ |
5f4ec28f | 41 | struct x86_pmu { |
faa28ae0 RR |
42 | const char *name; |
43 | int version; | |
39d81eab | 44 | int (*handle_irq)(struct pt_regs *, int); |
169e41eb | 45 | u64 (*save_disable_all)(void); |
b0f3f28e | 46 | void (*restore_all)(u64); |
7c90cc45 | 47 | void (*enable)(struct hw_perf_counter *, int); |
d4369891 | 48 | void (*disable)(struct hw_perf_counter *, int); |
169e41eb JSR |
49 | unsigned eventsel; |
50 | unsigned perfctr; | |
b0f3f28e PZ |
51 | u64 (*event_map)(int); |
52 | u64 (*raw_event)(u64); | |
169e41eb | 53 | int max_events; |
0933e5c6 RR |
54 | int num_counters; |
55 | int num_counters_fixed; | |
56 | int counter_bits; | |
57 | u64 counter_mask; | |
b56a3802 JSR |
58 | }; |
59 | ||
4a06bd85 | 60 | static struct x86_pmu x86_pmu __read_mostly; |
b56a3802 | 61 | |
b0f3f28e PZ |
62 | static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters) = { |
63 | .enabled = 1, | |
64 | }; | |
241771ef | 65 | |
b56a3802 JSR |
66 | /* |
67 | * Intel PerfMon v3. Used on Core2 and later. | |
68 | */ | |
b0f3f28e | 69 | static const u64 intel_perfmon_event_map[] = |
241771ef | 70 | { |
f650a672 | 71 | [PERF_COUNT_CPU_CYCLES] = 0x003c, |
241771ef IM |
72 | [PERF_COUNT_INSTRUCTIONS] = 0x00c0, |
73 | [PERF_COUNT_CACHE_REFERENCES] = 0x4f2e, | |
74 | [PERF_COUNT_CACHE_MISSES] = 0x412e, | |
75 | [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4, | |
76 | [PERF_COUNT_BRANCH_MISSES] = 0x00c5, | |
f650a672 | 77 | [PERF_COUNT_BUS_CYCLES] = 0x013c, |
241771ef IM |
78 | }; |
79 | ||
5f4ec28f | 80 | static u64 intel_pmu_event_map(int event) |
b56a3802 JSR |
81 | { |
82 | return intel_perfmon_event_map[event]; | |
83 | } | |
241771ef | 84 | |
5f4ec28f | 85 | static u64 intel_pmu_raw_event(u64 event) |
b0f3f28e | 86 | { |
82bae4f8 PZ |
87 | #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL |
88 | #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL | |
89 | #define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL | |
b0f3f28e PZ |
90 | |
91 | #define CORE_EVNTSEL_MASK \ | |
92 | (CORE_EVNTSEL_EVENT_MASK | \ | |
93 | CORE_EVNTSEL_UNIT_MASK | \ | |
94 | CORE_EVNTSEL_COUNTER_MASK) | |
95 | ||
96 | return event & CORE_EVNTSEL_MASK; | |
97 | } | |
98 | ||
f87ad35d JSR |
99 | /* |
100 | * AMD Performance Monitor K7 and later. | |
101 | */ | |
b0f3f28e | 102 | static const u64 amd_perfmon_event_map[] = |
f87ad35d JSR |
103 | { |
104 | [PERF_COUNT_CPU_CYCLES] = 0x0076, | |
105 | [PERF_COUNT_INSTRUCTIONS] = 0x00c0, | |
106 | [PERF_COUNT_CACHE_REFERENCES] = 0x0080, | |
107 | [PERF_COUNT_CACHE_MISSES] = 0x0081, | |
108 | [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4, | |
109 | [PERF_COUNT_BRANCH_MISSES] = 0x00c5, | |
110 | }; | |
111 | ||
5f4ec28f | 112 | static u64 amd_pmu_event_map(int event) |
f87ad35d JSR |
113 | { |
114 | return amd_perfmon_event_map[event]; | |
115 | } | |
116 | ||
5f4ec28f | 117 | static u64 amd_pmu_raw_event(u64 event) |
b0f3f28e | 118 | { |
82bae4f8 PZ |
119 | #define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL |
120 | #define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL | |
121 | #define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL | |
b0f3f28e PZ |
122 | |
123 | #define K7_EVNTSEL_MASK \ | |
124 | (K7_EVNTSEL_EVENT_MASK | \ | |
125 | K7_EVNTSEL_UNIT_MASK | \ | |
126 | K7_EVNTSEL_COUNTER_MASK) | |
127 | ||
128 | return event & K7_EVNTSEL_MASK; | |
129 | } | |
130 | ||
ee06094f IM |
131 | /* |
132 | * Propagate counter elapsed time into the generic counter. | |
133 | * Can only be executed on the CPU where the counter is active. | |
134 | * Returns the delta events processed. | |
135 | */ | |
136 | static void | |
137 | x86_perf_counter_update(struct perf_counter *counter, | |
138 | struct hw_perf_counter *hwc, int idx) | |
139 | { | |
140 | u64 prev_raw_count, new_raw_count, delta; | |
141 | ||
ee06094f IM |
142 | /* |
143 | * Careful: an NMI might modify the previous counter value. | |
144 | * | |
145 | * Our tactic to handle this is to first atomically read and | |
146 | * exchange a new raw count - then add that new-prev delta | |
147 | * count to the generic counter atomically: | |
148 | */ | |
149 | again: | |
150 | prev_raw_count = atomic64_read(&hwc->prev_count); | |
151 | rdmsrl(hwc->counter_base + idx, new_raw_count); | |
152 | ||
153 | if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count, | |
154 | new_raw_count) != prev_raw_count) | |
155 | goto again; | |
156 | ||
157 | /* | |
158 | * Now we have the new raw value and have updated the prev | |
159 | * timestamp already. We can now calculate the elapsed delta | |
160 | * (counter-)time and add that to the generic counter. | |
161 | * | |
162 | * Careful, not all hw sign-extends above the physical width | |
163 | * of the count, so we do that by clipping the delta to 32 bits: | |
164 | */ | |
165 | delta = (u64)(u32)((s32)new_raw_count - (s32)prev_raw_count); | |
ee06094f IM |
166 | |
167 | atomic64_add(delta, &counter->count); | |
168 | atomic64_sub(delta, &hwc->period_left); | |
169 | } | |
170 | ||
4e935e47 PZ |
171 | static atomic_t num_counters; |
172 | static DEFINE_MUTEX(pmc_reserve_mutex); | |
173 | ||
174 | static bool reserve_pmc_hardware(void) | |
175 | { | |
176 | int i; | |
177 | ||
178 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
179 | disable_lapic_nmi_watchdog(); | |
180 | ||
0933e5c6 | 181 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 | 182 | if (!reserve_perfctr_nmi(x86_pmu.perfctr + i)) |
4e935e47 PZ |
183 | goto perfctr_fail; |
184 | } | |
185 | ||
0933e5c6 | 186 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 | 187 | if (!reserve_evntsel_nmi(x86_pmu.eventsel + i)) |
4e935e47 PZ |
188 | goto eventsel_fail; |
189 | } | |
190 | ||
191 | return true; | |
192 | ||
193 | eventsel_fail: | |
194 | for (i--; i >= 0; i--) | |
4a06bd85 | 195 | release_evntsel_nmi(x86_pmu.eventsel + i); |
4e935e47 | 196 | |
0933e5c6 | 197 | i = x86_pmu.num_counters; |
4e935e47 PZ |
198 | |
199 | perfctr_fail: | |
200 | for (i--; i >= 0; i--) | |
4a06bd85 | 201 | release_perfctr_nmi(x86_pmu.perfctr + i); |
4e935e47 PZ |
202 | |
203 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
204 | enable_lapic_nmi_watchdog(); | |
205 | ||
206 | return false; | |
207 | } | |
208 | ||
209 | static void release_pmc_hardware(void) | |
210 | { | |
211 | int i; | |
212 | ||
0933e5c6 | 213 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 RR |
214 | release_perfctr_nmi(x86_pmu.perfctr + i); |
215 | release_evntsel_nmi(x86_pmu.eventsel + i); | |
4e935e47 PZ |
216 | } |
217 | ||
218 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
219 | enable_lapic_nmi_watchdog(); | |
220 | } | |
221 | ||
222 | static void hw_perf_counter_destroy(struct perf_counter *counter) | |
223 | { | |
224 | if (atomic_dec_and_mutex_lock(&num_counters, &pmc_reserve_mutex)) { | |
225 | release_pmc_hardware(); | |
226 | mutex_unlock(&pmc_reserve_mutex); | |
227 | } | |
228 | } | |
229 | ||
241771ef IM |
230 | /* |
231 | * Setup the hardware configuration for a given hw_event_type | |
232 | */ | |
621a01ea | 233 | static int __hw_perf_counter_init(struct perf_counter *counter) |
241771ef | 234 | { |
9f66a381 | 235 | struct perf_counter_hw_event *hw_event = &counter->hw_event; |
241771ef | 236 | struct hw_perf_counter *hwc = &counter->hw; |
4e935e47 | 237 | int err; |
241771ef | 238 | |
39d81eab RR |
239 | /* disable temporarily */ |
240 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
241 | return -ENOSYS; | |
242 | ||
241771ef IM |
243 | if (unlikely(!perf_counters_initialized)) |
244 | return -EINVAL; | |
245 | ||
4e935e47 PZ |
246 | err = 0; |
247 | if (atomic_inc_not_zero(&num_counters)) { | |
248 | mutex_lock(&pmc_reserve_mutex); | |
249 | if (atomic_read(&num_counters) == 0 && !reserve_pmc_hardware()) | |
250 | err = -EBUSY; | |
251 | else | |
252 | atomic_inc(&num_counters); | |
253 | mutex_unlock(&pmc_reserve_mutex); | |
254 | } | |
255 | if (err) | |
256 | return err; | |
257 | ||
241771ef | 258 | /* |
0475f9ea | 259 | * Generate PMC IRQs: |
241771ef IM |
260 | * (keep 'enabled' bit clear for now) |
261 | */ | |
0475f9ea | 262 | hwc->config = ARCH_PERFMON_EVENTSEL_INT; |
241771ef IM |
263 | |
264 | /* | |
0475f9ea | 265 | * Count user and OS events unless requested not to. |
241771ef | 266 | */ |
0475f9ea PM |
267 | if (!hw_event->exclude_user) |
268 | hwc->config |= ARCH_PERFMON_EVENTSEL_USR; | |
269 | if (!hw_event->exclude_kernel) | |
241771ef | 270 | hwc->config |= ARCH_PERFMON_EVENTSEL_OS; |
0475f9ea PM |
271 | |
272 | /* | |
273 | * If privileged enough, allow NMI events: | |
274 | */ | |
275 | hwc->nmi = 0; | |
276 | if (capable(CAP_SYS_ADMIN) && hw_event->nmi) | |
277 | hwc->nmi = 1; | |
241771ef | 278 | |
9f66a381 | 279 | hwc->irq_period = hw_event->irq_period; |
241771ef IM |
280 | /* |
281 | * Intel PMCs cannot be accessed sanely above 32 bit width, | |
282 | * so we install an artificial 1<<31 period regardless of | |
283 | * the generic counter period: | |
284 | */ | |
f87ad35d JSR |
285 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
286 | if ((s64)hwc->irq_period <= 0 || hwc->irq_period > 0x7FFFFFFF) | |
287 | hwc->irq_period = 0x7FFFFFFF; | |
241771ef | 288 | |
ee06094f | 289 | atomic64_set(&hwc->period_left, hwc->irq_period); |
241771ef IM |
290 | |
291 | /* | |
dfa7c899 | 292 | * Raw event type provide the config in the event structure |
241771ef | 293 | */ |
f4a2deb4 | 294 | if (perf_event_raw(hw_event)) { |
4a06bd85 | 295 | hwc->config |= x86_pmu.raw_event(perf_event_config(hw_event)); |
241771ef | 296 | } else { |
4a06bd85 | 297 | if (perf_event_id(hw_event) >= x86_pmu.max_events) |
241771ef IM |
298 | return -EINVAL; |
299 | /* | |
300 | * The generic map: | |
301 | */ | |
4a06bd85 | 302 | hwc->config |= x86_pmu.event_map(perf_event_id(hw_event)); |
241771ef | 303 | } |
241771ef | 304 | |
4e935e47 PZ |
305 | counter->destroy = hw_perf_counter_destroy; |
306 | ||
241771ef IM |
307 | return 0; |
308 | } | |
309 | ||
5f4ec28f | 310 | static u64 intel_pmu_save_disable_all(void) |
4ac13294 TG |
311 | { |
312 | u64 ctrl; | |
313 | ||
314 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); | |
862a1a5f | 315 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); |
2b9ff0db | 316 | |
4ac13294 | 317 | return ctrl; |
241771ef | 318 | } |
b56a3802 | 319 | |
5f4ec28f | 320 | static u64 amd_pmu_save_disable_all(void) |
f87ad35d | 321 | { |
b0f3f28e PZ |
322 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
323 | int enabled, idx; | |
324 | ||
325 | enabled = cpuc->enabled; | |
326 | cpuc->enabled = 0; | |
60b3df9c PZ |
327 | /* |
328 | * ensure we write the disable before we start disabling the | |
5f4ec28f RR |
329 | * counters proper, so that amd_pmu_enable_counter() does the |
330 | * right thing. | |
60b3df9c | 331 | */ |
b0f3f28e | 332 | barrier(); |
f87ad35d | 333 | |
0933e5c6 | 334 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
b0f3f28e PZ |
335 | u64 val; |
336 | ||
93904966 | 337 | if (!test_bit(idx, cpuc->active)) |
4295ee62 | 338 | continue; |
f87ad35d | 339 | rdmsrl(MSR_K7_EVNTSEL0 + idx, val); |
4295ee62 RR |
340 | if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE)) |
341 | continue; | |
342 | val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE; | |
343 | wrmsrl(MSR_K7_EVNTSEL0 + idx, val); | |
f87ad35d JSR |
344 | } |
345 | ||
b0f3f28e | 346 | return enabled; |
f87ad35d JSR |
347 | } |
348 | ||
b56a3802 JSR |
349 | u64 hw_perf_save_disable(void) |
350 | { | |
351 | if (unlikely(!perf_counters_initialized)) | |
352 | return 0; | |
353 | ||
4a06bd85 | 354 | return x86_pmu.save_disable_all(); |
b56a3802 | 355 | } |
b0f3f28e PZ |
356 | /* |
357 | * Exported because of ACPI idle | |
358 | */ | |
01b2838c | 359 | EXPORT_SYMBOL_GPL(hw_perf_save_disable); |
241771ef | 360 | |
5f4ec28f | 361 | static void intel_pmu_restore_all(u64 ctrl) |
b56a3802 JSR |
362 | { |
363 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); | |
364 | } | |
365 | ||
5f4ec28f | 366 | static void amd_pmu_restore_all(u64 ctrl) |
f87ad35d | 367 | { |
b0f3f28e | 368 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
f87ad35d JSR |
369 | int idx; |
370 | ||
b0f3f28e PZ |
371 | cpuc->enabled = ctrl; |
372 | barrier(); | |
373 | if (!ctrl) | |
374 | return; | |
375 | ||
0933e5c6 | 376 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
4295ee62 | 377 | u64 val; |
b0f3f28e | 378 | |
93904966 | 379 | if (!test_bit(idx, cpuc->active)) |
4295ee62 RR |
380 | continue; |
381 | rdmsrl(MSR_K7_EVNTSEL0 + idx, val); | |
382 | if (val & ARCH_PERFMON_EVENTSEL0_ENABLE) | |
383 | continue; | |
384 | val |= ARCH_PERFMON_EVENTSEL0_ENABLE; | |
385 | wrmsrl(MSR_K7_EVNTSEL0 + idx, val); | |
f87ad35d JSR |
386 | } |
387 | } | |
388 | ||
ee06094f IM |
389 | void hw_perf_restore(u64 ctrl) |
390 | { | |
2b9ff0db IM |
391 | if (unlikely(!perf_counters_initialized)) |
392 | return; | |
393 | ||
4a06bd85 | 394 | x86_pmu.restore_all(ctrl); |
ee06094f | 395 | } |
b0f3f28e PZ |
396 | /* |
397 | * Exported because of ACPI idle | |
398 | */ | |
ee06094f IM |
399 | EXPORT_SYMBOL_GPL(hw_perf_restore); |
400 | ||
b7f8859a | 401 | static inline u64 intel_pmu_get_status(u64 mask) |
b0f3f28e PZ |
402 | { |
403 | u64 status; | |
404 | ||
b0f3f28e PZ |
405 | if (unlikely(!perf_counters_initialized)) |
406 | return 0; | |
b7f8859a | 407 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); |
b0f3f28e | 408 | |
b7f8859a | 409 | return status; |
b0f3f28e PZ |
410 | } |
411 | ||
dee5d906 | 412 | static inline void intel_pmu_ack_status(u64 ack) |
b0f3f28e PZ |
413 | { |
414 | wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); | |
415 | } | |
416 | ||
7c90cc45 | 417 | static inline void x86_pmu_enable_counter(struct hw_perf_counter *hwc, int idx) |
b0f3f28e | 418 | { |
7c90cc45 | 419 | int err; |
b0f3f28e | 420 | |
b0f3f28e PZ |
421 | if (unlikely(!perf_counters_initialized)) |
422 | return; | |
423 | ||
7c90cc45 RR |
424 | err = checking_wrmsrl(hwc->config_base + idx, |
425 | hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE); | |
b0f3f28e PZ |
426 | } |
427 | ||
d4369891 | 428 | static inline void x86_pmu_disable_counter(struct hw_perf_counter *hwc, int idx) |
b0f3f28e | 429 | { |
d4369891 | 430 | int err; |
b0f3f28e | 431 | |
b0f3f28e PZ |
432 | if (unlikely(!perf_counters_initialized)) |
433 | return; | |
434 | ||
d4369891 RR |
435 | err = checking_wrmsrl(hwc->config_base + idx, |
436 | hwc->config); | |
b0f3f28e PZ |
437 | } |
438 | ||
2f18d1e8 | 439 | static inline void |
d4369891 | 440 | intel_pmu_disable_fixed(struct hw_perf_counter *hwc, int __idx) |
2f18d1e8 IM |
441 | { |
442 | int idx = __idx - X86_PMC_IDX_FIXED; | |
443 | u64 ctrl_val, mask; | |
444 | int err; | |
445 | ||
446 | mask = 0xfULL << (idx * 4); | |
447 | ||
448 | rdmsrl(hwc->config_base, ctrl_val); | |
449 | ctrl_val &= ~mask; | |
450 | err = checking_wrmsrl(hwc->config_base, ctrl_val); | |
451 | } | |
452 | ||
7e2ae347 | 453 | static inline void |
d4369891 | 454 | intel_pmu_disable_counter(struct hw_perf_counter *hwc, int idx) |
7e2ae347 | 455 | { |
d4369891 RR |
456 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { |
457 | intel_pmu_disable_fixed(hwc, idx); | |
458 | return; | |
459 | } | |
460 | ||
461 | x86_pmu_disable_counter(hwc, idx); | |
462 | } | |
463 | ||
464 | static inline void | |
465 | amd_pmu_disable_counter(struct hw_perf_counter *hwc, int idx) | |
466 | { | |
467 | x86_pmu_disable_counter(hwc, idx); | |
7e2ae347 IM |
468 | } |
469 | ||
2f18d1e8 | 470 | static DEFINE_PER_CPU(u64, prev_left[X86_PMC_IDX_MAX]); |
241771ef | 471 | |
ee06094f IM |
472 | /* |
473 | * Set the next IRQ period, based on the hwc->period_left value. | |
474 | * To be called with the counter disabled in hw: | |
475 | */ | |
476 | static void | |
26816c28 | 477 | x86_perf_counter_set_period(struct perf_counter *counter, |
ee06094f | 478 | struct hw_perf_counter *hwc, int idx) |
241771ef | 479 | { |
2f18d1e8 | 480 | s64 left = atomic64_read(&hwc->period_left); |
595258aa | 481 | s64 period = hwc->irq_period; |
2f18d1e8 | 482 | int err; |
ee06094f | 483 | |
ee06094f IM |
484 | /* |
485 | * If we are way outside a reasoable range then just skip forward: | |
486 | */ | |
487 | if (unlikely(left <= -period)) { | |
488 | left = period; | |
489 | atomic64_set(&hwc->period_left, left); | |
490 | } | |
491 | ||
492 | if (unlikely(left <= 0)) { | |
493 | left += period; | |
494 | atomic64_set(&hwc->period_left, left); | |
495 | } | |
241771ef | 496 | |
ee06094f IM |
497 | per_cpu(prev_left[idx], smp_processor_id()) = left; |
498 | ||
499 | /* | |
500 | * The hw counter starts counting from this counter offset, | |
501 | * mark it to be able to extra future deltas: | |
502 | */ | |
2f18d1e8 | 503 | atomic64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 504 | |
2f18d1e8 | 505 | err = checking_wrmsrl(hwc->counter_base + idx, |
0933e5c6 | 506 | (u64)(-left) & x86_pmu.counter_mask); |
2f18d1e8 IM |
507 | } |
508 | ||
509 | static inline void | |
7c90cc45 | 510 | intel_pmu_enable_fixed(struct hw_perf_counter *hwc, int __idx) |
2f18d1e8 IM |
511 | { |
512 | int idx = __idx - X86_PMC_IDX_FIXED; | |
513 | u64 ctrl_val, bits, mask; | |
514 | int err; | |
515 | ||
516 | /* | |
0475f9ea PM |
517 | * Enable IRQ generation (0x8), |
518 | * and enable ring-3 counting (0x2) and ring-0 counting (0x1) | |
519 | * if requested: | |
2f18d1e8 | 520 | */ |
0475f9ea PM |
521 | bits = 0x8ULL; |
522 | if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) | |
523 | bits |= 0x2; | |
2f18d1e8 IM |
524 | if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) |
525 | bits |= 0x1; | |
526 | bits <<= (idx * 4); | |
527 | mask = 0xfULL << (idx * 4); | |
528 | ||
529 | rdmsrl(hwc->config_base, ctrl_val); | |
530 | ctrl_val &= ~mask; | |
531 | ctrl_val |= bits; | |
532 | err = checking_wrmsrl(hwc->config_base, ctrl_val); | |
7e2ae347 IM |
533 | } |
534 | ||
7c90cc45 | 535 | static void intel_pmu_enable_counter(struct hw_perf_counter *hwc, int idx) |
7e2ae347 | 536 | { |
7c90cc45 RR |
537 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { |
538 | intel_pmu_enable_fixed(hwc, idx); | |
539 | return; | |
540 | } | |
541 | ||
542 | x86_pmu_enable_counter(hwc, idx); | |
543 | } | |
544 | ||
545 | static void amd_pmu_enable_counter(struct hw_perf_counter *hwc, int idx) | |
546 | { | |
547 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
548 | ||
549 | if (cpuc->enabled) | |
550 | x86_pmu_enable_counter(hwc, idx); | |
2b583d8b | 551 | else |
d4369891 | 552 | x86_pmu_disable_counter(hwc, idx); |
241771ef IM |
553 | } |
554 | ||
2f18d1e8 IM |
555 | static int |
556 | fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc) | |
862a1a5f | 557 | { |
2f18d1e8 IM |
558 | unsigned int event; |
559 | ||
f87ad35d JSR |
560 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) |
561 | return -1; | |
562 | ||
2f18d1e8 IM |
563 | if (unlikely(hwc->nmi)) |
564 | return -1; | |
565 | ||
566 | event = hwc->config & ARCH_PERFMON_EVENT_MASK; | |
567 | ||
4a06bd85 | 568 | if (unlikely(event == x86_pmu.event_map(PERF_COUNT_INSTRUCTIONS))) |
2f18d1e8 | 569 | return X86_PMC_IDX_FIXED_INSTRUCTIONS; |
4a06bd85 | 570 | if (unlikely(event == x86_pmu.event_map(PERF_COUNT_CPU_CYCLES))) |
2f18d1e8 | 571 | return X86_PMC_IDX_FIXED_CPU_CYCLES; |
4a06bd85 | 572 | if (unlikely(event == x86_pmu.event_map(PERF_COUNT_BUS_CYCLES))) |
2f18d1e8 IM |
573 | return X86_PMC_IDX_FIXED_BUS_CYCLES; |
574 | ||
862a1a5f IM |
575 | return -1; |
576 | } | |
577 | ||
ee06094f IM |
578 | /* |
579 | * Find a PMC slot for the freshly enabled / scheduled in counter: | |
580 | */ | |
4aeb0b42 | 581 | static int x86_pmu_enable(struct perf_counter *counter) |
241771ef IM |
582 | { |
583 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
584 | struct hw_perf_counter *hwc = &counter->hw; | |
2f18d1e8 | 585 | int idx; |
241771ef | 586 | |
2f18d1e8 IM |
587 | idx = fixed_mode_idx(counter, hwc); |
588 | if (idx >= 0) { | |
589 | /* | |
590 | * Try to get the fixed counter, if that is already taken | |
591 | * then try to get a generic counter: | |
592 | */ | |
593 | if (test_and_set_bit(idx, cpuc->used)) | |
594 | goto try_generic; | |
0dff86aa | 595 | |
2f18d1e8 IM |
596 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
597 | /* | |
598 | * We set it so that counter_base + idx in wrmsr/rdmsr maps to | |
599 | * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2: | |
600 | */ | |
601 | hwc->counter_base = | |
602 | MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED; | |
241771ef | 603 | hwc->idx = idx; |
2f18d1e8 IM |
604 | } else { |
605 | idx = hwc->idx; | |
606 | /* Try to get the previous generic counter again */ | |
607 | if (test_and_set_bit(idx, cpuc->used)) { | |
608 | try_generic: | |
0933e5c6 RR |
609 | idx = find_first_zero_bit(cpuc->used, |
610 | x86_pmu.num_counters); | |
611 | if (idx == x86_pmu.num_counters) | |
2f18d1e8 IM |
612 | return -EAGAIN; |
613 | ||
614 | set_bit(idx, cpuc->used); | |
615 | hwc->idx = idx; | |
616 | } | |
4a06bd85 RR |
617 | hwc->config_base = x86_pmu.eventsel; |
618 | hwc->counter_base = x86_pmu.perfctr; | |
241771ef IM |
619 | } |
620 | ||
621 | perf_counters_lapic_init(hwc->nmi); | |
622 | ||
d4369891 | 623 | x86_pmu.disable(hwc, idx); |
241771ef | 624 | |
862a1a5f | 625 | cpuc->counters[idx] = counter; |
09534238 | 626 | set_bit(idx, cpuc->active); |
7e2ae347 | 627 | |
26816c28 | 628 | x86_perf_counter_set_period(counter, hwc, idx); |
7c90cc45 | 629 | x86_pmu.enable(hwc, idx); |
95cdd2e7 IM |
630 | |
631 | return 0; | |
241771ef IM |
632 | } |
633 | ||
634 | void perf_counter_print_debug(void) | |
635 | { | |
2f18d1e8 | 636 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
0dff86aa | 637 | struct cpu_hw_counters *cpuc; |
1e125676 IM |
638 | int cpu, idx; |
639 | ||
0933e5c6 | 640 | if (!x86_pmu.num_counters) |
1e125676 | 641 | return; |
241771ef IM |
642 | |
643 | local_irq_disable(); | |
644 | ||
645 | cpu = smp_processor_id(); | |
0dff86aa | 646 | cpuc = &per_cpu(cpu_hw_counters, cpu); |
241771ef | 647 | |
faa28ae0 | 648 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
649 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
650 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
651 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
652 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
653 | ||
654 | pr_info("\n"); | |
655 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
656 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
657 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
658 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
f87ad35d | 659 | } |
a1ef58f4 | 660 | pr_info("CPU#%d: used: %016llx\n", cpu, *(u64 *)cpuc->used); |
241771ef | 661 | |
0933e5c6 | 662 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
4a06bd85 RR |
663 | rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl); |
664 | rdmsrl(x86_pmu.perfctr + idx, pmc_count); | |
241771ef | 665 | |
ee06094f | 666 | prev_left = per_cpu(prev_left[idx], cpu); |
241771ef | 667 | |
a1ef58f4 | 668 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 669 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 670 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 671 | cpu, idx, pmc_count); |
a1ef58f4 | 672 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 673 | cpu, idx, prev_left); |
241771ef | 674 | } |
0933e5c6 | 675 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
2f18d1e8 IM |
676 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
677 | ||
a1ef58f4 | 678 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
679 | cpu, idx, pmc_count); |
680 | } | |
241771ef IM |
681 | local_irq_enable(); |
682 | } | |
683 | ||
4aeb0b42 | 684 | static void x86_pmu_disable(struct perf_counter *counter) |
241771ef IM |
685 | { |
686 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
687 | struct hw_perf_counter *hwc = &counter->hw; | |
6f00cada | 688 | int idx = hwc->idx; |
241771ef | 689 | |
09534238 RR |
690 | /* |
691 | * Must be done before we disable, otherwise the nmi handler | |
692 | * could reenable again: | |
693 | */ | |
694 | clear_bit(idx, cpuc->active); | |
d4369891 | 695 | x86_pmu.disable(hwc, idx); |
241771ef | 696 | |
2f18d1e8 IM |
697 | /* |
698 | * Make sure the cleared pointer becomes visible before we | |
699 | * (potentially) free the counter: | |
700 | */ | |
527e26af | 701 | barrier(); |
241771ef | 702 | |
ee06094f IM |
703 | /* |
704 | * Drain the remaining delta count out of a counter | |
705 | * that we are disabling: | |
706 | */ | |
707 | x86_perf_counter_update(counter, hwc, idx); | |
09534238 RR |
708 | cpuc->counters[idx] = NULL; |
709 | clear_bit(idx, cpuc->used); | |
241771ef IM |
710 | } |
711 | ||
7e2ae347 | 712 | /* |
ee06094f IM |
713 | * Save and restart an expired counter. Called by NMI contexts, |
714 | * so it has to be careful about preempting normal counter ops: | |
7e2ae347 | 715 | */ |
55de0f2e | 716 | static void intel_pmu_save_and_restart(struct perf_counter *counter) |
241771ef IM |
717 | { |
718 | struct hw_perf_counter *hwc = &counter->hw; | |
719 | int idx = hwc->idx; | |
241771ef | 720 | |
ee06094f | 721 | x86_perf_counter_update(counter, hwc, idx); |
26816c28 | 722 | x86_perf_counter_set_period(counter, hwc, idx); |
7e2ae347 | 723 | |
2f18d1e8 | 724 | if (counter->state == PERF_COUNTER_STATE_ACTIVE) |
7c90cc45 | 725 | intel_pmu_enable_counter(hwc, idx); |
241771ef IM |
726 | } |
727 | ||
4b39fd96 MG |
728 | /* |
729 | * Maximum interrupt frequency of 100KHz per CPU | |
730 | */ | |
169e41eb | 731 | #define PERFMON_MAX_INTERRUPTS (100000/HZ) |
4b39fd96 | 732 | |
241771ef IM |
733 | /* |
734 | * This handler is triggered by the local APIC, so the APIC IRQ handling | |
735 | * rules apply: | |
736 | */ | |
39d81eab | 737 | static int intel_pmu_handle_irq(struct pt_regs *regs, int nmi) |
241771ef IM |
738 | { |
739 | int bit, cpu = smp_processor_id(); | |
4b39fd96 | 740 | u64 ack, status; |
1b023a96 | 741 | struct cpu_hw_counters *cpuc = &per_cpu(cpu_hw_counters, cpu); |
b0f3f28e | 742 | int ret = 0; |
43874d23 | 743 | |
55de0f2e | 744 | cpuc->throttle_ctrl = intel_pmu_save_disable_all(); |
241771ef | 745 | |
b7f8859a | 746 | status = intel_pmu_get_status(cpuc->throttle_ctrl); |
87b9cf46 IM |
747 | if (!status) |
748 | goto out; | |
749 | ||
b0f3f28e | 750 | ret = 1; |
241771ef | 751 | again: |
d278c484 | 752 | inc_irq_stat(apic_perf_irqs); |
241771ef | 753 | ack = status; |
2f18d1e8 | 754 | for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { |
862a1a5f | 755 | struct perf_counter *counter = cpuc->counters[bit]; |
241771ef IM |
756 | |
757 | clear_bit(bit, (unsigned long *) &status); | |
09534238 | 758 | if (!test_bit(bit, cpuc->active)) |
241771ef IM |
759 | continue; |
760 | ||
55de0f2e | 761 | intel_pmu_save_and_restart(counter); |
78f13e95 | 762 | if (perf_counter_overflow(counter, nmi, regs, 0)) |
d4369891 | 763 | intel_pmu_disable_counter(&counter->hw, bit); |
241771ef IM |
764 | } |
765 | ||
dee5d906 | 766 | intel_pmu_ack_status(ack); |
241771ef IM |
767 | |
768 | /* | |
769 | * Repeat if there is more work to be done: | |
770 | */ | |
b7f8859a | 771 | status = intel_pmu_get_status(cpuc->throttle_ctrl); |
241771ef IM |
772 | if (status) |
773 | goto again; | |
87b9cf46 | 774 | out: |
241771ef | 775 | /* |
1b023a96 | 776 | * Restore - do not reenable when global enable is off or throttled: |
241771ef | 777 | */ |
4b39fd96 | 778 | if (++cpuc->interrupts < PERFMON_MAX_INTERRUPTS) |
55de0f2e | 779 | intel_pmu_restore_all(cpuc->throttle_ctrl); |
b0f3f28e PZ |
780 | |
781 | return ret; | |
1b023a96 MG |
782 | } |
783 | ||
39d81eab RR |
784 | static int amd_pmu_handle_irq(struct pt_regs *regs, int nmi) { return 0; } |
785 | ||
1b023a96 MG |
786 | void perf_counter_unthrottle(void) |
787 | { | |
788 | struct cpu_hw_counters *cpuc; | |
789 | ||
790 | if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) | |
791 | return; | |
792 | ||
793 | if (unlikely(!perf_counters_initialized)) | |
794 | return; | |
795 | ||
b0f3f28e | 796 | cpuc = &__get_cpu_var(cpu_hw_counters); |
4b39fd96 | 797 | if (cpuc->interrupts >= PERFMON_MAX_INTERRUPTS) { |
1b023a96 | 798 | if (printk_ratelimit()) |
4b39fd96 | 799 | printk(KERN_WARNING "PERFMON: max interrupts exceeded!\n"); |
b0f3f28e | 800 | hw_perf_restore(cpuc->throttle_ctrl); |
1b023a96 | 801 | } |
4b39fd96 | 802 | cpuc->interrupts = 0; |
241771ef IM |
803 | } |
804 | ||
805 | void smp_perf_counter_interrupt(struct pt_regs *regs) | |
806 | { | |
807 | irq_enter(); | |
241771ef | 808 | apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR); |
b0f3f28e | 809 | ack_APIC_irq(); |
4a06bd85 | 810 | x86_pmu.handle_irq(regs, 0); |
241771ef IM |
811 | irq_exit(); |
812 | } | |
813 | ||
b6276f35 PZ |
814 | void smp_perf_pending_interrupt(struct pt_regs *regs) |
815 | { | |
816 | irq_enter(); | |
817 | ack_APIC_irq(); | |
818 | inc_irq_stat(apic_pending_irqs); | |
819 | perf_counter_do_pending(); | |
820 | irq_exit(); | |
821 | } | |
822 | ||
823 | void set_perf_counter_pending(void) | |
824 | { | |
825 | apic->send_IPI_self(LOCAL_PENDING_VECTOR); | |
826 | } | |
827 | ||
3415dd91 | 828 | void perf_counters_lapic_init(int nmi) |
241771ef IM |
829 | { |
830 | u32 apic_val; | |
831 | ||
832 | if (!perf_counters_initialized) | |
833 | return; | |
834 | /* | |
835 | * Enable the performance counter vector in the APIC LVT: | |
836 | */ | |
837 | apic_val = apic_read(APIC_LVTERR); | |
838 | ||
839 | apic_write(APIC_LVTERR, apic_val | APIC_LVT_MASKED); | |
840 | if (nmi) | |
841 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
842 | else | |
843 | apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR); | |
844 | apic_write(APIC_LVTERR, apic_val); | |
845 | } | |
846 | ||
847 | static int __kprobes | |
848 | perf_counter_nmi_handler(struct notifier_block *self, | |
849 | unsigned long cmd, void *__args) | |
850 | { | |
851 | struct die_args *args = __args; | |
852 | struct pt_regs *regs; | |
b0f3f28e PZ |
853 | int ret; |
854 | ||
855 | switch (cmd) { | |
856 | case DIE_NMI: | |
857 | case DIE_NMI_IPI: | |
858 | break; | |
241771ef | 859 | |
b0f3f28e | 860 | default: |
241771ef | 861 | return NOTIFY_DONE; |
b0f3f28e | 862 | } |
241771ef IM |
863 | |
864 | regs = args->regs; | |
865 | ||
866 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
4a06bd85 | 867 | ret = x86_pmu.handle_irq(regs, 1); |
241771ef | 868 | |
b0f3f28e | 869 | return ret ? NOTIFY_STOP : NOTIFY_OK; |
241771ef IM |
870 | } |
871 | ||
872 | static __read_mostly struct notifier_block perf_counter_nmi_notifier = { | |
5b75af0a MG |
873 | .notifier_call = perf_counter_nmi_handler, |
874 | .next = NULL, | |
875 | .priority = 1 | |
241771ef IM |
876 | }; |
877 | ||
5f4ec28f | 878 | static struct x86_pmu intel_pmu = { |
faa28ae0 | 879 | .name = "Intel", |
39d81eab | 880 | .handle_irq = intel_pmu_handle_irq, |
5f4ec28f RR |
881 | .save_disable_all = intel_pmu_save_disable_all, |
882 | .restore_all = intel_pmu_restore_all, | |
5f4ec28f RR |
883 | .enable = intel_pmu_enable_counter, |
884 | .disable = intel_pmu_disable_counter, | |
b56a3802 JSR |
885 | .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, |
886 | .perfctr = MSR_ARCH_PERFMON_PERFCTR0, | |
5f4ec28f RR |
887 | .event_map = intel_pmu_event_map, |
888 | .raw_event = intel_pmu_raw_event, | |
b56a3802 JSR |
889 | .max_events = ARRAY_SIZE(intel_perfmon_event_map), |
890 | }; | |
891 | ||
5f4ec28f | 892 | static struct x86_pmu amd_pmu = { |
faa28ae0 | 893 | .name = "AMD", |
39d81eab | 894 | .handle_irq = amd_pmu_handle_irq, |
5f4ec28f RR |
895 | .save_disable_all = amd_pmu_save_disable_all, |
896 | .restore_all = amd_pmu_restore_all, | |
5f4ec28f RR |
897 | .enable = amd_pmu_enable_counter, |
898 | .disable = amd_pmu_disable_counter, | |
f87ad35d JSR |
899 | .eventsel = MSR_K7_EVNTSEL0, |
900 | .perfctr = MSR_K7_PERFCTR0, | |
5f4ec28f RR |
901 | .event_map = amd_pmu_event_map, |
902 | .raw_event = amd_pmu_raw_event, | |
f87ad35d | 903 | .max_events = ARRAY_SIZE(amd_perfmon_event_map), |
0933e5c6 RR |
904 | .num_counters = 4, |
905 | .counter_bits = 48, | |
906 | .counter_mask = (1ULL << 48) - 1, | |
f87ad35d JSR |
907 | }; |
908 | ||
72eae04d | 909 | static int intel_pmu_init(void) |
241771ef | 910 | { |
7bb497bd | 911 | union cpuid10_edx edx; |
241771ef | 912 | union cpuid10_eax eax; |
703e937c | 913 | unsigned int unused; |
7bb497bd | 914 | unsigned int ebx; |
faa28ae0 | 915 | int version; |
241771ef | 916 | |
da1a776b | 917 | if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) |
72eae04d | 918 | return -ENODEV; |
da1a776b | 919 | |
241771ef IM |
920 | /* |
921 | * Check whether the Architectural PerfMon supports | |
922 | * Branch Misses Retired Event or not. | |
923 | */ | |
703e937c | 924 | cpuid(10, &eax.full, &ebx, &unused, &edx.full); |
241771ef | 925 | if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED) |
72eae04d | 926 | return -ENODEV; |
241771ef | 927 | |
faa28ae0 RR |
928 | version = eax.split.version_id; |
929 | if (version < 2) | |
72eae04d | 930 | return -ENODEV; |
7bb497bd | 931 | |
4a06bd85 | 932 | x86_pmu = intel_pmu; |
faa28ae0 | 933 | x86_pmu.version = version; |
0933e5c6 RR |
934 | x86_pmu.num_counters = eax.split.num_counters; |
935 | x86_pmu.num_counters_fixed = edx.split.num_counters_fixed; | |
936 | x86_pmu.counter_bits = eax.split.bit_width; | |
937 | x86_pmu.counter_mask = (1ULL << eax.split.bit_width) - 1; | |
b56a3802 | 938 | |
72eae04d | 939 | return 0; |
b56a3802 JSR |
940 | } |
941 | ||
72eae04d | 942 | static int amd_pmu_init(void) |
f87ad35d | 943 | { |
4a06bd85 | 944 | x86_pmu = amd_pmu; |
72eae04d | 945 | return 0; |
f87ad35d JSR |
946 | } |
947 | ||
b56a3802 JSR |
948 | void __init init_hw_perf_counters(void) |
949 | { | |
72eae04d RR |
950 | int err; |
951 | ||
b56a3802 JSR |
952 | switch (boot_cpu_data.x86_vendor) { |
953 | case X86_VENDOR_INTEL: | |
72eae04d | 954 | err = intel_pmu_init(); |
b56a3802 | 955 | break; |
f87ad35d | 956 | case X86_VENDOR_AMD: |
72eae04d | 957 | err = amd_pmu_init(); |
f87ad35d | 958 | break; |
4138960a RR |
959 | default: |
960 | return; | |
b56a3802 | 961 | } |
72eae04d | 962 | if (err != 0) |
b56a3802 JSR |
963 | return; |
964 | ||
faa28ae0 RR |
965 | pr_info("%s Performance Monitoring support detected.\n", x86_pmu.name); |
966 | pr_info("... version: %d\n", x86_pmu.version); | |
967 | pr_info("... bit width: %d\n", x86_pmu.counter_bits); | |
968 | ||
0933e5c6 RR |
969 | pr_info("... num counters: %d\n", x86_pmu.num_counters); |
970 | if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) { | |
971 | x86_pmu.num_counters = X86_PMC_MAX_GENERIC; | |
241771ef | 972 | WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!", |
0933e5c6 | 973 | x86_pmu.num_counters, X86_PMC_MAX_GENERIC); |
241771ef | 974 | } |
0933e5c6 RR |
975 | perf_counter_mask = (1 << x86_pmu.num_counters) - 1; |
976 | perf_max_counters = x86_pmu.num_counters; | |
241771ef | 977 | |
0933e5c6 | 978 | pr_info("... value mask: %016Lx\n", x86_pmu.counter_mask); |
2f18d1e8 | 979 | |
0933e5c6 RR |
980 | if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) { |
981 | x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED; | |
703e937c | 982 | WARN(1, KERN_ERR "hw perf counters fixed %d > max(%d), clipping!", |
0933e5c6 | 983 | x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED); |
703e937c | 984 | } |
0933e5c6 | 985 | pr_info("... fixed counters: %d\n", x86_pmu.num_counters_fixed); |
862a1a5f | 986 | |
0933e5c6 RR |
987 | perf_counter_mask |= |
988 | ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED; | |
241771ef | 989 | |
a1ef58f4 | 990 | pr_info("... counter mask: %016Lx\n", perf_counter_mask); |
75f224cf IM |
991 | perf_counters_initialized = true; |
992 | ||
241771ef IM |
993 | perf_counters_lapic_init(0); |
994 | register_die_notifier(&perf_counter_nmi_notifier); | |
241771ef | 995 | } |
621a01ea | 996 | |
bb775fc2 | 997 | static inline void x86_pmu_read(struct perf_counter *counter) |
ee06094f IM |
998 | { |
999 | x86_perf_counter_update(counter, &counter->hw, counter->hw.idx); | |
1000 | } | |
1001 | ||
4aeb0b42 RR |
1002 | static const struct pmu pmu = { |
1003 | .enable = x86_pmu_enable, | |
1004 | .disable = x86_pmu_disable, | |
1005 | .read = x86_pmu_read, | |
621a01ea IM |
1006 | }; |
1007 | ||
4aeb0b42 | 1008 | const struct pmu *hw_perf_counter_init(struct perf_counter *counter) |
621a01ea IM |
1009 | { |
1010 | int err; | |
1011 | ||
1012 | err = __hw_perf_counter_init(counter); | |
1013 | if (err) | |
9ea98e19 | 1014 | return ERR_PTR(err); |
621a01ea | 1015 | |
4aeb0b42 | 1016 | return &pmu; |
621a01ea | 1017 | } |
d7d59fb3 PZ |
1018 | |
1019 | /* | |
1020 | * callchain support | |
1021 | */ | |
1022 | ||
1023 | static inline | |
1024 | void callchain_store(struct perf_callchain_entry *entry, unsigned long ip) | |
1025 | { | |
1026 | if (entry->nr < MAX_STACK_DEPTH) | |
1027 | entry->ip[entry->nr++] = ip; | |
1028 | } | |
1029 | ||
1030 | static DEFINE_PER_CPU(struct perf_callchain_entry, irq_entry); | |
1031 | static DEFINE_PER_CPU(struct perf_callchain_entry, nmi_entry); | |
1032 | ||
1033 | ||
1034 | static void | |
1035 | backtrace_warning_symbol(void *data, char *msg, unsigned long symbol) | |
1036 | { | |
1037 | /* Ignore warnings */ | |
1038 | } | |
1039 | ||
1040 | static void backtrace_warning(void *data, char *msg) | |
1041 | { | |
1042 | /* Ignore warnings */ | |
1043 | } | |
1044 | ||
1045 | static int backtrace_stack(void *data, char *name) | |
1046 | { | |
1047 | /* Don't bother with IRQ stacks for now */ | |
1048 | return -1; | |
1049 | } | |
1050 | ||
1051 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
1052 | { | |
1053 | struct perf_callchain_entry *entry = data; | |
1054 | ||
1055 | if (reliable) | |
1056 | callchain_store(entry, addr); | |
1057 | } | |
1058 | ||
1059 | static const struct stacktrace_ops backtrace_ops = { | |
1060 | .warning = backtrace_warning, | |
1061 | .warning_symbol = backtrace_warning_symbol, | |
1062 | .stack = backtrace_stack, | |
1063 | .address = backtrace_address, | |
1064 | }; | |
1065 | ||
1066 | static void | |
1067 | perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1068 | { | |
1069 | unsigned long bp; | |
1070 | char *stack; | |
5872bdb8 | 1071 | int nr = entry->nr; |
d7d59fb3 PZ |
1072 | |
1073 | callchain_store(entry, instruction_pointer(regs)); | |
1074 | ||
1075 | stack = ((char *)regs + sizeof(struct pt_regs)); | |
1076 | #ifdef CONFIG_FRAME_POINTER | |
1077 | bp = frame_pointer(regs); | |
1078 | #else | |
1079 | bp = 0; | |
1080 | #endif | |
1081 | ||
1082 | dump_trace(NULL, regs, (void *)stack, bp, &backtrace_ops, entry); | |
5872bdb8 PZ |
1083 | |
1084 | entry->kernel = entry->nr - nr; | |
d7d59fb3 PZ |
1085 | } |
1086 | ||
1087 | ||
1088 | struct stack_frame { | |
1089 | const void __user *next_fp; | |
1090 | unsigned long return_address; | |
1091 | }; | |
1092 | ||
1093 | static int copy_stack_frame(const void __user *fp, struct stack_frame *frame) | |
1094 | { | |
1095 | int ret; | |
1096 | ||
1097 | if (!access_ok(VERIFY_READ, fp, sizeof(*frame))) | |
1098 | return 0; | |
1099 | ||
1100 | ret = 1; | |
1101 | pagefault_disable(); | |
1102 | if (__copy_from_user_inatomic(frame, fp, sizeof(*frame))) | |
1103 | ret = 0; | |
1104 | pagefault_enable(); | |
1105 | ||
1106 | return ret; | |
1107 | } | |
1108 | ||
1109 | static void | |
1110 | perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1111 | { | |
1112 | struct stack_frame frame; | |
1113 | const void __user *fp; | |
5872bdb8 | 1114 | int nr = entry->nr; |
d7d59fb3 PZ |
1115 | |
1116 | regs = (struct pt_regs *)current->thread.sp0 - 1; | |
1117 | fp = (void __user *)regs->bp; | |
1118 | ||
1119 | callchain_store(entry, regs->ip); | |
1120 | ||
1121 | while (entry->nr < MAX_STACK_DEPTH) { | |
1122 | frame.next_fp = NULL; | |
1123 | frame.return_address = 0; | |
1124 | ||
1125 | if (!copy_stack_frame(fp, &frame)) | |
1126 | break; | |
1127 | ||
1128 | if ((unsigned long)fp < user_stack_pointer(regs)) | |
1129 | break; | |
1130 | ||
1131 | callchain_store(entry, frame.return_address); | |
1132 | fp = frame.next_fp; | |
1133 | } | |
5872bdb8 PZ |
1134 | |
1135 | entry->user = entry->nr - nr; | |
d7d59fb3 PZ |
1136 | } |
1137 | ||
1138 | static void | |
1139 | perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1140 | { | |
1141 | int is_user; | |
1142 | ||
1143 | if (!regs) | |
1144 | return; | |
1145 | ||
1146 | is_user = user_mode(regs); | |
1147 | ||
1148 | if (!current || current->pid == 0) | |
1149 | return; | |
1150 | ||
1151 | if (is_user && current->state != TASK_RUNNING) | |
1152 | return; | |
1153 | ||
1154 | if (!is_user) | |
1155 | perf_callchain_kernel(regs, entry); | |
1156 | ||
1157 | if (current->mm) | |
1158 | perf_callchain_user(regs, entry); | |
1159 | } | |
1160 | ||
1161 | struct perf_callchain_entry *perf_callchain(struct pt_regs *regs) | |
1162 | { | |
1163 | struct perf_callchain_entry *entry; | |
1164 | ||
1165 | if (in_nmi()) | |
1166 | entry = &__get_cpu_var(nmi_entry); | |
1167 | else | |
1168 | entry = &__get_cpu_var(irq_entry); | |
1169 | ||
1170 | entry->nr = 0; | |
5872bdb8 PZ |
1171 | entry->hv = 0; |
1172 | entry->kernel = 0; | |
1173 | entry->user = 0; | |
d7d59fb3 PZ |
1174 | |
1175 | perf_do_callchain(regs, entry); | |
1176 | ||
1177 | return entry; | |
1178 | } |