Commit | Line | Data |
---|---|---|
241771ef IM |
1 | /* |
2 | * Performance counter x86 architecture code | |
3 | * | |
4 | * Copyright(C) 2008 Thomas Gleixner <tglx@linutronix.de> | |
5 | * Copyright(C) 2008 Red Hat, Inc., Ingo Molnar | |
b56a3802 | 6 | * Copyright(C) 2009 Jaswinder Singh Rajput |
39d81eab | 7 | * Copyright(C) 2009 Advanced Micro Devices, Inc., Robert Richter |
241771ef IM |
8 | * |
9 | * For licencing details see kernel-base/COPYING | |
10 | */ | |
11 | ||
12 | #include <linux/perf_counter.h> | |
13 | #include <linux/capability.h> | |
14 | #include <linux/notifier.h> | |
15 | #include <linux/hardirq.h> | |
16 | #include <linux/kprobes.h> | |
4ac13294 | 17 | #include <linux/module.h> |
241771ef IM |
18 | #include <linux/kdebug.h> |
19 | #include <linux/sched.h> | |
d7d59fb3 | 20 | #include <linux/uaccess.h> |
241771ef | 21 | |
241771ef | 22 | #include <asm/apic.h> |
d7d59fb3 | 23 | #include <asm/stacktrace.h> |
4e935e47 | 24 | #include <asm/nmi.h> |
241771ef IM |
25 | |
26 | static bool perf_counters_initialized __read_mostly; | |
27 | ||
28 | /* | |
29 | * Number of (generic) HW counters: | |
30 | */ | |
862a1a5f IM |
31 | static int nr_counters_generic __read_mostly; |
32 | static u64 perf_counter_mask __read_mostly; | |
2f18d1e8 | 33 | static u64 counter_value_mask __read_mostly; |
b0f3f28e | 34 | static int counter_value_bits __read_mostly; |
241771ef | 35 | |
862a1a5f | 36 | static int nr_counters_fixed __read_mostly; |
703e937c | 37 | |
241771ef | 38 | struct cpu_hw_counters { |
862a1a5f IM |
39 | struct perf_counter *counters[X86_PMC_IDX_MAX]; |
40 | unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
4b39fd96 | 41 | unsigned long interrupts; |
b0f3f28e | 42 | u64 throttle_ctrl; |
184fe4ab | 43 | unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
b0f3f28e | 44 | int enabled; |
241771ef IM |
45 | }; |
46 | ||
47 | /* | |
5f4ec28f | 48 | * struct x86_pmu - generic x86 pmu |
241771ef | 49 | */ |
5f4ec28f | 50 | struct x86_pmu { |
39d81eab | 51 | int (*handle_irq)(struct pt_regs *, int); |
169e41eb | 52 | u64 (*save_disable_all)(void); |
b0f3f28e PZ |
53 | void (*restore_all)(u64); |
54 | u64 (*get_status)(u64); | |
55 | void (*ack_status)(u64); | |
56 | void (*enable)(int, u64); | |
57 | void (*disable)(int, u64); | |
169e41eb JSR |
58 | unsigned eventsel; |
59 | unsigned perfctr; | |
b0f3f28e PZ |
60 | u64 (*event_map)(int); |
61 | u64 (*raw_event)(u64); | |
169e41eb | 62 | int max_events; |
b56a3802 JSR |
63 | }; |
64 | ||
5f4ec28f | 65 | static struct x86_pmu *x86_pmu __read_mostly; |
b56a3802 | 66 | |
b0f3f28e PZ |
67 | static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters) = { |
68 | .enabled = 1, | |
69 | }; | |
241771ef | 70 | |
7bb497bd IM |
71 | static __read_mostly int intel_perfmon_version; |
72 | ||
b56a3802 JSR |
73 | /* |
74 | * Intel PerfMon v3. Used on Core2 and later. | |
75 | */ | |
b0f3f28e | 76 | static const u64 intel_perfmon_event_map[] = |
241771ef | 77 | { |
f650a672 | 78 | [PERF_COUNT_CPU_CYCLES] = 0x003c, |
241771ef IM |
79 | [PERF_COUNT_INSTRUCTIONS] = 0x00c0, |
80 | [PERF_COUNT_CACHE_REFERENCES] = 0x4f2e, | |
81 | [PERF_COUNT_CACHE_MISSES] = 0x412e, | |
82 | [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4, | |
83 | [PERF_COUNT_BRANCH_MISSES] = 0x00c5, | |
f650a672 | 84 | [PERF_COUNT_BUS_CYCLES] = 0x013c, |
241771ef IM |
85 | }; |
86 | ||
5f4ec28f | 87 | static u64 intel_pmu_event_map(int event) |
b56a3802 JSR |
88 | { |
89 | return intel_perfmon_event_map[event]; | |
90 | } | |
241771ef | 91 | |
5f4ec28f | 92 | static u64 intel_pmu_raw_event(u64 event) |
b0f3f28e | 93 | { |
82bae4f8 PZ |
94 | #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL |
95 | #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL | |
96 | #define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL | |
b0f3f28e PZ |
97 | |
98 | #define CORE_EVNTSEL_MASK \ | |
99 | (CORE_EVNTSEL_EVENT_MASK | \ | |
100 | CORE_EVNTSEL_UNIT_MASK | \ | |
101 | CORE_EVNTSEL_COUNTER_MASK) | |
102 | ||
103 | return event & CORE_EVNTSEL_MASK; | |
104 | } | |
105 | ||
f87ad35d JSR |
106 | /* |
107 | * AMD Performance Monitor K7 and later. | |
108 | */ | |
b0f3f28e | 109 | static const u64 amd_perfmon_event_map[] = |
f87ad35d JSR |
110 | { |
111 | [PERF_COUNT_CPU_CYCLES] = 0x0076, | |
112 | [PERF_COUNT_INSTRUCTIONS] = 0x00c0, | |
113 | [PERF_COUNT_CACHE_REFERENCES] = 0x0080, | |
114 | [PERF_COUNT_CACHE_MISSES] = 0x0081, | |
115 | [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4, | |
116 | [PERF_COUNT_BRANCH_MISSES] = 0x00c5, | |
117 | }; | |
118 | ||
5f4ec28f | 119 | static u64 amd_pmu_event_map(int event) |
f87ad35d JSR |
120 | { |
121 | return amd_perfmon_event_map[event]; | |
122 | } | |
123 | ||
5f4ec28f | 124 | static u64 amd_pmu_raw_event(u64 event) |
b0f3f28e | 125 | { |
82bae4f8 PZ |
126 | #define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL |
127 | #define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL | |
128 | #define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL | |
b0f3f28e PZ |
129 | |
130 | #define K7_EVNTSEL_MASK \ | |
131 | (K7_EVNTSEL_EVENT_MASK | \ | |
132 | K7_EVNTSEL_UNIT_MASK | \ | |
133 | K7_EVNTSEL_COUNTER_MASK) | |
134 | ||
135 | return event & K7_EVNTSEL_MASK; | |
136 | } | |
137 | ||
ee06094f IM |
138 | /* |
139 | * Propagate counter elapsed time into the generic counter. | |
140 | * Can only be executed on the CPU where the counter is active. | |
141 | * Returns the delta events processed. | |
142 | */ | |
143 | static void | |
144 | x86_perf_counter_update(struct perf_counter *counter, | |
145 | struct hw_perf_counter *hwc, int idx) | |
146 | { | |
147 | u64 prev_raw_count, new_raw_count, delta; | |
148 | ||
ee06094f IM |
149 | /* |
150 | * Careful: an NMI might modify the previous counter value. | |
151 | * | |
152 | * Our tactic to handle this is to first atomically read and | |
153 | * exchange a new raw count - then add that new-prev delta | |
154 | * count to the generic counter atomically: | |
155 | */ | |
156 | again: | |
157 | prev_raw_count = atomic64_read(&hwc->prev_count); | |
158 | rdmsrl(hwc->counter_base + idx, new_raw_count); | |
159 | ||
160 | if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count, | |
161 | new_raw_count) != prev_raw_count) | |
162 | goto again; | |
163 | ||
164 | /* | |
165 | * Now we have the new raw value and have updated the prev | |
166 | * timestamp already. We can now calculate the elapsed delta | |
167 | * (counter-)time and add that to the generic counter. | |
168 | * | |
169 | * Careful, not all hw sign-extends above the physical width | |
170 | * of the count, so we do that by clipping the delta to 32 bits: | |
171 | */ | |
172 | delta = (u64)(u32)((s32)new_raw_count - (s32)prev_raw_count); | |
ee06094f IM |
173 | |
174 | atomic64_add(delta, &counter->count); | |
175 | atomic64_sub(delta, &hwc->period_left); | |
176 | } | |
177 | ||
4e935e47 PZ |
178 | static atomic_t num_counters; |
179 | static DEFINE_MUTEX(pmc_reserve_mutex); | |
180 | ||
181 | static bool reserve_pmc_hardware(void) | |
182 | { | |
183 | int i; | |
184 | ||
185 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
186 | disable_lapic_nmi_watchdog(); | |
187 | ||
188 | for (i = 0; i < nr_counters_generic; i++) { | |
5f4ec28f | 189 | if (!reserve_perfctr_nmi(x86_pmu->perfctr + i)) |
4e935e47 PZ |
190 | goto perfctr_fail; |
191 | } | |
192 | ||
193 | for (i = 0; i < nr_counters_generic; i++) { | |
5f4ec28f | 194 | if (!reserve_evntsel_nmi(x86_pmu->eventsel + i)) |
4e935e47 PZ |
195 | goto eventsel_fail; |
196 | } | |
197 | ||
198 | return true; | |
199 | ||
200 | eventsel_fail: | |
201 | for (i--; i >= 0; i--) | |
5f4ec28f | 202 | release_evntsel_nmi(x86_pmu->eventsel + i); |
4e935e47 PZ |
203 | |
204 | i = nr_counters_generic; | |
205 | ||
206 | perfctr_fail: | |
207 | for (i--; i >= 0; i--) | |
5f4ec28f | 208 | release_perfctr_nmi(x86_pmu->perfctr + i); |
4e935e47 PZ |
209 | |
210 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
211 | enable_lapic_nmi_watchdog(); | |
212 | ||
213 | return false; | |
214 | } | |
215 | ||
216 | static void release_pmc_hardware(void) | |
217 | { | |
218 | int i; | |
219 | ||
220 | for (i = 0; i < nr_counters_generic; i++) { | |
5f4ec28f RR |
221 | release_perfctr_nmi(x86_pmu->perfctr + i); |
222 | release_evntsel_nmi(x86_pmu->eventsel + i); | |
4e935e47 PZ |
223 | } |
224 | ||
225 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
226 | enable_lapic_nmi_watchdog(); | |
227 | } | |
228 | ||
229 | static void hw_perf_counter_destroy(struct perf_counter *counter) | |
230 | { | |
231 | if (atomic_dec_and_mutex_lock(&num_counters, &pmc_reserve_mutex)) { | |
232 | release_pmc_hardware(); | |
233 | mutex_unlock(&pmc_reserve_mutex); | |
234 | } | |
235 | } | |
236 | ||
241771ef IM |
237 | /* |
238 | * Setup the hardware configuration for a given hw_event_type | |
239 | */ | |
621a01ea | 240 | static int __hw_perf_counter_init(struct perf_counter *counter) |
241771ef | 241 | { |
9f66a381 | 242 | struct perf_counter_hw_event *hw_event = &counter->hw_event; |
241771ef | 243 | struct hw_perf_counter *hwc = &counter->hw; |
4e935e47 | 244 | int err; |
241771ef | 245 | |
39d81eab RR |
246 | /* disable temporarily */ |
247 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
248 | return -ENOSYS; | |
249 | ||
241771ef IM |
250 | if (unlikely(!perf_counters_initialized)) |
251 | return -EINVAL; | |
252 | ||
4e935e47 PZ |
253 | err = 0; |
254 | if (atomic_inc_not_zero(&num_counters)) { | |
255 | mutex_lock(&pmc_reserve_mutex); | |
256 | if (atomic_read(&num_counters) == 0 && !reserve_pmc_hardware()) | |
257 | err = -EBUSY; | |
258 | else | |
259 | atomic_inc(&num_counters); | |
260 | mutex_unlock(&pmc_reserve_mutex); | |
261 | } | |
262 | if (err) | |
263 | return err; | |
264 | ||
241771ef | 265 | /* |
0475f9ea | 266 | * Generate PMC IRQs: |
241771ef IM |
267 | * (keep 'enabled' bit clear for now) |
268 | */ | |
0475f9ea | 269 | hwc->config = ARCH_PERFMON_EVENTSEL_INT; |
241771ef IM |
270 | |
271 | /* | |
0475f9ea | 272 | * Count user and OS events unless requested not to. |
241771ef | 273 | */ |
0475f9ea PM |
274 | if (!hw_event->exclude_user) |
275 | hwc->config |= ARCH_PERFMON_EVENTSEL_USR; | |
276 | if (!hw_event->exclude_kernel) | |
241771ef | 277 | hwc->config |= ARCH_PERFMON_EVENTSEL_OS; |
0475f9ea PM |
278 | |
279 | /* | |
280 | * If privileged enough, allow NMI events: | |
281 | */ | |
282 | hwc->nmi = 0; | |
283 | if (capable(CAP_SYS_ADMIN) && hw_event->nmi) | |
284 | hwc->nmi = 1; | |
241771ef | 285 | |
9f66a381 | 286 | hwc->irq_period = hw_event->irq_period; |
241771ef IM |
287 | /* |
288 | * Intel PMCs cannot be accessed sanely above 32 bit width, | |
289 | * so we install an artificial 1<<31 period regardless of | |
290 | * the generic counter period: | |
291 | */ | |
f87ad35d JSR |
292 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
293 | if ((s64)hwc->irq_period <= 0 || hwc->irq_period > 0x7FFFFFFF) | |
294 | hwc->irq_period = 0x7FFFFFFF; | |
241771ef | 295 | |
ee06094f | 296 | atomic64_set(&hwc->period_left, hwc->irq_period); |
241771ef IM |
297 | |
298 | /* | |
dfa7c899 | 299 | * Raw event type provide the config in the event structure |
241771ef | 300 | */ |
f4a2deb4 | 301 | if (perf_event_raw(hw_event)) { |
5f4ec28f | 302 | hwc->config |= x86_pmu->raw_event(perf_event_config(hw_event)); |
241771ef | 303 | } else { |
5f4ec28f | 304 | if (perf_event_id(hw_event) >= x86_pmu->max_events) |
241771ef IM |
305 | return -EINVAL; |
306 | /* | |
307 | * The generic map: | |
308 | */ | |
5f4ec28f | 309 | hwc->config |= x86_pmu->event_map(perf_event_id(hw_event)); |
241771ef | 310 | } |
241771ef | 311 | |
4e935e47 PZ |
312 | counter->destroy = hw_perf_counter_destroy; |
313 | ||
241771ef IM |
314 | return 0; |
315 | } | |
316 | ||
5f4ec28f | 317 | static u64 intel_pmu_save_disable_all(void) |
4ac13294 TG |
318 | { |
319 | u64 ctrl; | |
320 | ||
321 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); | |
862a1a5f | 322 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); |
2b9ff0db | 323 | |
4ac13294 | 324 | return ctrl; |
241771ef | 325 | } |
b56a3802 | 326 | |
5f4ec28f | 327 | static u64 amd_pmu_save_disable_all(void) |
f87ad35d | 328 | { |
b0f3f28e PZ |
329 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
330 | int enabled, idx; | |
331 | ||
332 | enabled = cpuc->enabled; | |
333 | cpuc->enabled = 0; | |
60b3df9c PZ |
334 | /* |
335 | * ensure we write the disable before we start disabling the | |
5f4ec28f RR |
336 | * counters proper, so that amd_pmu_enable_counter() does the |
337 | * right thing. | |
60b3df9c | 338 | */ |
b0f3f28e | 339 | barrier(); |
f87ad35d JSR |
340 | |
341 | for (idx = 0; idx < nr_counters_generic; idx++) { | |
b0f3f28e PZ |
342 | u64 val; |
343 | ||
4295ee62 RR |
344 | if (!test_bit(idx, cpuc->active_mask)) |
345 | continue; | |
f87ad35d | 346 | rdmsrl(MSR_K7_EVNTSEL0 + idx, val); |
4295ee62 RR |
347 | if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE)) |
348 | continue; | |
349 | val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE; | |
350 | wrmsrl(MSR_K7_EVNTSEL0 + idx, val); | |
f87ad35d JSR |
351 | } |
352 | ||
b0f3f28e | 353 | return enabled; |
f87ad35d JSR |
354 | } |
355 | ||
b56a3802 JSR |
356 | u64 hw_perf_save_disable(void) |
357 | { | |
358 | if (unlikely(!perf_counters_initialized)) | |
359 | return 0; | |
360 | ||
5f4ec28f | 361 | return x86_pmu->save_disable_all(); |
b56a3802 | 362 | } |
b0f3f28e PZ |
363 | /* |
364 | * Exported because of ACPI idle | |
365 | */ | |
01b2838c | 366 | EXPORT_SYMBOL_GPL(hw_perf_save_disable); |
241771ef | 367 | |
5f4ec28f | 368 | static void intel_pmu_restore_all(u64 ctrl) |
b56a3802 JSR |
369 | { |
370 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); | |
371 | } | |
372 | ||
5f4ec28f | 373 | static void amd_pmu_restore_all(u64 ctrl) |
f87ad35d | 374 | { |
b0f3f28e | 375 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
f87ad35d JSR |
376 | int idx; |
377 | ||
b0f3f28e PZ |
378 | cpuc->enabled = ctrl; |
379 | barrier(); | |
380 | if (!ctrl) | |
381 | return; | |
382 | ||
f87ad35d | 383 | for (idx = 0; idx < nr_counters_generic; idx++) { |
4295ee62 | 384 | u64 val; |
b0f3f28e | 385 | |
4295ee62 RR |
386 | if (!test_bit(idx, cpuc->active_mask)) |
387 | continue; | |
388 | rdmsrl(MSR_K7_EVNTSEL0 + idx, val); | |
389 | if (val & ARCH_PERFMON_EVENTSEL0_ENABLE) | |
390 | continue; | |
391 | val |= ARCH_PERFMON_EVENTSEL0_ENABLE; | |
392 | wrmsrl(MSR_K7_EVNTSEL0 + idx, val); | |
f87ad35d JSR |
393 | } |
394 | } | |
395 | ||
ee06094f IM |
396 | void hw_perf_restore(u64 ctrl) |
397 | { | |
2b9ff0db IM |
398 | if (unlikely(!perf_counters_initialized)) |
399 | return; | |
400 | ||
5f4ec28f | 401 | x86_pmu->restore_all(ctrl); |
ee06094f | 402 | } |
b0f3f28e PZ |
403 | /* |
404 | * Exported because of ACPI idle | |
405 | */ | |
ee06094f IM |
406 | EXPORT_SYMBOL_GPL(hw_perf_restore); |
407 | ||
5f4ec28f | 408 | static u64 intel_pmu_get_status(u64 mask) |
b0f3f28e PZ |
409 | { |
410 | u64 status; | |
411 | ||
412 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
413 | ||
414 | return status; | |
415 | } | |
416 | ||
5f4ec28f | 417 | static u64 amd_pmu_get_status(u64 mask) |
b0f3f28e PZ |
418 | { |
419 | u64 status = 0; | |
420 | int idx; | |
421 | ||
422 | for (idx = 0; idx < nr_counters_generic; idx++) { | |
423 | s64 val; | |
424 | ||
425 | if (!(mask & (1 << idx))) | |
426 | continue; | |
427 | ||
428 | rdmsrl(MSR_K7_PERFCTR0 + idx, val); | |
429 | val <<= (64 - counter_value_bits); | |
430 | if (val >= 0) | |
431 | status |= (1 << idx); | |
432 | } | |
433 | ||
434 | return status; | |
435 | } | |
436 | ||
437 | static u64 hw_perf_get_status(u64 mask) | |
438 | { | |
439 | if (unlikely(!perf_counters_initialized)) | |
440 | return 0; | |
441 | ||
5f4ec28f | 442 | return x86_pmu->get_status(mask); |
b0f3f28e PZ |
443 | } |
444 | ||
5f4ec28f | 445 | static void intel_pmu_ack_status(u64 ack) |
b0f3f28e PZ |
446 | { |
447 | wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); | |
448 | } | |
449 | ||
5f4ec28f | 450 | static void amd_pmu_ack_status(u64 ack) |
b0f3f28e PZ |
451 | { |
452 | } | |
453 | ||
454 | static void hw_perf_ack_status(u64 ack) | |
455 | { | |
456 | if (unlikely(!perf_counters_initialized)) | |
457 | return; | |
458 | ||
5f4ec28f | 459 | x86_pmu->ack_status(ack); |
b0f3f28e PZ |
460 | } |
461 | ||
5f4ec28f | 462 | static void intel_pmu_enable_counter(int idx, u64 config) |
b0f3f28e PZ |
463 | { |
464 | wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + idx, | |
465 | config | ARCH_PERFMON_EVENTSEL0_ENABLE); | |
466 | } | |
467 | ||
5f4ec28f | 468 | static void amd_pmu_enable_counter(int idx, u64 config) |
b0f3f28e PZ |
469 | { |
470 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
471 | ||
184fe4ab | 472 | set_bit(idx, cpuc->active_mask); |
b0f3f28e PZ |
473 | if (cpuc->enabled) |
474 | config |= ARCH_PERFMON_EVENTSEL0_ENABLE; | |
475 | ||
476 | wrmsrl(MSR_K7_EVNTSEL0 + idx, config); | |
477 | } | |
478 | ||
479 | static void hw_perf_enable(int idx, u64 config) | |
480 | { | |
481 | if (unlikely(!perf_counters_initialized)) | |
482 | return; | |
483 | ||
5f4ec28f | 484 | x86_pmu->enable(idx, config); |
b0f3f28e PZ |
485 | } |
486 | ||
5f4ec28f | 487 | static void intel_pmu_disable_counter(int idx, u64 config) |
b0f3f28e PZ |
488 | { |
489 | wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + idx, config); | |
490 | } | |
491 | ||
5f4ec28f | 492 | static void amd_pmu_disable_counter(int idx, u64 config) |
b0f3f28e PZ |
493 | { |
494 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
495 | ||
184fe4ab | 496 | clear_bit(idx, cpuc->active_mask); |
b0f3f28e PZ |
497 | wrmsrl(MSR_K7_EVNTSEL0 + idx, config); |
498 | ||
499 | } | |
500 | ||
501 | static void hw_perf_disable(int idx, u64 config) | |
502 | { | |
503 | if (unlikely(!perf_counters_initialized)) | |
504 | return; | |
505 | ||
5f4ec28f | 506 | x86_pmu->disable(idx, config); |
b0f3f28e PZ |
507 | } |
508 | ||
2f18d1e8 IM |
509 | static inline void |
510 | __pmc_fixed_disable(struct perf_counter *counter, | |
511 | struct hw_perf_counter *hwc, unsigned int __idx) | |
512 | { | |
513 | int idx = __idx - X86_PMC_IDX_FIXED; | |
514 | u64 ctrl_val, mask; | |
515 | int err; | |
516 | ||
517 | mask = 0xfULL << (idx * 4); | |
518 | ||
519 | rdmsrl(hwc->config_base, ctrl_val); | |
520 | ctrl_val &= ~mask; | |
521 | err = checking_wrmsrl(hwc->config_base, ctrl_val); | |
522 | } | |
523 | ||
7e2ae347 | 524 | static inline void |
4aeb0b42 RR |
525 | __x86_pmu_disable(struct perf_counter *counter, |
526 | struct hw_perf_counter *hwc, unsigned int idx) | |
7e2ae347 | 527 | { |
2f18d1e8 | 528 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) |
2b583d8b JSR |
529 | __pmc_fixed_disable(counter, hwc, idx); |
530 | else | |
b0f3f28e | 531 | hw_perf_disable(idx, hwc->config); |
7e2ae347 IM |
532 | } |
533 | ||
2f18d1e8 | 534 | static DEFINE_PER_CPU(u64, prev_left[X86_PMC_IDX_MAX]); |
241771ef | 535 | |
ee06094f IM |
536 | /* |
537 | * Set the next IRQ period, based on the hwc->period_left value. | |
538 | * To be called with the counter disabled in hw: | |
539 | */ | |
540 | static void | |
541 | __hw_perf_counter_set_period(struct perf_counter *counter, | |
542 | struct hw_perf_counter *hwc, int idx) | |
241771ef | 543 | { |
2f18d1e8 | 544 | s64 left = atomic64_read(&hwc->period_left); |
595258aa | 545 | s64 period = hwc->irq_period; |
2f18d1e8 | 546 | int err; |
ee06094f | 547 | |
ee06094f IM |
548 | /* |
549 | * If we are way outside a reasoable range then just skip forward: | |
550 | */ | |
551 | if (unlikely(left <= -period)) { | |
552 | left = period; | |
553 | atomic64_set(&hwc->period_left, left); | |
554 | } | |
555 | ||
556 | if (unlikely(left <= 0)) { | |
557 | left += period; | |
558 | atomic64_set(&hwc->period_left, left); | |
559 | } | |
241771ef | 560 | |
ee06094f IM |
561 | per_cpu(prev_left[idx], smp_processor_id()) = left; |
562 | ||
563 | /* | |
564 | * The hw counter starts counting from this counter offset, | |
565 | * mark it to be able to extra future deltas: | |
566 | */ | |
2f18d1e8 | 567 | atomic64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 568 | |
2f18d1e8 IM |
569 | err = checking_wrmsrl(hwc->counter_base + idx, |
570 | (u64)(-left) & counter_value_mask); | |
571 | } | |
572 | ||
573 | static inline void | |
574 | __pmc_fixed_enable(struct perf_counter *counter, | |
575 | struct hw_perf_counter *hwc, unsigned int __idx) | |
576 | { | |
577 | int idx = __idx - X86_PMC_IDX_FIXED; | |
578 | u64 ctrl_val, bits, mask; | |
579 | int err; | |
580 | ||
581 | /* | |
0475f9ea PM |
582 | * Enable IRQ generation (0x8), |
583 | * and enable ring-3 counting (0x2) and ring-0 counting (0x1) | |
584 | * if requested: | |
2f18d1e8 | 585 | */ |
0475f9ea PM |
586 | bits = 0x8ULL; |
587 | if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) | |
588 | bits |= 0x2; | |
2f18d1e8 IM |
589 | if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) |
590 | bits |= 0x1; | |
591 | bits <<= (idx * 4); | |
592 | mask = 0xfULL << (idx * 4); | |
593 | ||
594 | rdmsrl(hwc->config_base, ctrl_val); | |
595 | ctrl_val &= ~mask; | |
596 | ctrl_val |= bits; | |
597 | err = checking_wrmsrl(hwc->config_base, ctrl_val); | |
7e2ae347 IM |
598 | } |
599 | ||
ee06094f | 600 | static void |
4aeb0b42 RR |
601 | __x86_pmu_enable(struct perf_counter *counter, |
602 | struct hw_perf_counter *hwc, int idx) | |
7e2ae347 | 603 | { |
2f18d1e8 | 604 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) |
2b583d8b JSR |
605 | __pmc_fixed_enable(counter, hwc, idx); |
606 | else | |
b0f3f28e | 607 | hw_perf_enable(idx, hwc->config); |
241771ef IM |
608 | } |
609 | ||
2f18d1e8 IM |
610 | static int |
611 | fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc) | |
862a1a5f | 612 | { |
2f18d1e8 IM |
613 | unsigned int event; |
614 | ||
f87ad35d JSR |
615 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) |
616 | return -1; | |
617 | ||
2f18d1e8 IM |
618 | if (unlikely(hwc->nmi)) |
619 | return -1; | |
620 | ||
621 | event = hwc->config & ARCH_PERFMON_EVENT_MASK; | |
622 | ||
5f4ec28f | 623 | if (unlikely(event == x86_pmu->event_map(PERF_COUNT_INSTRUCTIONS))) |
2f18d1e8 | 624 | return X86_PMC_IDX_FIXED_INSTRUCTIONS; |
5f4ec28f | 625 | if (unlikely(event == x86_pmu->event_map(PERF_COUNT_CPU_CYCLES))) |
2f18d1e8 | 626 | return X86_PMC_IDX_FIXED_CPU_CYCLES; |
5f4ec28f | 627 | if (unlikely(event == x86_pmu->event_map(PERF_COUNT_BUS_CYCLES))) |
2f18d1e8 IM |
628 | return X86_PMC_IDX_FIXED_BUS_CYCLES; |
629 | ||
862a1a5f IM |
630 | return -1; |
631 | } | |
632 | ||
ee06094f IM |
633 | /* |
634 | * Find a PMC slot for the freshly enabled / scheduled in counter: | |
635 | */ | |
4aeb0b42 | 636 | static int x86_pmu_enable(struct perf_counter *counter) |
241771ef IM |
637 | { |
638 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
639 | struct hw_perf_counter *hwc = &counter->hw; | |
2f18d1e8 | 640 | int idx; |
241771ef | 641 | |
2f18d1e8 IM |
642 | idx = fixed_mode_idx(counter, hwc); |
643 | if (idx >= 0) { | |
644 | /* | |
645 | * Try to get the fixed counter, if that is already taken | |
646 | * then try to get a generic counter: | |
647 | */ | |
648 | if (test_and_set_bit(idx, cpuc->used)) | |
649 | goto try_generic; | |
0dff86aa | 650 | |
2f18d1e8 IM |
651 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
652 | /* | |
653 | * We set it so that counter_base + idx in wrmsr/rdmsr maps to | |
654 | * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2: | |
655 | */ | |
656 | hwc->counter_base = | |
657 | MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED; | |
241771ef | 658 | hwc->idx = idx; |
2f18d1e8 IM |
659 | } else { |
660 | idx = hwc->idx; | |
661 | /* Try to get the previous generic counter again */ | |
662 | if (test_and_set_bit(idx, cpuc->used)) { | |
663 | try_generic: | |
664 | idx = find_first_zero_bit(cpuc->used, nr_counters_generic); | |
665 | if (idx == nr_counters_generic) | |
666 | return -EAGAIN; | |
667 | ||
668 | set_bit(idx, cpuc->used); | |
669 | hwc->idx = idx; | |
670 | } | |
5f4ec28f RR |
671 | hwc->config_base = x86_pmu->eventsel; |
672 | hwc->counter_base = x86_pmu->perfctr; | |
241771ef IM |
673 | } |
674 | ||
675 | perf_counters_lapic_init(hwc->nmi); | |
676 | ||
4aeb0b42 | 677 | __x86_pmu_disable(counter, hwc, idx); |
241771ef | 678 | |
862a1a5f | 679 | cpuc->counters[idx] = counter; |
2f18d1e8 IM |
680 | /* |
681 | * Make it visible before enabling the hw: | |
682 | */ | |
527e26af | 683 | barrier(); |
7e2ae347 | 684 | |
ee06094f | 685 | __hw_perf_counter_set_period(counter, hwc, idx); |
4aeb0b42 | 686 | __x86_pmu_enable(counter, hwc, idx); |
95cdd2e7 IM |
687 | |
688 | return 0; | |
241771ef IM |
689 | } |
690 | ||
691 | void perf_counter_print_debug(void) | |
692 | { | |
2f18d1e8 | 693 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
0dff86aa | 694 | struct cpu_hw_counters *cpuc; |
1e125676 IM |
695 | int cpu, idx; |
696 | ||
862a1a5f | 697 | if (!nr_counters_generic) |
1e125676 | 698 | return; |
241771ef IM |
699 | |
700 | local_irq_disable(); | |
701 | ||
702 | cpu = smp_processor_id(); | |
0dff86aa | 703 | cpuc = &per_cpu(cpu_hw_counters, cpu); |
241771ef | 704 | |
7bb497bd | 705 | if (intel_perfmon_version >= 2) { |
a1ef58f4 JSR |
706 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
707 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
708 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
709 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
710 | ||
711 | pr_info("\n"); | |
712 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
713 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
714 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
715 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
f87ad35d | 716 | } |
a1ef58f4 | 717 | pr_info("CPU#%d: used: %016llx\n", cpu, *(u64 *)cpuc->used); |
241771ef | 718 | |
862a1a5f | 719 | for (idx = 0; idx < nr_counters_generic; idx++) { |
5f4ec28f RR |
720 | rdmsrl(x86_pmu->eventsel + idx, pmc_ctrl); |
721 | rdmsrl(x86_pmu->perfctr + idx, pmc_count); | |
241771ef | 722 | |
ee06094f | 723 | prev_left = per_cpu(prev_left[idx], cpu); |
241771ef | 724 | |
a1ef58f4 | 725 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 726 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 727 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 728 | cpu, idx, pmc_count); |
a1ef58f4 | 729 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 730 | cpu, idx, prev_left); |
241771ef | 731 | } |
2f18d1e8 IM |
732 | for (idx = 0; idx < nr_counters_fixed; idx++) { |
733 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); | |
734 | ||
a1ef58f4 | 735 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
736 | cpu, idx, pmc_count); |
737 | } | |
241771ef IM |
738 | local_irq_enable(); |
739 | } | |
740 | ||
4aeb0b42 | 741 | static void x86_pmu_disable(struct perf_counter *counter) |
241771ef IM |
742 | { |
743 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
744 | struct hw_perf_counter *hwc = &counter->hw; | |
745 | unsigned int idx = hwc->idx; | |
746 | ||
4aeb0b42 | 747 | __x86_pmu_disable(counter, hwc, idx); |
241771ef IM |
748 | |
749 | clear_bit(idx, cpuc->used); | |
862a1a5f | 750 | cpuc->counters[idx] = NULL; |
2f18d1e8 IM |
751 | /* |
752 | * Make sure the cleared pointer becomes visible before we | |
753 | * (potentially) free the counter: | |
754 | */ | |
527e26af | 755 | barrier(); |
241771ef | 756 | |
ee06094f IM |
757 | /* |
758 | * Drain the remaining delta count out of a counter | |
759 | * that we are disabling: | |
760 | */ | |
761 | x86_perf_counter_update(counter, hwc, idx); | |
241771ef IM |
762 | } |
763 | ||
7e2ae347 | 764 | /* |
ee06094f IM |
765 | * Save and restart an expired counter. Called by NMI contexts, |
766 | * so it has to be careful about preempting normal counter ops: | |
7e2ae347 | 767 | */ |
241771ef IM |
768 | static void perf_save_and_restart(struct perf_counter *counter) |
769 | { | |
770 | struct hw_perf_counter *hwc = &counter->hw; | |
771 | int idx = hwc->idx; | |
241771ef | 772 | |
ee06094f IM |
773 | x86_perf_counter_update(counter, hwc, idx); |
774 | __hw_perf_counter_set_period(counter, hwc, idx); | |
7e2ae347 | 775 | |
2f18d1e8 | 776 | if (counter->state == PERF_COUNTER_STATE_ACTIVE) |
4aeb0b42 | 777 | __x86_pmu_enable(counter, hwc, idx); |
241771ef IM |
778 | } |
779 | ||
4b39fd96 MG |
780 | /* |
781 | * Maximum interrupt frequency of 100KHz per CPU | |
782 | */ | |
169e41eb | 783 | #define PERFMON_MAX_INTERRUPTS (100000/HZ) |
4b39fd96 | 784 | |
241771ef IM |
785 | /* |
786 | * This handler is triggered by the local APIC, so the APIC IRQ handling | |
787 | * rules apply: | |
788 | */ | |
39d81eab | 789 | static int intel_pmu_handle_irq(struct pt_regs *regs, int nmi) |
241771ef IM |
790 | { |
791 | int bit, cpu = smp_processor_id(); | |
4b39fd96 | 792 | u64 ack, status; |
1b023a96 | 793 | struct cpu_hw_counters *cpuc = &per_cpu(cpu_hw_counters, cpu); |
b0f3f28e | 794 | int ret = 0; |
43874d23 | 795 | |
b0f3f28e | 796 | cpuc->throttle_ctrl = hw_perf_save_disable(); |
241771ef | 797 | |
b0f3f28e | 798 | status = hw_perf_get_status(cpuc->throttle_ctrl); |
87b9cf46 IM |
799 | if (!status) |
800 | goto out; | |
801 | ||
b0f3f28e | 802 | ret = 1; |
241771ef | 803 | again: |
d278c484 | 804 | inc_irq_stat(apic_perf_irqs); |
241771ef | 805 | ack = status; |
2f18d1e8 | 806 | for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { |
862a1a5f | 807 | struct perf_counter *counter = cpuc->counters[bit]; |
241771ef IM |
808 | |
809 | clear_bit(bit, (unsigned long *) &status); | |
810 | if (!counter) | |
811 | continue; | |
812 | ||
813 | perf_save_and_restart(counter); | |
78f13e95 | 814 | if (perf_counter_overflow(counter, nmi, regs, 0)) |
4aeb0b42 | 815 | __x86_pmu_disable(counter, &counter->hw, bit); |
241771ef IM |
816 | } |
817 | ||
b0f3f28e | 818 | hw_perf_ack_status(ack); |
241771ef IM |
819 | |
820 | /* | |
821 | * Repeat if there is more work to be done: | |
822 | */ | |
b0f3f28e | 823 | status = hw_perf_get_status(cpuc->throttle_ctrl); |
241771ef IM |
824 | if (status) |
825 | goto again; | |
87b9cf46 | 826 | out: |
241771ef | 827 | /* |
1b023a96 | 828 | * Restore - do not reenable when global enable is off or throttled: |
241771ef | 829 | */ |
4b39fd96 | 830 | if (++cpuc->interrupts < PERFMON_MAX_INTERRUPTS) |
b0f3f28e PZ |
831 | hw_perf_restore(cpuc->throttle_ctrl); |
832 | ||
833 | return ret; | |
1b023a96 MG |
834 | } |
835 | ||
39d81eab RR |
836 | static int amd_pmu_handle_irq(struct pt_regs *regs, int nmi) { return 0; } |
837 | ||
1b023a96 MG |
838 | void perf_counter_unthrottle(void) |
839 | { | |
840 | struct cpu_hw_counters *cpuc; | |
841 | ||
842 | if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) | |
843 | return; | |
844 | ||
845 | if (unlikely(!perf_counters_initialized)) | |
846 | return; | |
847 | ||
b0f3f28e | 848 | cpuc = &__get_cpu_var(cpu_hw_counters); |
4b39fd96 | 849 | if (cpuc->interrupts >= PERFMON_MAX_INTERRUPTS) { |
1b023a96 | 850 | if (printk_ratelimit()) |
4b39fd96 | 851 | printk(KERN_WARNING "PERFMON: max interrupts exceeded!\n"); |
b0f3f28e | 852 | hw_perf_restore(cpuc->throttle_ctrl); |
1b023a96 | 853 | } |
4b39fd96 | 854 | cpuc->interrupts = 0; |
241771ef IM |
855 | } |
856 | ||
857 | void smp_perf_counter_interrupt(struct pt_regs *regs) | |
858 | { | |
859 | irq_enter(); | |
241771ef | 860 | apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR); |
b0f3f28e | 861 | ack_APIC_irq(); |
39d81eab | 862 | x86_pmu->handle_irq(regs, 0); |
241771ef IM |
863 | irq_exit(); |
864 | } | |
865 | ||
b6276f35 PZ |
866 | void smp_perf_pending_interrupt(struct pt_regs *regs) |
867 | { | |
868 | irq_enter(); | |
869 | ack_APIC_irq(); | |
870 | inc_irq_stat(apic_pending_irqs); | |
871 | perf_counter_do_pending(); | |
872 | irq_exit(); | |
873 | } | |
874 | ||
875 | void set_perf_counter_pending(void) | |
876 | { | |
877 | apic->send_IPI_self(LOCAL_PENDING_VECTOR); | |
878 | } | |
879 | ||
3415dd91 | 880 | void perf_counters_lapic_init(int nmi) |
241771ef IM |
881 | { |
882 | u32 apic_val; | |
883 | ||
884 | if (!perf_counters_initialized) | |
885 | return; | |
886 | /* | |
887 | * Enable the performance counter vector in the APIC LVT: | |
888 | */ | |
889 | apic_val = apic_read(APIC_LVTERR); | |
890 | ||
891 | apic_write(APIC_LVTERR, apic_val | APIC_LVT_MASKED); | |
892 | if (nmi) | |
893 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
894 | else | |
895 | apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR); | |
896 | apic_write(APIC_LVTERR, apic_val); | |
897 | } | |
898 | ||
899 | static int __kprobes | |
900 | perf_counter_nmi_handler(struct notifier_block *self, | |
901 | unsigned long cmd, void *__args) | |
902 | { | |
903 | struct die_args *args = __args; | |
904 | struct pt_regs *regs; | |
b0f3f28e PZ |
905 | int ret; |
906 | ||
907 | switch (cmd) { | |
908 | case DIE_NMI: | |
909 | case DIE_NMI_IPI: | |
910 | break; | |
241771ef | 911 | |
b0f3f28e | 912 | default: |
241771ef | 913 | return NOTIFY_DONE; |
b0f3f28e | 914 | } |
241771ef IM |
915 | |
916 | regs = args->regs; | |
917 | ||
918 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
39d81eab | 919 | ret = x86_pmu->handle_irq(regs, 1); |
241771ef | 920 | |
b0f3f28e | 921 | return ret ? NOTIFY_STOP : NOTIFY_OK; |
241771ef IM |
922 | } |
923 | ||
924 | static __read_mostly struct notifier_block perf_counter_nmi_notifier = { | |
5b75af0a MG |
925 | .notifier_call = perf_counter_nmi_handler, |
926 | .next = NULL, | |
927 | .priority = 1 | |
241771ef IM |
928 | }; |
929 | ||
5f4ec28f | 930 | static struct x86_pmu intel_pmu = { |
39d81eab | 931 | .handle_irq = intel_pmu_handle_irq, |
5f4ec28f RR |
932 | .save_disable_all = intel_pmu_save_disable_all, |
933 | .restore_all = intel_pmu_restore_all, | |
934 | .get_status = intel_pmu_get_status, | |
935 | .ack_status = intel_pmu_ack_status, | |
936 | .enable = intel_pmu_enable_counter, | |
937 | .disable = intel_pmu_disable_counter, | |
b56a3802 JSR |
938 | .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, |
939 | .perfctr = MSR_ARCH_PERFMON_PERFCTR0, | |
5f4ec28f RR |
940 | .event_map = intel_pmu_event_map, |
941 | .raw_event = intel_pmu_raw_event, | |
b56a3802 JSR |
942 | .max_events = ARRAY_SIZE(intel_perfmon_event_map), |
943 | }; | |
944 | ||
5f4ec28f | 945 | static struct x86_pmu amd_pmu = { |
39d81eab | 946 | .handle_irq = amd_pmu_handle_irq, |
5f4ec28f RR |
947 | .save_disable_all = amd_pmu_save_disable_all, |
948 | .restore_all = amd_pmu_restore_all, | |
949 | .get_status = amd_pmu_get_status, | |
950 | .ack_status = amd_pmu_ack_status, | |
951 | .enable = amd_pmu_enable_counter, | |
952 | .disable = amd_pmu_disable_counter, | |
f87ad35d JSR |
953 | .eventsel = MSR_K7_EVNTSEL0, |
954 | .perfctr = MSR_K7_PERFCTR0, | |
5f4ec28f RR |
955 | .event_map = amd_pmu_event_map, |
956 | .raw_event = amd_pmu_raw_event, | |
f87ad35d JSR |
957 | .max_events = ARRAY_SIZE(amd_perfmon_event_map), |
958 | }; | |
959 | ||
5f4ec28f | 960 | static struct x86_pmu *intel_pmu_init(void) |
241771ef | 961 | { |
7bb497bd | 962 | union cpuid10_edx edx; |
241771ef | 963 | union cpuid10_eax eax; |
703e937c | 964 | unsigned int unused; |
7bb497bd | 965 | unsigned int ebx; |
241771ef | 966 | |
da1a776b RR |
967 | if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) |
968 | return NULL; | |
969 | ||
241771ef IM |
970 | /* |
971 | * Check whether the Architectural PerfMon supports | |
972 | * Branch Misses Retired Event or not. | |
973 | */ | |
703e937c | 974 | cpuid(10, &eax.full, &ebx, &unused, &edx.full); |
241771ef | 975 | if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED) |
b56a3802 | 976 | return NULL; |
241771ef | 977 | |
7bb497bd IM |
978 | intel_perfmon_version = eax.split.version_id; |
979 | if (intel_perfmon_version < 2) | |
980 | return NULL; | |
981 | ||
a1ef58f4 | 982 | pr_info("Intel Performance Monitoring support detected.\n"); |
7bb497bd | 983 | pr_info("... version: %d\n", intel_perfmon_version); |
a1ef58f4 JSR |
984 | pr_info("... bit width: %d\n", eax.split.bit_width); |
985 | pr_info("... mask length: %d\n", eax.split.mask_length); | |
b56a3802 | 986 | |
862a1a5f | 987 | nr_counters_generic = eax.split.num_counters; |
b56a3802 JSR |
988 | nr_counters_fixed = edx.split.num_counters_fixed; |
989 | counter_value_mask = (1ULL << eax.split.bit_width) - 1; | |
990 | ||
5f4ec28f | 991 | return &intel_pmu; |
b56a3802 JSR |
992 | } |
993 | ||
5f4ec28f | 994 | static struct x86_pmu *amd_pmu_init(void) |
f87ad35d JSR |
995 | { |
996 | nr_counters_generic = 4; | |
997 | nr_counters_fixed = 0; | |
b5e8acf6 PZ |
998 | counter_value_mask = 0x0000FFFFFFFFFFFFULL; |
999 | counter_value_bits = 48; | |
f87ad35d | 1000 | |
a1ef58f4 | 1001 | pr_info("AMD Performance Monitoring support detected.\n"); |
f87ad35d | 1002 | |
5f4ec28f | 1003 | return &amd_pmu; |
f87ad35d JSR |
1004 | } |
1005 | ||
b56a3802 JSR |
1006 | void __init init_hw_perf_counters(void) |
1007 | { | |
b56a3802 JSR |
1008 | switch (boot_cpu_data.x86_vendor) { |
1009 | case X86_VENDOR_INTEL: | |
5f4ec28f | 1010 | x86_pmu = intel_pmu_init(); |
b56a3802 | 1011 | break; |
f87ad35d | 1012 | case X86_VENDOR_AMD: |
5f4ec28f | 1013 | x86_pmu = amd_pmu_init(); |
f87ad35d | 1014 | break; |
4138960a RR |
1015 | default: |
1016 | return; | |
b56a3802 | 1017 | } |
5f4ec28f | 1018 | if (!x86_pmu) |
b56a3802 JSR |
1019 | return; |
1020 | ||
a1ef58f4 | 1021 | pr_info("... num counters: %d\n", nr_counters_generic); |
862a1a5f IM |
1022 | if (nr_counters_generic > X86_PMC_MAX_GENERIC) { |
1023 | nr_counters_generic = X86_PMC_MAX_GENERIC; | |
241771ef | 1024 | WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!", |
862a1a5f | 1025 | nr_counters_generic, X86_PMC_MAX_GENERIC); |
241771ef | 1026 | } |
862a1a5f IM |
1027 | perf_counter_mask = (1 << nr_counters_generic) - 1; |
1028 | perf_max_counters = nr_counters_generic; | |
241771ef | 1029 | |
a1ef58f4 | 1030 | pr_info("... value mask: %016Lx\n", counter_value_mask); |
2f18d1e8 | 1031 | |
862a1a5f IM |
1032 | if (nr_counters_fixed > X86_PMC_MAX_FIXED) { |
1033 | nr_counters_fixed = X86_PMC_MAX_FIXED; | |
703e937c | 1034 | WARN(1, KERN_ERR "hw perf counters fixed %d > max(%d), clipping!", |
862a1a5f | 1035 | nr_counters_fixed, X86_PMC_MAX_FIXED); |
703e937c | 1036 | } |
a1ef58f4 | 1037 | pr_info("... fixed counters: %d\n", nr_counters_fixed); |
862a1a5f IM |
1038 | |
1039 | perf_counter_mask |= ((1LL << nr_counters_fixed)-1) << X86_PMC_IDX_FIXED; | |
241771ef | 1040 | |
a1ef58f4 | 1041 | pr_info("... counter mask: %016Lx\n", perf_counter_mask); |
75f224cf IM |
1042 | perf_counters_initialized = true; |
1043 | ||
241771ef IM |
1044 | perf_counters_lapic_init(0); |
1045 | register_die_notifier(&perf_counter_nmi_notifier); | |
241771ef | 1046 | } |
621a01ea | 1047 | |
4aeb0b42 | 1048 | static void x86_pmu_read(struct perf_counter *counter) |
ee06094f IM |
1049 | { |
1050 | x86_perf_counter_update(counter, &counter->hw, counter->hw.idx); | |
1051 | } | |
1052 | ||
4aeb0b42 RR |
1053 | static const struct pmu pmu = { |
1054 | .enable = x86_pmu_enable, | |
1055 | .disable = x86_pmu_disable, | |
1056 | .read = x86_pmu_read, | |
621a01ea IM |
1057 | }; |
1058 | ||
4aeb0b42 | 1059 | const struct pmu *hw_perf_counter_init(struct perf_counter *counter) |
621a01ea IM |
1060 | { |
1061 | int err; | |
1062 | ||
1063 | err = __hw_perf_counter_init(counter); | |
1064 | if (err) | |
9ea98e19 | 1065 | return ERR_PTR(err); |
621a01ea | 1066 | |
4aeb0b42 | 1067 | return &pmu; |
621a01ea | 1068 | } |
d7d59fb3 PZ |
1069 | |
1070 | /* | |
1071 | * callchain support | |
1072 | */ | |
1073 | ||
1074 | static inline | |
1075 | void callchain_store(struct perf_callchain_entry *entry, unsigned long ip) | |
1076 | { | |
1077 | if (entry->nr < MAX_STACK_DEPTH) | |
1078 | entry->ip[entry->nr++] = ip; | |
1079 | } | |
1080 | ||
1081 | static DEFINE_PER_CPU(struct perf_callchain_entry, irq_entry); | |
1082 | static DEFINE_PER_CPU(struct perf_callchain_entry, nmi_entry); | |
1083 | ||
1084 | ||
1085 | static void | |
1086 | backtrace_warning_symbol(void *data, char *msg, unsigned long symbol) | |
1087 | { | |
1088 | /* Ignore warnings */ | |
1089 | } | |
1090 | ||
1091 | static void backtrace_warning(void *data, char *msg) | |
1092 | { | |
1093 | /* Ignore warnings */ | |
1094 | } | |
1095 | ||
1096 | static int backtrace_stack(void *data, char *name) | |
1097 | { | |
1098 | /* Don't bother with IRQ stacks for now */ | |
1099 | return -1; | |
1100 | } | |
1101 | ||
1102 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
1103 | { | |
1104 | struct perf_callchain_entry *entry = data; | |
1105 | ||
1106 | if (reliable) | |
1107 | callchain_store(entry, addr); | |
1108 | } | |
1109 | ||
1110 | static const struct stacktrace_ops backtrace_ops = { | |
1111 | .warning = backtrace_warning, | |
1112 | .warning_symbol = backtrace_warning_symbol, | |
1113 | .stack = backtrace_stack, | |
1114 | .address = backtrace_address, | |
1115 | }; | |
1116 | ||
1117 | static void | |
1118 | perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1119 | { | |
1120 | unsigned long bp; | |
1121 | char *stack; | |
5872bdb8 | 1122 | int nr = entry->nr; |
d7d59fb3 PZ |
1123 | |
1124 | callchain_store(entry, instruction_pointer(regs)); | |
1125 | ||
1126 | stack = ((char *)regs + sizeof(struct pt_regs)); | |
1127 | #ifdef CONFIG_FRAME_POINTER | |
1128 | bp = frame_pointer(regs); | |
1129 | #else | |
1130 | bp = 0; | |
1131 | #endif | |
1132 | ||
1133 | dump_trace(NULL, regs, (void *)stack, bp, &backtrace_ops, entry); | |
5872bdb8 PZ |
1134 | |
1135 | entry->kernel = entry->nr - nr; | |
d7d59fb3 PZ |
1136 | } |
1137 | ||
1138 | ||
1139 | struct stack_frame { | |
1140 | const void __user *next_fp; | |
1141 | unsigned long return_address; | |
1142 | }; | |
1143 | ||
1144 | static int copy_stack_frame(const void __user *fp, struct stack_frame *frame) | |
1145 | { | |
1146 | int ret; | |
1147 | ||
1148 | if (!access_ok(VERIFY_READ, fp, sizeof(*frame))) | |
1149 | return 0; | |
1150 | ||
1151 | ret = 1; | |
1152 | pagefault_disable(); | |
1153 | if (__copy_from_user_inatomic(frame, fp, sizeof(*frame))) | |
1154 | ret = 0; | |
1155 | pagefault_enable(); | |
1156 | ||
1157 | return ret; | |
1158 | } | |
1159 | ||
1160 | static void | |
1161 | perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1162 | { | |
1163 | struct stack_frame frame; | |
1164 | const void __user *fp; | |
5872bdb8 | 1165 | int nr = entry->nr; |
d7d59fb3 PZ |
1166 | |
1167 | regs = (struct pt_regs *)current->thread.sp0 - 1; | |
1168 | fp = (void __user *)regs->bp; | |
1169 | ||
1170 | callchain_store(entry, regs->ip); | |
1171 | ||
1172 | while (entry->nr < MAX_STACK_DEPTH) { | |
1173 | frame.next_fp = NULL; | |
1174 | frame.return_address = 0; | |
1175 | ||
1176 | if (!copy_stack_frame(fp, &frame)) | |
1177 | break; | |
1178 | ||
1179 | if ((unsigned long)fp < user_stack_pointer(regs)) | |
1180 | break; | |
1181 | ||
1182 | callchain_store(entry, frame.return_address); | |
1183 | fp = frame.next_fp; | |
1184 | } | |
5872bdb8 PZ |
1185 | |
1186 | entry->user = entry->nr - nr; | |
d7d59fb3 PZ |
1187 | } |
1188 | ||
1189 | static void | |
1190 | perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1191 | { | |
1192 | int is_user; | |
1193 | ||
1194 | if (!regs) | |
1195 | return; | |
1196 | ||
1197 | is_user = user_mode(regs); | |
1198 | ||
1199 | if (!current || current->pid == 0) | |
1200 | return; | |
1201 | ||
1202 | if (is_user && current->state != TASK_RUNNING) | |
1203 | return; | |
1204 | ||
1205 | if (!is_user) | |
1206 | perf_callchain_kernel(regs, entry); | |
1207 | ||
1208 | if (current->mm) | |
1209 | perf_callchain_user(regs, entry); | |
1210 | } | |
1211 | ||
1212 | struct perf_callchain_entry *perf_callchain(struct pt_regs *regs) | |
1213 | { | |
1214 | struct perf_callchain_entry *entry; | |
1215 | ||
1216 | if (in_nmi()) | |
1217 | entry = &__get_cpu_var(nmi_entry); | |
1218 | else | |
1219 | entry = &__get_cpu_var(irq_entry); | |
1220 | ||
1221 | entry->nr = 0; | |
5872bdb8 PZ |
1222 | entry->hv = 0; |
1223 | entry->kernel = 0; | |
1224 | entry->user = 0; | |
d7d59fb3 PZ |
1225 | |
1226 | perf_do_callchain(regs, entry); | |
1227 | ||
1228 | return entry; | |
1229 | } |