Commit | Line | Data |
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241771ef IM |
1 | /* |
2 | * Performance counter x86 architecture code | |
3 | * | |
4 | * Copyright(C) 2008 Thomas Gleixner <tglx@linutronix.de> | |
5 | * Copyright(C) 2008 Red Hat, Inc., Ingo Molnar | |
6 | * | |
7 | * For licencing details see kernel-base/COPYING | |
8 | */ | |
9 | ||
10 | #include <linux/perf_counter.h> | |
11 | #include <linux/capability.h> | |
12 | #include <linux/notifier.h> | |
13 | #include <linux/hardirq.h> | |
14 | #include <linux/kprobes.h> | |
4ac13294 | 15 | #include <linux/module.h> |
241771ef IM |
16 | #include <linux/kdebug.h> |
17 | #include <linux/sched.h> | |
18 | ||
5c167b85 | 19 | #include <asm/perf_counter.h> |
241771ef IM |
20 | #include <asm/apic.h> |
21 | ||
22 | static bool perf_counters_initialized __read_mostly; | |
23 | ||
24 | /* | |
25 | * Number of (generic) HW counters: | |
26 | */ | |
862a1a5f IM |
27 | static int nr_counters_generic __read_mostly; |
28 | static u64 perf_counter_mask __read_mostly; | |
241771ef | 29 | |
862a1a5f | 30 | static int nr_counters_fixed __read_mostly; |
703e937c | 31 | |
241771ef | 32 | struct cpu_hw_counters { |
862a1a5f IM |
33 | struct perf_counter *counters[X86_PMC_IDX_MAX]; |
34 | unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
241771ef IM |
35 | }; |
36 | ||
37 | /* | |
38 | * Intel PerfMon v3. Used on Core2 and later. | |
39 | */ | |
40 | static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters); | |
41 | ||
94c46572 | 42 | static const int intel_perfmon_event_map[] = |
241771ef IM |
43 | { |
44 | [PERF_COUNT_CYCLES] = 0x003c, | |
45 | [PERF_COUNT_INSTRUCTIONS] = 0x00c0, | |
46 | [PERF_COUNT_CACHE_REFERENCES] = 0x4f2e, | |
47 | [PERF_COUNT_CACHE_MISSES] = 0x412e, | |
48 | [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4, | |
49 | [PERF_COUNT_BRANCH_MISSES] = 0x00c5, | |
50 | }; | |
51 | ||
94c46572 | 52 | static const int max_intel_perfmon_events = ARRAY_SIZE(intel_perfmon_event_map); |
241771ef | 53 | |
ee06094f IM |
54 | /* |
55 | * Propagate counter elapsed time into the generic counter. | |
56 | * Can only be executed on the CPU where the counter is active. | |
57 | * Returns the delta events processed. | |
58 | */ | |
59 | static void | |
60 | x86_perf_counter_update(struct perf_counter *counter, | |
61 | struct hw_perf_counter *hwc, int idx) | |
62 | { | |
63 | u64 prev_raw_count, new_raw_count, delta; | |
64 | ||
ee06094f IM |
65 | /* |
66 | * Careful: an NMI might modify the previous counter value. | |
67 | * | |
68 | * Our tactic to handle this is to first atomically read and | |
69 | * exchange a new raw count - then add that new-prev delta | |
70 | * count to the generic counter atomically: | |
71 | */ | |
72 | again: | |
73 | prev_raw_count = atomic64_read(&hwc->prev_count); | |
74 | rdmsrl(hwc->counter_base + idx, new_raw_count); | |
75 | ||
76 | if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count, | |
77 | new_raw_count) != prev_raw_count) | |
78 | goto again; | |
79 | ||
80 | /* | |
81 | * Now we have the new raw value and have updated the prev | |
82 | * timestamp already. We can now calculate the elapsed delta | |
83 | * (counter-)time and add that to the generic counter. | |
84 | * | |
85 | * Careful, not all hw sign-extends above the physical width | |
86 | * of the count, so we do that by clipping the delta to 32 bits: | |
87 | */ | |
88 | delta = (u64)(u32)((s32)new_raw_count - (s32)prev_raw_count); | |
ee06094f IM |
89 | |
90 | atomic64_add(delta, &counter->count); | |
91 | atomic64_sub(delta, &hwc->period_left); | |
92 | } | |
93 | ||
241771ef IM |
94 | /* |
95 | * Setup the hardware configuration for a given hw_event_type | |
96 | */ | |
621a01ea | 97 | static int __hw_perf_counter_init(struct perf_counter *counter) |
241771ef | 98 | { |
9f66a381 | 99 | struct perf_counter_hw_event *hw_event = &counter->hw_event; |
241771ef IM |
100 | struct hw_perf_counter *hwc = &counter->hw; |
101 | ||
102 | if (unlikely(!perf_counters_initialized)) | |
103 | return -EINVAL; | |
104 | ||
105 | /* | |
106 | * Count user events, and generate PMC IRQs: | |
107 | * (keep 'enabled' bit clear for now) | |
108 | */ | |
109 | hwc->config = ARCH_PERFMON_EVENTSEL_USR | ARCH_PERFMON_EVENTSEL_INT; | |
110 | ||
111 | /* | |
112 | * If privileged enough, count OS events too, and allow | |
113 | * NMI events as well: | |
114 | */ | |
115 | hwc->nmi = 0; | |
116 | if (capable(CAP_SYS_ADMIN)) { | |
117 | hwc->config |= ARCH_PERFMON_EVENTSEL_OS; | |
9f66a381 | 118 | if (hw_event->nmi) |
241771ef IM |
119 | hwc->nmi = 1; |
120 | } | |
121 | ||
9f66a381 IM |
122 | hwc->config_base = MSR_ARCH_PERFMON_EVENTSEL0; |
123 | hwc->counter_base = MSR_ARCH_PERFMON_PERFCTR0; | |
241771ef | 124 | |
9f66a381 | 125 | hwc->irq_period = hw_event->irq_period; |
241771ef IM |
126 | /* |
127 | * Intel PMCs cannot be accessed sanely above 32 bit width, | |
128 | * so we install an artificial 1<<31 period regardless of | |
129 | * the generic counter period: | |
130 | */ | |
ee06094f | 131 | if ((s64)hwc->irq_period <= 0 || hwc->irq_period > 0x7FFFFFFF) |
241771ef IM |
132 | hwc->irq_period = 0x7FFFFFFF; |
133 | ||
ee06094f | 134 | atomic64_set(&hwc->period_left, hwc->irq_period); |
241771ef IM |
135 | |
136 | /* | |
dfa7c899 | 137 | * Raw event type provide the config in the event structure |
241771ef | 138 | */ |
9f66a381 IM |
139 | if (hw_event->raw) { |
140 | hwc->config |= hw_event->type; | |
241771ef | 141 | } else { |
9f66a381 | 142 | if (hw_event->type >= max_intel_perfmon_events) |
241771ef IM |
143 | return -EINVAL; |
144 | /* | |
145 | * The generic map: | |
146 | */ | |
9f66a381 | 147 | hwc->config |= intel_perfmon_event_map[hw_event->type]; |
241771ef | 148 | } |
241771ef IM |
149 | counter->wakeup_pending = 0; |
150 | ||
151 | return 0; | |
152 | } | |
153 | ||
241771ef IM |
154 | void hw_perf_enable_all(void) |
155 | { | |
2b9ff0db IM |
156 | if (unlikely(!perf_counters_initialized)) |
157 | return; | |
158 | ||
862a1a5f | 159 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, perf_counter_mask); |
241771ef IM |
160 | } |
161 | ||
01b2838c | 162 | u64 hw_perf_save_disable(void) |
4ac13294 TG |
163 | { |
164 | u64 ctrl; | |
165 | ||
2b9ff0db IM |
166 | if (unlikely(!perf_counters_initialized)) |
167 | return 0; | |
168 | ||
4ac13294 | 169 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
862a1a5f | 170 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); |
2b9ff0db | 171 | |
4ac13294 | 172 | return ctrl; |
241771ef | 173 | } |
01b2838c | 174 | EXPORT_SYMBOL_GPL(hw_perf_save_disable); |
241771ef | 175 | |
ee06094f IM |
176 | void hw_perf_restore(u64 ctrl) |
177 | { | |
2b9ff0db IM |
178 | if (unlikely(!perf_counters_initialized)) |
179 | return; | |
180 | ||
862a1a5f | 181 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
ee06094f IM |
182 | } |
183 | EXPORT_SYMBOL_GPL(hw_perf_restore); | |
184 | ||
7e2ae347 | 185 | static inline void |
eb2b8618 | 186 | __pmc_generic_disable(struct perf_counter *counter, |
ee06094f | 187 | struct hw_perf_counter *hwc, unsigned int idx) |
7e2ae347 | 188 | { |
ee06094f IM |
189 | int err; |
190 | ||
191 | err = wrmsr_safe(hwc->config_base + idx, hwc->config, 0); | |
7e2ae347 IM |
192 | } |
193 | ||
eb2b8618 | 194 | static DEFINE_PER_CPU(u64, prev_left[X86_PMC_MAX_GENERIC]); |
241771ef | 195 | |
ee06094f IM |
196 | /* |
197 | * Set the next IRQ period, based on the hwc->period_left value. | |
198 | * To be called with the counter disabled in hw: | |
199 | */ | |
200 | static void | |
201 | __hw_perf_counter_set_period(struct perf_counter *counter, | |
202 | struct hw_perf_counter *hwc, int idx) | |
241771ef | 203 | { |
ee06094f IM |
204 | s32 left = atomic64_read(&hwc->period_left); |
205 | s32 period = hwc->irq_period; | |
206 | ||
ee06094f IM |
207 | /* |
208 | * If we are way outside a reasoable range then just skip forward: | |
209 | */ | |
210 | if (unlikely(left <= -period)) { | |
211 | left = period; | |
212 | atomic64_set(&hwc->period_left, left); | |
213 | } | |
214 | ||
215 | if (unlikely(left <= 0)) { | |
216 | left += period; | |
217 | atomic64_set(&hwc->period_left, left); | |
218 | } | |
241771ef | 219 | |
ee06094f IM |
220 | per_cpu(prev_left[idx], smp_processor_id()) = left; |
221 | ||
222 | /* | |
223 | * The hw counter starts counting from this counter offset, | |
224 | * mark it to be able to extra future deltas: | |
225 | */ | |
226 | atomic64_set(&hwc->prev_count, (u64)(s64)-left); | |
227 | ||
228 | wrmsr(hwc->counter_base + idx, -left, 0); | |
7e2ae347 IM |
229 | } |
230 | ||
ee06094f | 231 | static void |
eb2b8618 | 232 | __pmc_generic_enable(struct perf_counter *counter, |
ee06094f | 233 | struct hw_perf_counter *hwc, int idx) |
7e2ae347 IM |
234 | { |
235 | wrmsr(hwc->config_base + idx, | |
236 | hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE, 0); | |
241771ef IM |
237 | } |
238 | ||
862a1a5f IM |
239 | static int fixed_mode_idx(struct hw_perf_counter *hwc) |
240 | { | |
241 | return -1; | |
242 | } | |
243 | ||
ee06094f IM |
244 | /* |
245 | * Find a PMC slot for the freshly enabled / scheduled in counter: | |
246 | */ | |
95cdd2e7 | 247 | static int pmc_generic_enable(struct perf_counter *counter) |
241771ef IM |
248 | { |
249 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
250 | struct hw_perf_counter *hwc = &counter->hw; | |
251 | int idx = hwc->idx; | |
252 | ||
253 | /* Try to get the previous counter again */ | |
254 | if (test_and_set_bit(idx, cpuc->used)) { | |
862a1a5f | 255 | idx = find_first_zero_bit(cpuc->used, nr_counters_generic); |
95cdd2e7 IM |
256 | if (idx == nr_counters_generic) |
257 | return -EAGAIN; | |
0dff86aa | 258 | |
241771ef IM |
259 | set_bit(idx, cpuc->used); |
260 | hwc->idx = idx; | |
261 | } | |
262 | ||
263 | perf_counters_lapic_init(hwc->nmi); | |
264 | ||
eb2b8618 | 265 | __pmc_generic_disable(counter, hwc, idx); |
241771ef | 266 | |
862a1a5f | 267 | cpuc->counters[idx] = counter; |
7e2ae347 | 268 | |
ee06094f | 269 | __hw_perf_counter_set_period(counter, hwc, idx); |
eb2b8618 | 270 | __pmc_generic_enable(counter, hwc, idx); |
95cdd2e7 IM |
271 | |
272 | return 0; | |
241771ef IM |
273 | } |
274 | ||
275 | void perf_counter_print_debug(void) | |
276 | { | |
ee06094f | 277 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left; |
0dff86aa | 278 | struct cpu_hw_counters *cpuc; |
1e125676 IM |
279 | int cpu, idx; |
280 | ||
862a1a5f | 281 | if (!nr_counters_generic) |
1e125676 | 282 | return; |
241771ef IM |
283 | |
284 | local_irq_disable(); | |
285 | ||
286 | cpu = smp_processor_id(); | |
0dff86aa | 287 | cpuc = &per_cpu(cpu_hw_counters, cpu); |
241771ef | 288 | |
1e125676 IM |
289 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
290 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
291 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
241771ef IM |
292 | |
293 | printk(KERN_INFO "\n"); | |
294 | printk(KERN_INFO "CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
295 | printk(KERN_INFO "CPU#%d: status: %016llx\n", cpu, status); | |
296 | printk(KERN_INFO "CPU#%d: overflow: %016llx\n", cpu, overflow); | |
0dff86aa | 297 | printk(KERN_INFO "CPU#%d: used: %016llx\n", cpu, *(u64 *)cpuc->used); |
241771ef | 298 | |
862a1a5f | 299 | for (idx = 0; idx < nr_counters_generic; idx++) { |
1e125676 IM |
300 | rdmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + idx, pmc_ctrl); |
301 | rdmsrl(MSR_ARCH_PERFMON_PERFCTR0 + idx, pmc_count); | |
241771ef | 302 | |
ee06094f | 303 | prev_left = per_cpu(prev_left[idx], cpu); |
241771ef IM |
304 | |
305 | printk(KERN_INFO "CPU#%d: PMC%d ctrl: %016llx\n", | |
306 | cpu, idx, pmc_ctrl); | |
307 | printk(KERN_INFO "CPU#%d: PMC%d count: %016llx\n", | |
308 | cpu, idx, pmc_count); | |
ee06094f IM |
309 | printk(KERN_INFO "CPU#%d: PMC%d left: %016llx\n", |
310 | cpu, idx, prev_left); | |
241771ef IM |
311 | } |
312 | local_irq_enable(); | |
313 | } | |
314 | ||
eb2b8618 | 315 | static void pmc_generic_disable(struct perf_counter *counter) |
241771ef IM |
316 | { |
317 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
318 | struct hw_perf_counter *hwc = &counter->hw; | |
319 | unsigned int idx = hwc->idx; | |
320 | ||
eb2b8618 | 321 | __pmc_generic_disable(counter, hwc, idx); |
241771ef IM |
322 | |
323 | clear_bit(idx, cpuc->used); | |
862a1a5f | 324 | cpuc->counters[idx] = NULL; |
241771ef | 325 | |
ee06094f IM |
326 | /* |
327 | * Drain the remaining delta count out of a counter | |
328 | * that we are disabling: | |
329 | */ | |
330 | x86_perf_counter_update(counter, hwc, idx); | |
241771ef IM |
331 | } |
332 | ||
333 | static void perf_store_irq_data(struct perf_counter *counter, u64 data) | |
334 | { | |
335 | struct perf_data *irqdata = counter->irqdata; | |
336 | ||
337 | if (irqdata->len > PERF_DATA_BUFLEN - sizeof(u64)) { | |
338 | irqdata->overrun++; | |
339 | } else { | |
340 | u64 *p = (u64 *) &irqdata->data[irqdata->len]; | |
341 | ||
342 | *p = data; | |
343 | irqdata->len += sizeof(u64); | |
344 | } | |
345 | } | |
346 | ||
7e2ae347 | 347 | /* |
ee06094f IM |
348 | * Save and restart an expired counter. Called by NMI contexts, |
349 | * so it has to be careful about preempting normal counter ops: | |
7e2ae347 | 350 | */ |
241771ef IM |
351 | static void perf_save_and_restart(struct perf_counter *counter) |
352 | { | |
353 | struct hw_perf_counter *hwc = &counter->hw; | |
354 | int idx = hwc->idx; | |
7e2ae347 | 355 | u64 pmc_ctrl; |
241771ef | 356 | |
1e125676 | 357 | rdmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + idx, pmc_ctrl); |
241771ef | 358 | |
ee06094f IM |
359 | x86_perf_counter_update(counter, hwc, idx); |
360 | __hw_perf_counter_set_period(counter, hwc, idx); | |
7e2ae347 IM |
361 | |
362 | if (pmc_ctrl & ARCH_PERFMON_EVENTSEL0_ENABLE) | |
eb2b8618 | 363 | __pmc_generic_enable(counter, hwc, idx); |
241771ef IM |
364 | } |
365 | ||
366 | static void | |
04289bb9 | 367 | perf_handle_group(struct perf_counter *sibling, u64 *status, u64 *overflown) |
241771ef | 368 | { |
04289bb9 | 369 | struct perf_counter *counter, *group_leader = sibling->group_leader; |
241771ef | 370 | |
04289bb9 | 371 | /* |
ee06094f | 372 | * Store sibling timestamps (if any): |
04289bb9 IM |
373 | */ |
374 | list_for_each_entry(counter, &group_leader->sibling_list, list_entry) { | |
ee06094f | 375 | x86_perf_counter_update(counter, &counter->hw, counter->hw.idx); |
04289bb9 | 376 | perf_store_irq_data(sibling, counter->hw_event.type); |
ee06094f | 377 | perf_store_irq_data(sibling, atomic64_read(&counter->count)); |
241771ef IM |
378 | } |
379 | } | |
380 | ||
381 | /* | |
382 | * This handler is triggered by the local APIC, so the APIC IRQ handling | |
383 | * rules apply: | |
384 | */ | |
385 | static void __smp_perf_counter_interrupt(struct pt_regs *regs, int nmi) | |
386 | { | |
387 | int bit, cpu = smp_processor_id(); | |
43874d23 | 388 | u64 ack, status, saved_global; |
241771ef | 389 | struct cpu_hw_counters *cpuc; |
43874d23 IM |
390 | |
391 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, saved_global); | |
241771ef | 392 | |
241771ef | 393 | /* Disable counters globally */ |
862a1a5f | 394 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); |
241771ef IM |
395 | ack_APIC_irq(); |
396 | ||
397 | cpuc = &per_cpu(cpu_hw_counters, cpu); | |
398 | ||
87b9cf46 IM |
399 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); |
400 | if (!status) | |
401 | goto out; | |
402 | ||
241771ef IM |
403 | again: |
404 | ack = status; | |
862a1a5f IM |
405 | for_each_bit(bit, (unsigned long *) &status, nr_counters_generic) { |
406 | struct perf_counter *counter = cpuc->counters[bit]; | |
241771ef IM |
407 | |
408 | clear_bit(bit, (unsigned long *) &status); | |
409 | if (!counter) | |
410 | continue; | |
411 | ||
412 | perf_save_and_restart(counter); | |
413 | ||
9f66a381 | 414 | switch (counter->hw_event.record_type) { |
241771ef IM |
415 | case PERF_RECORD_SIMPLE: |
416 | continue; | |
417 | case PERF_RECORD_IRQ: | |
418 | perf_store_irq_data(counter, instruction_pointer(regs)); | |
419 | break; | |
420 | case PERF_RECORD_GROUP: | |
241771ef IM |
421 | perf_handle_group(counter, &status, &ack); |
422 | break; | |
423 | } | |
424 | /* | |
425 | * From NMI context we cannot call into the scheduler to | |
eb2b8618 | 426 | * do a task wakeup - but we mark these generic as |
241771ef IM |
427 | * wakeup_pending and initate a wakeup callback: |
428 | */ | |
429 | if (nmi) { | |
430 | counter->wakeup_pending = 1; | |
431 | set_tsk_thread_flag(current, TIF_PERF_COUNTERS); | |
432 | } else { | |
433 | wake_up(&counter->waitq); | |
434 | } | |
435 | } | |
436 | ||
862a1a5f | 437 | wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); |
241771ef IM |
438 | |
439 | /* | |
440 | * Repeat if there is more work to be done: | |
441 | */ | |
442 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
443 | if (status) | |
444 | goto again; | |
87b9cf46 | 445 | out: |
241771ef | 446 | /* |
43874d23 | 447 | * Restore - do not reenable when global enable is off: |
241771ef | 448 | */ |
862a1a5f | 449 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, saved_global); |
241771ef IM |
450 | } |
451 | ||
452 | void smp_perf_counter_interrupt(struct pt_regs *regs) | |
453 | { | |
454 | irq_enter(); | |
92bf73e9 | 455 | inc_irq_stat(apic_perf_irqs); |
241771ef IM |
456 | apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR); |
457 | __smp_perf_counter_interrupt(regs, 0); | |
458 | ||
459 | irq_exit(); | |
460 | } | |
461 | ||
462 | /* | |
463 | * This handler is triggered by NMI contexts: | |
464 | */ | |
465 | void perf_counter_notify(struct pt_regs *regs) | |
466 | { | |
467 | struct cpu_hw_counters *cpuc; | |
468 | unsigned long flags; | |
469 | int bit, cpu; | |
470 | ||
471 | local_irq_save(flags); | |
472 | cpu = smp_processor_id(); | |
473 | cpuc = &per_cpu(cpu_hw_counters, cpu); | |
474 | ||
862a1a5f IM |
475 | for_each_bit(bit, cpuc->used, X86_PMC_IDX_MAX) { |
476 | struct perf_counter *counter = cpuc->counters[bit]; | |
241771ef IM |
477 | |
478 | if (!counter) | |
479 | continue; | |
480 | ||
481 | if (counter->wakeup_pending) { | |
482 | counter->wakeup_pending = 0; | |
483 | wake_up(&counter->waitq); | |
484 | } | |
485 | } | |
486 | ||
487 | local_irq_restore(flags); | |
488 | } | |
489 | ||
490 | void __cpuinit perf_counters_lapic_init(int nmi) | |
491 | { | |
492 | u32 apic_val; | |
493 | ||
494 | if (!perf_counters_initialized) | |
495 | return; | |
496 | /* | |
497 | * Enable the performance counter vector in the APIC LVT: | |
498 | */ | |
499 | apic_val = apic_read(APIC_LVTERR); | |
500 | ||
501 | apic_write(APIC_LVTERR, apic_val | APIC_LVT_MASKED); | |
502 | if (nmi) | |
503 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
504 | else | |
505 | apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR); | |
506 | apic_write(APIC_LVTERR, apic_val); | |
507 | } | |
508 | ||
509 | static int __kprobes | |
510 | perf_counter_nmi_handler(struct notifier_block *self, | |
511 | unsigned long cmd, void *__args) | |
512 | { | |
513 | struct die_args *args = __args; | |
514 | struct pt_regs *regs; | |
515 | ||
516 | if (likely(cmd != DIE_NMI_IPI)) | |
517 | return NOTIFY_DONE; | |
518 | ||
519 | regs = args->regs; | |
520 | ||
521 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
522 | __smp_perf_counter_interrupt(regs, 1); | |
523 | ||
524 | return NOTIFY_STOP; | |
525 | } | |
526 | ||
527 | static __read_mostly struct notifier_block perf_counter_nmi_notifier = { | |
528 | .notifier_call = perf_counter_nmi_handler | |
529 | }; | |
530 | ||
531 | void __init init_hw_perf_counters(void) | |
532 | { | |
533 | union cpuid10_eax eax; | |
241771ef | 534 | unsigned int ebx; |
703e937c IM |
535 | unsigned int unused; |
536 | union cpuid10_edx edx; | |
241771ef IM |
537 | |
538 | if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) | |
539 | return; | |
540 | ||
541 | /* | |
542 | * Check whether the Architectural PerfMon supports | |
543 | * Branch Misses Retired Event or not. | |
544 | */ | |
703e937c | 545 | cpuid(10, &eax.full, &ebx, &unused, &edx.full); |
241771ef IM |
546 | if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED) |
547 | return; | |
548 | ||
549 | printk(KERN_INFO "Intel Performance Monitoring support detected.\n"); | |
550 | ||
703e937c IM |
551 | printk(KERN_INFO "... version: %d\n", eax.split.version_id); |
552 | printk(KERN_INFO "... num counters: %d\n", eax.split.num_counters); | |
862a1a5f IM |
553 | nr_counters_generic = eax.split.num_counters; |
554 | if (nr_counters_generic > X86_PMC_MAX_GENERIC) { | |
555 | nr_counters_generic = X86_PMC_MAX_GENERIC; | |
241771ef | 556 | WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!", |
862a1a5f | 557 | nr_counters_generic, X86_PMC_MAX_GENERIC); |
241771ef | 558 | } |
862a1a5f IM |
559 | perf_counter_mask = (1 << nr_counters_generic) - 1; |
560 | perf_max_counters = nr_counters_generic; | |
241771ef | 561 | |
703e937c IM |
562 | printk(KERN_INFO "... bit width: %d\n", eax.split.bit_width); |
563 | printk(KERN_INFO "... mask length: %d\n", eax.split.mask_length); | |
564 | ||
862a1a5f IM |
565 | nr_counters_fixed = edx.split.num_counters_fixed; |
566 | if (nr_counters_fixed > X86_PMC_MAX_FIXED) { | |
567 | nr_counters_fixed = X86_PMC_MAX_FIXED; | |
703e937c | 568 | WARN(1, KERN_ERR "hw perf counters fixed %d > max(%d), clipping!", |
862a1a5f | 569 | nr_counters_fixed, X86_PMC_MAX_FIXED); |
703e937c | 570 | } |
862a1a5f IM |
571 | printk(KERN_INFO "... fixed counters: %d\n", nr_counters_fixed); |
572 | ||
573 | perf_counter_mask |= ((1LL << nr_counters_fixed)-1) << X86_PMC_IDX_FIXED; | |
241771ef | 574 | |
862a1a5f | 575 | printk(KERN_INFO "... counter mask: %016Lx\n", perf_counter_mask); |
75f224cf IM |
576 | perf_counters_initialized = true; |
577 | ||
241771ef IM |
578 | perf_counters_lapic_init(0); |
579 | register_die_notifier(&perf_counter_nmi_notifier); | |
241771ef | 580 | } |
621a01ea | 581 | |
eb2b8618 | 582 | static void pmc_generic_read(struct perf_counter *counter) |
ee06094f IM |
583 | { |
584 | x86_perf_counter_update(counter, &counter->hw, counter->hw.idx); | |
585 | } | |
586 | ||
5c92d124 | 587 | static const struct hw_perf_counter_ops x86_perf_counter_ops = { |
7671581f IM |
588 | .enable = pmc_generic_enable, |
589 | .disable = pmc_generic_disable, | |
590 | .read = pmc_generic_read, | |
621a01ea IM |
591 | }; |
592 | ||
5c92d124 IM |
593 | const struct hw_perf_counter_ops * |
594 | hw_perf_counter_init(struct perf_counter *counter) | |
621a01ea IM |
595 | { |
596 | int err; | |
597 | ||
598 | err = __hw_perf_counter_init(counter); | |
599 | if (err) | |
600 | return NULL; | |
601 | ||
602 | return &x86_perf_counter_ops; | |
603 | } |