Commit | Line | Data |
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1da177e4 LT |
1 | /* Generic MTRR (Memory Type Range Register) driver. |
2 | ||
3 | Copyright (C) 1997-2000 Richard Gooch | |
4 | Copyright (c) 2002 Patrick Mochel | |
5 | ||
6 | This library is free software; you can redistribute it and/or | |
7 | modify it under the terms of the GNU Library General Public | |
8 | License as published by the Free Software Foundation; either | |
9 | version 2 of the License, or (at your option) any later version. | |
10 | ||
11 | This library is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | Library General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU Library General Public | |
17 | License along with this library; if not, write to the Free | |
18 | Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | ||
20 | Richard Gooch may be reached by email at rgooch@atnf.csiro.au | |
21 | The postal address is: | |
22 | Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia. | |
23 | ||
24 | Source: "Pentium Pro Family Developer's Manual, Volume 3: | |
25 | Operating System Writer's Guide" (Intel document number 242692), | |
26 | section 11.11.7 | |
27 | ||
28 | This was cleaned and made readable by Patrick Mochel <mochel@osdl.org> | |
29 | on 6-7 March 2002. | |
30 | Source: Intel Architecture Software Developers Manual, Volume 3: | |
31 | System Programming Guide; Section 9.11. (1997 edition - PPro). | |
32 | */ | |
33 | ||
34 | #include <linux/module.h> | |
35 | #include <linux/init.h> | |
36 | #include <linux/pci.h> | |
37 | #include <linux/smp.h> | |
38 | #include <linux/cpu.h> | |
14cc3e2b | 39 | #include <linux/mutex.h> |
1da177e4 | 40 | |
99fc8d42 | 41 | #include <asm/e820.h> |
1da177e4 | 42 | #include <asm/mtrr.h> |
1da177e4 LT |
43 | #include <asm/uaccess.h> |
44 | #include <asm/processor.h> | |
45 | #include <asm/msr.h> | |
46 | #include "mtrr.h" | |
47 | ||
1da177e4 LT |
48 | u32 num_var_ranges = 0; |
49 | ||
99fc8d42 | 50 | unsigned int mtrr_usage_table[MAX_VAR_RANGES]; |
14cc3e2b | 51 | static DEFINE_MUTEX(mtrr_mutex); |
1da177e4 | 52 | |
6c5806ca | 53 | u64 size_or_mask, size_and_mask; |
1da177e4 LT |
54 | |
55 | static struct mtrr_ops * mtrr_ops[X86_VENDOR_NUM] = {}; | |
56 | ||
57 | struct mtrr_ops * mtrr_if = NULL; | |
58 | ||
59 | static void set_mtrr(unsigned int reg, unsigned long base, | |
60 | unsigned long size, mtrr_type type); | |
61 | ||
475850c8 | 62 | #ifndef CONFIG_X86_64 |
1da177e4 | 63 | extern int arr3_protected; |
475850c8 JB |
64 | #else |
65 | #define arr3_protected 0 | |
66 | #endif | |
1da177e4 LT |
67 | |
68 | void set_mtrr_ops(struct mtrr_ops * ops) | |
69 | { | |
70 | if (ops->vendor && ops->vendor < X86_VENDOR_NUM) | |
71 | mtrr_ops[ops->vendor] = ops; | |
72 | } | |
73 | ||
74 | /* Returns non-zero if we have the write-combining memory type */ | |
75 | static int have_wrcomb(void) | |
76 | { | |
77 | struct pci_dev *dev; | |
a6954ba2 | 78 | u8 rev; |
1da177e4 LT |
79 | |
80 | if ((dev = pci_get_class(PCI_CLASS_BRIDGE_HOST << 8, NULL)) != NULL) { | |
a6954ba2 | 81 | /* ServerWorks LE chipsets < rev 6 have problems with write-combining |
1da177e4 LT |
82 | Don't allow it and leave room for other chipsets to be tagged */ |
83 | if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS && | |
84 | dev->device == PCI_DEVICE_ID_SERVERWORKS_LE) { | |
a6954ba2 LR |
85 | pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev); |
86 | if (rev <= 5) { | |
87 | printk(KERN_INFO "mtrr: Serverworks LE rev < 6 detected. Write-combining disabled.\n"); | |
88 | pci_dev_put(dev); | |
89 | return 0; | |
90 | } | |
1da177e4 | 91 | } |
a6954ba2 | 92 | /* Intel 450NX errata # 23. Non ascending cacheline evictions to |
1da177e4 LT |
93 | write combining memory may resulting in data corruption */ |
94 | if (dev->vendor == PCI_VENDOR_ID_INTEL && | |
95 | dev->device == PCI_DEVICE_ID_INTEL_82451NX) { | |
96 | printk(KERN_INFO "mtrr: Intel 450NX MMC detected. Write-combining disabled.\n"); | |
97 | pci_dev_put(dev); | |
98 | return 0; | |
99 | } | |
100 | pci_dev_put(dev); | |
101 | } | |
102 | return (mtrr_if->have_wrcomb ? mtrr_if->have_wrcomb() : 0); | |
103 | } | |
104 | ||
105 | /* This function returns the number of variable MTRRs */ | |
106 | static void __init set_num_var_ranges(void) | |
107 | { | |
108 | unsigned long config = 0, dummy; | |
109 | ||
110 | if (use_intel()) { | |
111 | rdmsr(MTRRcap_MSR, config, dummy); | |
112 | } else if (is_cpu(AMD)) | |
113 | config = 2; | |
114 | else if (is_cpu(CYRIX) || is_cpu(CENTAUR)) | |
115 | config = 8; | |
116 | num_var_ranges = config & 0xff; | |
117 | } | |
118 | ||
119 | static void __init init_table(void) | |
120 | { | |
121 | int i, max; | |
122 | ||
123 | max = num_var_ranges; | |
1da177e4 | 124 | for (i = 0; i < max; i++) |
99fc8d42 | 125 | mtrr_usage_table[i] = 1; |
1da177e4 LT |
126 | } |
127 | ||
128 | struct set_mtrr_data { | |
129 | atomic_t count; | |
130 | atomic_t gate; | |
131 | unsigned long smp_base; | |
132 | unsigned long smp_size; | |
133 | unsigned int smp_reg; | |
134 | mtrr_type smp_type; | |
135 | }; | |
136 | ||
1da177e4 LT |
137 | static void ipi_handler(void *info) |
138 | /* [SUMMARY] Synchronisation handler. Executed by "other" CPUs. | |
139 | [RETURNS] Nothing. | |
140 | */ | |
141 | { | |
4e2947f1 | 142 | #ifdef CONFIG_SMP |
1da177e4 LT |
143 | struct set_mtrr_data *data = info; |
144 | unsigned long flags; | |
145 | ||
146 | local_irq_save(flags); | |
147 | ||
148 | atomic_dec(&data->count); | |
149 | while(!atomic_read(&data->gate)) | |
150 | cpu_relax(); | |
151 | ||
152 | /* The master has cleared me to execute */ | |
153 | if (data->smp_reg != ~0U) | |
154 | mtrr_if->set(data->smp_reg, data->smp_base, | |
155 | data->smp_size, data->smp_type); | |
156 | else | |
157 | mtrr_if->set_all(); | |
158 | ||
159 | atomic_dec(&data->count); | |
160 | while(atomic_read(&data->gate)) | |
161 | cpu_relax(); | |
162 | ||
163 | atomic_dec(&data->count); | |
164 | local_irq_restore(flags); | |
1da177e4 | 165 | #endif |
4e2947f1 | 166 | } |
1da177e4 | 167 | |
365bff80 JB |
168 | static inline int types_compatible(mtrr_type type1, mtrr_type type2) { |
169 | return type1 == MTRR_TYPE_UNCACHABLE || | |
170 | type2 == MTRR_TYPE_UNCACHABLE || | |
171 | (type1 == MTRR_TYPE_WRTHROUGH && type2 == MTRR_TYPE_WRBACK) || | |
172 | (type1 == MTRR_TYPE_WRBACK && type2 == MTRR_TYPE_WRTHROUGH); | |
173 | } | |
174 | ||
1da177e4 LT |
175 | /** |
176 | * set_mtrr - update mtrrs on all processors | |
177 | * @reg: mtrr in question | |
178 | * @base: mtrr base | |
179 | * @size: mtrr size | |
180 | * @type: mtrr type | |
181 | * | |
182 | * This is kinda tricky, but fortunately, Intel spelled it out for us cleanly: | |
183 | * | |
184 | * 1. Send IPI to do the following: | |
185 | * 2. Disable Interrupts | |
186 | * 3. Wait for all procs to do so | |
187 | * 4. Enter no-fill cache mode | |
188 | * 5. Flush caches | |
189 | * 6. Clear PGE bit | |
190 | * 7. Flush all TLBs | |
191 | * 8. Disable all range registers | |
192 | * 9. Update the MTRRs | |
193 | * 10. Enable all range registers | |
194 | * 11. Flush all TLBs and caches again | |
195 | * 12. Enter normal cache mode and reenable caching | |
196 | * 13. Set PGE | |
197 | * 14. Wait for buddies to catch up | |
198 | * 15. Enable interrupts. | |
199 | * | |
200 | * What does that mean for us? Well, first we set data.count to the number | |
201 | * of CPUs. As each CPU disables interrupts, it'll decrement it once. We wait | |
202 | * until it hits 0 and proceed. We set the data.gate flag and reset data.count. | |
203 | * Meanwhile, they are waiting for that flag to be set. Once it's set, each | |
204 | * CPU goes through the transition of updating MTRRs. The CPU vendors may each do it | |
205 | * differently, so we call mtrr_if->set() callback and let them take care of it. | |
206 | * When they're done, they again decrement data->count and wait for data.gate to | |
207 | * be reset. | |
208 | * When we finish, we wait for data.count to hit 0 and toggle the data.gate flag. | |
209 | * Everyone then enables interrupts and we all continue on. | |
210 | * | |
211 | * Note that the mechanism is the same for UP systems, too; all the SMP stuff | |
212 | * becomes nops. | |
213 | */ | |
214 | static void set_mtrr(unsigned int reg, unsigned long base, | |
215 | unsigned long size, mtrr_type type) | |
216 | { | |
217 | struct set_mtrr_data data; | |
218 | unsigned long flags; | |
219 | ||
220 | data.smp_reg = reg; | |
221 | data.smp_base = base; | |
222 | data.smp_size = size; | |
223 | data.smp_type = type; | |
224 | atomic_set(&data.count, num_booting_cpus() - 1); | |
d25c1ba2 LP |
225 | /* make sure data.count is visible before unleashing other CPUs */ |
226 | smp_wmb(); | |
1da177e4 LT |
227 | atomic_set(&data.gate,0); |
228 | ||
229 | /* Start the ball rolling on other CPUs */ | |
230 | if (smp_call_function(ipi_handler, &data, 1, 0) != 0) | |
231 | panic("mtrr: timed out waiting for other CPUs\n"); | |
232 | ||
233 | local_irq_save(flags); | |
234 | ||
235 | while(atomic_read(&data.count)) | |
236 | cpu_relax(); | |
237 | ||
238 | /* ok, reset count and toggle gate */ | |
239 | atomic_set(&data.count, num_booting_cpus() - 1); | |
d25c1ba2 | 240 | smp_wmb(); |
1da177e4 LT |
241 | atomic_set(&data.gate,1); |
242 | ||
243 | /* do our MTRR business */ | |
244 | ||
245 | /* HACK! | |
246 | * We use this same function to initialize the mtrrs on boot. | |
247 | * The state of the boot cpu's mtrrs has been saved, and we want | |
248 | * to replicate across all the APs. | |
249 | * If we're doing that @reg is set to something special... | |
250 | */ | |
251 | if (reg != ~0U) | |
252 | mtrr_if->set(reg,base,size,type); | |
253 | ||
254 | /* wait for the others */ | |
255 | while(atomic_read(&data.count)) | |
256 | cpu_relax(); | |
257 | ||
258 | atomic_set(&data.count, num_booting_cpus() - 1); | |
d25c1ba2 | 259 | smp_wmb(); |
1da177e4 LT |
260 | atomic_set(&data.gate,0); |
261 | ||
262 | /* | |
263 | * Wait here for everyone to have seen the gate change | |
264 | * So we're the last ones to touch 'data' | |
265 | */ | |
266 | while(atomic_read(&data.count)) | |
267 | cpu_relax(); | |
268 | ||
269 | local_irq_restore(flags); | |
270 | } | |
271 | ||
272 | /** | |
273 | * mtrr_add_page - Add a memory type region | |
9b483417 AM |
274 | * @base: Physical base address of region in pages (in units of 4 kB!) |
275 | * @size: Physical size of region in pages (4 kB) | |
1da177e4 LT |
276 | * @type: Type of MTRR desired |
277 | * @increment: If this is true do usage counting on the region | |
278 | * | |
279 | * Memory type region registers control the caching on newer Intel and | |
280 | * non Intel processors. This function allows drivers to request an | |
281 | * MTRR is added. The details and hardware specifics of each processor's | |
282 | * implementation are hidden from the caller, but nevertheless the | |
283 | * caller should expect to need to provide a power of two size on an | |
284 | * equivalent power of two boundary. | |
285 | * | |
286 | * If the region cannot be added either because all regions are in use | |
287 | * or the CPU cannot support it a negative value is returned. On success | |
288 | * the register number for this entry is returned, but should be treated | |
289 | * as a cookie only. | |
290 | * | |
291 | * On a multiprocessor machine the changes are made to all processors. | |
292 | * This is required on x86 by the Intel processors. | |
293 | * | |
294 | * The available types are | |
295 | * | |
296 | * %MTRR_TYPE_UNCACHABLE - No caching | |
297 | * | |
298 | * %MTRR_TYPE_WRBACK - Write data back in bursts whenever | |
299 | * | |
300 | * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts | |
301 | * | |
302 | * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes | |
303 | * | |
304 | * BUGS: Needs a quiet flag for the cases where drivers do not mind | |
305 | * failures and do not wish system log messages to be sent. | |
306 | */ | |
307 | ||
308 | int mtrr_add_page(unsigned long base, unsigned long size, | |
2d2ee8de | 309 | unsigned int type, bool increment) |
1da177e4 | 310 | { |
365bff80 | 311 | int i, replace, error; |
1da177e4 | 312 | mtrr_type ltype; |
365bff80 | 313 | unsigned long lbase, lsize; |
1da177e4 LT |
314 | |
315 | if (!mtrr_if) | |
316 | return -ENXIO; | |
317 | ||
318 | if ((error = mtrr_if->validate_add_page(base,size,type))) | |
319 | return error; | |
320 | ||
321 | if (type >= MTRR_NUM_TYPES) { | |
322 | printk(KERN_WARNING "mtrr: type: %u invalid\n", type); | |
323 | return -EINVAL; | |
324 | } | |
325 | ||
326 | /* If the type is WC, check that this processor supports it */ | |
327 | if ((type == MTRR_TYPE_WRCOMB) && !have_wrcomb()) { | |
328 | printk(KERN_WARNING | |
329 | "mtrr: your processor doesn't support write-combining\n"); | |
330 | return -ENOSYS; | |
331 | } | |
332 | ||
365bff80 JB |
333 | if (!size) { |
334 | printk(KERN_WARNING "mtrr: zero sized request\n"); | |
335 | return -EINVAL; | |
336 | } | |
337 | ||
1da177e4 LT |
338 | if (base & size_or_mask || size & size_or_mask) { |
339 | printk(KERN_WARNING "mtrr: base or size exceeds the MTRR width\n"); | |
340 | return -EINVAL; | |
341 | } | |
342 | ||
343 | error = -EINVAL; | |
365bff80 | 344 | replace = -1; |
1da177e4 | 345 | |
3b520b23 | 346 | /* No CPU hotplug when we change MTRR entries */ |
86ef5c9a | 347 | get_online_cpus(); |
1da177e4 | 348 | /* Search for existing MTRR */ |
14cc3e2b | 349 | mutex_lock(&mtrr_mutex); |
1da177e4 LT |
350 | for (i = 0; i < num_var_ranges; ++i) { |
351 | mtrr_if->get(i, &lbase, &lsize, <ype); | |
365bff80 | 352 | if (!lsize || base > lbase + lsize - 1 || base + size - 1 < lbase) |
1da177e4 LT |
353 | continue; |
354 | /* At this point we know there is some kind of overlap/enclosure */ | |
365bff80 JB |
355 | if (base < lbase || base + size - 1 > lbase + lsize - 1) { |
356 | if (base <= lbase && base + size - 1 >= lbase + lsize - 1) { | |
357 | /* New region encloses an existing region */ | |
358 | if (type == ltype) { | |
359 | replace = replace == -1 ? i : -2; | |
360 | continue; | |
361 | } | |
362 | else if (types_compatible(type, ltype)) | |
363 | continue; | |
364 | } | |
1da177e4 LT |
365 | printk(KERN_WARNING |
366 | "mtrr: 0x%lx000,0x%lx000 overlaps existing" | |
365bff80 | 367 | " 0x%lx000,0x%lx000\n", base, size, lbase, |
1da177e4 LT |
368 | lsize); |
369 | goto out; | |
370 | } | |
371 | /* New region is enclosed by an existing region */ | |
372 | if (ltype != type) { | |
365bff80 | 373 | if (types_compatible(type, ltype)) |
1da177e4 LT |
374 | continue; |
375 | printk (KERN_WARNING "mtrr: type mismatch for %lx000,%lx000 old: %s new: %s\n", | |
376 | base, size, mtrr_attrib_to_str(ltype), | |
377 | mtrr_attrib_to_str(type)); | |
378 | goto out; | |
379 | } | |
380 | if (increment) | |
99fc8d42 | 381 | ++mtrr_usage_table[i]; |
1da177e4 LT |
382 | error = i; |
383 | goto out; | |
384 | } | |
385 | /* Search for an empty MTRR */ | |
365bff80 | 386 | i = mtrr_if->get_free_region(base, size, replace); |
1da177e4 LT |
387 | if (i >= 0) { |
388 | set_mtrr(i, base, size, type); | |
99fc8d42 JB |
389 | if (likely(replace < 0)) { |
390 | mtrr_usage_table[i] = 1; | |
391 | } else { | |
392 | mtrr_usage_table[i] = mtrr_usage_table[replace]; | |
2d2ee8de | 393 | if (increment) |
99fc8d42 | 394 | mtrr_usage_table[i]++; |
365bff80 JB |
395 | if (unlikely(replace != i)) { |
396 | set_mtrr(replace, 0, 0, 0); | |
99fc8d42 | 397 | mtrr_usage_table[replace] = 0; |
365bff80 JB |
398 | } |
399 | } | |
1da177e4 LT |
400 | } else |
401 | printk(KERN_INFO "mtrr: no more MTRRs available\n"); | |
402 | error = i; | |
403 | out: | |
14cc3e2b | 404 | mutex_unlock(&mtrr_mutex); |
86ef5c9a | 405 | put_online_cpus(); |
1da177e4 LT |
406 | return error; |
407 | } | |
408 | ||
c92c6ffd AM |
409 | static int mtrr_check(unsigned long base, unsigned long size) |
410 | { | |
411 | if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) { | |
412 | printk(KERN_WARNING | |
413 | "mtrr: size and base must be multiples of 4 kiB\n"); | |
414 | printk(KERN_DEBUG | |
415 | "mtrr: size: 0x%lx base: 0x%lx\n", size, base); | |
416 | dump_stack(); | |
417 | return -1; | |
418 | } | |
419 | return 0; | |
420 | } | |
421 | ||
1da177e4 LT |
422 | /** |
423 | * mtrr_add - Add a memory type region | |
424 | * @base: Physical base address of region | |
425 | * @size: Physical size of region | |
426 | * @type: Type of MTRR desired | |
427 | * @increment: If this is true do usage counting on the region | |
428 | * | |
429 | * Memory type region registers control the caching on newer Intel and | |
430 | * non Intel processors. This function allows drivers to request an | |
431 | * MTRR is added. The details and hardware specifics of each processor's | |
432 | * implementation are hidden from the caller, but nevertheless the | |
433 | * caller should expect to need to provide a power of two size on an | |
434 | * equivalent power of two boundary. | |
435 | * | |
436 | * If the region cannot be added either because all regions are in use | |
437 | * or the CPU cannot support it a negative value is returned. On success | |
438 | * the register number for this entry is returned, but should be treated | |
439 | * as a cookie only. | |
440 | * | |
441 | * On a multiprocessor machine the changes are made to all processors. | |
442 | * This is required on x86 by the Intel processors. | |
443 | * | |
444 | * The available types are | |
445 | * | |
446 | * %MTRR_TYPE_UNCACHABLE - No caching | |
447 | * | |
448 | * %MTRR_TYPE_WRBACK - Write data back in bursts whenever | |
449 | * | |
450 | * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts | |
451 | * | |
452 | * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes | |
453 | * | |
454 | * BUGS: Needs a quiet flag for the cases where drivers do not mind | |
455 | * failures and do not wish system log messages to be sent. | |
456 | */ | |
457 | ||
458 | int | |
459 | mtrr_add(unsigned long base, unsigned long size, unsigned int type, | |
2d2ee8de | 460 | bool increment) |
1da177e4 | 461 | { |
c92c6ffd | 462 | if (mtrr_check(base, size)) |
1da177e4 | 463 | return -EINVAL; |
1da177e4 LT |
464 | return mtrr_add_page(base >> PAGE_SHIFT, size >> PAGE_SHIFT, type, |
465 | increment); | |
466 | } | |
467 | ||
468 | /** | |
469 | * mtrr_del_page - delete a memory type region | |
470 | * @reg: Register returned by mtrr_add | |
471 | * @base: Physical base address | |
472 | * @size: Size of region | |
473 | * | |
474 | * If register is supplied then base and size are ignored. This is | |
475 | * how drivers should call it. | |
476 | * | |
477 | * Releases an MTRR region. If the usage count drops to zero the | |
478 | * register is freed and the region returns to default state. | |
479 | * On success the register is returned, on failure a negative error | |
480 | * code. | |
481 | */ | |
482 | ||
483 | int mtrr_del_page(int reg, unsigned long base, unsigned long size) | |
484 | { | |
485 | int i, max; | |
486 | mtrr_type ltype; | |
365bff80 | 487 | unsigned long lbase, lsize; |
1da177e4 LT |
488 | int error = -EINVAL; |
489 | ||
490 | if (!mtrr_if) | |
491 | return -ENXIO; | |
492 | ||
493 | max = num_var_ranges; | |
3b520b23 | 494 | /* No CPU hotplug when we change MTRR entries */ |
86ef5c9a | 495 | get_online_cpus(); |
14cc3e2b | 496 | mutex_lock(&mtrr_mutex); |
1da177e4 LT |
497 | if (reg < 0) { |
498 | /* Search for existing MTRR */ | |
499 | for (i = 0; i < max; ++i) { | |
500 | mtrr_if->get(i, &lbase, &lsize, <ype); | |
501 | if (lbase == base && lsize == size) { | |
502 | reg = i; | |
503 | break; | |
504 | } | |
505 | } | |
506 | if (reg < 0) { | |
507 | printk(KERN_DEBUG "mtrr: no MTRR for %lx000,%lx000 found\n", base, | |
508 | size); | |
509 | goto out; | |
510 | } | |
511 | } | |
512 | if (reg >= max) { | |
513 | printk(KERN_WARNING "mtrr: register: %d too big\n", reg); | |
514 | goto out; | |
515 | } | |
516 | if (is_cpu(CYRIX) && !use_intel()) { | |
517 | if ((reg == 3) && arr3_protected) { | |
518 | printk(KERN_WARNING "mtrr: ARR3 cannot be changed\n"); | |
519 | goto out; | |
520 | } | |
521 | } | |
522 | mtrr_if->get(reg, &lbase, &lsize, <ype); | |
523 | if (lsize < 1) { | |
524 | printk(KERN_WARNING "mtrr: MTRR %d not used\n", reg); | |
525 | goto out; | |
526 | } | |
99fc8d42 | 527 | if (mtrr_usage_table[reg] < 1) { |
1da177e4 LT |
528 | printk(KERN_WARNING "mtrr: reg: %d has count=0\n", reg); |
529 | goto out; | |
530 | } | |
99fc8d42 | 531 | if (--mtrr_usage_table[reg] < 1) |
1da177e4 LT |
532 | set_mtrr(reg, 0, 0, 0); |
533 | error = reg; | |
534 | out: | |
14cc3e2b | 535 | mutex_unlock(&mtrr_mutex); |
86ef5c9a | 536 | put_online_cpus(); |
1da177e4 LT |
537 | return error; |
538 | } | |
539 | /** | |
540 | * mtrr_del - delete a memory type region | |
541 | * @reg: Register returned by mtrr_add | |
542 | * @base: Physical base address | |
543 | * @size: Size of region | |
544 | * | |
545 | * If register is supplied then base and size are ignored. This is | |
546 | * how drivers should call it. | |
547 | * | |
548 | * Releases an MTRR region. If the usage count drops to zero the | |
549 | * register is freed and the region returns to default state. | |
550 | * On success the register is returned, on failure a negative error | |
551 | * code. | |
552 | */ | |
553 | ||
554 | int | |
555 | mtrr_del(int reg, unsigned long base, unsigned long size) | |
556 | { | |
c92c6ffd | 557 | if (mtrr_check(base, size)) |
1da177e4 | 558 | return -EINVAL; |
1da177e4 LT |
559 | return mtrr_del_page(reg, base >> PAGE_SHIFT, size >> PAGE_SHIFT); |
560 | } | |
561 | ||
562 | EXPORT_SYMBOL(mtrr_add); | |
563 | EXPORT_SYMBOL(mtrr_del); | |
564 | ||
565 | /* HACK ALERT! | |
566 | * These should be called implicitly, but we can't yet until all the initcall | |
567 | * stuff is done... | |
568 | */ | |
569 | extern void amd_init_mtrr(void); | |
570 | extern void cyrix_init_mtrr(void); | |
571 | extern void centaur_init_mtrr(void); | |
572 | ||
573 | static void __init init_ifs(void) | |
574 | { | |
475850c8 | 575 | #ifndef CONFIG_X86_64 |
1da177e4 LT |
576 | amd_init_mtrr(); |
577 | cyrix_init_mtrr(); | |
578 | centaur_init_mtrr(); | |
475850c8 | 579 | #endif |
1da177e4 LT |
580 | } |
581 | ||
3b520b23 SL |
582 | /* The suspend/resume methods are only for CPU without MTRR. CPU using generic |
583 | * MTRR driver doesn't require this | |
584 | */ | |
1da177e4 LT |
585 | struct mtrr_value { |
586 | mtrr_type ltype; | |
587 | unsigned long lbase; | |
365bff80 | 588 | unsigned long lsize; |
1da177e4 LT |
589 | }; |
590 | ||
99fc8d42 | 591 | static struct mtrr_value mtrr_state[MAX_VAR_RANGES]; |
1da177e4 | 592 | |
829ca9a3 | 593 | static int mtrr_save(struct sys_device * sysdev, pm_message_t state) |
1da177e4 LT |
594 | { |
595 | int i; | |
1da177e4 LT |
596 | |
597 | for (i = 0; i < num_var_ranges; i++) { | |
598 | mtrr_if->get(i, | |
599 | &mtrr_state[i].lbase, | |
600 | &mtrr_state[i].lsize, | |
601 | &mtrr_state[i].ltype); | |
602 | } | |
603 | return 0; | |
604 | } | |
605 | ||
606 | static int mtrr_restore(struct sys_device * sysdev) | |
607 | { | |
608 | int i; | |
609 | ||
610 | for (i = 0; i < num_var_ranges; i++) { | |
611 | if (mtrr_state[i].lsize) | |
612 | set_mtrr(i, | |
613 | mtrr_state[i].lbase, | |
614 | mtrr_state[i].lsize, | |
615 | mtrr_state[i].ltype); | |
616 | } | |
1da177e4 LT |
617 | return 0; |
618 | } | |
619 | ||
620 | ||
621 | ||
622 | static struct sysdev_driver mtrr_sysdev_driver = { | |
623 | .suspend = mtrr_save, | |
624 | .resume = mtrr_restore, | |
625 | }; | |
626 | ||
99fc8d42 JB |
627 | #ifdef CONFIG_X86_64 |
628 | static int disable_mtrr_trim; | |
629 | ||
630 | static int __init disable_mtrr_trim_setup(char *str) | |
631 | { | |
632 | disable_mtrr_trim = 1; | |
633 | return 0; | |
634 | } | |
635 | early_param("disable_mtrr_trim", disable_mtrr_trim_setup); | |
636 | ||
637 | /* | |
638 | * Newer AMD K8s and later CPUs have a special magic MSR way to force WB | |
639 | * for memory >4GB. Check for that here. | |
640 | * Note this won't check if the MTRRs < 4GB where the magic bit doesn't | |
641 | * apply to are wrong, but so far we don't know of any such case in the wild. | |
642 | */ | |
643 | #define Tom2Enabled (1U << 21) | |
644 | #define Tom2ForceMemTypeWB (1U << 22) | |
645 | ||
646 | static __init int amd_special_default_mtrr(unsigned long end_pfn) | |
647 | { | |
648 | u32 l, h; | |
649 | ||
650 | /* Doesn't apply to memory < 4GB */ | |
651 | if (end_pfn <= (0xffffffff >> PAGE_SHIFT)) | |
652 | return 0; | |
653 | if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) | |
654 | return 0; | |
655 | if (boot_cpu_data.x86 < 0xf || boot_cpu_data.x86 > 0x11) | |
656 | return 0; | |
657 | /* In case some hypervisor doesn't pass SYSCFG through */ | |
658 | if (rdmsr_safe(MSR_K8_SYSCFG, &l, &h) < 0) | |
659 | return 0; | |
660 | /* | |
661 | * Memory between 4GB and top of mem is forced WB by this magic bit. | |
662 | * Reserved before K8RevF, but should be zero there. | |
663 | */ | |
664 | if ((l & (Tom2Enabled | Tom2ForceMemTypeWB)) == | |
665 | (Tom2Enabled | Tom2ForceMemTypeWB)) | |
666 | return 1; | |
667 | return 0; | |
668 | } | |
669 | ||
670 | /** | |
671 | * mtrr_trim_uncached_memory - trim RAM not covered by MTRRs | |
672 | * | |
673 | * Some buggy BIOSes don't setup the MTRRs properly for systems with certain | |
674 | * memory configurations. This routine checks that the highest MTRR matches | |
675 | * the end of memory, to make sure the MTRRs having a write back type cover | |
676 | * all of the memory the kernel is intending to use. If not, it'll trim any | |
677 | * memory off the end by adjusting end_pfn, removing it from the kernel's | |
678 | * allocation pools, warning the user with an obnoxious message. | |
679 | */ | |
680 | int __init mtrr_trim_uncached_memory(unsigned long end_pfn) | |
681 | { | |
682 | unsigned long i, base, size, highest_addr = 0, def, dummy; | |
683 | mtrr_type type; | |
684 | u64 trim_start, trim_size; | |
685 | ||
686 | /* | |
687 | * Make sure we only trim uncachable memory on machines that | |
688 | * support the Intel MTRR architecture: | |
689 | */ | |
690 | rdmsr(MTRRdefType_MSR, def, dummy); | |
691 | def &= 0xff; | |
692 | if (!is_cpu(INTEL) || disable_mtrr_trim || def != MTRR_TYPE_UNCACHABLE) | |
693 | return 0; | |
694 | ||
695 | /* Find highest cached pfn */ | |
696 | for (i = 0; i < num_var_ranges; i++) { | |
697 | mtrr_if->get(i, &base, &size, &type); | |
698 | if (type != MTRR_TYPE_WRBACK) | |
699 | continue; | |
700 | base <<= PAGE_SHIFT; | |
701 | size <<= PAGE_SHIFT; | |
702 | if (highest_addr < base + size) | |
703 | highest_addr = base + size; | |
704 | } | |
705 | ||
706 | if (amd_special_default_mtrr(end_pfn)) | |
707 | return 0; | |
708 | ||
709 | if ((highest_addr >> PAGE_SHIFT) < end_pfn) { | |
710 | printk(KERN_WARNING "***************\n"); | |
711 | printk(KERN_WARNING "**** WARNING: likely BIOS bug\n"); | |
712 | printk(KERN_WARNING "**** MTRRs don't cover all of " | |
713 | "memory, trimmed %ld pages\n", end_pfn - | |
714 | (highest_addr >> PAGE_SHIFT)); | |
715 | printk(KERN_WARNING "***************\n"); | |
716 | ||
717 | printk(KERN_INFO "update e820 for mtrr\n"); | |
718 | trim_start = highest_addr; | |
719 | trim_size = end_pfn; | |
720 | trim_size <<= PAGE_SHIFT; | |
721 | trim_size -= trim_start; | |
722 | add_memory_region(trim_start, trim_size, E820_RESERVED); | |
723 | update_e820(); | |
724 | return 1; | |
725 | } | |
726 | ||
727 | return 0; | |
728 | } | |
729 | #endif | |
1da177e4 LT |
730 | |
731 | /** | |
3b520b23 | 732 | * mtrr_bp_init - initialize mtrrs on the boot CPU |
1da177e4 LT |
733 | * |
734 | * This needs to be called early; before any of the other CPUs are | |
735 | * initialized (i.e. before smp_init()). | |
736 | * | |
737 | */ | |
9ef231a4 | 738 | void __init mtrr_bp_init(void) |
1da177e4 LT |
739 | { |
740 | init_ifs(); | |
741 | ||
742 | if (cpu_has_mtrr) { | |
743 | mtrr_if = &generic_mtrr_ops; | |
744 | size_or_mask = 0xff000000; /* 36 bits */ | |
745 | size_and_mask = 0x00f00000; | |
1f2c958a AK |
746 | |
747 | /* This is an AMD specific MSR, but we assume(hope?) that | |
748 | Intel will implement it to when they extend the address | |
749 | bus of the Xeon. */ | |
750 | if (cpuid_eax(0x80000000) >= 0x80000008) { | |
751 | u32 phys_addr; | |
752 | phys_addr = cpuid_eax(0x80000008) & 0xff; | |
af9c142d SL |
753 | /* CPUID workaround for Intel 0F33/0F34 CPU */ |
754 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | |
755 | boot_cpu_data.x86 == 0xF && | |
756 | boot_cpu_data.x86_model == 0x3 && | |
757 | (boot_cpu_data.x86_mask == 0x3 || | |
758 | boot_cpu_data.x86_mask == 0x4)) | |
759 | phys_addr = 36; | |
760 | ||
6c5806ca AH |
761 | size_or_mask = ~((1ULL << (phys_addr - PAGE_SHIFT)) - 1); |
762 | size_and_mask = ~size_or_mask & 0xfffff00000ULL; | |
1f2c958a AK |
763 | } else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR && |
764 | boot_cpu_data.x86 == 6) { | |
765 | /* VIA C* family have Intel style MTRRs, but | |
766 | don't support PAE */ | |
767 | size_or_mask = 0xfff00000; /* 32 bits */ | |
768 | size_and_mask = 0; | |
1da177e4 LT |
769 | } |
770 | } else { | |
771 | switch (boot_cpu_data.x86_vendor) { | |
772 | case X86_VENDOR_AMD: | |
773 | if (cpu_has_k6_mtrr) { | |
774 | /* Pre-Athlon (K6) AMD CPU MTRRs */ | |
775 | mtrr_if = mtrr_ops[X86_VENDOR_AMD]; | |
776 | size_or_mask = 0xfff00000; /* 32 bits */ | |
777 | size_and_mask = 0; | |
778 | } | |
779 | break; | |
780 | case X86_VENDOR_CENTAUR: | |
781 | if (cpu_has_centaur_mcr) { | |
782 | mtrr_if = mtrr_ops[X86_VENDOR_CENTAUR]; | |
783 | size_or_mask = 0xfff00000; /* 32 bits */ | |
784 | size_and_mask = 0; | |
785 | } | |
786 | break; | |
787 | case X86_VENDOR_CYRIX: | |
788 | if (cpu_has_cyrix_arr) { | |
789 | mtrr_if = mtrr_ops[X86_VENDOR_CYRIX]; | |
790 | size_or_mask = 0xfff00000; /* 32 bits */ | |
791 | size_and_mask = 0; | |
792 | } | |
793 | break; | |
794 | default: | |
795 | break; | |
796 | } | |
797 | } | |
1da177e4 LT |
798 | |
799 | if (mtrr_if) { | |
800 | set_num_var_ranges(); | |
801 | init_table(); | |
3b520b23 SL |
802 | if (use_intel()) |
803 | get_mtrr_state(); | |
1da177e4 | 804 | } |
1da177e4 LT |
805 | } |
806 | ||
3b520b23 SL |
807 | void mtrr_ap_init(void) |
808 | { | |
809 | unsigned long flags; | |
810 | ||
811 | if (!mtrr_if || !use_intel()) | |
812 | return; | |
813 | /* | |
14cc3e2b | 814 | * Ideally we should hold mtrr_mutex here to avoid mtrr entries changed, |
3b520b23 SL |
815 | * but this routine will be called in cpu boot time, holding the lock |
816 | * breaks it. This routine is called in two cases: 1.very earily time | |
817 | * of software resume, when there absolutely isn't mtrr entry changes; | |
818 | * 2.cpu hotadd time. We let mtrr_add/del_page hold cpuhotplug lock to | |
819 | * prevent mtrr entry changes | |
820 | */ | |
821 | local_irq_save(flags); | |
822 | ||
823 | mtrr_if->set_all(); | |
824 | ||
825 | local_irq_restore(flags); | |
826 | } | |
827 | ||
2b1f6278 BK |
828 | /** |
829 | * Save current fixed-range MTRR state of the BSP | |
830 | */ | |
831 | void mtrr_save_state(void) | |
832 | { | |
c8f2518e | 833 | smp_call_function_single(0, mtrr_save_fixed_ranges, NULL, 1, 1); |
2b1f6278 BK |
834 | } |
835 | ||
3b520b23 SL |
836 | static int __init mtrr_init_finialize(void) |
837 | { | |
838 | if (!mtrr_if) | |
839 | return 0; | |
840 | if (use_intel()) | |
841 | mtrr_state_warn(); | |
842 | else { | |
27b46d76 | 843 | /* The CPUs haven't MTRR and seem to not support SMP. They have |
3b520b23 SL |
844 | * specific drivers, we use a tricky method to support |
845 | * suspend/resume for them. | |
846 | * TBD: is there any system with such CPU which supports | |
847 | * suspend/resume? if no, we should remove the code. | |
848 | */ | |
849 | sysdev_driver_register(&cpu_sysdev_class, | |
850 | &mtrr_sysdev_driver); | |
851 | } | |
852 | return 0; | |
853 | } | |
854 | subsys_initcall(mtrr_init_finialize); |