Commit | Line | Data |
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1da177e4 LT |
1 | /* Generic MTRR (Memory Type Range Register) driver. |
2 | ||
3 | Copyright (C) 1997-2000 Richard Gooch | |
4 | Copyright (c) 2002 Patrick Mochel | |
5 | ||
6 | This library is free software; you can redistribute it and/or | |
7 | modify it under the terms of the GNU Library General Public | |
8 | License as published by the Free Software Foundation; either | |
9 | version 2 of the License, or (at your option) any later version. | |
10 | ||
11 | This library is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | Library General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU Library General Public | |
17 | License along with this library; if not, write to the Free | |
18 | Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | ||
20 | Richard Gooch may be reached by email at rgooch@atnf.csiro.au | |
21 | The postal address is: | |
22 | Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia. | |
23 | ||
24 | Source: "Pentium Pro Family Developer's Manual, Volume 3: | |
25 | Operating System Writer's Guide" (Intel document number 242692), | |
26 | section 11.11.7 | |
27 | ||
28 | This was cleaned and made readable by Patrick Mochel <mochel@osdl.org> | |
29 | on 6-7 March 2002. | |
30 | Source: Intel Architecture Software Developers Manual, Volume 3: | |
31 | System Programming Guide; Section 9.11. (1997 edition - PPro). | |
32 | */ | |
33 | ||
34 | #include <linux/module.h> | |
35 | #include <linux/init.h> | |
36 | #include <linux/pci.h> | |
37 | #include <linux/smp.h> | |
38 | #include <linux/cpu.h> | |
14cc3e2b | 39 | #include <linux/mutex.h> |
1da177e4 | 40 | |
99fc8d42 | 41 | #include <asm/e820.h> |
1da177e4 | 42 | #include <asm/mtrr.h> |
1da177e4 LT |
43 | #include <asm/uaccess.h> |
44 | #include <asm/processor.h> | |
45 | #include <asm/msr.h> | |
46 | #include "mtrr.h" | |
47 | ||
1da177e4 LT |
48 | u32 num_var_ranges = 0; |
49 | ||
99fc8d42 | 50 | unsigned int mtrr_usage_table[MAX_VAR_RANGES]; |
14cc3e2b | 51 | static DEFINE_MUTEX(mtrr_mutex); |
1da177e4 | 52 | |
6c5806ca | 53 | u64 size_or_mask, size_and_mask; |
1da177e4 LT |
54 | |
55 | static struct mtrr_ops * mtrr_ops[X86_VENDOR_NUM] = {}; | |
56 | ||
57 | struct mtrr_ops * mtrr_if = NULL; | |
58 | ||
59 | static void set_mtrr(unsigned int reg, unsigned long base, | |
60 | unsigned long size, mtrr_type type); | |
61 | ||
1da177e4 LT |
62 | void set_mtrr_ops(struct mtrr_ops * ops) |
63 | { | |
64 | if (ops->vendor && ops->vendor < X86_VENDOR_NUM) | |
65 | mtrr_ops[ops->vendor] = ops; | |
66 | } | |
67 | ||
68 | /* Returns non-zero if we have the write-combining memory type */ | |
69 | static int have_wrcomb(void) | |
70 | { | |
71 | struct pci_dev *dev; | |
a6954ba2 | 72 | u8 rev; |
1da177e4 LT |
73 | |
74 | if ((dev = pci_get_class(PCI_CLASS_BRIDGE_HOST << 8, NULL)) != NULL) { | |
a6954ba2 | 75 | /* ServerWorks LE chipsets < rev 6 have problems with write-combining |
1da177e4 LT |
76 | Don't allow it and leave room for other chipsets to be tagged */ |
77 | if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS && | |
78 | dev->device == PCI_DEVICE_ID_SERVERWORKS_LE) { | |
a6954ba2 LR |
79 | pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev); |
80 | if (rev <= 5) { | |
81 | printk(KERN_INFO "mtrr: Serverworks LE rev < 6 detected. Write-combining disabled.\n"); | |
82 | pci_dev_put(dev); | |
83 | return 0; | |
84 | } | |
1da177e4 | 85 | } |
a6954ba2 | 86 | /* Intel 450NX errata # 23. Non ascending cacheline evictions to |
1da177e4 LT |
87 | write combining memory may resulting in data corruption */ |
88 | if (dev->vendor == PCI_VENDOR_ID_INTEL && | |
89 | dev->device == PCI_DEVICE_ID_INTEL_82451NX) { | |
90 | printk(KERN_INFO "mtrr: Intel 450NX MMC detected. Write-combining disabled.\n"); | |
91 | pci_dev_put(dev); | |
92 | return 0; | |
93 | } | |
94 | pci_dev_put(dev); | |
95 | } | |
96 | return (mtrr_if->have_wrcomb ? mtrr_if->have_wrcomb() : 0); | |
97 | } | |
98 | ||
99 | /* This function returns the number of variable MTRRs */ | |
100 | static void __init set_num_var_ranges(void) | |
101 | { | |
102 | unsigned long config = 0, dummy; | |
103 | ||
104 | if (use_intel()) { | |
105 | rdmsr(MTRRcap_MSR, config, dummy); | |
106 | } else if (is_cpu(AMD)) | |
107 | config = 2; | |
108 | else if (is_cpu(CYRIX) || is_cpu(CENTAUR)) | |
109 | config = 8; | |
110 | num_var_ranges = config & 0xff; | |
111 | } | |
112 | ||
113 | static void __init init_table(void) | |
114 | { | |
115 | int i, max; | |
116 | ||
117 | max = num_var_ranges; | |
1da177e4 | 118 | for (i = 0; i < max; i++) |
99fc8d42 | 119 | mtrr_usage_table[i] = 1; |
1da177e4 LT |
120 | } |
121 | ||
122 | struct set_mtrr_data { | |
123 | atomic_t count; | |
124 | atomic_t gate; | |
125 | unsigned long smp_base; | |
126 | unsigned long smp_size; | |
127 | unsigned int smp_reg; | |
128 | mtrr_type smp_type; | |
129 | }; | |
130 | ||
1da177e4 LT |
131 | static void ipi_handler(void *info) |
132 | /* [SUMMARY] Synchronisation handler. Executed by "other" CPUs. | |
133 | [RETURNS] Nothing. | |
134 | */ | |
135 | { | |
4e2947f1 | 136 | #ifdef CONFIG_SMP |
1da177e4 LT |
137 | struct set_mtrr_data *data = info; |
138 | unsigned long flags; | |
139 | ||
140 | local_irq_save(flags); | |
141 | ||
142 | atomic_dec(&data->count); | |
143 | while(!atomic_read(&data->gate)) | |
144 | cpu_relax(); | |
145 | ||
146 | /* The master has cleared me to execute */ | |
147 | if (data->smp_reg != ~0U) | |
148 | mtrr_if->set(data->smp_reg, data->smp_base, | |
149 | data->smp_size, data->smp_type); | |
150 | else | |
151 | mtrr_if->set_all(); | |
152 | ||
153 | atomic_dec(&data->count); | |
154 | while(atomic_read(&data->gate)) | |
155 | cpu_relax(); | |
156 | ||
157 | atomic_dec(&data->count); | |
158 | local_irq_restore(flags); | |
1da177e4 | 159 | #endif |
4e2947f1 | 160 | } |
1da177e4 | 161 | |
365bff80 JB |
162 | static inline int types_compatible(mtrr_type type1, mtrr_type type2) { |
163 | return type1 == MTRR_TYPE_UNCACHABLE || | |
164 | type2 == MTRR_TYPE_UNCACHABLE || | |
165 | (type1 == MTRR_TYPE_WRTHROUGH && type2 == MTRR_TYPE_WRBACK) || | |
166 | (type1 == MTRR_TYPE_WRBACK && type2 == MTRR_TYPE_WRTHROUGH); | |
167 | } | |
168 | ||
1da177e4 LT |
169 | /** |
170 | * set_mtrr - update mtrrs on all processors | |
171 | * @reg: mtrr in question | |
172 | * @base: mtrr base | |
173 | * @size: mtrr size | |
174 | * @type: mtrr type | |
175 | * | |
176 | * This is kinda tricky, but fortunately, Intel spelled it out for us cleanly: | |
177 | * | |
178 | * 1. Send IPI to do the following: | |
179 | * 2. Disable Interrupts | |
180 | * 3. Wait for all procs to do so | |
181 | * 4. Enter no-fill cache mode | |
182 | * 5. Flush caches | |
183 | * 6. Clear PGE bit | |
184 | * 7. Flush all TLBs | |
185 | * 8. Disable all range registers | |
186 | * 9. Update the MTRRs | |
187 | * 10. Enable all range registers | |
188 | * 11. Flush all TLBs and caches again | |
189 | * 12. Enter normal cache mode and reenable caching | |
190 | * 13. Set PGE | |
191 | * 14. Wait for buddies to catch up | |
192 | * 15. Enable interrupts. | |
193 | * | |
194 | * What does that mean for us? Well, first we set data.count to the number | |
195 | * of CPUs. As each CPU disables interrupts, it'll decrement it once. We wait | |
196 | * until it hits 0 and proceed. We set the data.gate flag and reset data.count. | |
197 | * Meanwhile, they are waiting for that flag to be set. Once it's set, each | |
198 | * CPU goes through the transition of updating MTRRs. The CPU vendors may each do it | |
199 | * differently, so we call mtrr_if->set() callback and let them take care of it. | |
200 | * When they're done, they again decrement data->count and wait for data.gate to | |
201 | * be reset. | |
202 | * When we finish, we wait for data.count to hit 0 and toggle the data.gate flag. | |
203 | * Everyone then enables interrupts and we all continue on. | |
204 | * | |
205 | * Note that the mechanism is the same for UP systems, too; all the SMP stuff | |
206 | * becomes nops. | |
207 | */ | |
208 | static void set_mtrr(unsigned int reg, unsigned long base, | |
209 | unsigned long size, mtrr_type type) | |
210 | { | |
211 | struct set_mtrr_data data; | |
212 | unsigned long flags; | |
213 | ||
214 | data.smp_reg = reg; | |
215 | data.smp_base = base; | |
216 | data.smp_size = size; | |
217 | data.smp_type = type; | |
218 | atomic_set(&data.count, num_booting_cpus() - 1); | |
d25c1ba2 LP |
219 | /* make sure data.count is visible before unleashing other CPUs */ |
220 | smp_wmb(); | |
1da177e4 LT |
221 | atomic_set(&data.gate,0); |
222 | ||
223 | /* Start the ball rolling on other CPUs */ | |
224 | if (smp_call_function(ipi_handler, &data, 1, 0) != 0) | |
225 | panic("mtrr: timed out waiting for other CPUs\n"); | |
226 | ||
227 | local_irq_save(flags); | |
228 | ||
229 | while(atomic_read(&data.count)) | |
230 | cpu_relax(); | |
231 | ||
232 | /* ok, reset count and toggle gate */ | |
233 | atomic_set(&data.count, num_booting_cpus() - 1); | |
d25c1ba2 | 234 | smp_wmb(); |
1da177e4 LT |
235 | atomic_set(&data.gate,1); |
236 | ||
237 | /* do our MTRR business */ | |
238 | ||
239 | /* HACK! | |
240 | * We use this same function to initialize the mtrrs on boot. | |
241 | * The state of the boot cpu's mtrrs has been saved, and we want | |
242 | * to replicate across all the APs. | |
243 | * If we're doing that @reg is set to something special... | |
244 | */ | |
245 | if (reg != ~0U) | |
246 | mtrr_if->set(reg,base,size,type); | |
247 | ||
248 | /* wait for the others */ | |
249 | while(atomic_read(&data.count)) | |
250 | cpu_relax(); | |
251 | ||
252 | atomic_set(&data.count, num_booting_cpus() - 1); | |
d25c1ba2 | 253 | smp_wmb(); |
1da177e4 LT |
254 | atomic_set(&data.gate,0); |
255 | ||
256 | /* | |
257 | * Wait here for everyone to have seen the gate change | |
258 | * So we're the last ones to touch 'data' | |
259 | */ | |
260 | while(atomic_read(&data.count)) | |
261 | cpu_relax(); | |
262 | ||
263 | local_irq_restore(flags); | |
264 | } | |
265 | ||
266 | /** | |
267 | * mtrr_add_page - Add a memory type region | |
9b483417 AM |
268 | * @base: Physical base address of region in pages (in units of 4 kB!) |
269 | * @size: Physical size of region in pages (4 kB) | |
1da177e4 LT |
270 | * @type: Type of MTRR desired |
271 | * @increment: If this is true do usage counting on the region | |
272 | * | |
273 | * Memory type region registers control the caching on newer Intel and | |
274 | * non Intel processors. This function allows drivers to request an | |
275 | * MTRR is added. The details and hardware specifics of each processor's | |
276 | * implementation are hidden from the caller, but nevertheless the | |
277 | * caller should expect to need to provide a power of two size on an | |
278 | * equivalent power of two boundary. | |
279 | * | |
280 | * If the region cannot be added either because all regions are in use | |
281 | * or the CPU cannot support it a negative value is returned. On success | |
282 | * the register number for this entry is returned, but should be treated | |
283 | * as a cookie only. | |
284 | * | |
285 | * On a multiprocessor machine the changes are made to all processors. | |
286 | * This is required on x86 by the Intel processors. | |
287 | * | |
288 | * The available types are | |
289 | * | |
290 | * %MTRR_TYPE_UNCACHABLE - No caching | |
291 | * | |
292 | * %MTRR_TYPE_WRBACK - Write data back in bursts whenever | |
293 | * | |
294 | * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts | |
295 | * | |
296 | * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes | |
297 | * | |
298 | * BUGS: Needs a quiet flag for the cases where drivers do not mind | |
299 | * failures and do not wish system log messages to be sent. | |
300 | */ | |
301 | ||
302 | int mtrr_add_page(unsigned long base, unsigned long size, | |
2d2ee8de | 303 | unsigned int type, bool increment) |
1da177e4 | 304 | { |
365bff80 | 305 | int i, replace, error; |
1da177e4 | 306 | mtrr_type ltype; |
365bff80 | 307 | unsigned long lbase, lsize; |
1da177e4 LT |
308 | |
309 | if (!mtrr_if) | |
310 | return -ENXIO; | |
311 | ||
312 | if ((error = mtrr_if->validate_add_page(base,size,type))) | |
313 | return error; | |
314 | ||
315 | if (type >= MTRR_NUM_TYPES) { | |
316 | printk(KERN_WARNING "mtrr: type: %u invalid\n", type); | |
317 | return -EINVAL; | |
318 | } | |
319 | ||
320 | /* If the type is WC, check that this processor supports it */ | |
321 | if ((type == MTRR_TYPE_WRCOMB) && !have_wrcomb()) { | |
322 | printk(KERN_WARNING | |
323 | "mtrr: your processor doesn't support write-combining\n"); | |
324 | return -ENOSYS; | |
325 | } | |
326 | ||
365bff80 JB |
327 | if (!size) { |
328 | printk(KERN_WARNING "mtrr: zero sized request\n"); | |
329 | return -EINVAL; | |
330 | } | |
331 | ||
1da177e4 LT |
332 | if (base & size_or_mask || size & size_or_mask) { |
333 | printk(KERN_WARNING "mtrr: base or size exceeds the MTRR width\n"); | |
334 | return -EINVAL; | |
335 | } | |
336 | ||
337 | error = -EINVAL; | |
365bff80 | 338 | replace = -1; |
1da177e4 | 339 | |
3b520b23 | 340 | /* No CPU hotplug when we change MTRR entries */ |
86ef5c9a | 341 | get_online_cpus(); |
1da177e4 | 342 | /* Search for existing MTRR */ |
14cc3e2b | 343 | mutex_lock(&mtrr_mutex); |
1da177e4 LT |
344 | for (i = 0; i < num_var_ranges; ++i) { |
345 | mtrr_if->get(i, &lbase, &lsize, <ype); | |
365bff80 | 346 | if (!lsize || base > lbase + lsize - 1 || base + size - 1 < lbase) |
1da177e4 LT |
347 | continue; |
348 | /* At this point we know there is some kind of overlap/enclosure */ | |
365bff80 JB |
349 | if (base < lbase || base + size - 1 > lbase + lsize - 1) { |
350 | if (base <= lbase && base + size - 1 >= lbase + lsize - 1) { | |
351 | /* New region encloses an existing region */ | |
352 | if (type == ltype) { | |
353 | replace = replace == -1 ? i : -2; | |
354 | continue; | |
355 | } | |
356 | else if (types_compatible(type, ltype)) | |
357 | continue; | |
358 | } | |
1da177e4 LT |
359 | printk(KERN_WARNING |
360 | "mtrr: 0x%lx000,0x%lx000 overlaps existing" | |
365bff80 | 361 | " 0x%lx000,0x%lx000\n", base, size, lbase, |
1da177e4 LT |
362 | lsize); |
363 | goto out; | |
364 | } | |
365 | /* New region is enclosed by an existing region */ | |
366 | if (ltype != type) { | |
365bff80 | 367 | if (types_compatible(type, ltype)) |
1da177e4 LT |
368 | continue; |
369 | printk (KERN_WARNING "mtrr: type mismatch for %lx000,%lx000 old: %s new: %s\n", | |
370 | base, size, mtrr_attrib_to_str(ltype), | |
371 | mtrr_attrib_to_str(type)); | |
372 | goto out; | |
373 | } | |
374 | if (increment) | |
99fc8d42 | 375 | ++mtrr_usage_table[i]; |
1da177e4 LT |
376 | error = i; |
377 | goto out; | |
378 | } | |
379 | /* Search for an empty MTRR */ | |
365bff80 | 380 | i = mtrr_if->get_free_region(base, size, replace); |
1da177e4 LT |
381 | if (i >= 0) { |
382 | set_mtrr(i, base, size, type); | |
99fc8d42 JB |
383 | if (likely(replace < 0)) { |
384 | mtrr_usage_table[i] = 1; | |
385 | } else { | |
386 | mtrr_usage_table[i] = mtrr_usage_table[replace]; | |
2d2ee8de | 387 | if (increment) |
99fc8d42 | 388 | mtrr_usage_table[i]++; |
365bff80 JB |
389 | if (unlikely(replace != i)) { |
390 | set_mtrr(replace, 0, 0, 0); | |
99fc8d42 | 391 | mtrr_usage_table[replace] = 0; |
365bff80 JB |
392 | } |
393 | } | |
1da177e4 LT |
394 | } else |
395 | printk(KERN_INFO "mtrr: no more MTRRs available\n"); | |
396 | error = i; | |
397 | out: | |
14cc3e2b | 398 | mutex_unlock(&mtrr_mutex); |
86ef5c9a | 399 | put_online_cpus(); |
1da177e4 LT |
400 | return error; |
401 | } | |
402 | ||
c92c6ffd AM |
403 | static int mtrr_check(unsigned long base, unsigned long size) |
404 | { | |
405 | if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) { | |
406 | printk(KERN_WARNING | |
407 | "mtrr: size and base must be multiples of 4 kiB\n"); | |
408 | printk(KERN_DEBUG | |
409 | "mtrr: size: 0x%lx base: 0x%lx\n", size, base); | |
410 | dump_stack(); | |
411 | return -1; | |
412 | } | |
413 | return 0; | |
414 | } | |
415 | ||
1da177e4 LT |
416 | /** |
417 | * mtrr_add - Add a memory type region | |
418 | * @base: Physical base address of region | |
419 | * @size: Physical size of region | |
420 | * @type: Type of MTRR desired | |
421 | * @increment: If this is true do usage counting on the region | |
422 | * | |
423 | * Memory type region registers control the caching on newer Intel and | |
424 | * non Intel processors. This function allows drivers to request an | |
425 | * MTRR is added. The details and hardware specifics of each processor's | |
426 | * implementation are hidden from the caller, but nevertheless the | |
427 | * caller should expect to need to provide a power of two size on an | |
428 | * equivalent power of two boundary. | |
429 | * | |
430 | * If the region cannot be added either because all regions are in use | |
431 | * or the CPU cannot support it a negative value is returned. On success | |
432 | * the register number for this entry is returned, but should be treated | |
433 | * as a cookie only. | |
434 | * | |
435 | * On a multiprocessor machine the changes are made to all processors. | |
436 | * This is required on x86 by the Intel processors. | |
437 | * | |
438 | * The available types are | |
439 | * | |
440 | * %MTRR_TYPE_UNCACHABLE - No caching | |
441 | * | |
442 | * %MTRR_TYPE_WRBACK - Write data back in bursts whenever | |
443 | * | |
444 | * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts | |
445 | * | |
446 | * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes | |
447 | * | |
448 | * BUGS: Needs a quiet flag for the cases where drivers do not mind | |
449 | * failures and do not wish system log messages to be sent. | |
450 | */ | |
451 | ||
452 | int | |
453 | mtrr_add(unsigned long base, unsigned long size, unsigned int type, | |
2d2ee8de | 454 | bool increment) |
1da177e4 | 455 | { |
c92c6ffd | 456 | if (mtrr_check(base, size)) |
1da177e4 | 457 | return -EINVAL; |
1da177e4 LT |
458 | return mtrr_add_page(base >> PAGE_SHIFT, size >> PAGE_SHIFT, type, |
459 | increment); | |
460 | } | |
461 | ||
462 | /** | |
463 | * mtrr_del_page - delete a memory type region | |
464 | * @reg: Register returned by mtrr_add | |
465 | * @base: Physical base address | |
466 | * @size: Size of region | |
467 | * | |
468 | * If register is supplied then base and size are ignored. This is | |
469 | * how drivers should call it. | |
470 | * | |
471 | * Releases an MTRR region. If the usage count drops to zero the | |
472 | * register is freed and the region returns to default state. | |
473 | * On success the register is returned, on failure a negative error | |
474 | * code. | |
475 | */ | |
476 | ||
477 | int mtrr_del_page(int reg, unsigned long base, unsigned long size) | |
478 | { | |
479 | int i, max; | |
480 | mtrr_type ltype; | |
365bff80 | 481 | unsigned long lbase, lsize; |
1da177e4 LT |
482 | int error = -EINVAL; |
483 | ||
484 | if (!mtrr_if) | |
485 | return -ENXIO; | |
486 | ||
487 | max = num_var_ranges; | |
3b520b23 | 488 | /* No CPU hotplug when we change MTRR entries */ |
86ef5c9a | 489 | get_online_cpus(); |
14cc3e2b | 490 | mutex_lock(&mtrr_mutex); |
1da177e4 LT |
491 | if (reg < 0) { |
492 | /* Search for existing MTRR */ | |
493 | for (i = 0; i < max; ++i) { | |
494 | mtrr_if->get(i, &lbase, &lsize, <ype); | |
495 | if (lbase == base && lsize == size) { | |
496 | reg = i; | |
497 | break; | |
498 | } | |
499 | } | |
500 | if (reg < 0) { | |
501 | printk(KERN_DEBUG "mtrr: no MTRR for %lx000,%lx000 found\n", base, | |
502 | size); | |
503 | goto out; | |
504 | } | |
505 | } | |
506 | if (reg >= max) { | |
507 | printk(KERN_WARNING "mtrr: register: %d too big\n", reg); | |
508 | goto out; | |
509 | } | |
1da177e4 LT |
510 | mtrr_if->get(reg, &lbase, &lsize, <ype); |
511 | if (lsize < 1) { | |
512 | printk(KERN_WARNING "mtrr: MTRR %d not used\n", reg); | |
513 | goto out; | |
514 | } | |
99fc8d42 | 515 | if (mtrr_usage_table[reg] < 1) { |
1da177e4 LT |
516 | printk(KERN_WARNING "mtrr: reg: %d has count=0\n", reg); |
517 | goto out; | |
518 | } | |
99fc8d42 | 519 | if (--mtrr_usage_table[reg] < 1) |
1da177e4 LT |
520 | set_mtrr(reg, 0, 0, 0); |
521 | error = reg; | |
522 | out: | |
14cc3e2b | 523 | mutex_unlock(&mtrr_mutex); |
86ef5c9a | 524 | put_online_cpus(); |
1da177e4 LT |
525 | return error; |
526 | } | |
527 | /** | |
528 | * mtrr_del - delete a memory type region | |
529 | * @reg: Register returned by mtrr_add | |
530 | * @base: Physical base address | |
531 | * @size: Size of region | |
532 | * | |
533 | * If register is supplied then base and size are ignored. This is | |
534 | * how drivers should call it. | |
535 | * | |
536 | * Releases an MTRR region. If the usage count drops to zero the | |
537 | * register is freed and the region returns to default state. | |
538 | * On success the register is returned, on failure a negative error | |
539 | * code. | |
540 | */ | |
541 | ||
542 | int | |
543 | mtrr_del(int reg, unsigned long base, unsigned long size) | |
544 | { | |
c92c6ffd | 545 | if (mtrr_check(base, size)) |
1da177e4 | 546 | return -EINVAL; |
1da177e4 LT |
547 | return mtrr_del_page(reg, base >> PAGE_SHIFT, size >> PAGE_SHIFT); |
548 | } | |
549 | ||
550 | EXPORT_SYMBOL(mtrr_add); | |
551 | EXPORT_SYMBOL(mtrr_del); | |
552 | ||
553 | /* HACK ALERT! | |
554 | * These should be called implicitly, but we can't yet until all the initcall | |
555 | * stuff is done... | |
556 | */ | |
1da177e4 LT |
557 | static void __init init_ifs(void) |
558 | { | |
475850c8 | 559 | #ifndef CONFIG_X86_64 |
1da177e4 LT |
560 | amd_init_mtrr(); |
561 | cyrix_init_mtrr(); | |
562 | centaur_init_mtrr(); | |
475850c8 | 563 | #endif |
1da177e4 LT |
564 | } |
565 | ||
3b520b23 SL |
566 | /* The suspend/resume methods are only for CPU without MTRR. CPU using generic |
567 | * MTRR driver doesn't require this | |
568 | */ | |
1da177e4 LT |
569 | struct mtrr_value { |
570 | mtrr_type ltype; | |
571 | unsigned long lbase; | |
365bff80 | 572 | unsigned long lsize; |
1da177e4 LT |
573 | }; |
574 | ||
99fc8d42 | 575 | static struct mtrr_value mtrr_state[MAX_VAR_RANGES]; |
1da177e4 | 576 | |
829ca9a3 | 577 | static int mtrr_save(struct sys_device * sysdev, pm_message_t state) |
1da177e4 LT |
578 | { |
579 | int i; | |
1da177e4 LT |
580 | |
581 | for (i = 0; i < num_var_ranges; i++) { | |
582 | mtrr_if->get(i, | |
583 | &mtrr_state[i].lbase, | |
584 | &mtrr_state[i].lsize, | |
585 | &mtrr_state[i].ltype); | |
586 | } | |
587 | return 0; | |
588 | } | |
589 | ||
590 | static int mtrr_restore(struct sys_device * sysdev) | |
591 | { | |
592 | int i; | |
593 | ||
594 | for (i = 0; i < num_var_ranges; i++) { | |
595 | if (mtrr_state[i].lsize) | |
596 | set_mtrr(i, | |
597 | mtrr_state[i].lbase, | |
598 | mtrr_state[i].lsize, | |
599 | mtrr_state[i].ltype); | |
600 | } | |
1da177e4 LT |
601 | return 0; |
602 | } | |
603 | ||
604 | ||
605 | ||
606 | static struct sysdev_driver mtrr_sysdev_driver = { | |
607 | .suspend = mtrr_save, | |
608 | .resume = mtrr_restore, | |
609 | }; | |
610 | ||
99fc8d42 JB |
611 | static int disable_mtrr_trim; |
612 | ||
613 | static int __init disable_mtrr_trim_setup(char *str) | |
614 | { | |
615 | disable_mtrr_trim = 1; | |
616 | return 0; | |
617 | } | |
618 | early_param("disable_mtrr_trim", disable_mtrr_trim_setup); | |
619 | ||
620 | /* | |
621 | * Newer AMD K8s and later CPUs have a special magic MSR way to force WB | |
622 | * for memory >4GB. Check for that here. | |
623 | * Note this won't check if the MTRRs < 4GB where the magic bit doesn't | |
624 | * apply to are wrong, but so far we don't know of any such case in the wild. | |
625 | */ | |
626 | #define Tom2Enabled (1U << 21) | |
627 | #define Tom2ForceMemTypeWB (1U << 22) | |
628 | ||
093af8d7 | 629 | static __init int amd_special_default_mtrr(void) |
99fc8d42 JB |
630 | { |
631 | u32 l, h; | |
632 | ||
99fc8d42 JB |
633 | if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) |
634 | return 0; | |
635 | if (boot_cpu_data.x86 < 0xf || boot_cpu_data.x86 > 0x11) | |
636 | return 0; | |
637 | /* In case some hypervisor doesn't pass SYSCFG through */ | |
638 | if (rdmsr_safe(MSR_K8_SYSCFG, &l, &h) < 0) | |
639 | return 0; | |
640 | /* | |
641 | * Memory between 4GB and top of mem is forced WB by this magic bit. | |
642 | * Reserved before K8RevF, but should be zero there. | |
643 | */ | |
644 | if ((l & (Tom2Enabled | Tom2ForceMemTypeWB)) == | |
645 | (Tom2Enabled | Tom2ForceMemTypeWB)) | |
646 | return 1; | |
647 | return 0; | |
648 | } | |
649 | ||
650 | /** | |
651 | * mtrr_trim_uncached_memory - trim RAM not covered by MTRRs | |
652 | * | |
653 | * Some buggy BIOSes don't setup the MTRRs properly for systems with certain | |
654 | * memory configurations. This routine checks that the highest MTRR matches | |
655 | * the end of memory, to make sure the MTRRs having a write back type cover | |
656 | * all of the memory the kernel is intending to use. If not, it'll trim any | |
657 | * memory off the end by adjusting end_pfn, removing it from the kernel's | |
658 | * allocation pools, warning the user with an obnoxious message. | |
659 | */ | |
660 | int __init mtrr_trim_uncached_memory(unsigned long end_pfn) | |
661 | { | |
20651af9 | 662 | unsigned long i, base, size, highest_pfn = 0, def, dummy; |
99fc8d42 JB |
663 | mtrr_type type; |
664 | u64 trim_start, trim_size; | |
665 | ||
666 | /* | |
667 | * Make sure we only trim uncachable memory on machines that | |
668 | * support the Intel MTRR architecture: | |
669 | */ | |
093af8d7 YL |
670 | if (!is_cpu(INTEL) || disable_mtrr_trim) |
671 | return 0; | |
99fc8d42 JB |
672 | rdmsr(MTRRdefType_MSR, def, dummy); |
673 | def &= 0xff; | |
093af8d7 YL |
674 | if (def != MTRR_TYPE_UNCACHABLE) |
675 | return 0; | |
676 | ||
677 | if (amd_special_default_mtrr()) | |
99fc8d42 JB |
678 | return 0; |
679 | ||
680 | /* Find highest cached pfn */ | |
681 | for (i = 0; i < num_var_ranges; i++) { | |
682 | mtrr_if->get(i, &base, &size, &type); | |
683 | if (type != MTRR_TYPE_WRBACK) | |
684 | continue; | |
20651af9 YL |
685 | if (highest_pfn < base + size) |
686 | highest_pfn = base + size; | |
99fc8d42 JB |
687 | } |
688 | ||
093af8d7 | 689 | /* kvm/qemu doesn't have mtrr set right, don't trim them all */ |
20651af9 | 690 | if (!highest_pfn) { |
cd7d72bb IM |
691 | printk(KERN_WARNING "WARNING: strange, CPU MTRRs all blank?\n"); |
692 | WARN_ON(1); | |
99fc8d42 | 693 | return 0; |
093af8d7 | 694 | } |
99fc8d42 | 695 | |
20651af9 | 696 | if (highest_pfn < end_pfn) { |
cd7d72bb | 697 | printk(KERN_WARNING "WARNING: BIOS bug: CPU MTRRs don't cover" |
20651af9 YL |
698 | " all of memory, losing %luMB of RAM.\n", |
699 | (end_pfn - highest_pfn) >> (20 - PAGE_SHIFT)); | |
cd7d72bb IM |
700 | |
701 | WARN_ON(1); | |
99fc8d42 JB |
702 | |
703 | printk(KERN_INFO "update e820 for mtrr\n"); | |
20651af9 YL |
704 | trim_start = highest_pfn; |
705 | trim_start <<= PAGE_SHIFT; | |
99fc8d42 JB |
706 | trim_size = end_pfn; |
707 | trim_size <<= PAGE_SHIFT; | |
708 | trim_size -= trim_start; | |
709 | add_memory_region(trim_start, trim_size, E820_RESERVED); | |
710 | update_e820(); | |
711 | return 1; | |
712 | } | |
713 | ||
714 | return 0; | |
715 | } | |
1da177e4 LT |
716 | |
717 | /** | |
3b520b23 | 718 | * mtrr_bp_init - initialize mtrrs on the boot CPU |
1da177e4 LT |
719 | * |
720 | * This needs to be called early; before any of the other CPUs are | |
721 | * initialized (i.e. before smp_init()). | |
722 | * | |
723 | */ | |
9ef231a4 | 724 | void __init mtrr_bp_init(void) |
1da177e4 LT |
725 | { |
726 | init_ifs(); | |
727 | ||
728 | if (cpu_has_mtrr) { | |
729 | mtrr_if = &generic_mtrr_ops; | |
730 | size_or_mask = 0xff000000; /* 36 bits */ | |
731 | size_and_mask = 0x00f00000; | |
1f2c958a AK |
732 | |
733 | /* This is an AMD specific MSR, but we assume(hope?) that | |
734 | Intel will implement it to when they extend the address | |
735 | bus of the Xeon. */ | |
736 | if (cpuid_eax(0x80000000) >= 0x80000008) { | |
737 | u32 phys_addr; | |
738 | phys_addr = cpuid_eax(0x80000008) & 0xff; | |
af9c142d SL |
739 | /* CPUID workaround for Intel 0F33/0F34 CPU */ |
740 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | |
741 | boot_cpu_data.x86 == 0xF && | |
742 | boot_cpu_data.x86_model == 0x3 && | |
743 | (boot_cpu_data.x86_mask == 0x3 || | |
744 | boot_cpu_data.x86_mask == 0x4)) | |
745 | phys_addr = 36; | |
746 | ||
6c5806ca AH |
747 | size_or_mask = ~((1ULL << (phys_addr - PAGE_SHIFT)) - 1); |
748 | size_and_mask = ~size_or_mask & 0xfffff00000ULL; | |
1f2c958a AK |
749 | } else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR && |
750 | boot_cpu_data.x86 == 6) { | |
751 | /* VIA C* family have Intel style MTRRs, but | |
752 | don't support PAE */ | |
753 | size_or_mask = 0xfff00000; /* 32 bits */ | |
754 | size_and_mask = 0; | |
1da177e4 LT |
755 | } |
756 | } else { | |
757 | switch (boot_cpu_data.x86_vendor) { | |
758 | case X86_VENDOR_AMD: | |
759 | if (cpu_has_k6_mtrr) { | |
760 | /* Pre-Athlon (K6) AMD CPU MTRRs */ | |
761 | mtrr_if = mtrr_ops[X86_VENDOR_AMD]; | |
762 | size_or_mask = 0xfff00000; /* 32 bits */ | |
763 | size_and_mask = 0; | |
764 | } | |
765 | break; | |
766 | case X86_VENDOR_CENTAUR: | |
767 | if (cpu_has_centaur_mcr) { | |
768 | mtrr_if = mtrr_ops[X86_VENDOR_CENTAUR]; | |
769 | size_or_mask = 0xfff00000; /* 32 bits */ | |
770 | size_and_mask = 0; | |
771 | } | |
772 | break; | |
773 | case X86_VENDOR_CYRIX: | |
774 | if (cpu_has_cyrix_arr) { | |
775 | mtrr_if = mtrr_ops[X86_VENDOR_CYRIX]; | |
776 | size_or_mask = 0xfff00000; /* 32 bits */ | |
777 | size_and_mask = 0; | |
778 | } | |
779 | break; | |
780 | default: | |
781 | break; | |
782 | } | |
783 | } | |
1da177e4 LT |
784 | |
785 | if (mtrr_if) { | |
786 | set_num_var_ranges(); | |
787 | init_table(); | |
3b520b23 SL |
788 | if (use_intel()) |
789 | get_mtrr_state(); | |
1da177e4 | 790 | } |
1da177e4 LT |
791 | } |
792 | ||
3b520b23 SL |
793 | void mtrr_ap_init(void) |
794 | { | |
795 | unsigned long flags; | |
796 | ||
797 | if (!mtrr_if || !use_intel()) | |
798 | return; | |
799 | /* | |
14cc3e2b | 800 | * Ideally we should hold mtrr_mutex here to avoid mtrr entries changed, |
3b520b23 SL |
801 | * but this routine will be called in cpu boot time, holding the lock |
802 | * breaks it. This routine is called in two cases: 1.very earily time | |
803 | * of software resume, when there absolutely isn't mtrr entry changes; | |
804 | * 2.cpu hotadd time. We let mtrr_add/del_page hold cpuhotplug lock to | |
805 | * prevent mtrr entry changes | |
806 | */ | |
807 | local_irq_save(flags); | |
808 | ||
809 | mtrr_if->set_all(); | |
810 | ||
811 | local_irq_restore(flags); | |
812 | } | |
813 | ||
2b1f6278 BK |
814 | /** |
815 | * Save current fixed-range MTRR state of the BSP | |
816 | */ | |
817 | void mtrr_save_state(void) | |
818 | { | |
c8f2518e | 819 | smp_call_function_single(0, mtrr_save_fixed_ranges, NULL, 1, 1); |
2b1f6278 BK |
820 | } |
821 | ||
3b520b23 SL |
822 | static int __init mtrr_init_finialize(void) |
823 | { | |
824 | if (!mtrr_if) | |
825 | return 0; | |
826 | if (use_intel()) | |
827 | mtrr_state_warn(); | |
828 | else { | |
27b46d76 | 829 | /* The CPUs haven't MTRR and seem to not support SMP. They have |
3b520b23 SL |
830 | * specific drivers, we use a tricky method to support |
831 | * suspend/resume for them. | |
832 | * TBD: is there any system with such CPU which supports | |
833 | * suspend/resume? if no, we should remove the code. | |
834 | */ | |
835 | sysdev_driver_register(&cpu_sysdev_class, | |
836 | &mtrr_sysdev_driver); | |
837 | } | |
838 | return 0; | |
839 | } | |
840 | subsys_initcall(mtrr_init_finialize); |