Commit | Line | Data |
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1da177e4 LT |
1 | /* Generic MTRR (Memory Type Range Register) driver. |
2 | ||
3 | Copyright (C) 1997-2000 Richard Gooch | |
4 | Copyright (c) 2002 Patrick Mochel | |
5 | ||
6 | This library is free software; you can redistribute it and/or | |
7 | modify it under the terms of the GNU Library General Public | |
8 | License as published by the Free Software Foundation; either | |
9 | version 2 of the License, or (at your option) any later version. | |
10 | ||
11 | This library is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | Library General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU Library General Public | |
17 | License along with this library; if not, write to the Free | |
18 | Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | ||
20 | Richard Gooch may be reached by email at rgooch@atnf.csiro.au | |
21 | The postal address is: | |
22 | Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia. | |
23 | ||
24 | Source: "Pentium Pro Family Developer's Manual, Volume 3: | |
25 | Operating System Writer's Guide" (Intel document number 242692), | |
26 | section 11.11.7 | |
27 | ||
28 | This was cleaned and made readable by Patrick Mochel <mochel@osdl.org> | |
29 | on 6-7 March 2002. | |
30 | Source: Intel Architecture Software Developers Manual, Volume 3: | |
31 | System Programming Guide; Section 9.11. (1997 edition - PPro). | |
32 | */ | |
33 | ||
34 | #include <linux/module.h> | |
35 | #include <linux/init.h> | |
36 | #include <linux/pci.h> | |
37 | #include <linux/smp.h> | |
38 | #include <linux/cpu.h> | |
14cc3e2b | 39 | #include <linux/mutex.h> |
95ffa243 | 40 | #include <linux/sort.h> |
1da177e4 | 41 | |
99fc8d42 | 42 | #include <asm/e820.h> |
1da177e4 | 43 | #include <asm/mtrr.h> |
1da177e4 LT |
44 | #include <asm/uaccess.h> |
45 | #include <asm/processor.h> | |
46 | #include <asm/msr.h> | |
4147c874 | 47 | #include <asm/kvm_para.h> |
1da177e4 LT |
48 | #include "mtrr.h" |
49 | ||
1da177e4 LT |
50 | u32 num_var_ranges = 0; |
51 | ||
b558bc0a | 52 | unsigned int mtrr_usage_table[MTRR_MAX_VAR_RANGES]; |
14cc3e2b | 53 | static DEFINE_MUTEX(mtrr_mutex); |
1da177e4 | 54 | |
6c5806ca | 55 | u64 size_or_mask, size_and_mask; |
1da177e4 LT |
56 | |
57 | static struct mtrr_ops * mtrr_ops[X86_VENDOR_NUM] = {}; | |
58 | ||
59 | struct mtrr_ops * mtrr_if = NULL; | |
60 | ||
61 | static void set_mtrr(unsigned int reg, unsigned long base, | |
62 | unsigned long size, mtrr_type type); | |
63 | ||
1da177e4 LT |
64 | void set_mtrr_ops(struct mtrr_ops * ops) |
65 | { | |
66 | if (ops->vendor && ops->vendor < X86_VENDOR_NUM) | |
67 | mtrr_ops[ops->vendor] = ops; | |
68 | } | |
69 | ||
70 | /* Returns non-zero if we have the write-combining memory type */ | |
71 | static int have_wrcomb(void) | |
72 | { | |
73 | struct pci_dev *dev; | |
a6954ba2 | 74 | u8 rev; |
1da177e4 LT |
75 | |
76 | if ((dev = pci_get_class(PCI_CLASS_BRIDGE_HOST << 8, NULL)) != NULL) { | |
a6954ba2 | 77 | /* ServerWorks LE chipsets < rev 6 have problems with write-combining |
1da177e4 LT |
78 | Don't allow it and leave room for other chipsets to be tagged */ |
79 | if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS && | |
80 | dev->device == PCI_DEVICE_ID_SERVERWORKS_LE) { | |
a6954ba2 LR |
81 | pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev); |
82 | if (rev <= 5) { | |
83 | printk(KERN_INFO "mtrr: Serverworks LE rev < 6 detected. Write-combining disabled.\n"); | |
84 | pci_dev_put(dev); | |
85 | return 0; | |
86 | } | |
1da177e4 | 87 | } |
a6954ba2 | 88 | /* Intel 450NX errata # 23. Non ascending cacheline evictions to |
1da177e4 LT |
89 | write combining memory may resulting in data corruption */ |
90 | if (dev->vendor == PCI_VENDOR_ID_INTEL && | |
91 | dev->device == PCI_DEVICE_ID_INTEL_82451NX) { | |
92 | printk(KERN_INFO "mtrr: Intel 450NX MMC detected. Write-combining disabled.\n"); | |
93 | pci_dev_put(dev); | |
94 | return 0; | |
95 | } | |
96 | pci_dev_put(dev); | |
97 | } | |
98 | return (mtrr_if->have_wrcomb ? mtrr_if->have_wrcomb() : 0); | |
99 | } | |
100 | ||
101 | /* This function returns the number of variable MTRRs */ | |
102 | static void __init set_num_var_ranges(void) | |
103 | { | |
104 | unsigned long config = 0, dummy; | |
105 | ||
106 | if (use_intel()) { | |
107 | rdmsr(MTRRcap_MSR, config, dummy); | |
108 | } else if (is_cpu(AMD)) | |
109 | config = 2; | |
110 | else if (is_cpu(CYRIX) || is_cpu(CENTAUR)) | |
111 | config = 8; | |
112 | num_var_ranges = config & 0xff; | |
113 | } | |
114 | ||
115 | static void __init init_table(void) | |
116 | { | |
117 | int i, max; | |
118 | ||
119 | max = num_var_ranges; | |
1da177e4 | 120 | for (i = 0; i < max; i++) |
99fc8d42 | 121 | mtrr_usage_table[i] = 1; |
1da177e4 LT |
122 | } |
123 | ||
124 | struct set_mtrr_data { | |
125 | atomic_t count; | |
126 | atomic_t gate; | |
127 | unsigned long smp_base; | |
128 | unsigned long smp_size; | |
129 | unsigned int smp_reg; | |
130 | mtrr_type smp_type; | |
131 | }; | |
132 | ||
1da177e4 LT |
133 | static void ipi_handler(void *info) |
134 | /* [SUMMARY] Synchronisation handler. Executed by "other" CPUs. | |
135 | [RETURNS] Nothing. | |
136 | */ | |
137 | { | |
4e2947f1 | 138 | #ifdef CONFIG_SMP |
1da177e4 LT |
139 | struct set_mtrr_data *data = info; |
140 | unsigned long flags; | |
141 | ||
142 | local_irq_save(flags); | |
143 | ||
144 | atomic_dec(&data->count); | |
145 | while(!atomic_read(&data->gate)) | |
146 | cpu_relax(); | |
147 | ||
148 | /* The master has cleared me to execute */ | |
149 | if (data->smp_reg != ~0U) | |
150 | mtrr_if->set(data->smp_reg, data->smp_base, | |
151 | data->smp_size, data->smp_type); | |
152 | else | |
153 | mtrr_if->set_all(); | |
154 | ||
155 | atomic_dec(&data->count); | |
156 | while(atomic_read(&data->gate)) | |
157 | cpu_relax(); | |
158 | ||
159 | atomic_dec(&data->count); | |
160 | local_irq_restore(flags); | |
1da177e4 | 161 | #endif |
4e2947f1 | 162 | } |
1da177e4 | 163 | |
365bff80 JB |
164 | static inline int types_compatible(mtrr_type type1, mtrr_type type2) { |
165 | return type1 == MTRR_TYPE_UNCACHABLE || | |
166 | type2 == MTRR_TYPE_UNCACHABLE || | |
167 | (type1 == MTRR_TYPE_WRTHROUGH && type2 == MTRR_TYPE_WRBACK) || | |
168 | (type1 == MTRR_TYPE_WRBACK && type2 == MTRR_TYPE_WRTHROUGH); | |
169 | } | |
170 | ||
1da177e4 LT |
171 | /** |
172 | * set_mtrr - update mtrrs on all processors | |
173 | * @reg: mtrr in question | |
174 | * @base: mtrr base | |
175 | * @size: mtrr size | |
176 | * @type: mtrr type | |
177 | * | |
178 | * This is kinda tricky, but fortunately, Intel spelled it out for us cleanly: | |
179 | * | |
180 | * 1. Send IPI to do the following: | |
181 | * 2. Disable Interrupts | |
182 | * 3. Wait for all procs to do so | |
183 | * 4. Enter no-fill cache mode | |
184 | * 5. Flush caches | |
185 | * 6. Clear PGE bit | |
186 | * 7. Flush all TLBs | |
187 | * 8. Disable all range registers | |
188 | * 9. Update the MTRRs | |
189 | * 10. Enable all range registers | |
190 | * 11. Flush all TLBs and caches again | |
191 | * 12. Enter normal cache mode and reenable caching | |
192 | * 13. Set PGE | |
193 | * 14. Wait for buddies to catch up | |
194 | * 15. Enable interrupts. | |
195 | * | |
196 | * What does that mean for us? Well, first we set data.count to the number | |
197 | * of CPUs. As each CPU disables interrupts, it'll decrement it once. We wait | |
198 | * until it hits 0 and proceed. We set the data.gate flag and reset data.count. | |
199 | * Meanwhile, they are waiting for that flag to be set. Once it's set, each | |
200 | * CPU goes through the transition of updating MTRRs. The CPU vendors may each do it | |
201 | * differently, so we call mtrr_if->set() callback and let them take care of it. | |
202 | * When they're done, they again decrement data->count and wait for data.gate to | |
203 | * be reset. | |
204 | * When we finish, we wait for data.count to hit 0 and toggle the data.gate flag. | |
205 | * Everyone then enables interrupts and we all continue on. | |
206 | * | |
207 | * Note that the mechanism is the same for UP systems, too; all the SMP stuff | |
208 | * becomes nops. | |
209 | */ | |
210 | static void set_mtrr(unsigned int reg, unsigned long base, | |
211 | unsigned long size, mtrr_type type) | |
212 | { | |
213 | struct set_mtrr_data data; | |
214 | unsigned long flags; | |
215 | ||
216 | data.smp_reg = reg; | |
217 | data.smp_base = base; | |
218 | data.smp_size = size; | |
219 | data.smp_type = type; | |
220 | atomic_set(&data.count, num_booting_cpus() - 1); | |
d25c1ba2 LP |
221 | /* make sure data.count is visible before unleashing other CPUs */ |
222 | smp_wmb(); | |
1da177e4 LT |
223 | atomic_set(&data.gate,0); |
224 | ||
225 | /* Start the ball rolling on other CPUs */ | |
8691e5a8 | 226 | if (smp_call_function(ipi_handler, &data, 0) != 0) |
1da177e4 LT |
227 | panic("mtrr: timed out waiting for other CPUs\n"); |
228 | ||
229 | local_irq_save(flags); | |
230 | ||
231 | while(atomic_read(&data.count)) | |
232 | cpu_relax(); | |
233 | ||
234 | /* ok, reset count and toggle gate */ | |
235 | atomic_set(&data.count, num_booting_cpus() - 1); | |
d25c1ba2 | 236 | smp_wmb(); |
1da177e4 LT |
237 | atomic_set(&data.gate,1); |
238 | ||
239 | /* do our MTRR business */ | |
240 | ||
241 | /* HACK! | |
242 | * We use this same function to initialize the mtrrs on boot. | |
243 | * The state of the boot cpu's mtrrs has been saved, and we want | |
244 | * to replicate across all the APs. | |
245 | * If we're doing that @reg is set to something special... | |
246 | */ | |
247 | if (reg != ~0U) | |
248 | mtrr_if->set(reg,base,size,type); | |
249 | ||
250 | /* wait for the others */ | |
251 | while(atomic_read(&data.count)) | |
252 | cpu_relax(); | |
253 | ||
254 | atomic_set(&data.count, num_booting_cpus() - 1); | |
d25c1ba2 | 255 | smp_wmb(); |
1da177e4 LT |
256 | atomic_set(&data.gate,0); |
257 | ||
258 | /* | |
259 | * Wait here for everyone to have seen the gate change | |
260 | * So we're the last ones to touch 'data' | |
261 | */ | |
262 | while(atomic_read(&data.count)) | |
263 | cpu_relax(); | |
264 | ||
265 | local_irq_restore(flags); | |
266 | } | |
267 | ||
268 | /** | |
269 | * mtrr_add_page - Add a memory type region | |
9b483417 AM |
270 | * @base: Physical base address of region in pages (in units of 4 kB!) |
271 | * @size: Physical size of region in pages (4 kB) | |
1da177e4 LT |
272 | * @type: Type of MTRR desired |
273 | * @increment: If this is true do usage counting on the region | |
274 | * | |
275 | * Memory type region registers control the caching on newer Intel and | |
276 | * non Intel processors. This function allows drivers to request an | |
277 | * MTRR is added. The details and hardware specifics of each processor's | |
278 | * implementation are hidden from the caller, but nevertheless the | |
279 | * caller should expect to need to provide a power of two size on an | |
280 | * equivalent power of two boundary. | |
281 | * | |
282 | * If the region cannot be added either because all regions are in use | |
283 | * or the CPU cannot support it a negative value is returned. On success | |
284 | * the register number for this entry is returned, but should be treated | |
285 | * as a cookie only. | |
286 | * | |
287 | * On a multiprocessor machine the changes are made to all processors. | |
288 | * This is required on x86 by the Intel processors. | |
289 | * | |
290 | * The available types are | |
291 | * | |
292 | * %MTRR_TYPE_UNCACHABLE - No caching | |
293 | * | |
294 | * %MTRR_TYPE_WRBACK - Write data back in bursts whenever | |
295 | * | |
296 | * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts | |
297 | * | |
298 | * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes | |
299 | * | |
300 | * BUGS: Needs a quiet flag for the cases where drivers do not mind | |
301 | * failures and do not wish system log messages to be sent. | |
302 | */ | |
303 | ||
304 | int mtrr_add_page(unsigned long base, unsigned long size, | |
2d2ee8de | 305 | unsigned int type, bool increment) |
1da177e4 | 306 | { |
365bff80 | 307 | int i, replace, error; |
1da177e4 | 308 | mtrr_type ltype; |
365bff80 | 309 | unsigned long lbase, lsize; |
1da177e4 LT |
310 | |
311 | if (!mtrr_if) | |
312 | return -ENXIO; | |
313 | ||
314 | if ((error = mtrr_if->validate_add_page(base,size,type))) | |
315 | return error; | |
316 | ||
317 | if (type >= MTRR_NUM_TYPES) { | |
318 | printk(KERN_WARNING "mtrr: type: %u invalid\n", type); | |
319 | return -EINVAL; | |
320 | } | |
321 | ||
322 | /* If the type is WC, check that this processor supports it */ | |
323 | if ((type == MTRR_TYPE_WRCOMB) && !have_wrcomb()) { | |
324 | printk(KERN_WARNING | |
325 | "mtrr: your processor doesn't support write-combining\n"); | |
326 | return -ENOSYS; | |
327 | } | |
328 | ||
365bff80 JB |
329 | if (!size) { |
330 | printk(KERN_WARNING "mtrr: zero sized request\n"); | |
331 | return -EINVAL; | |
332 | } | |
333 | ||
1da177e4 LT |
334 | if (base & size_or_mask || size & size_or_mask) { |
335 | printk(KERN_WARNING "mtrr: base or size exceeds the MTRR width\n"); | |
336 | return -EINVAL; | |
337 | } | |
338 | ||
339 | error = -EINVAL; | |
365bff80 | 340 | replace = -1; |
1da177e4 | 341 | |
3b520b23 | 342 | /* No CPU hotplug when we change MTRR entries */ |
86ef5c9a | 343 | get_online_cpus(); |
1da177e4 | 344 | /* Search for existing MTRR */ |
14cc3e2b | 345 | mutex_lock(&mtrr_mutex); |
1da177e4 LT |
346 | for (i = 0; i < num_var_ranges; ++i) { |
347 | mtrr_if->get(i, &lbase, &lsize, <ype); | |
365bff80 | 348 | if (!lsize || base > lbase + lsize - 1 || base + size - 1 < lbase) |
1da177e4 LT |
349 | continue; |
350 | /* At this point we know there is some kind of overlap/enclosure */ | |
365bff80 JB |
351 | if (base < lbase || base + size - 1 > lbase + lsize - 1) { |
352 | if (base <= lbase && base + size - 1 >= lbase + lsize - 1) { | |
353 | /* New region encloses an existing region */ | |
354 | if (type == ltype) { | |
355 | replace = replace == -1 ? i : -2; | |
356 | continue; | |
357 | } | |
358 | else if (types_compatible(type, ltype)) | |
359 | continue; | |
360 | } | |
1da177e4 LT |
361 | printk(KERN_WARNING |
362 | "mtrr: 0x%lx000,0x%lx000 overlaps existing" | |
365bff80 | 363 | " 0x%lx000,0x%lx000\n", base, size, lbase, |
1da177e4 LT |
364 | lsize); |
365 | goto out; | |
366 | } | |
367 | /* New region is enclosed by an existing region */ | |
368 | if (ltype != type) { | |
365bff80 | 369 | if (types_compatible(type, ltype)) |
1da177e4 LT |
370 | continue; |
371 | printk (KERN_WARNING "mtrr: type mismatch for %lx000,%lx000 old: %s new: %s\n", | |
372 | base, size, mtrr_attrib_to_str(ltype), | |
373 | mtrr_attrib_to_str(type)); | |
374 | goto out; | |
375 | } | |
376 | if (increment) | |
99fc8d42 | 377 | ++mtrr_usage_table[i]; |
1da177e4 LT |
378 | error = i; |
379 | goto out; | |
380 | } | |
381 | /* Search for an empty MTRR */ | |
365bff80 | 382 | i = mtrr_if->get_free_region(base, size, replace); |
1da177e4 LT |
383 | if (i >= 0) { |
384 | set_mtrr(i, base, size, type); | |
99fc8d42 JB |
385 | if (likely(replace < 0)) { |
386 | mtrr_usage_table[i] = 1; | |
387 | } else { | |
388 | mtrr_usage_table[i] = mtrr_usage_table[replace]; | |
2d2ee8de | 389 | if (increment) |
99fc8d42 | 390 | mtrr_usage_table[i]++; |
365bff80 JB |
391 | if (unlikely(replace != i)) { |
392 | set_mtrr(replace, 0, 0, 0); | |
99fc8d42 | 393 | mtrr_usage_table[replace] = 0; |
365bff80 JB |
394 | } |
395 | } | |
1da177e4 LT |
396 | } else |
397 | printk(KERN_INFO "mtrr: no more MTRRs available\n"); | |
398 | error = i; | |
399 | out: | |
14cc3e2b | 400 | mutex_unlock(&mtrr_mutex); |
86ef5c9a | 401 | put_online_cpus(); |
1da177e4 LT |
402 | return error; |
403 | } | |
404 | ||
c92c6ffd AM |
405 | static int mtrr_check(unsigned long base, unsigned long size) |
406 | { | |
407 | if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) { | |
408 | printk(KERN_WARNING | |
409 | "mtrr: size and base must be multiples of 4 kiB\n"); | |
410 | printk(KERN_DEBUG | |
411 | "mtrr: size: 0x%lx base: 0x%lx\n", size, base); | |
412 | dump_stack(); | |
413 | return -1; | |
414 | } | |
415 | return 0; | |
416 | } | |
417 | ||
1da177e4 LT |
418 | /** |
419 | * mtrr_add - Add a memory type region | |
420 | * @base: Physical base address of region | |
421 | * @size: Physical size of region | |
422 | * @type: Type of MTRR desired | |
423 | * @increment: If this is true do usage counting on the region | |
424 | * | |
425 | * Memory type region registers control the caching on newer Intel and | |
426 | * non Intel processors. This function allows drivers to request an | |
427 | * MTRR is added. The details and hardware specifics of each processor's | |
428 | * implementation are hidden from the caller, but nevertheless the | |
429 | * caller should expect to need to provide a power of two size on an | |
430 | * equivalent power of two boundary. | |
431 | * | |
432 | * If the region cannot be added either because all regions are in use | |
433 | * or the CPU cannot support it a negative value is returned. On success | |
434 | * the register number for this entry is returned, but should be treated | |
435 | * as a cookie only. | |
436 | * | |
437 | * On a multiprocessor machine the changes are made to all processors. | |
438 | * This is required on x86 by the Intel processors. | |
439 | * | |
440 | * The available types are | |
441 | * | |
442 | * %MTRR_TYPE_UNCACHABLE - No caching | |
443 | * | |
444 | * %MTRR_TYPE_WRBACK - Write data back in bursts whenever | |
445 | * | |
446 | * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts | |
447 | * | |
448 | * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes | |
449 | * | |
450 | * BUGS: Needs a quiet flag for the cases where drivers do not mind | |
451 | * failures and do not wish system log messages to be sent. | |
452 | */ | |
453 | ||
454 | int | |
455 | mtrr_add(unsigned long base, unsigned long size, unsigned int type, | |
2d2ee8de | 456 | bool increment) |
1da177e4 | 457 | { |
c92c6ffd | 458 | if (mtrr_check(base, size)) |
1da177e4 | 459 | return -EINVAL; |
1da177e4 LT |
460 | return mtrr_add_page(base >> PAGE_SHIFT, size >> PAGE_SHIFT, type, |
461 | increment); | |
462 | } | |
463 | ||
464 | /** | |
465 | * mtrr_del_page - delete a memory type region | |
466 | * @reg: Register returned by mtrr_add | |
467 | * @base: Physical base address | |
468 | * @size: Size of region | |
469 | * | |
470 | * If register is supplied then base and size are ignored. This is | |
471 | * how drivers should call it. | |
472 | * | |
473 | * Releases an MTRR region. If the usage count drops to zero the | |
474 | * register is freed and the region returns to default state. | |
475 | * On success the register is returned, on failure a negative error | |
476 | * code. | |
477 | */ | |
478 | ||
479 | int mtrr_del_page(int reg, unsigned long base, unsigned long size) | |
480 | { | |
481 | int i, max; | |
482 | mtrr_type ltype; | |
365bff80 | 483 | unsigned long lbase, lsize; |
1da177e4 LT |
484 | int error = -EINVAL; |
485 | ||
486 | if (!mtrr_if) | |
487 | return -ENXIO; | |
488 | ||
489 | max = num_var_ranges; | |
3b520b23 | 490 | /* No CPU hotplug when we change MTRR entries */ |
86ef5c9a | 491 | get_online_cpus(); |
14cc3e2b | 492 | mutex_lock(&mtrr_mutex); |
1da177e4 LT |
493 | if (reg < 0) { |
494 | /* Search for existing MTRR */ | |
495 | for (i = 0; i < max; ++i) { | |
496 | mtrr_if->get(i, &lbase, &lsize, <ype); | |
497 | if (lbase == base && lsize == size) { | |
498 | reg = i; | |
499 | break; | |
500 | } | |
501 | } | |
502 | if (reg < 0) { | |
503 | printk(KERN_DEBUG "mtrr: no MTRR for %lx000,%lx000 found\n", base, | |
504 | size); | |
505 | goto out; | |
506 | } | |
507 | } | |
508 | if (reg >= max) { | |
509 | printk(KERN_WARNING "mtrr: register: %d too big\n", reg); | |
510 | goto out; | |
511 | } | |
1da177e4 LT |
512 | mtrr_if->get(reg, &lbase, &lsize, <ype); |
513 | if (lsize < 1) { | |
514 | printk(KERN_WARNING "mtrr: MTRR %d not used\n", reg); | |
515 | goto out; | |
516 | } | |
99fc8d42 | 517 | if (mtrr_usage_table[reg] < 1) { |
1da177e4 LT |
518 | printk(KERN_WARNING "mtrr: reg: %d has count=0\n", reg); |
519 | goto out; | |
520 | } | |
99fc8d42 | 521 | if (--mtrr_usage_table[reg] < 1) |
1da177e4 LT |
522 | set_mtrr(reg, 0, 0, 0); |
523 | error = reg; | |
524 | out: | |
14cc3e2b | 525 | mutex_unlock(&mtrr_mutex); |
86ef5c9a | 526 | put_online_cpus(); |
1da177e4 LT |
527 | return error; |
528 | } | |
529 | /** | |
530 | * mtrr_del - delete a memory type region | |
531 | * @reg: Register returned by mtrr_add | |
532 | * @base: Physical base address | |
533 | * @size: Size of region | |
534 | * | |
535 | * If register is supplied then base and size are ignored. This is | |
536 | * how drivers should call it. | |
537 | * | |
538 | * Releases an MTRR region. If the usage count drops to zero the | |
539 | * register is freed and the region returns to default state. | |
540 | * On success the register is returned, on failure a negative error | |
541 | * code. | |
542 | */ | |
543 | ||
544 | int | |
545 | mtrr_del(int reg, unsigned long base, unsigned long size) | |
546 | { | |
c92c6ffd | 547 | if (mtrr_check(base, size)) |
1da177e4 | 548 | return -EINVAL; |
1da177e4 LT |
549 | return mtrr_del_page(reg, base >> PAGE_SHIFT, size >> PAGE_SHIFT); |
550 | } | |
551 | ||
552 | EXPORT_SYMBOL(mtrr_add); | |
553 | EXPORT_SYMBOL(mtrr_del); | |
554 | ||
555 | /* HACK ALERT! | |
556 | * These should be called implicitly, but we can't yet until all the initcall | |
557 | * stuff is done... | |
558 | */ | |
1da177e4 LT |
559 | static void __init init_ifs(void) |
560 | { | |
475850c8 | 561 | #ifndef CONFIG_X86_64 |
1da177e4 LT |
562 | amd_init_mtrr(); |
563 | cyrix_init_mtrr(); | |
564 | centaur_init_mtrr(); | |
475850c8 | 565 | #endif |
1da177e4 LT |
566 | } |
567 | ||
3b520b23 SL |
568 | /* The suspend/resume methods are only for CPU without MTRR. CPU using generic |
569 | * MTRR driver doesn't require this | |
570 | */ | |
1da177e4 LT |
571 | struct mtrr_value { |
572 | mtrr_type ltype; | |
573 | unsigned long lbase; | |
365bff80 | 574 | unsigned long lsize; |
1da177e4 LT |
575 | }; |
576 | ||
b558bc0a | 577 | static struct mtrr_value mtrr_state[MTRR_MAX_VAR_RANGES]; |
1da177e4 | 578 | |
829ca9a3 | 579 | static int mtrr_save(struct sys_device * sysdev, pm_message_t state) |
1da177e4 LT |
580 | { |
581 | int i; | |
1da177e4 LT |
582 | |
583 | for (i = 0; i < num_var_ranges; i++) { | |
584 | mtrr_if->get(i, | |
585 | &mtrr_state[i].lbase, | |
586 | &mtrr_state[i].lsize, | |
587 | &mtrr_state[i].ltype); | |
588 | } | |
589 | return 0; | |
590 | } | |
591 | ||
592 | static int mtrr_restore(struct sys_device * sysdev) | |
593 | { | |
594 | int i; | |
595 | ||
596 | for (i = 0; i < num_var_ranges; i++) { | |
597 | if (mtrr_state[i].lsize) | |
598 | set_mtrr(i, | |
599 | mtrr_state[i].lbase, | |
600 | mtrr_state[i].lsize, | |
601 | mtrr_state[i].ltype); | |
602 | } | |
1da177e4 LT |
603 | return 0; |
604 | } | |
605 | ||
606 | ||
607 | ||
608 | static struct sysdev_driver mtrr_sysdev_driver = { | |
609 | .suspend = mtrr_save, | |
610 | .resume = mtrr_restore, | |
611 | }; | |
612 | ||
0d890355 | 613 | int __initdata changed_by_mtrr_cleanup; |
1da177e4 LT |
614 | |
615 | /** | |
3b520b23 | 616 | * mtrr_bp_init - initialize mtrrs on the boot CPU |
1da177e4 LT |
617 | * |
618 | * This needs to be called early; before any of the other CPUs are | |
619 | * initialized (i.e. before smp_init()). | |
620 | * | |
621 | */ | |
9ef231a4 | 622 | void __init mtrr_bp_init(void) |
1da177e4 | 623 | { |
95ffa243 | 624 | u32 phys_addr; |
1da177e4 LT |
625 | init_ifs(); |
626 | ||
95ffa243 YL |
627 | phys_addr = 32; |
628 | ||
1da177e4 LT |
629 | if (cpu_has_mtrr) { |
630 | mtrr_if = &generic_mtrr_ops; | |
631 | size_or_mask = 0xff000000; /* 36 bits */ | |
632 | size_and_mask = 0x00f00000; | |
95ffa243 | 633 | phys_addr = 36; |
1f2c958a AK |
634 | |
635 | /* This is an AMD specific MSR, but we assume(hope?) that | |
636 | Intel will implement it to when they extend the address | |
637 | bus of the Xeon. */ | |
638 | if (cpuid_eax(0x80000000) >= 0x80000008) { | |
1f2c958a | 639 | phys_addr = cpuid_eax(0x80000008) & 0xff; |
af9c142d SL |
640 | /* CPUID workaround for Intel 0F33/0F34 CPU */ |
641 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | |
642 | boot_cpu_data.x86 == 0xF && | |
643 | boot_cpu_data.x86_model == 0x3 && | |
644 | (boot_cpu_data.x86_mask == 0x3 || | |
645 | boot_cpu_data.x86_mask == 0x4)) | |
646 | phys_addr = 36; | |
647 | ||
6c5806ca AH |
648 | size_or_mask = ~((1ULL << (phys_addr - PAGE_SHIFT)) - 1); |
649 | size_and_mask = ~size_or_mask & 0xfffff00000ULL; | |
1f2c958a AK |
650 | } else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR && |
651 | boot_cpu_data.x86 == 6) { | |
652 | /* VIA C* family have Intel style MTRRs, but | |
653 | don't support PAE */ | |
654 | size_or_mask = 0xfff00000; /* 32 bits */ | |
655 | size_and_mask = 0; | |
95ffa243 | 656 | phys_addr = 32; |
1da177e4 LT |
657 | } |
658 | } else { | |
659 | switch (boot_cpu_data.x86_vendor) { | |
660 | case X86_VENDOR_AMD: | |
661 | if (cpu_has_k6_mtrr) { | |
662 | /* Pre-Athlon (K6) AMD CPU MTRRs */ | |
663 | mtrr_if = mtrr_ops[X86_VENDOR_AMD]; | |
664 | size_or_mask = 0xfff00000; /* 32 bits */ | |
665 | size_and_mask = 0; | |
666 | } | |
667 | break; | |
668 | case X86_VENDOR_CENTAUR: | |
669 | if (cpu_has_centaur_mcr) { | |
670 | mtrr_if = mtrr_ops[X86_VENDOR_CENTAUR]; | |
671 | size_or_mask = 0xfff00000; /* 32 bits */ | |
672 | size_and_mask = 0; | |
673 | } | |
674 | break; | |
675 | case X86_VENDOR_CYRIX: | |
676 | if (cpu_has_cyrix_arr) { | |
677 | mtrr_if = mtrr_ops[X86_VENDOR_CYRIX]; | |
678 | size_or_mask = 0xfff00000; /* 32 bits */ | |
679 | size_and_mask = 0; | |
680 | } | |
681 | break; | |
682 | default: | |
683 | break; | |
684 | } | |
685 | } | |
1da177e4 LT |
686 | |
687 | if (mtrr_if) { | |
688 | set_num_var_ranges(); | |
689 | init_table(); | |
95ffa243 | 690 | if (use_intel()) { |
3b520b23 | 691 | get_mtrr_state(); |
95ffa243 | 692 | |
12031a62 YL |
693 | if (mtrr_cleanup(phys_addr)) { |
694 | changed_by_mtrr_cleanup = 1; | |
95ffa243 | 695 | mtrr_if->set_all(); |
12031a62 | 696 | } |
95ffa243 YL |
697 | |
698 | } | |
1da177e4 | 699 | } |
1da177e4 LT |
700 | } |
701 | ||
3b520b23 SL |
702 | void mtrr_ap_init(void) |
703 | { | |
704 | unsigned long flags; | |
705 | ||
706 | if (!mtrr_if || !use_intel()) | |
707 | return; | |
708 | /* | |
14cc3e2b | 709 | * Ideally we should hold mtrr_mutex here to avoid mtrr entries changed, |
3b520b23 SL |
710 | * but this routine will be called in cpu boot time, holding the lock |
711 | * breaks it. This routine is called in two cases: 1.very earily time | |
712 | * of software resume, when there absolutely isn't mtrr entry changes; | |
713 | * 2.cpu hotadd time. We let mtrr_add/del_page hold cpuhotplug lock to | |
714 | * prevent mtrr entry changes | |
715 | */ | |
716 | local_irq_save(flags); | |
717 | ||
718 | mtrr_if->set_all(); | |
719 | ||
720 | local_irq_restore(flags); | |
721 | } | |
722 | ||
2b1f6278 BK |
723 | /** |
724 | * Save current fixed-range MTRR state of the BSP | |
725 | */ | |
726 | void mtrr_save_state(void) | |
727 | { | |
8691e5a8 | 728 | smp_call_function_single(0, mtrr_save_fixed_ranges, NULL, 1); |
2b1f6278 BK |
729 | } |
730 | ||
3b520b23 SL |
731 | static int __init mtrr_init_finialize(void) |
732 | { | |
733 | if (!mtrr_if) | |
734 | return 0; | |
95ffa243 | 735 | if (use_intel()) { |
12031a62 | 736 | if (!changed_by_mtrr_cleanup) |
95ffa243 YL |
737 | mtrr_state_warn(); |
738 | } else { | |
27b46d76 | 739 | /* The CPUs haven't MTRR and seem to not support SMP. They have |
3b520b23 SL |
740 | * specific drivers, we use a tricky method to support |
741 | * suspend/resume for them. | |
742 | * TBD: is there any system with such CPU which supports | |
743 | * suspend/resume? if no, we should remove the code. | |
744 | */ | |
745 | sysdev_driver_register(&cpu_sysdev_class, | |
746 | &mtrr_sysdev_driver); | |
747 | } | |
748 | return 0; | |
749 | } | |
750 | subsys_initcall(mtrr_init_finialize); |