[linux-2.6-block.git] / arch / x86 / kernel / cpu / mtrr / cyrix.c

#include <linux/init.h>
#include <linux/io.h>
#include <linux/mm.h>

#include <asm/processor-cyrix.h>
#include <asm/processor-flags.h>
#include <asm/mtrr.h>
#include <asm/msr.h>

#include "mtrr.h"

static void
cyrix_get_arr(unsigned int reg, unsigned long *base,
	      unsigned long *size, mtrr_type * type)
{
	unsigned char arr, ccr3, rcr, shift;
	unsigned long flags;

	arr = CX86_ARR_BASE + (reg << 1) + reg;	/* avoid multiplication by 3 */

	local_irq_save(flags);

	ccr3 = getCx86(CX86_CCR3);
	setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);	/* enable MAPEN */
	((unsigned char *)base)[3] = getCx86(arr);
	((unsigned char *)base)[2] = getCx86(arr + 1);
	((unsigned char *)base)[1] = getCx86(arr + 2);
	rcr = getCx86(CX86_RCR_BASE + reg);
	setCx86(CX86_CCR3, ccr3);			/* disable MAPEN */

	local_irq_restore(flags);

	shift = ((unsigned char *) base)[1] & 0x0f;
	*base >>= PAGE_SHIFT;

	/*
	 * Power of two, at least 4K on ARR0-ARR6, 256K on ARR7
	 * Note: shift==0xf means 4G, this is unsupported.
	 */
	if (shift)
		*size = (reg < 7 ? 0x1UL : 0x40UL) << (shift - 1);
	else
		*size = 0;

	/* Bit 0 is Cache Enable on ARR7, Cache Disable on ARR0-ARR6 */
	if (reg < 7) {
		switch (rcr) {
		case 1:
			*type = MTRR_TYPE_UNCACHABLE;
			break;
		case 8:
			*type = MTRR_TYPE_WRBACK;
			break;
		case 9:
			*type = MTRR_TYPE_WRCOMB;
			break;
		case 24:
		default:
			*type = MTRR_TYPE_WRTHROUGH;
			break;
		}
	} else {
		switch (rcr) {
		case 0:
			*type = MTRR_TYPE_UNCACHABLE;
			break;
		case 8:
			*type = MTRR_TYPE_WRCOMB;
			break;
		case 9:
			*type = MTRR_TYPE_WRBACK;
			break;
		case 25:
		default:
			*type = MTRR_TYPE_WRTHROUGH;
			break;
		}
	}
}

/*
 * cyrix_get_free_region - get a free ARR.
 *
 * @base: the starting (base) address of the region.
 * @size: the size (in bytes) of the region.
 *
 * Returns: the index of the region on success, else -1 on error.
*/
static int
cyrix_get_free_region(unsigned long base, unsigned long size, int replace_reg)
{
	unsigned long lbase, lsize;
	mtrr_type ltype;
	int i;

	switch (replace_reg) {
	case 7:
		if (size < 0x40)
			break;
	case 6:
	case 5:
	case 4:
		return replace_reg;
	case 3:
	case 2:
	case 1:
	case 0:
		return replace_reg;
	}
	/* If we are to set up a region >32M then look at ARR7 immediately */
	if (size > 0x2000) {
		cyrix_get_arr(7, &lbase, &lsize, &ltype);
		if (lsize == 0)
			return 7;
		/* Else try ARR0-ARR6 first  */
	} else {
		for (i = 0; i < 7; i++) {
			cyrix_get_arr(i, &lbase, &lsize, &ltype);
			if (lsize == 0)
				return i;
		}
		/*
		 * ARR0-ARR6 isn't free
		 * try ARR7 but its size must be at least 256K
		 */
		cyrix_get_arr(i, &lbase, &lsize, &ltype);
		if ((lsize == 0) && (size >= 0x40))
			return i;
	}
	return -ENOSPC;
}

static u32 cr4, ccr3;

static void prepare_set(void)
{
	u32 cr0;

	/*  Save value of CR4 and clear Page Global Enable (bit 7)  */
	if (cpu_has_pge) {
		cr4 = read_cr4();
		write_cr4(cr4 & ~X86_CR4_PGE);
	}

	/*
	 * Disable and flush caches.
	 * Note that wbinvd flushes the TLBs as a side-effect
	 */
	cr0 = read_cr0() | X86_CR0_CD;
	wbinvd();
	write_cr0(cr0);
	wbinvd();

	/* Cyrix ARRs - everything else was excluded at the top */
	ccr3 = getCx86(CX86_CCR3);

	/* Cyrix ARRs - everything else was excluded at the top */
	setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);
}

static void post_set(void)
{
	/* Flush caches and TLBs */
	wbinvd();

	/* Cyrix ARRs - everything else was excluded at the top */
	setCx86(CX86_CCR3, ccr3);

	/* Enable caches */
	write_cr0(read_cr0() & 0xbfffffff);

	/* Restore value of CR4 */
	if (cpu_has_pge)
		write_cr4(cr4);
}

static void cyrix_set_arr(unsigned int reg, unsigned long base,
			  unsigned long size, mtrr_type type)
{
	unsigned char arr, arr_type, arr_size;

	arr = CX86_ARR_BASE + (reg << 1) + reg;	/* avoid multiplication by 3 */

	/* count down from 32M (ARR0-ARR6) or from 2G (ARR7) */
	if (reg >= 7)
		size >>= 6;

	size &= 0x7fff;		/* make sure arr_size <= 14 */
	for (arr_size = 0; size; arr_size++, size >>= 1)
		;

	if (reg < 7) {
		switch (type) {
		case MTRR_TYPE_UNCACHABLE:
			arr_type = 1;
			break;
		case MTRR_TYPE_WRCOMB:
			arr_type = 9;
			break;
		case MTRR_TYPE_WRTHROUGH:
			arr_type = 24;
			break;
		default:
			arr_type = 8;
			break;
		}
	} else {
		switch (type) {
		case MTRR_TYPE_UNCACHABLE:
			arr_type = 0;
			break;
		case MTRR_TYPE_WRCOMB:
			arr_type = 8;
			break;
		case MTRR_TYPE_WRTHROUGH:
			arr_type = 25;
			break;
		default:
			arr_type = 9;
			break;
		}
	}

	prepare_set();

	base <<= PAGE_SHIFT;
	setCx86(arr + 0,  ((unsigned char *)&base)[3]);
	setCx86(arr + 1,  ((unsigned char *)&base)[2]);
	setCx86(arr + 2, (((unsigned char *)&base)[1]) | arr_size);
	setCx86(CX86_RCR_BASE + reg, arr_type);

	post_set();
}

typedef struct {
	unsigned long	base;
	unsigned long	size;
	mtrr_type	type;
} arr_state_t;

static arr_state_t arr_state[8] = {
	{0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL},
	{0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}
};

static unsigned char ccr_state[7] = { 0, 0, 0, 0, 0, 0, 0 };

static void cyrix_set_all(void)
{
	int i;

	prepare_set();

	/* the CCRs are not contiguous */
	for (i = 0; i < 4; i++)
		setCx86(CX86_CCR0 + i, ccr_state[i]);
	for (; i < 7; i++)
		setCx86(CX86_CCR4 + i, ccr_state[i]);

	for (i = 0; i < 8; i++) {
		cyrix_set_arr(i, arr_state[i].base,
			      arr_state[i].size, arr_state[i].type);
	}

	post_set();
}

static struct mtrr_ops cyrix_mtrr_ops = {
	.vendor            = X86_VENDOR_CYRIX,
	.set_all	   = cyrix_set_all,
	.set               = cyrix_set_arr,
	.get               = cyrix_get_arr,
	.get_free_region   = cyrix_get_free_region,
	.validate_add_page = generic_validate_add_page,
	.have_wrcomb       = positive_have_wrcomb,
};

int __init cyrix_init_mtrr(void)
{
	set_mtrr_ops(&cyrix_mtrr_ops);
	return 0;
}
Commit	Line	Data
1da177e4	1	#include <linux/init.h>
23110377	2	#include <linux/io.h>
1da177e4	3	#include <linux/mm.h>
23110377	4
f25f64ed	5	#include <asm/processor-cyrix.h>
7ebad705	6	#include <asm/processor-flags.h>
23110377 JSR	7	#include <asm/mtrr.h>
	8	#include <asm/msr.h>
	9
1da177e4 LT	10	#include "mtrr.h"
1da177e4 LT	11
1da177e4 LT	12	static void
1da177e4 LT	13	cyrix_get_arr(unsigned int reg, unsigned long *base,
365bff80	14	unsigned long size, mtrr_type type)
1da177e4	15	{
1da177e4	16	unsigned char arr, ccr3, rcr, shift;
23110377	17	unsigned long flags;
1da177e4 LT	18
	19	arr = CX86_ARR_BASE + (reg << 1) + reg; /* avoid multiplication by 3 */
	20
1da177e4 LT	21	local_irq_save(flags);
	22
	23	ccr3 = getCx86(CX86_CCR3);
	24	setCx86(CX86_CCR3, (ccr3 & 0x0f) \| 0x10); /* enable MAPEN */
23110377 JSR	25	((unsigned char *)base)[3] = getCx86(arr);
	26	((unsigned char *)base)[2] = getCx86(arr + 1);
	27	((unsigned char *)base)[1] = getCx86(arr + 2);
1da177e4	28	rcr = getCx86(CX86_RCR_BASE + reg);
23110377	29	setCx86(CX86_CCR3, ccr3); /* disable MAPEN */
1da177e4	30
1da177e4	31	local_irq_restore(flags);
23110377	32
1da177e4 LT	33	shift = ((unsigned char *) base)[1] & 0x0f;
	34	*base >>= PAGE_SHIFT;
	35
23110377 JSR	36	/*
23110377 JSR	37	* Power of two, at least 4K on ARR0-ARR6, 256K on ARR7
1da177e4 LT	38	* Note: shift==0xf means 4G, this is unsupported.
	39	*/
	40	if (shift)
	41	*size = (reg < 7 ? 0x1UL : 0x40UL) << (shift - 1);
	42	else
	43	*size = 0;
	44
	45	/* Bit 0 is Cache Enable on ARR7, Cache Disable on ARR0-ARR6 */
	46	if (reg < 7) {
	47	switch (rcr) {
	48	case 1:
	49	*type = MTRR_TYPE_UNCACHABLE;
	50	break;
	51	case 8:
	52	*type = MTRR_TYPE_WRBACK;
	53	break;
	54	case 9:
	55	*type = MTRR_TYPE_WRCOMB;
	56	break;
	57	case 24:
	58	default:
	59	*type = MTRR_TYPE_WRTHROUGH;
	60	break;
	61	}
	62	} else {
	63	switch (rcr) {
	64	case 0:
	65	*type = MTRR_TYPE_UNCACHABLE;
	66	break;
	67	case 8:
	68	*type = MTRR_TYPE_WRCOMB;
	69	break;
	70	case 9:
	71	*type = MTRR_TYPE_WRBACK;
	72	break;
	73	case 25:
	74	default:
	75	*type = MTRR_TYPE_WRTHROUGH;
	76	break;
	77	}
	78	}
	79	}
	80
23110377 JSR	81	/*
	82	* cyrix_get_free_region - get a free ARR.
	83	*
	84	* @base: the starting (base) address of the region.
	85	* @size: the size (in bytes) of the region.
	86	*
	87	* Returns: the index of the region on success, else -1 on error.
	88	*/
1da177e4	89	static int
365bff80	90	cyrix_get_free_region(unsigned long base, unsigned long size, int replace_reg)
1da177e4	91	{
365bff80	92	unsigned long lbase, lsize;
23110377 JSR	93	mtrr_type ltype;
23110377 JSR	94	int i;
1da177e4	95
365bff80 JB	96	switch (replace_reg) {
	97	case 7:
	98	if (size < 0x40)
	99	break;
	100	case 6:
	101	case 5:
	102	case 4:
	103	return replace_reg;
	104	case 3:
365bff80 JB	105	case 2:
	106	case 1:
	107	case 0:
	108	return replace_reg;
	109	}
1da177e4 LT	110	/* If we are to set up a region >32M then look at ARR7 immediately */
	111	if (size > 0x2000) {
	112	cyrix_get_arr(7, &lbase, &lsize, &ltype);
	113	if (lsize == 0)
	114	return 7;
23110377	115	/* Else try ARR0-ARR6 first */
1da177e4 LT	116	} else {
	117	for (i = 0; i < 7; i++) {
	118	cyrix_get_arr(i, &lbase, &lsize, &ltype);
1da177e4 LT	119	if (lsize == 0)
	120	return i;
	121	}
23110377 JSR	122	/*
	123	* ARR0-ARR6 isn't free
	124	* try ARR7 but its size must be at least 256K
	125	*/
1da177e4 LT	126	cyrix_get_arr(i, &lbase, &lsize, &ltype);
	127	if ((lsize == 0) && (size >= 0x40))
	128	return i;
	129	}
	130	return -ENOSPC;
	131	}
	132
23110377	133	static u32 cr4, ccr3;
1da177e4 LT	134
	135	static void prepare_set(void)
	136	{
	137	u32 cr0;
	138
	139	/* Save value of CR4 and clear Page Global Enable (bit 7) */
23110377	140	if (cpu_has_pge) {
1da177e4	141	cr4 = read_cr4();
17304383	142	write_cr4(cr4 & ~X86_CR4_PGE);
1da177e4 LT	143	}
1da177e4 LT	144
23110377 JSR	145	/*
	146	* Disable and flush caches.
	147	* Note that wbinvd flushes the TLBs as a side-effect
	148	*/
7ebad705	149	cr0 = read_cr0() \| X86_CR0_CD;
1da177e4 LT	150	wbinvd();
	151	write_cr0(cr0);
	152	wbinvd();
	153
27b46d76	154	/* Cyrix ARRs - everything else was excluded at the top */
1da177e4 LT	155	ccr3 = getCx86(CX86_CCR3);
1da177e4 LT	156
27b46d76	157	/* Cyrix ARRs - everything else was excluded at the top */
1da177e4	158	setCx86(CX86_CCR3, (ccr3 & 0x0f) \| 0x10);
1da177e4 LT	159	}
	160
	161	static void post_set(void)
	162	{
23110377	163	/* Flush caches and TLBs */
1da177e4 LT	164	wbinvd();
	165
	166	/* Cyrix ARRs - everything else was excluded at the top */
	167	setCx86(CX86_CCR3, ccr3);
23110377 JSR	168
23110377 JSR	169	/* Enable caches */
1da177e4 LT	170	write_cr0(read_cr0() & 0xbfffffff);
1da177e4 LT	171
23110377 JSR	172	/* Restore value of CR4 */
23110377 JSR	173	if (cpu_has_pge)
1da177e4 LT	174	write_cr4(cr4);
	175	}
	176
	177	static void cyrix_set_arr(unsigned int reg, unsigned long base,
	178	unsigned long size, mtrr_type type)
	179	{
	180	unsigned char arr, arr_type, arr_size;
	181
	182	arr = CX86_ARR_BASE + (reg << 1) + reg; /* avoid multiplication by 3 */
	183
	184	/* count down from 32M (ARR0-ARR6) or from 2G (ARR7) */
	185	if (reg >= 7)
	186	size >>= 6;
	187
	188	size &= 0x7fff; /* make sure arr_size <= 14 */
23110377 JSR	189	for (arr_size = 0; size; arr_size++, size >>= 1)
23110377 JSR	190	;
1da177e4 LT	191
	192	if (reg < 7) {
	193	switch (type) {
	194	case MTRR_TYPE_UNCACHABLE:
	195	arr_type = 1;
	196	break;
	197	case MTRR_TYPE_WRCOMB:
	198	arr_type = 9;
	199	break;
	200	case MTRR_TYPE_WRTHROUGH:
	201	arr_type = 24;
	202	break;
	203	default:
	204	arr_type = 8;
	205	break;
	206	}
	207	} else {
	208	switch (type) {
	209	case MTRR_TYPE_UNCACHABLE:
	210	arr_type = 0;
	211	break;
	212	case MTRR_TYPE_WRCOMB:
	213	arr_type = 8;
	214	break;
	215	case MTRR_TYPE_WRTHROUGH:
	216	arr_type = 25;
	217	break;
	218	default:
	219	arr_type = 9;
	220	break;
	221	}
	222	}
	223
	224	prepare_set();
	225
	226	base <<= PAGE_SHIFT;
23110377 JSR	227	setCx86(arr + 0, ((unsigned char *)&base)[3]);
	228	setCx86(arr + 1, ((unsigned char *)&base)[2]);
	229	setCx86(arr + 2, (((unsigned char *)&base)[1]) \| arr_size);
1da177e4 LT	230	setCx86(CX86_RCR_BASE + reg, arr_type);
	231
	232	post_set();
	233	}
	234
	235	typedef struct {
23110377 JSR	236	unsigned long base;
	237	unsigned long size;
	238	mtrr_type type;
1da177e4 LT	239	} arr_state_t;
1da177e4 LT	240
80581c43	241	static arr_state_t arr_state[8] = {
1da177e4 LT	242	{0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL},
	243	{0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}
	244	};
	245
80581c43	246	static unsigned char ccr_state[7] = { 0, 0, 0, 0, 0, 0, 0 };
1da177e4 LT	247
	248	static void cyrix_set_all(void)
	249	{
	250	int i;
	251
	252	prepare_set();
	253
	254	/* the CCRs are not contiguous */
	255	for (i = 0; i < 4; i++)
	256	setCx86(CX86_CCR0 + i, ccr_state[i]);
	257	for (; i < 7; i++)
	258	setCx86(CX86_CCR4 + i, ccr_state[i]);
23110377 JSR	259
	260	for (i = 0; i < 8; i++) {
	261	cyrix_set_arr(i, arr_state[i].base,
1da177e4	262	arr_state[i].size, arr_state[i].type);
23110377	263	}
1da177e4 LT	264
	265	post_set();
	266	}
	267
1da177e4 LT	268	static struct mtrr_ops cyrix_mtrr_ops = {
1da177e4 LT	269	.vendor = X86_VENDOR_CYRIX,
1da177e4 LT	270	.set_all = cyrix_set_all,
	271	.set = cyrix_set_arr,
	272	.get = cyrix_get_arr,
	273	.get_free_region = cyrix_get_free_region,
	274	.validate_add_page = generic_validate_add_page,
	275	.have_wrcomb = positive_have_wrcomb,
	276	};
	277
	278	int __init cyrix_init_mtrr(void)
	279	{
	280	set_mtrr_ops(&cyrix_mtrr_ops);
	281	return 0;
	282	}