Commit | Line | Data |
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1da177e4 | 1 | /* |
6b44e72a | 2 | * Intel CPU Microcode Update Driver for Linux |
1da177e4 | 3 | * |
6b44e72a BP |
4 | * Copyright (C) 2000-2006 Tigran Aivazian <tigran@aivazian.fsnet.co.uk> |
5 | * 2006 Shaohua Li <shaohua.li@intel.com> | |
1da177e4 | 6 | * |
fe055896 BP |
7 | * Intel CPU microcode early update for Linux |
8 | * | |
9 | * Copyright (C) 2012 Fenghua Yu <fenghua.yu@intel.com> | |
10 | * H Peter Anvin" <hpa@zytor.com> | |
11 | * | |
6b44e72a BP |
12 | * This program is free software; you can redistribute it and/or |
13 | * modify it under the terms of the GNU General Public License | |
14 | * as published by the Free Software Foundation; either version | |
15 | * 2 of the License, or (at your option) any later version. | |
1da177e4 | 16 | */ |
f58e1f53 | 17 | |
fe055896 BP |
18 | /* |
19 | * This needs to be before all headers so that pr_debug in printk.h doesn't turn | |
20 | * printk calls into no_printk(). | |
21 | * | |
22 | *#define DEBUG | |
23 | */ | |
6b26e1bf | 24 | #define pr_fmt(fmt) "microcode: " fmt |
f58e1f53 | 25 | |
fe055896 | 26 | #include <linux/earlycpio.h> |
4bae1967 | 27 | #include <linux/firmware.h> |
4bae1967 | 28 | #include <linux/uaccess.h> |
fe055896 BP |
29 | #include <linux/vmalloc.h> |
30 | #include <linux/initrd.h> | |
4bae1967 | 31 | #include <linux/kernel.h> |
fe055896 BP |
32 | #include <linux/slab.h> |
33 | #include <linux/cpu.h> | |
34 | #include <linux/mm.h> | |
1da177e4 | 35 | |
9cd4d78e | 36 | #include <asm/microcode_intel.h> |
4bae1967 | 37 | #include <asm/processor.h> |
fe055896 BP |
38 | #include <asm/tlbflush.h> |
39 | #include <asm/setup.h> | |
4bae1967 | 40 | #include <asm/msr.h> |
1da177e4 | 41 | |
f8bb45e2 | 42 | /* |
9f3cc2a0 BP |
43 | * Temporary microcode blobs pointers storage. We note here during early load |
44 | * the pointers to microcode blobs we've got from whatever storage (detached | |
45 | * initrd, builtin). Later on, we put those into final storage | |
46 | * mc_saved_data.mc_saved. | |
47 | * | |
48 | * Important: those are offsets from the beginning of initrd or absolute | |
49 | * addresses within the kernel image when built-in. | |
f8bb45e2 BP |
50 | */ |
51 | static unsigned long mc_tmp_ptrs[MAX_UCODE_COUNT]; | |
52 | ||
fe055896 | 53 | static struct mc_saved_data { |
4fe9349f | 54 | unsigned int num_saved; |
fe055896 BP |
55 | struct microcode_intel **mc_saved; |
56 | } mc_saved_data; | |
57 | ||
6c545647 BP |
58 | /* Microcode blobs within the initrd. 0 if builtin. */ |
59 | static struct ucode_blobs { | |
60 | unsigned long start; | |
61 | bool valid; | |
62 | } blobs; | |
63 | ||
9f3cc2a0 | 64 | /* Go through saved patches and find the one suitable for the current CPU. */ |
fe055896 | 65 | static enum ucode_state |
9198251a | 66 | find_microcode_patch(struct microcode_intel **saved, |
fe055896 BP |
67 | unsigned int num_saved, struct ucode_cpu_info *uci) |
68 | { | |
69 | struct microcode_intel *ucode_ptr, *new_mc = NULL; | |
70 | struct microcode_header_intel *mc_hdr; | |
71 | int new_rev, ret, i; | |
72 | ||
73 | new_rev = uci->cpu_sig.rev; | |
74 | ||
75 | for (i = 0; i < num_saved; i++) { | |
76 | ucode_ptr = saved[i]; | |
77 | mc_hdr = (struct microcode_header_intel *)ucode_ptr; | |
78 | ||
79 | ret = has_newer_microcode(ucode_ptr, | |
80 | uci->cpu_sig.sig, | |
81 | uci->cpu_sig.pf, | |
82 | new_rev); | |
83 | if (!ret) | |
84 | continue; | |
85 | ||
86 | new_rev = mc_hdr->rev; | |
87 | new_mc = ucode_ptr; | |
88 | } | |
89 | ||
90 | if (!new_mc) | |
91 | return UCODE_NFOUND; | |
92 | ||
93 | uci->mc = (struct microcode_intel *)new_mc; | |
94 | return UCODE_OK; | |
95 | } | |
96 | ||
97 | static inline void | |
f8bb45e2 BP |
98 | copy_ptrs(struct microcode_intel **mc_saved, unsigned long *mc_ptrs, |
99 | unsigned long off, int num_saved) | |
fe055896 BP |
100 | { |
101 | int i; | |
102 | ||
103 | for (i = 0; i < num_saved; i++) | |
f8bb45e2 | 104 | mc_saved[i] = (struct microcode_intel *)(mc_ptrs[i] + off); |
fe055896 BP |
105 | } |
106 | ||
107 | #ifdef CONFIG_X86_32 | |
108 | static void | |
bd6fe58d | 109 | microcode_phys(struct microcode_intel **mc_saved_tmp, struct mc_saved_data *mcs) |
fe055896 BP |
110 | { |
111 | int i; | |
112 | struct microcode_intel ***mc_saved; | |
113 | ||
bd6fe58d BP |
114 | mc_saved = (struct microcode_intel ***)__pa_nodebug(&mcs->mc_saved); |
115 | ||
4fe9349f | 116 | for (i = 0; i < mcs->num_saved; i++) { |
fe055896 BP |
117 | struct microcode_intel *p; |
118 | ||
bd6fe58d | 119 | p = *(struct microcode_intel **)__pa_nodebug(mcs->mc_saved + i); |
fe055896 BP |
120 | mc_saved_tmp[i] = (struct microcode_intel *)__pa_nodebug(p); |
121 | } | |
122 | } | |
123 | #endif | |
124 | ||
125 | static enum ucode_state | |
f8bb45e2 BP |
126 | load_microcode(struct mc_saved_data *mcs, unsigned long *mc_ptrs, |
127 | unsigned long offset, struct ucode_cpu_info *uci) | |
fe055896 BP |
128 | { |
129 | struct microcode_intel *mc_saved_tmp[MAX_UCODE_COUNT]; | |
4fe9349f | 130 | unsigned int count = mcs->num_saved; |
fe055896 | 131 | |
bd6fe58d | 132 | if (!mcs->mc_saved) { |
f8bb45e2 | 133 | copy_ptrs(mc_saved_tmp, mc_ptrs, offset, count); |
fe055896 | 134 | |
9198251a | 135 | return find_microcode_patch(mc_saved_tmp, count, uci); |
fe055896 BP |
136 | } else { |
137 | #ifdef CONFIG_X86_32 | |
bd6fe58d | 138 | microcode_phys(mc_saved_tmp, mcs); |
9198251a | 139 | return find_microcode_patch(mc_saved_tmp, count, uci); |
fe055896 | 140 | #else |
9198251a | 141 | return find_microcode_patch(mcs->mc_saved, count, uci); |
fe055896 BP |
142 | #endif |
143 | } | |
144 | } | |
145 | ||
146 | /* | |
147 | * Given CPU signature and a microcode patch, this function finds if the | |
148 | * microcode patch has matching family and model with the CPU. | |
149 | */ | |
150 | static enum ucode_state | |
151 | matching_model_microcode(struct microcode_header_intel *mc_header, | |
152 | unsigned long sig) | |
153 | { | |
154 | unsigned int fam, model; | |
155 | unsigned int fam_ucode, model_ucode; | |
156 | struct extended_sigtable *ext_header; | |
157 | unsigned long total_size = get_totalsize(mc_header); | |
158 | unsigned long data_size = get_datasize(mc_header); | |
159 | int ext_sigcount, i; | |
160 | struct extended_signature *ext_sig; | |
161 | ||
99f925ce | 162 | fam = x86_family(sig); |
fe055896 BP |
163 | model = x86_model(sig); |
164 | ||
99f925ce | 165 | fam_ucode = x86_family(mc_header->sig); |
fe055896 BP |
166 | model_ucode = x86_model(mc_header->sig); |
167 | ||
168 | if (fam == fam_ucode && model == model_ucode) | |
169 | return UCODE_OK; | |
170 | ||
171 | /* Look for ext. headers: */ | |
172 | if (total_size <= data_size + MC_HEADER_SIZE) | |
173 | return UCODE_NFOUND; | |
174 | ||
175 | ext_header = (void *) mc_header + data_size + MC_HEADER_SIZE; | |
176 | ext_sig = (void *)ext_header + EXT_HEADER_SIZE; | |
177 | ext_sigcount = ext_header->count; | |
178 | ||
179 | for (i = 0; i < ext_sigcount; i++) { | |
99f925ce | 180 | fam_ucode = x86_family(ext_sig->sig); |
fe055896 BP |
181 | model_ucode = x86_model(ext_sig->sig); |
182 | ||
183 | if (fam == fam_ucode && model == model_ucode) | |
184 | return UCODE_OK; | |
185 | ||
186 | ext_sig++; | |
187 | } | |
188 | return UCODE_NFOUND; | |
189 | } | |
190 | ||
191 | static int | |
bd6fe58d | 192 | save_microcode(struct mc_saved_data *mcs, |
fe055896 | 193 | struct microcode_intel **mc_saved_src, |
4fe9349f | 194 | unsigned int num_saved) |
fe055896 BP |
195 | { |
196 | int i, j; | |
197 | struct microcode_intel **saved_ptr; | |
198 | int ret; | |
199 | ||
4fe9349f | 200 | if (!num_saved) |
fe055896 BP |
201 | return -EINVAL; |
202 | ||
203 | /* | |
204 | * Copy new microcode data. | |
205 | */ | |
4fe9349f | 206 | saved_ptr = kcalloc(num_saved, sizeof(struct microcode_intel *), GFP_KERNEL); |
fe055896 BP |
207 | if (!saved_ptr) |
208 | return -ENOMEM; | |
209 | ||
4fe9349f | 210 | for (i = 0; i < num_saved; i++) { |
fe055896 BP |
211 | struct microcode_header_intel *mc_hdr; |
212 | struct microcode_intel *mc; | |
213 | unsigned long size; | |
214 | ||
215 | if (!mc_saved_src[i]) { | |
216 | ret = -EINVAL; | |
217 | goto err; | |
218 | } | |
219 | ||
220 | mc = mc_saved_src[i]; | |
221 | mc_hdr = &mc->hdr; | |
222 | size = get_totalsize(mc_hdr); | |
223 | ||
9cc6f743 | 224 | saved_ptr[i] = kmemdup(mc, size, GFP_KERNEL); |
fe055896 BP |
225 | if (!saved_ptr[i]) { |
226 | ret = -ENOMEM; | |
227 | goto err; | |
228 | } | |
fe055896 BP |
229 | } |
230 | ||
231 | /* | |
232 | * Point to newly saved microcode. | |
233 | */ | |
4fe9349f BP |
234 | mcs->mc_saved = saved_ptr; |
235 | mcs->num_saved = num_saved; | |
fe055896 BP |
236 | |
237 | return 0; | |
238 | ||
239 | err: | |
240 | for (j = 0; j <= i; j++) | |
241 | kfree(saved_ptr[j]); | |
242 | kfree(saved_ptr); | |
243 | ||
244 | return ret; | |
245 | } | |
246 | ||
247 | /* | |
248 | * A microcode patch in ucode_ptr is saved into mc_saved | |
249 | * - if it has matching signature and newer revision compared to an existing | |
250 | * patch mc_saved. | |
251 | * - or if it is a newly discovered microcode patch. | |
252 | * | |
253 | * The microcode patch should have matching model with CPU. | |
254 | * | |
255 | * Returns: The updated number @num_saved of saved microcode patches. | |
256 | */ | |
257 | static unsigned int _save_mc(struct microcode_intel **mc_saved, | |
258 | u8 *ucode_ptr, unsigned int num_saved) | |
259 | { | |
260 | struct microcode_header_intel *mc_hdr, *mc_saved_hdr; | |
261 | unsigned int sig, pf; | |
262 | int found = 0, i; | |
263 | ||
264 | mc_hdr = (struct microcode_header_intel *)ucode_ptr; | |
265 | ||
266 | for (i = 0; i < num_saved; i++) { | |
267 | mc_saved_hdr = (struct microcode_header_intel *)mc_saved[i]; | |
268 | sig = mc_saved_hdr->sig; | |
269 | pf = mc_saved_hdr->pf; | |
270 | ||
271 | if (!find_matching_signature(ucode_ptr, sig, pf)) | |
272 | continue; | |
273 | ||
274 | found = 1; | |
275 | ||
276 | if (mc_hdr->rev <= mc_saved_hdr->rev) | |
277 | continue; | |
278 | ||
279 | /* | |
280 | * Found an older ucode saved earlier. Replace it with | |
281 | * this newer one. | |
282 | */ | |
283 | mc_saved[i] = (struct microcode_intel *)ucode_ptr; | |
284 | break; | |
285 | } | |
286 | ||
287 | /* Newly detected microcode, save it to memory. */ | |
288 | if (i >= num_saved && !found) | |
289 | mc_saved[num_saved++] = (struct microcode_intel *)ucode_ptr; | |
290 | ||
291 | return num_saved; | |
292 | } | |
293 | ||
294 | /* | |
295 | * Get microcode matching with BSP's model. Only CPUs with the same model as | |
296 | * BSP can stay in the platform. | |
297 | */ | |
298 | static enum ucode_state __init | |
f96fde53 BP |
299 | get_matching_model_microcode(unsigned long start, void *data, size_t size, |
300 | struct mc_saved_data *mcs, unsigned long *mc_ptrs, | |
fe055896 BP |
301 | struct ucode_cpu_info *uci) |
302 | { | |
fe055896 | 303 | struct microcode_intel *mc_saved_tmp[MAX_UCODE_COUNT]; |
f96fde53 | 304 | struct microcode_header_intel *mc_header; |
4fe9349f | 305 | unsigned int num_saved = mcs->num_saved; |
f96fde53 BP |
306 | enum ucode_state state = UCODE_OK; |
307 | unsigned int leftover = size; | |
308 | u8 *ucode_ptr = data; | |
309 | unsigned int mc_size; | |
fe055896 BP |
310 | int i; |
311 | ||
4fe9349f | 312 | while (leftover && num_saved < ARRAY_SIZE(mc_saved_tmp)) { |
fe055896 BP |
313 | |
314 | if (leftover < sizeof(mc_header)) | |
315 | break; | |
316 | ||
317 | mc_header = (struct microcode_header_intel *)ucode_ptr; | |
318 | ||
319 | mc_size = get_totalsize(mc_header); | |
320 | if (!mc_size || mc_size > leftover || | |
321 | microcode_sanity_check(ucode_ptr, 0) < 0) | |
322 | break; | |
323 | ||
324 | leftover -= mc_size; | |
325 | ||
326 | /* | |
327 | * Since APs with same family and model as the BSP may boot in | |
328 | * the platform, we need to find and save microcode patches | |
329 | * with the same family and model as the BSP. | |
330 | */ | |
f96fde53 | 331 | if (matching_model_microcode(mc_header, uci->cpu_sig.sig) != UCODE_OK) { |
fe055896 BP |
332 | ucode_ptr += mc_size; |
333 | continue; | |
334 | } | |
335 | ||
4fe9349f | 336 | num_saved = _save_mc(mc_saved_tmp, ucode_ptr, num_saved); |
fe055896 BP |
337 | |
338 | ucode_ptr += mc_size; | |
339 | } | |
340 | ||
341 | if (leftover) { | |
342 | state = UCODE_ERROR; | |
f96fde53 | 343 | return state; |
fe055896 BP |
344 | } |
345 | ||
4fe9349f | 346 | if (!num_saved) { |
fe055896 | 347 | state = UCODE_NFOUND; |
f96fde53 | 348 | return state; |
fe055896 BP |
349 | } |
350 | ||
4fe9349f | 351 | for (i = 0; i < num_saved; i++) |
f8bb45e2 | 352 | mc_ptrs[i] = (unsigned long)mc_saved_tmp[i] - start; |
fe055896 | 353 | |
4fe9349f | 354 | mcs->num_saved = num_saved; |
f96fde53 | 355 | |
fe055896 BP |
356 | return state; |
357 | } | |
358 | ||
359 | static int collect_cpu_info_early(struct ucode_cpu_info *uci) | |
360 | { | |
361 | unsigned int val[2]; | |
362 | unsigned int family, model; | |
363 | struct cpu_signature csig; | |
364 | unsigned int eax, ebx, ecx, edx; | |
365 | ||
366 | csig.sig = 0; | |
367 | csig.pf = 0; | |
368 | csig.rev = 0; | |
369 | ||
370 | memset(uci, 0, sizeof(*uci)); | |
371 | ||
372 | eax = 0x00000001; | |
373 | ecx = 0; | |
374 | native_cpuid(&eax, &ebx, &ecx, &edx); | |
375 | csig.sig = eax; | |
376 | ||
99f925ce | 377 | family = x86_family(csig.sig); |
fe055896 BP |
378 | model = x86_model(csig.sig); |
379 | ||
380 | if ((model >= 5) || (family > 6)) { | |
381 | /* get processor flags from MSR 0x17 */ | |
382 | native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); | |
383 | csig.pf = 1 << ((val[1] >> 18) & 7); | |
384 | } | |
c416e611 | 385 | native_wrmsrl(MSR_IA32_UCODE_REV, 0); |
fe055896 BP |
386 | |
387 | /* As documented in the SDM: Do a CPUID 1 here */ | |
388 | sync_core(); | |
389 | ||
390 | /* get the current revision from MSR 0x8B */ | |
391 | native_rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]); | |
392 | ||
393 | csig.rev = val[1]; | |
394 | ||
395 | uci->cpu_sig = csig; | |
396 | uci->valid = 1; | |
397 | ||
398 | return 0; | |
399 | } | |
400 | ||
fe055896 BP |
401 | static void show_saved_mc(void) |
402 | { | |
c595ac2b | 403 | #ifdef DEBUG |
fe055896 BP |
404 | int i, j; |
405 | unsigned int sig, pf, rev, total_size, data_size, date; | |
406 | struct ucode_cpu_info uci; | |
407 | ||
4fe9349f | 408 | if (!mc_saved_data.num_saved) { |
fe055896 BP |
409 | pr_debug("no microcode data saved.\n"); |
410 | return; | |
411 | } | |
4fe9349f | 412 | pr_debug("Total microcode saved: %d\n", mc_saved_data.num_saved); |
fe055896 BP |
413 | |
414 | collect_cpu_info_early(&uci); | |
415 | ||
416 | sig = uci.cpu_sig.sig; | |
417 | pf = uci.cpu_sig.pf; | |
418 | rev = uci.cpu_sig.rev; | |
419 | pr_debug("CPU: sig=0x%x, pf=0x%x, rev=0x%x\n", sig, pf, rev); | |
420 | ||
4fe9349f | 421 | for (i = 0; i < mc_saved_data.num_saved; i++) { |
fe055896 BP |
422 | struct microcode_header_intel *mc_saved_header; |
423 | struct extended_sigtable *ext_header; | |
424 | int ext_sigcount; | |
425 | struct extended_signature *ext_sig; | |
426 | ||
427 | mc_saved_header = (struct microcode_header_intel *) | |
428 | mc_saved_data.mc_saved[i]; | |
429 | sig = mc_saved_header->sig; | |
430 | pf = mc_saved_header->pf; | |
431 | rev = mc_saved_header->rev; | |
432 | total_size = get_totalsize(mc_saved_header); | |
433 | data_size = get_datasize(mc_saved_header); | |
434 | date = mc_saved_header->date; | |
435 | ||
c19ca6cb | 436 | pr_debug("mc_saved[%d]: sig=0x%x, pf=0x%x, rev=0x%x, total size=0x%x, date = %04x-%02x-%02x\n", |
fe055896 BP |
437 | i, sig, pf, rev, total_size, |
438 | date & 0xffff, | |
439 | date >> 24, | |
440 | (date >> 16) & 0xff); | |
441 | ||
442 | /* Look for ext. headers: */ | |
443 | if (total_size <= data_size + MC_HEADER_SIZE) | |
444 | continue; | |
445 | ||
446 | ext_header = (void *) mc_saved_header + data_size + MC_HEADER_SIZE; | |
447 | ext_sigcount = ext_header->count; | |
448 | ext_sig = (void *)ext_header + EXT_HEADER_SIZE; | |
449 | ||
450 | for (j = 0; j < ext_sigcount; j++) { | |
451 | sig = ext_sig->sig; | |
452 | pf = ext_sig->pf; | |
453 | ||
454 | pr_debug("\tExtended[%d]: sig=0x%x, pf=0x%x\n", | |
455 | j, sig, pf); | |
456 | ||
457 | ext_sig++; | |
458 | } | |
459 | ||
460 | } | |
fe055896 | 461 | #endif |
c595ac2b | 462 | } |
fe055896 | 463 | |
fe055896 BP |
464 | /* |
465 | * Save this mc into mc_saved_data. So it will be loaded early when a CPU is | |
466 | * hot added or resumes. | |
467 | * | |
468 | * Please make sure this mc should be a valid microcode patch before calling | |
469 | * this function. | |
470 | */ | |
0c5fa827 | 471 | static void save_mc_for_early(u8 *mc) |
fe055896 | 472 | { |
0c5fa827 | 473 | #ifdef CONFIG_HOTPLUG_CPU |
9f3cc2a0 | 474 | /* Synchronization during CPU hotplug. */ |
0c5fa827 BP |
475 | static DEFINE_MUTEX(x86_cpu_microcode_mutex); |
476 | ||
fe055896 BP |
477 | struct microcode_intel *mc_saved_tmp[MAX_UCODE_COUNT]; |
478 | unsigned int mc_saved_count_init; | |
4fe9349f | 479 | unsigned int num_saved; |
fe055896 | 480 | struct microcode_intel **mc_saved; |
0c5fa827 | 481 | int ret, i; |
fe055896 | 482 | |
fe055896 BP |
483 | mutex_lock(&x86_cpu_microcode_mutex); |
484 | ||
4fe9349f BP |
485 | mc_saved_count_init = mc_saved_data.num_saved; |
486 | num_saved = mc_saved_data.num_saved; | |
fe055896 BP |
487 | mc_saved = mc_saved_data.mc_saved; |
488 | ||
4fe9349f | 489 | if (mc_saved && num_saved) |
fe055896 | 490 | memcpy(mc_saved_tmp, mc_saved, |
4fe9349f | 491 | num_saved * sizeof(struct microcode_intel *)); |
fe055896 BP |
492 | /* |
493 | * Save the microcode patch mc in mc_save_tmp structure if it's a newer | |
494 | * version. | |
495 | */ | |
4fe9349f | 496 | num_saved = _save_mc(mc_saved_tmp, mc, num_saved); |
fe055896 BP |
497 | |
498 | /* | |
499 | * Save the mc_save_tmp in global mc_saved_data. | |
500 | */ | |
4fe9349f | 501 | ret = save_microcode(&mc_saved_data, mc_saved_tmp, num_saved); |
fe055896 BP |
502 | if (ret) { |
503 | pr_err("Cannot save microcode patch.\n"); | |
504 | goto out; | |
505 | } | |
506 | ||
507 | show_saved_mc(); | |
508 | ||
509 | /* | |
510 | * Free old saved microcode data. | |
511 | */ | |
512 | if (mc_saved) { | |
513 | for (i = 0; i < mc_saved_count_init; i++) | |
514 | kfree(mc_saved[i]); | |
515 | kfree(mc_saved); | |
516 | } | |
517 | ||
518 | out: | |
519 | mutex_unlock(&x86_cpu_microcode_mutex); | |
fe055896 | 520 | #endif |
0c5fa827 | 521 | } |
fe055896 BP |
522 | |
523 | static bool __init load_builtin_intel_microcode(struct cpio_data *cp) | |
524 | { | |
525 | #ifdef CONFIG_X86_64 | |
526 | unsigned int eax = 0x00000001, ebx, ecx = 0, edx; | |
fe055896 BP |
527 | char name[30]; |
528 | ||
529 | native_cpuid(&eax, &ebx, &ecx, &edx); | |
530 | ||
99f925ce BP |
531 | sprintf(name, "intel-ucode/%02x-%02x-%02x", |
532 | x86_family(eax), x86_model(eax), x86_stepping(eax)); | |
fe055896 BP |
533 | |
534 | return get_builtin_firmware(cp, name); | |
535 | #else | |
536 | return false; | |
537 | #endif | |
538 | } | |
539 | ||
fe055896 BP |
540 | /* |
541 | * Print ucode update info. | |
542 | */ | |
543 | static void | |
544 | print_ucode_info(struct ucode_cpu_info *uci, unsigned int date) | |
545 | { | |
b7f500ae BP |
546 | pr_info_once("microcode updated early to revision 0x%x, date = %04x-%02x-%02x\n", |
547 | uci->cpu_sig.rev, | |
548 | date & 0xffff, | |
549 | date >> 24, | |
550 | (date >> 16) & 0xff); | |
fe055896 BP |
551 | } |
552 | ||
553 | #ifdef CONFIG_X86_32 | |
554 | ||
555 | static int delay_ucode_info; | |
556 | static int current_mc_date; | |
557 | ||
558 | /* | |
559 | * Print early updated ucode info after printk works. This is delayed info dump. | |
560 | */ | |
561 | void show_ucode_info_early(void) | |
562 | { | |
563 | struct ucode_cpu_info uci; | |
564 | ||
565 | if (delay_ucode_info) { | |
566 | collect_cpu_info_early(&uci); | |
567 | print_ucode_info(&uci, current_mc_date); | |
568 | delay_ucode_info = 0; | |
569 | } | |
570 | } | |
571 | ||
572 | /* | |
573 | * At this point, we can not call printk() yet. Keep microcode patch number in | |
574 | * mc_saved_data.mc_saved and delay printing microcode info in | |
575 | * show_ucode_info_early() until printk() works. | |
576 | */ | |
577 | static void print_ucode(struct ucode_cpu_info *uci) | |
578 | { | |
de778275 | 579 | struct microcode_intel *mc; |
fe055896 BP |
580 | int *delay_ucode_info_p; |
581 | int *current_mc_date_p; | |
582 | ||
de778275 BP |
583 | mc = uci->mc; |
584 | if (!mc) | |
fe055896 BP |
585 | return; |
586 | ||
587 | delay_ucode_info_p = (int *)__pa_nodebug(&delay_ucode_info); | |
588 | current_mc_date_p = (int *)__pa_nodebug(¤t_mc_date); | |
589 | ||
590 | *delay_ucode_info_p = 1; | |
de778275 | 591 | *current_mc_date_p = mc->hdr.date; |
fe055896 BP |
592 | } |
593 | #else | |
594 | ||
595 | /* | |
596 | * Flush global tlb. We only do this in x86_64 where paging has been enabled | |
597 | * already and PGE should be enabled as well. | |
598 | */ | |
599 | static inline void flush_tlb_early(void) | |
600 | { | |
601 | __native_flush_tlb_global_irq_disabled(); | |
602 | } | |
603 | ||
604 | static inline void print_ucode(struct ucode_cpu_info *uci) | |
605 | { | |
de778275 | 606 | struct microcode_intel *mc; |
fe055896 | 607 | |
de778275 BP |
608 | mc = uci->mc; |
609 | if (!mc) | |
fe055896 BP |
610 | return; |
611 | ||
de778275 | 612 | print_ucode_info(uci, mc->hdr.date); |
fe055896 BP |
613 | } |
614 | #endif | |
615 | ||
616 | static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) | |
617 | { | |
de778275 | 618 | struct microcode_intel *mc; |
fe055896 BP |
619 | unsigned int val[2]; |
620 | ||
de778275 BP |
621 | mc = uci->mc; |
622 | if (!mc) | |
fe055896 BP |
623 | return 0; |
624 | ||
625 | /* write microcode via MSR 0x79 */ | |
c416e611 BP |
626 | native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); |
627 | native_wrmsrl(MSR_IA32_UCODE_REV, 0); | |
fe055896 BP |
628 | |
629 | /* As documented in the SDM: Do a CPUID 1 here */ | |
630 | sync_core(); | |
631 | ||
632 | /* get the current revision from MSR 0x8B */ | |
633 | native_rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]); | |
de778275 | 634 | if (val[1] != mc->hdr.rev) |
fe055896 BP |
635 | return -1; |
636 | ||
637 | #ifdef CONFIG_X86_64 | |
638 | /* Flush global tlb. This is precaution. */ | |
639 | flush_tlb_early(); | |
640 | #endif | |
641 | uci->cpu_sig.rev = val[1]; | |
642 | ||
643 | if (early) | |
644 | print_ucode(uci); | |
645 | else | |
de778275 | 646 | print_ucode_info(uci, mc->hdr.date); |
fe055896 BP |
647 | |
648 | return 0; | |
649 | } | |
650 | ||
651 | /* | |
652 | * This function converts microcode patch offsets previously stored in | |
f8bb45e2 | 653 | * mc_tmp_ptrs to pointers and stores the pointers in mc_saved_data. |
fe055896 BP |
654 | */ |
655 | int __init save_microcode_in_initrd_intel(void) | |
656 | { | |
fe055896 | 657 | struct microcode_intel *mc_saved[MAX_UCODE_COUNT]; |
6c545647 BP |
658 | unsigned int count = mc_saved_data.num_saved; |
659 | unsigned long offset = 0; | |
660 | int ret; | |
fe055896 | 661 | |
4fe9349f | 662 | if (!count) |
6c545647 | 663 | return 0; |
fe055896 | 664 | |
6c545647 BP |
665 | /* |
666 | * We have found a valid initrd but it might've been relocated in the | |
667 | * meantime so get its updated address. | |
668 | */ | |
669 | if (IS_ENABLED(CONFIG_BLK_DEV_INITRD) && blobs.valid) | |
670 | offset = initrd_start; | |
671 | ||
672 | copy_ptrs(mc_saved, mc_tmp_ptrs, offset, count); | |
4fe9349f | 673 | |
fe055896 BP |
674 | ret = save_microcode(&mc_saved_data, mc_saved, count); |
675 | if (ret) | |
676 | pr_err("Cannot save microcode patches from initrd.\n"); | |
fa6788b8 BP |
677 | else |
678 | show_saved_mc(); | |
fe055896 BP |
679 | |
680 | return ret; | |
681 | } | |
682 | ||
6c545647 BP |
683 | static __init enum ucode_state |
684 | __scan_microcode_initrd(struct cpio_data *cd, struct ucode_blobs *blbp) | |
685 | { | |
686 | #ifdef CONFIG_BLK_DEV_INITRD | |
6c545647 BP |
687 | static __initdata char ucode_name[] = "kernel/x86/microcode/GenuineIntel.bin"; |
688 | char *p = IS_ENABLED(CONFIG_X86_32) ? (char *)__pa_nodebug(ucode_name) | |
689 | : ucode_name; | |
690 | # ifdef CONFIG_X86_32 | |
691 | unsigned long start = 0, size; | |
692 | struct boot_params *params; | |
693 | ||
694 | params = (struct boot_params *)__pa_nodebug(&boot_params); | |
695 | size = params->hdr.ramdisk_size; | |
696 | ||
697 | /* | |
698 | * Set start only if we have an initrd image. We cannot use initrd_start | |
699 | * because it is not set that early yet. | |
700 | */ | |
701 | start = (size ? params->hdr.ramdisk_image : 0); | |
702 | ||
703 | # else /* CONFIG_X86_64 */ | |
704 | unsigned long start = 0, size; | |
705 | ||
706 | size = (u64)boot_params.ext_ramdisk_size << 32; | |
707 | size |= boot_params.hdr.ramdisk_size; | |
708 | ||
709 | if (size) { | |
710 | start = (u64)boot_params.ext_ramdisk_image << 32; | |
711 | start |= boot_params.hdr.ramdisk_image; | |
712 | ||
713 | start += PAGE_OFFSET; | |
714 | } | |
715 | # endif | |
716 | ||
852ad5b9 | 717 | *cd = find_cpio_data(p, (void *)start, size, NULL); |
6c545647 BP |
718 | if (cd->data) { |
719 | blbp->start = start; | |
720 | blbp->valid = true; | |
721 | ||
722 | return UCODE_OK; | |
723 | } else | |
724 | #endif /* CONFIG_BLK_DEV_INITRD */ | |
725 | return UCODE_ERROR; | |
726 | } | |
727 | ||
728 | static __init enum ucode_state | |
729 | scan_microcode(struct mc_saved_data *mcs, unsigned long *mc_ptrs, | |
730 | struct ucode_cpu_info *uci, struct ucode_blobs *blbp) | |
731 | { | |
732 | struct cpio_data cd = { NULL, 0, "" }; | |
733 | enum ucode_state ret; | |
734 | ||
735 | /* try built-in microcode first */ | |
736 | if (load_builtin_intel_microcode(&cd)) | |
737 | /* | |
738 | * Invalidate blobs as we might've gotten an initrd too, | |
739 | * supplied by the boot loader, by mistake or simply forgotten | |
740 | * there. That's fine, we ignore it since we've found builtin | |
741 | * microcode already. | |
742 | */ | |
743 | blbp->valid = false; | |
744 | else { | |
745 | ret = __scan_microcode_initrd(&cd, blbp); | |
746 | if (ret != UCODE_OK) | |
747 | return ret; | |
748 | } | |
749 | ||
750 | return get_matching_model_microcode(blbp->start, cd.data, cd.size, | |
751 | mcs, mc_ptrs, uci); | |
752 | } | |
753 | ||
fe055896 | 754 | static void __init |
f8bb45e2 | 755 | _load_ucode_intel_bsp(struct mc_saved_data *mcs, unsigned long *mc_ptrs, |
6c545647 | 756 | struct ucode_blobs *blbp) |
fe055896 BP |
757 | { |
758 | struct ucode_cpu_info uci; | |
759 | enum ucode_state ret; | |
760 | ||
761 | collect_cpu_info_early(&uci); | |
762 | ||
6c545647 | 763 | ret = scan_microcode(mcs, mc_ptrs, &uci, blbp); |
fe055896 BP |
764 | if (ret != UCODE_OK) |
765 | return; | |
766 | ||
6c545647 | 767 | ret = load_microcode(mcs, mc_ptrs, blbp->start, &uci); |
fe055896 BP |
768 | if (ret != UCODE_OK) |
769 | return; | |
770 | ||
771 | apply_microcode_early(&uci, true); | |
772 | } | |
773 | ||
774 | void __init load_ucode_intel_bsp(void) | |
775 | { | |
6c545647 BP |
776 | struct ucode_blobs *blobs_p; |
777 | struct mc_saved_data *mcs; | |
778 | unsigned long *ptrs; | |
264285ac | 779 | |
6c545647 BP |
780 | #ifdef CONFIG_X86_32 |
781 | mcs = (struct mc_saved_data *)__pa_nodebug(&mc_saved_data); | |
782 | ptrs = (unsigned long *)__pa_nodebug(&mc_tmp_ptrs); | |
783 | blobs_p = (struct ucode_blobs *)__pa_nodebug(&blobs); | |
fe055896 | 784 | #else |
6c545647 BP |
785 | mcs = &mc_saved_data; |
786 | ptrs = mc_tmp_ptrs; | |
787 | blobs_p = &blobs; | |
fe055896 | 788 | #endif |
6c545647 BP |
789 | |
790 | _load_ucode_intel_bsp(mcs, ptrs, blobs_p); | |
fe055896 BP |
791 | } |
792 | ||
793 | void load_ucode_intel_ap(void) | |
794 | { | |
6c545647 | 795 | struct ucode_blobs *blobs_p; |
efaad554 | 796 | unsigned long *ptrs, start = 0; |
6c545647 | 797 | struct mc_saved_data *mcs; |
bd6fe58d | 798 | struct ucode_cpu_info uci; |
fe055896 | 799 | enum ucode_state ret; |
fe055896 | 800 | |
6c545647 BP |
801 | #ifdef CONFIG_X86_32 |
802 | mcs = (struct mc_saved_data *)__pa_nodebug(&mc_saved_data); | |
803 | ptrs = (unsigned long *)__pa_nodebug(mc_tmp_ptrs); | |
804 | blobs_p = (struct ucode_blobs *)__pa_nodebug(&blobs); | |
fe055896 | 805 | #else |
6c545647 BP |
806 | mcs = &mc_saved_data; |
807 | ptrs = mc_tmp_ptrs; | |
808 | blobs_p = &blobs; | |
fe055896 BP |
809 | #endif |
810 | ||
811 | /* | |
812 | * If there is no valid ucode previously saved in memory, no need to | |
813 | * update ucode on this AP. | |
814 | */ | |
6c545647 | 815 | if (!mcs->num_saved) |
fe055896 BP |
816 | return; |
817 | ||
efaad554 BP |
818 | if (blobs_p->valid) { |
819 | start = blobs_p->start; | |
820 | ||
821 | #ifdef CONFIG_RANDOMIZE_MEMORY | |
822 | /* | |
823 | * Pay attention to CONFIG_RANDOMIZE_MEMORY=y as it shuffles | |
824 | * physmem mapping too and there we have the initrd. | |
825 | */ | |
826 | start += PAGE_OFFSET - __PAGE_OFFSET_BASE; | |
827 | #endif | |
828 | } | |
829 | ||
fe055896 | 830 | collect_cpu_info_early(&uci); |
efaad554 | 831 | ret = load_microcode(mcs, ptrs, start, &uci); |
fe055896 BP |
832 | if (ret != UCODE_OK) |
833 | return; | |
834 | ||
835 | apply_microcode_early(&uci, true); | |
836 | } | |
837 | ||
838 | void reload_ucode_intel(void) | |
839 | { | |
840 | struct ucode_cpu_info uci; | |
841 | enum ucode_state ret; | |
842 | ||
4fe9349f | 843 | if (!mc_saved_data.num_saved) |
fe055896 BP |
844 | return; |
845 | ||
846 | collect_cpu_info_early(&uci); | |
847 | ||
9198251a | 848 | ret = find_microcode_patch(mc_saved_data.mc_saved, |
4fe9349f | 849 | mc_saved_data.num_saved, &uci); |
fe055896 BP |
850 | if (ret != UCODE_OK) |
851 | return; | |
852 | ||
853 | apply_microcode_early(&uci, false); | |
854 | } | |
855 | ||
d45de409 | 856 | static int collect_cpu_info(int cpu_num, struct cpu_signature *csig) |
1da177e4 | 857 | { |
354542d0 | 858 | static struct cpu_signature prev; |
92cb7612 | 859 | struct cpuinfo_x86 *c = &cpu_data(cpu_num); |
1da177e4 LT |
860 | unsigned int val[2]; |
861 | ||
d45de409 | 862 | memset(csig, 0, sizeof(*csig)); |
1da177e4 | 863 | |
d45de409 | 864 | csig->sig = cpuid_eax(0x00000001); |
9a3110bf SL |
865 | |
866 | if ((c->x86_model >= 5) || (c->x86 > 6)) { | |
867 | /* get processor flags from MSR 0x17 */ | |
868 | rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); | |
d45de409 | 869 | csig->pf = 1 << ((val[1] >> 18) & 7); |
1da177e4 LT |
870 | } |
871 | ||
506ed6b5 | 872 | csig->rev = c->microcode; |
354542d0 AK |
873 | |
874 | /* No extra locking on prev, races are harmless. */ | |
875 | if (csig->sig != prev.sig || csig->pf != prev.pf || csig->rev != prev.rev) { | |
876 | pr_info("sig=0x%x, pf=0x%x, revision=0x%x\n", | |
877 | csig->sig, csig->pf, csig->rev); | |
878 | prev = *csig; | |
879 | } | |
d45de409 DA |
880 | |
881 | return 0; | |
1da177e4 LT |
882 | } |
883 | ||
9a3110bf SL |
884 | /* |
885 | * return 0 - no update found | |
886 | * return 1 - found update | |
9a3110bf | 887 | */ |
de778275 | 888 | static int get_matching_mc(struct microcode_intel *mc, int cpu) |
9a3110bf | 889 | { |
9cd4d78e FY |
890 | struct cpu_signature cpu_sig; |
891 | unsigned int csig, cpf, crev; | |
9a3110bf | 892 | |
9cd4d78e | 893 | collect_cpu_info(cpu, &cpu_sig); |
a0a29b62 | 894 | |
9cd4d78e FY |
895 | csig = cpu_sig.sig; |
896 | cpf = cpu_sig.pf; | |
897 | crev = cpu_sig.rev; | |
9a3110bf | 898 | |
de778275 | 899 | return has_newer_microcode(mc, csig, cpf, crev); |
1da177e4 LT |
900 | } |
901 | ||
532ed374 | 902 | static int apply_microcode_intel(int cpu) |
1da177e4 | 903 | { |
de778275 | 904 | struct microcode_intel *mc; |
4bae1967 | 905 | struct ucode_cpu_info *uci; |
26cbaa4d | 906 | struct cpuinfo_x86 *c; |
1da177e4 | 907 | unsigned int val[2]; |
354542d0 | 908 | static int prev_rev; |
4bae1967 | 909 | |
9a3110bf | 910 | /* We should bind the task to the CPU */ |
26cbaa4d | 911 | if (WARN_ON(raw_smp_processor_id() != cpu)) |
58b5f2cc | 912 | return -1; |
9a3110bf | 913 | |
58b5f2cc BP |
914 | uci = ucode_cpu_info + cpu; |
915 | mc = uci->mc; | |
de778275 | 916 | if (!mc) |
871b72dd | 917 | return 0; |
1da177e4 | 918 | |
9cd4d78e FY |
919 | /* |
920 | * Microcode on this CPU could be updated earlier. Only apply the | |
de778275 | 921 | * microcode patch in mc when it is newer than the one on this |
9cd4d78e FY |
922 | * CPU. |
923 | */ | |
de778275 | 924 | if (!get_matching_mc(mc, cpu)) |
9cd4d78e FY |
925 | return 0; |
926 | ||
1da177e4 | 927 | /* write microcode via MSR 0x79 */ |
c416e611 BP |
928 | wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); |
929 | wrmsrl(MSR_IA32_UCODE_REV, 0); | |
1da177e4 | 930 | |
506ed6b5 | 931 | /* As documented in the SDM: Do a CPUID 1 here */ |
487472bc | 932 | sync_core(); |
245067d1 | 933 | |
1da177e4 LT |
934 | /* get the current revision from MSR 0x8B */ |
935 | rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]); | |
936 | ||
de778275 | 937 | if (val[1] != mc->hdr.rev) { |
f58e1f53 | 938 | pr_err("CPU%d update to revision 0x%x failed\n", |
26cbaa4d | 939 | cpu, mc->hdr.rev); |
871b72dd | 940 | return -1; |
9a3110bf | 941 | } |
26cbaa4d | 942 | |
354542d0 AK |
943 | if (val[1] != prev_rev) { |
944 | pr_info("updated to revision 0x%x, date = %04x-%02x-%02x\n", | |
945 | val[1], | |
946 | mc->hdr.date & 0xffff, | |
947 | mc->hdr.date >> 24, | |
948 | (mc->hdr.date >> 16) & 0xff); | |
949 | prev_rev = val[1]; | |
950 | } | |
4bae1967 | 951 | |
26cbaa4d BP |
952 | c = &cpu_data(cpu); |
953 | ||
d45de409 | 954 | uci->cpu_sig.rev = val[1]; |
506ed6b5 | 955 | c->microcode = val[1]; |
871b72dd DA |
956 | |
957 | return 0; | |
1da177e4 LT |
958 | } |
959 | ||
871b72dd DA |
960 | static enum ucode_state generic_load_microcode(int cpu, void *data, size_t size, |
961 | int (*get_ucode_data)(void *, const void *, size_t)) | |
9a3110bf | 962 | { |
a0a29b62 | 963 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; |
938179b4 | 964 | u8 *ucode_ptr = data, *new_mc = NULL, *mc = NULL; |
a0a29b62 DA |
965 | int new_rev = uci->cpu_sig.rev; |
966 | unsigned int leftover = size; | |
871b72dd | 967 | enum ucode_state state = UCODE_OK; |
938179b4 | 968 | unsigned int curr_mc_size = 0; |
9cd4d78e | 969 | unsigned int csig, cpf; |
9a3110bf | 970 | |
a0a29b62 DA |
971 | while (leftover) { |
972 | struct microcode_header_intel mc_header; | |
973 | unsigned int mc_size; | |
9a3110bf | 974 | |
35a9ff4e QC |
975 | if (leftover < sizeof(mc_header)) { |
976 | pr_err("error! Truncated header in microcode data file\n"); | |
977 | break; | |
978 | } | |
979 | ||
a0a29b62 DA |
980 | if (get_ucode_data(&mc_header, ucode_ptr, sizeof(mc_header))) |
981 | break; | |
a30a6a2c | 982 | |
a0a29b62 DA |
983 | mc_size = get_totalsize(&mc_header); |
984 | if (!mc_size || mc_size > leftover) { | |
f58e1f53 | 985 | pr_err("error! Bad data in microcode data file\n"); |
a0a29b62 DA |
986 | break; |
987 | } | |
a30a6a2c | 988 | |
938179b4 DS |
989 | /* For performance reasons, reuse mc area when possible */ |
990 | if (!mc || mc_size > curr_mc_size) { | |
5cdd2de0 | 991 | vfree(mc); |
938179b4 DS |
992 | mc = vmalloc(mc_size); |
993 | if (!mc) | |
994 | break; | |
995 | curr_mc_size = mc_size; | |
996 | } | |
a0a29b62 DA |
997 | |
998 | if (get_ucode_data(mc, ucode_ptr, mc_size) || | |
9cd4d78e | 999 | microcode_sanity_check(mc, 1) < 0) { |
a0a29b62 DA |
1000 | break; |
1001 | } | |
1002 | ||
9cd4d78e FY |
1003 | csig = uci->cpu_sig.sig; |
1004 | cpf = uci->cpu_sig.pf; | |
8de3eafc | 1005 | if (has_newer_microcode(mc, csig, cpf, new_rev)) { |
5cdd2de0 | 1006 | vfree(new_mc); |
a0a29b62 DA |
1007 | new_rev = mc_header.rev; |
1008 | new_mc = mc; | |
938179b4 DS |
1009 | mc = NULL; /* trigger new vmalloc */ |
1010 | } | |
a0a29b62 DA |
1011 | |
1012 | ucode_ptr += mc_size; | |
1013 | leftover -= mc_size; | |
a30a6a2c SL |
1014 | } |
1015 | ||
5cdd2de0 | 1016 | vfree(mc); |
938179b4 | 1017 | |
871b72dd | 1018 | if (leftover) { |
5cdd2de0 | 1019 | vfree(new_mc); |
871b72dd | 1020 | state = UCODE_ERROR; |
4bae1967 | 1021 | goto out; |
871b72dd | 1022 | } |
4bae1967 | 1023 | |
871b72dd DA |
1024 | if (!new_mc) { |
1025 | state = UCODE_NFOUND; | |
4bae1967 | 1026 | goto out; |
a30a6a2c | 1027 | } |
a0a29b62 | 1028 | |
5cdd2de0 | 1029 | vfree(uci->mc); |
4bae1967 IM |
1030 | uci->mc = (struct microcode_intel *)new_mc; |
1031 | ||
9cd4d78e FY |
1032 | /* |
1033 | * If early loading microcode is supported, save this mc into | |
1034 | * permanent memory. So it will be loaded early when a CPU is hot added | |
1035 | * or resumes. | |
1036 | */ | |
1037 | save_mc_for_early(new_mc); | |
1038 | ||
f58e1f53 JP |
1039 | pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n", |
1040 | cpu, new_rev, uci->cpu_sig.rev); | |
871b72dd DA |
1041 | out: |
1042 | return state; | |
a30a6a2c SL |
1043 | } |
1044 | ||
a0a29b62 DA |
1045 | static int get_ucode_fw(void *to, const void *from, size_t n) |
1046 | { | |
1047 | memcpy(to, from, n); | |
1048 | return 0; | |
1049 | } | |
a30a6a2c | 1050 | |
48e30685 BP |
1051 | static enum ucode_state request_microcode_fw(int cpu, struct device *device, |
1052 | bool refresh_fw) | |
a30a6a2c SL |
1053 | { |
1054 | char name[30]; | |
92cb7612 | 1055 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
a30a6a2c | 1056 | const struct firmware *firmware; |
871b72dd | 1057 | enum ucode_state ret; |
a30a6a2c | 1058 | |
3e135d88 | 1059 | sprintf(name, "intel-ucode/%02x-%02x-%02x", |
a30a6a2c | 1060 | c->x86, c->x86_model, c->x86_mask); |
871b72dd | 1061 | |
75da02b2 | 1062 | if (request_firmware_direct(&firmware, name, device)) { |
f58e1f53 | 1063 | pr_debug("data file %s load failed\n", name); |
871b72dd | 1064 | return UCODE_NFOUND; |
a30a6a2c | 1065 | } |
a0a29b62 | 1066 | |
dd3feda7 JSR |
1067 | ret = generic_load_microcode(cpu, (void *)firmware->data, |
1068 | firmware->size, &get_ucode_fw); | |
a0a29b62 | 1069 | |
a30a6a2c SL |
1070 | release_firmware(firmware); |
1071 | ||
a0a29b62 DA |
1072 | return ret; |
1073 | } | |
1074 | ||
1075 | static int get_ucode_user(void *to, const void *from, size_t n) | |
1076 | { | |
1077 | return copy_from_user(to, from, n); | |
1078 | } | |
1079 | ||
871b72dd DA |
1080 | static enum ucode_state |
1081 | request_microcode_user(int cpu, const void __user *buf, size_t size) | |
a0a29b62 | 1082 | { |
dd3feda7 | 1083 | return generic_load_microcode(cpu, (void *)buf, size, &get_ucode_user); |
a30a6a2c SL |
1084 | } |
1085 | ||
8d86f390 | 1086 | static void microcode_fini_cpu(int cpu) |
a30a6a2c SL |
1087 | { |
1088 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; | |
1089 | ||
18dbc916 DA |
1090 | vfree(uci->mc); |
1091 | uci->mc = NULL; | |
a30a6a2c | 1092 | } |
8d86f390 | 1093 | |
4db646b1 | 1094 | static struct microcode_ops microcode_intel_ops = { |
a0a29b62 DA |
1095 | .request_microcode_user = request_microcode_user, |
1096 | .request_microcode_fw = request_microcode_fw, | |
8d86f390 | 1097 | .collect_cpu_info = collect_cpu_info, |
532ed374 | 1098 | .apply_microcode = apply_microcode_intel, |
8d86f390 PO |
1099 | .microcode_fini_cpu = microcode_fini_cpu, |
1100 | }; | |
1101 | ||
18dbc916 | 1102 | struct microcode_ops * __init init_intel_microcode(void) |
8d86f390 | 1103 | { |
9a2bc335 | 1104 | struct cpuinfo_x86 *c = &boot_cpu_data; |
7164b3f5 SB |
1105 | |
1106 | if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 || | |
1107 | cpu_has(c, X86_FEATURE_IA64)) { | |
1108 | pr_err("Intel CPU family 0x%x not supported\n", c->x86); | |
1109 | return NULL; | |
1110 | } | |
1111 | ||
18dbc916 | 1112 | return µcode_intel_ops; |
8d86f390 PO |
1113 | } |
1114 |