x86/microcode/intel: Unexport save_mc_for_early()
[linux-2.6-block.git] / arch / x86 / kernel / cpu / microcode / intel.c
CommitLineData
1da177e4 1/*
6b44e72a 2 * Intel CPU Microcode Update Driver for Linux
1da177e4 3 *
6b44e72a
BP
4 * Copyright (C) 2000-2006 Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
5 * 2006 Shaohua Li <shaohua.li@intel.com>
1da177e4 6 *
fe055896
BP
7 * Intel CPU microcode early update for Linux
8 *
9 * Copyright (C) 2012 Fenghua Yu <fenghua.yu@intel.com>
10 * H Peter Anvin" <hpa@zytor.com>
11 *
6b44e72a
BP
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version
15 * 2 of the License, or (at your option) any later version.
1da177e4 16 */
f58e1f53 17
fe055896
BP
18/*
19 * This needs to be before all headers so that pr_debug in printk.h doesn't turn
20 * printk calls into no_printk().
21 *
22 *#define DEBUG
23 */
6b26e1bf 24#define pr_fmt(fmt) "microcode: " fmt
f58e1f53 25
fe055896 26#include <linux/earlycpio.h>
4bae1967 27#include <linux/firmware.h>
4bae1967 28#include <linux/uaccess.h>
fe055896
BP
29#include <linux/vmalloc.h>
30#include <linux/initrd.h>
4bae1967 31#include <linux/kernel.h>
fe055896
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32#include <linux/slab.h>
33#include <linux/cpu.h>
34#include <linux/mm.h>
1da177e4 35
9cd4d78e 36#include <asm/microcode_intel.h>
4bae1967 37#include <asm/processor.h>
fe055896
BP
38#include <asm/tlbflush.h>
39#include <asm/setup.h>
4bae1967 40#include <asm/msr.h>
1da177e4 41
f8bb45e2
BP
42/*
43 * Temporary microcode blobs pointers storage. We note here the pointers to
44 * microcode blobs we've got from whatever storage (detached initrd, builtin).
45 * Later on, we put those into final storage mc_saved_data.mc_saved.
46 */
47static unsigned long mc_tmp_ptrs[MAX_UCODE_COUNT];
48
fe055896 49static struct mc_saved_data {
4fe9349f 50 unsigned int num_saved;
fe055896
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51 struct microcode_intel **mc_saved;
52} mc_saved_data;
53
6c545647
BP
54/* Microcode blobs within the initrd. 0 if builtin. */
55static struct ucode_blobs {
56 unsigned long start;
57 bool valid;
58} blobs;
59
fe055896 60static enum ucode_state
9198251a 61find_microcode_patch(struct microcode_intel **saved,
fe055896
BP
62 unsigned int num_saved, struct ucode_cpu_info *uci)
63{
64 struct microcode_intel *ucode_ptr, *new_mc = NULL;
65 struct microcode_header_intel *mc_hdr;
66 int new_rev, ret, i;
67
68 new_rev = uci->cpu_sig.rev;
69
70 for (i = 0; i < num_saved; i++) {
71 ucode_ptr = saved[i];
72 mc_hdr = (struct microcode_header_intel *)ucode_ptr;
73
74 ret = has_newer_microcode(ucode_ptr,
75 uci->cpu_sig.sig,
76 uci->cpu_sig.pf,
77 new_rev);
78 if (!ret)
79 continue;
80
81 new_rev = mc_hdr->rev;
82 new_mc = ucode_ptr;
83 }
84
85 if (!new_mc)
86 return UCODE_NFOUND;
87
88 uci->mc = (struct microcode_intel *)new_mc;
89 return UCODE_OK;
90}
91
92static inline void
f8bb45e2
BP
93copy_ptrs(struct microcode_intel **mc_saved, unsigned long *mc_ptrs,
94 unsigned long off, int num_saved)
fe055896
BP
95{
96 int i;
97
98 for (i = 0; i < num_saved; i++)
f8bb45e2 99 mc_saved[i] = (struct microcode_intel *)(mc_ptrs[i] + off);
fe055896
BP
100}
101
102#ifdef CONFIG_X86_32
103static void
bd6fe58d 104microcode_phys(struct microcode_intel **mc_saved_tmp, struct mc_saved_data *mcs)
fe055896
BP
105{
106 int i;
107 struct microcode_intel ***mc_saved;
108
bd6fe58d
BP
109 mc_saved = (struct microcode_intel ***)__pa_nodebug(&mcs->mc_saved);
110
4fe9349f 111 for (i = 0; i < mcs->num_saved; i++) {
fe055896
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112 struct microcode_intel *p;
113
bd6fe58d 114 p = *(struct microcode_intel **)__pa_nodebug(mcs->mc_saved + i);
fe055896
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115 mc_saved_tmp[i] = (struct microcode_intel *)__pa_nodebug(p);
116 }
117}
118#endif
119
120static enum ucode_state
f8bb45e2
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121load_microcode(struct mc_saved_data *mcs, unsigned long *mc_ptrs,
122 unsigned long offset, struct ucode_cpu_info *uci)
fe055896
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123{
124 struct microcode_intel *mc_saved_tmp[MAX_UCODE_COUNT];
4fe9349f 125 unsigned int count = mcs->num_saved;
fe055896 126
bd6fe58d 127 if (!mcs->mc_saved) {
f8bb45e2 128 copy_ptrs(mc_saved_tmp, mc_ptrs, offset, count);
fe055896 129
9198251a 130 return find_microcode_patch(mc_saved_tmp, count, uci);
fe055896
BP
131 } else {
132#ifdef CONFIG_X86_32
bd6fe58d 133 microcode_phys(mc_saved_tmp, mcs);
9198251a 134 return find_microcode_patch(mc_saved_tmp, count, uci);
fe055896 135#else
9198251a 136 return find_microcode_patch(mcs->mc_saved, count, uci);
fe055896
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137#endif
138 }
139}
140
141/*
142 * Given CPU signature and a microcode patch, this function finds if the
143 * microcode patch has matching family and model with the CPU.
144 */
145static enum ucode_state
146matching_model_microcode(struct microcode_header_intel *mc_header,
147 unsigned long sig)
148{
149 unsigned int fam, model;
150 unsigned int fam_ucode, model_ucode;
151 struct extended_sigtable *ext_header;
152 unsigned long total_size = get_totalsize(mc_header);
153 unsigned long data_size = get_datasize(mc_header);
154 int ext_sigcount, i;
155 struct extended_signature *ext_sig;
156
99f925ce 157 fam = x86_family(sig);
fe055896
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158 model = x86_model(sig);
159
99f925ce 160 fam_ucode = x86_family(mc_header->sig);
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161 model_ucode = x86_model(mc_header->sig);
162
163 if (fam == fam_ucode && model == model_ucode)
164 return UCODE_OK;
165
166 /* Look for ext. headers: */
167 if (total_size <= data_size + MC_HEADER_SIZE)
168 return UCODE_NFOUND;
169
170 ext_header = (void *) mc_header + data_size + MC_HEADER_SIZE;
171 ext_sig = (void *)ext_header + EXT_HEADER_SIZE;
172 ext_sigcount = ext_header->count;
173
174 for (i = 0; i < ext_sigcount; i++) {
99f925ce 175 fam_ucode = x86_family(ext_sig->sig);
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176 model_ucode = x86_model(ext_sig->sig);
177
178 if (fam == fam_ucode && model == model_ucode)
179 return UCODE_OK;
180
181 ext_sig++;
182 }
183 return UCODE_NFOUND;
184}
185
186static int
bd6fe58d 187save_microcode(struct mc_saved_data *mcs,
fe055896 188 struct microcode_intel **mc_saved_src,
4fe9349f 189 unsigned int num_saved)
fe055896
BP
190{
191 int i, j;
192 struct microcode_intel **saved_ptr;
193 int ret;
194
4fe9349f 195 if (!num_saved)
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196 return -EINVAL;
197
198 /*
199 * Copy new microcode data.
200 */
4fe9349f 201 saved_ptr = kcalloc(num_saved, sizeof(struct microcode_intel *), GFP_KERNEL);
fe055896
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202 if (!saved_ptr)
203 return -ENOMEM;
204
4fe9349f 205 for (i = 0; i < num_saved; i++) {
fe055896
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206 struct microcode_header_intel *mc_hdr;
207 struct microcode_intel *mc;
208 unsigned long size;
209
210 if (!mc_saved_src[i]) {
211 ret = -EINVAL;
212 goto err;
213 }
214
215 mc = mc_saved_src[i];
216 mc_hdr = &mc->hdr;
217 size = get_totalsize(mc_hdr);
218
9cc6f743 219 saved_ptr[i] = kmemdup(mc, size, GFP_KERNEL);
fe055896
BP
220 if (!saved_ptr[i]) {
221 ret = -ENOMEM;
222 goto err;
223 }
fe055896
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224 }
225
226 /*
227 * Point to newly saved microcode.
228 */
4fe9349f
BP
229 mcs->mc_saved = saved_ptr;
230 mcs->num_saved = num_saved;
fe055896
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231
232 return 0;
233
234err:
235 for (j = 0; j <= i; j++)
236 kfree(saved_ptr[j]);
237 kfree(saved_ptr);
238
239 return ret;
240}
241
242/*
243 * A microcode patch in ucode_ptr is saved into mc_saved
244 * - if it has matching signature and newer revision compared to an existing
245 * patch mc_saved.
246 * - or if it is a newly discovered microcode patch.
247 *
248 * The microcode patch should have matching model with CPU.
249 *
250 * Returns: The updated number @num_saved of saved microcode patches.
251 */
252static unsigned int _save_mc(struct microcode_intel **mc_saved,
253 u8 *ucode_ptr, unsigned int num_saved)
254{
255 struct microcode_header_intel *mc_hdr, *mc_saved_hdr;
256 unsigned int sig, pf;
257 int found = 0, i;
258
259 mc_hdr = (struct microcode_header_intel *)ucode_ptr;
260
261 for (i = 0; i < num_saved; i++) {
262 mc_saved_hdr = (struct microcode_header_intel *)mc_saved[i];
263 sig = mc_saved_hdr->sig;
264 pf = mc_saved_hdr->pf;
265
266 if (!find_matching_signature(ucode_ptr, sig, pf))
267 continue;
268
269 found = 1;
270
271 if (mc_hdr->rev <= mc_saved_hdr->rev)
272 continue;
273
274 /*
275 * Found an older ucode saved earlier. Replace it with
276 * this newer one.
277 */
278 mc_saved[i] = (struct microcode_intel *)ucode_ptr;
279 break;
280 }
281
282 /* Newly detected microcode, save it to memory. */
283 if (i >= num_saved && !found)
284 mc_saved[num_saved++] = (struct microcode_intel *)ucode_ptr;
285
286 return num_saved;
287}
288
289/*
290 * Get microcode matching with BSP's model. Only CPUs with the same model as
291 * BSP can stay in the platform.
292 */
293static enum ucode_state __init
f96fde53
BP
294get_matching_model_microcode(unsigned long start, void *data, size_t size,
295 struct mc_saved_data *mcs, unsigned long *mc_ptrs,
fe055896
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296 struct ucode_cpu_info *uci)
297{
fe055896 298 struct microcode_intel *mc_saved_tmp[MAX_UCODE_COUNT];
f96fde53 299 struct microcode_header_intel *mc_header;
4fe9349f 300 unsigned int num_saved = mcs->num_saved;
f96fde53
BP
301 enum ucode_state state = UCODE_OK;
302 unsigned int leftover = size;
303 u8 *ucode_ptr = data;
304 unsigned int mc_size;
fe055896
BP
305 int i;
306
4fe9349f 307 while (leftover && num_saved < ARRAY_SIZE(mc_saved_tmp)) {
fe055896
BP
308
309 if (leftover < sizeof(mc_header))
310 break;
311
312 mc_header = (struct microcode_header_intel *)ucode_ptr;
313
314 mc_size = get_totalsize(mc_header);
315 if (!mc_size || mc_size > leftover ||
316 microcode_sanity_check(ucode_ptr, 0) < 0)
317 break;
318
319 leftover -= mc_size;
320
321 /*
322 * Since APs with same family and model as the BSP may boot in
323 * the platform, we need to find and save microcode patches
324 * with the same family and model as the BSP.
325 */
f96fde53 326 if (matching_model_microcode(mc_header, uci->cpu_sig.sig) != UCODE_OK) {
fe055896
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327 ucode_ptr += mc_size;
328 continue;
329 }
330
4fe9349f 331 num_saved = _save_mc(mc_saved_tmp, ucode_ptr, num_saved);
fe055896
BP
332
333 ucode_ptr += mc_size;
334 }
335
336 if (leftover) {
337 state = UCODE_ERROR;
f96fde53 338 return state;
fe055896
BP
339 }
340
4fe9349f 341 if (!num_saved) {
fe055896 342 state = UCODE_NFOUND;
f96fde53 343 return state;
fe055896
BP
344 }
345
4fe9349f 346 for (i = 0; i < num_saved; i++)
f8bb45e2 347 mc_ptrs[i] = (unsigned long)mc_saved_tmp[i] - start;
fe055896 348
4fe9349f 349 mcs->num_saved = num_saved;
f96fde53 350
fe055896
BP
351 return state;
352}
353
354static int collect_cpu_info_early(struct ucode_cpu_info *uci)
355{
356 unsigned int val[2];
357 unsigned int family, model;
358 struct cpu_signature csig;
359 unsigned int eax, ebx, ecx, edx;
360
361 csig.sig = 0;
362 csig.pf = 0;
363 csig.rev = 0;
364
365 memset(uci, 0, sizeof(*uci));
366
367 eax = 0x00000001;
368 ecx = 0;
369 native_cpuid(&eax, &ebx, &ecx, &edx);
370 csig.sig = eax;
371
99f925ce 372 family = x86_family(csig.sig);
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373 model = x86_model(csig.sig);
374
375 if ((model >= 5) || (family > 6)) {
376 /* get processor flags from MSR 0x17 */
377 native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
378 csig.pf = 1 << ((val[1] >> 18) & 7);
379 }
c416e611 380 native_wrmsrl(MSR_IA32_UCODE_REV, 0);
fe055896
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381
382 /* As documented in the SDM: Do a CPUID 1 here */
383 sync_core();
384
385 /* get the current revision from MSR 0x8B */
386 native_rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
387
388 csig.rev = val[1];
389
390 uci->cpu_sig = csig;
391 uci->valid = 1;
392
393 return 0;
394}
395
fe055896
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396static void show_saved_mc(void)
397{
c595ac2b 398#ifdef DEBUG
fe055896
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399 int i, j;
400 unsigned int sig, pf, rev, total_size, data_size, date;
401 struct ucode_cpu_info uci;
402
4fe9349f 403 if (!mc_saved_data.num_saved) {
fe055896
BP
404 pr_debug("no microcode data saved.\n");
405 return;
406 }
4fe9349f 407 pr_debug("Total microcode saved: %d\n", mc_saved_data.num_saved);
fe055896
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408
409 collect_cpu_info_early(&uci);
410
411 sig = uci.cpu_sig.sig;
412 pf = uci.cpu_sig.pf;
413 rev = uci.cpu_sig.rev;
414 pr_debug("CPU: sig=0x%x, pf=0x%x, rev=0x%x\n", sig, pf, rev);
415
4fe9349f 416 for (i = 0; i < mc_saved_data.num_saved; i++) {
fe055896
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417 struct microcode_header_intel *mc_saved_header;
418 struct extended_sigtable *ext_header;
419 int ext_sigcount;
420 struct extended_signature *ext_sig;
421
422 mc_saved_header = (struct microcode_header_intel *)
423 mc_saved_data.mc_saved[i];
424 sig = mc_saved_header->sig;
425 pf = mc_saved_header->pf;
426 rev = mc_saved_header->rev;
427 total_size = get_totalsize(mc_saved_header);
428 data_size = get_datasize(mc_saved_header);
429 date = mc_saved_header->date;
430
c19ca6cb 431 pr_debug("mc_saved[%d]: sig=0x%x, pf=0x%x, rev=0x%x, total size=0x%x, date = %04x-%02x-%02x\n",
fe055896
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432 i, sig, pf, rev, total_size,
433 date & 0xffff,
434 date >> 24,
435 (date >> 16) & 0xff);
436
437 /* Look for ext. headers: */
438 if (total_size <= data_size + MC_HEADER_SIZE)
439 continue;
440
441 ext_header = (void *) mc_saved_header + data_size + MC_HEADER_SIZE;
442 ext_sigcount = ext_header->count;
443 ext_sig = (void *)ext_header + EXT_HEADER_SIZE;
444
445 for (j = 0; j < ext_sigcount; j++) {
446 sig = ext_sig->sig;
447 pf = ext_sig->pf;
448
449 pr_debug("\tExtended[%d]: sig=0x%x, pf=0x%x\n",
450 j, sig, pf);
451
452 ext_sig++;
453 }
454
455 }
fe055896 456#endif
c595ac2b 457}
fe055896 458
fe055896
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459/*
460 * Save this mc into mc_saved_data. So it will be loaded early when a CPU is
461 * hot added or resumes.
462 *
463 * Please make sure this mc should be a valid microcode patch before calling
464 * this function.
465 */
0c5fa827 466static void save_mc_for_early(u8 *mc)
fe055896 467{
0c5fa827
BP
468#ifdef CONFIG_HOTPLUG_CPU
469 static DEFINE_MUTEX(x86_cpu_microcode_mutex);
470
fe055896
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471 struct microcode_intel *mc_saved_tmp[MAX_UCODE_COUNT];
472 unsigned int mc_saved_count_init;
4fe9349f 473 unsigned int num_saved;
fe055896 474 struct microcode_intel **mc_saved;
0c5fa827 475 int ret, i;
fe055896
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476
477 /*
478 * Hold hotplug lock so mc_saved_data is not accessed by a CPU in
479 * hotplug.
480 */
481 mutex_lock(&x86_cpu_microcode_mutex);
482
4fe9349f
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483 mc_saved_count_init = mc_saved_data.num_saved;
484 num_saved = mc_saved_data.num_saved;
fe055896
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485 mc_saved = mc_saved_data.mc_saved;
486
4fe9349f 487 if (mc_saved && num_saved)
fe055896 488 memcpy(mc_saved_tmp, mc_saved,
4fe9349f 489 num_saved * sizeof(struct microcode_intel *));
fe055896
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490 /*
491 * Save the microcode patch mc in mc_save_tmp structure if it's a newer
492 * version.
493 */
4fe9349f 494 num_saved = _save_mc(mc_saved_tmp, mc, num_saved);
fe055896
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495
496 /*
497 * Save the mc_save_tmp in global mc_saved_data.
498 */
4fe9349f 499 ret = save_microcode(&mc_saved_data, mc_saved_tmp, num_saved);
fe055896
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500 if (ret) {
501 pr_err("Cannot save microcode patch.\n");
502 goto out;
503 }
504
505 show_saved_mc();
506
507 /*
508 * Free old saved microcode data.
509 */
510 if (mc_saved) {
511 for (i = 0; i < mc_saved_count_init; i++)
512 kfree(mc_saved[i]);
513 kfree(mc_saved);
514 }
515
516out:
517 mutex_unlock(&x86_cpu_microcode_mutex);
fe055896 518#endif
0c5fa827 519}
fe055896
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520
521static bool __init load_builtin_intel_microcode(struct cpio_data *cp)
522{
523#ifdef CONFIG_X86_64
524 unsigned int eax = 0x00000001, ebx, ecx = 0, edx;
fe055896
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525 char name[30];
526
527 native_cpuid(&eax, &ebx, &ecx, &edx);
528
99f925ce
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529 sprintf(name, "intel-ucode/%02x-%02x-%02x",
530 x86_family(eax), x86_model(eax), x86_stepping(eax));
fe055896
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531
532 return get_builtin_firmware(cp, name);
533#else
534 return false;
535#endif
536}
537
fe055896
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538/*
539 * Print ucode update info.
540 */
541static void
542print_ucode_info(struct ucode_cpu_info *uci, unsigned int date)
543{
b7f500ae
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544 pr_info_once("microcode updated early to revision 0x%x, date = %04x-%02x-%02x\n",
545 uci->cpu_sig.rev,
546 date & 0xffff,
547 date >> 24,
548 (date >> 16) & 0xff);
fe055896
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549}
550
551#ifdef CONFIG_X86_32
552
553static int delay_ucode_info;
554static int current_mc_date;
555
556/*
557 * Print early updated ucode info after printk works. This is delayed info dump.
558 */
559void show_ucode_info_early(void)
560{
561 struct ucode_cpu_info uci;
562
563 if (delay_ucode_info) {
564 collect_cpu_info_early(&uci);
565 print_ucode_info(&uci, current_mc_date);
566 delay_ucode_info = 0;
567 }
568}
569
570/*
571 * At this point, we can not call printk() yet. Keep microcode patch number in
572 * mc_saved_data.mc_saved and delay printing microcode info in
573 * show_ucode_info_early() until printk() works.
574 */
575static void print_ucode(struct ucode_cpu_info *uci)
576{
de778275 577 struct microcode_intel *mc;
fe055896
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578 int *delay_ucode_info_p;
579 int *current_mc_date_p;
580
de778275
BP
581 mc = uci->mc;
582 if (!mc)
fe055896
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583 return;
584
585 delay_ucode_info_p = (int *)__pa_nodebug(&delay_ucode_info);
586 current_mc_date_p = (int *)__pa_nodebug(&current_mc_date);
587
588 *delay_ucode_info_p = 1;
de778275 589 *current_mc_date_p = mc->hdr.date;
fe055896
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590}
591#else
592
593/*
594 * Flush global tlb. We only do this in x86_64 where paging has been enabled
595 * already and PGE should be enabled as well.
596 */
597static inline void flush_tlb_early(void)
598{
599 __native_flush_tlb_global_irq_disabled();
600}
601
602static inline void print_ucode(struct ucode_cpu_info *uci)
603{
de778275 604 struct microcode_intel *mc;
fe055896 605
de778275
BP
606 mc = uci->mc;
607 if (!mc)
fe055896
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608 return;
609
de778275 610 print_ucode_info(uci, mc->hdr.date);
fe055896
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611}
612#endif
613
614static int apply_microcode_early(struct ucode_cpu_info *uci, bool early)
615{
de778275 616 struct microcode_intel *mc;
fe055896
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617 unsigned int val[2];
618
de778275
BP
619 mc = uci->mc;
620 if (!mc)
fe055896
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621 return 0;
622
623 /* write microcode via MSR 0x79 */
c416e611
BP
624 native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
625 native_wrmsrl(MSR_IA32_UCODE_REV, 0);
fe055896
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626
627 /* As documented in the SDM: Do a CPUID 1 here */
628 sync_core();
629
630 /* get the current revision from MSR 0x8B */
631 native_rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
de778275 632 if (val[1] != mc->hdr.rev)
fe055896
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633 return -1;
634
635#ifdef CONFIG_X86_64
636 /* Flush global tlb. This is precaution. */
637 flush_tlb_early();
638#endif
639 uci->cpu_sig.rev = val[1];
640
641 if (early)
642 print_ucode(uci);
643 else
de778275 644 print_ucode_info(uci, mc->hdr.date);
fe055896
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645
646 return 0;
647}
648
649/*
650 * This function converts microcode patch offsets previously stored in
f8bb45e2 651 * mc_tmp_ptrs to pointers and stores the pointers in mc_saved_data.
fe055896
BP
652 */
653int __init save_microcode_in_initrd_intel(void)
654{
fe055896 655 struct microcode_intel *mc_saved[MAX_UCODE_COUNT];
6c545647
BP
656 unsigned int count = mc_saved_data.num_saved;
657 unsigned long offset = 0;
658 int ret;
fe055896 659
4fe9349f 660 if (!count)
6c545647 661 return 0;
fe055896 662
6c545647
BP
663 /*
664 * We have found a valid initrd but it might've been relocated in the
665 * meantime so get its updated address.
666 */
667 if (IS_ENABLED(CONFIG_BLK_DEV_INITRD) && blobs.valid)
668 offset = initrd_start;
669
670 copy_ptrs(mc_saved, mc_tmp_ptrs, offset, count);
4fe9349f 671
fe055896
BP
672 ret = save_microcode(&mc_saved_data, mc_saved, count);
673 if (ret)
674 pr_err("Cannot save microcode patches from initrd.\n");
fa6788b8
BP
675 else
676 show_saved_mc();
fe055896
BP
677
678 return ret;
679}
680
6c545647
BP
681static __init enum ucode_state
682__scan_microcode_initrd(struct cpio_data *cd, struct ucode_blobs *blbp)
683{
684#ifdef CONFIG_BLK_DEV_INITRD
6c545647
BP
685 static __initdata char ucode_name[] = "kernel/x86/microcode/GenuineIntel.bin";
686 char *p = IS_ENABLED(CONFIG_X86_32) ? (char *)__pa_nodebug(ucode_name)
687 : ucode_name;
688# ifdef CONFIG_X86_32
689 unsigned long start = 0, size;
690 struct boot_params *params;
691
692 params = (struct boot_params *)__pa_nodebug(&boot_params);
693 size = params->hdr.ramdisk_size;
694
695 /*
696 * Set start only if we have an initrd image. We cannot use initrd_start
697 * because it is not set that early yet.
698 */
699 start = (size ? params->hdr.ramdisk_image : 0);
700
701# else /* CONFIG_X86_64 */
702 unsigned long start = 0, size;
703
704 size = (u64)boot_params.ext_ramdisk_size << 32;
705 size |= boot_params.hdr.ramdisk_size;
706
707 if (size) {
708 start = (u64)boot_params.ext_ramdisk_image << 32;
709 start |= boot_params.hdr.ramdisk_image;
710
711 start += PAGE_OFFSET;
712 }
713# endif
714
852ad5b9 715 *cd = find_cpio_data(p, (void *)start, size, NULL);
6c545647
BP
716 if (cd->data) {
717 blbp->start = start;
718 blbp->valid = true;
719
720 return UCODE_OK;
721 } else
722#endif /* CONFIG_BLK_DEV_INITRD */
723 return UCODE_ERROR;
724}
725
726static __init enum ucode_state
727scan_microcode(struct mc_saved_data *mcs, unsigned long *mc_ptrs,
728 struct ucode_cpu_info *uci, struct ucode_blobs *blbp)
729{
730 struct cpio_data cd = { NULL, 0, "" };
731 enum ucode_state ret;
732
733 /* try built-in microcode first */
734 if (load_builtin_intel_microcode(&cd))
735 /*
736 * Invalidate blobs as we might've gotten an initrd too,
737 * supplied by the boot loader, by mistake or simply forgotten
738 * there. That's fine, we ignore it since we've found builtin
739 * microcode already.
740 */
741 blbp->valid = false;
742 else {
743 ret = __scan_microcode_initrd(&cd, blbp);
744 if (ret != UCODE_OK)
745 return ret;
746 }
747
748 return get_matching_model_microcode(blbp->start, cd.data, cd.size,
749 mcs, mc_ptrs, uci);
750}
751
fe055896 752static void __init
f8bb45e2 753_load_ucode_intel_bsp(struct mc_saved_data *mcs, unsigned long *mc_ptrs,
6c545647 754 struct ucode_blobs *blbp)
fe055896
BP
755{
756 struct ucode_cpu_info uci;
757 enum ucode_state ret;
758
759 collect_cpu_info_early(&uci);
760
6c545647 761 ret = scan_microcode(mcs, mc_ptrs, &uci, blbp);
fe055896
BP
762 if (ret != UCODE_OK)
763 return;
764
6c545647 765 ret = load_microcode(mcs, mc_ptrs, blbp->start, &uci);
fe055896
BP
766 if (ret != UCODE_OK)
767 return;
768
769 apply_microcode_early(&uci, true);
770}
771
772void __init load_ucode_intel_bsp(void)
773{
6c545647
BP
774 struct ucode_blobs *blobs_p;
775 struct mc_saved_data *mcs;
776 unsigned long *ptrs;
264285ac 777
6c545647
BP
778#ifdef CONFIG_X86_32
779 mcs = (struct mc_saved_data *)__pa_nodebug(&mc_saved_data);
780 ptrs = (unsigned long *)__pa_nodebug(&mc_tmp_ptrs);
781 blobs_p = (struct ucode_blobs *)__pa_nodebug(&blobs);
fe055896 782#else
6c545647
BP
783 mcs = &mc_saved_data;
784 ptrs = mc_tmp_ptrs;
785 blobs_p = &blobs;
fe055896 786#endif
6c545647
BP
787
788 _load_ucode_intel_bsp(mcs, ptrs, blobs_p);
fe055896
BP
789}
790
791void load_ucode_intel_ap(void)
792{
6c545647
BP
793 struct ucode_blobs *blobs_p;
794 struct mc_saved_data *mcs;
bd6fe58d 795 struct ucode_cpu_info uci;
fe055896 796 enum ucode_state ret;
6c545647 797 unsigned long *ptrs;
fe055896 798
6c545647
BP
799#ifdef CONFIG_X86_32
800 mcs = (struct mc_saved_data *)__pa_nodebug(&mc_saved_data);
801 ptrs = (unsigned long *)__pa_nodebug(mc_tmp_ptrs);
802 blobs_p = (struct ucode_blobs *)__pa_nodebug(&blobs);
fe055896 803#else
6c545647
BP
804 mcs = &mc_saved_data;
805 ptrs = mc_tmp_ptrs;
806 blobs_p = &blobs;
fe055896
BP
807#endif
808
809 /*
810 * If there is no valid ucode previously saved in memory, no need to
811 * update ucode on this AP.
812 */
6c545647 813 if (!mcs->num_saved)
fe055896
BP
814 return;
815
816 collect_cpu_info_early(&uci);
6c545647 817 ret = load_microcode(mcs, ptrs, blobs_p->start, &uci);
fe055896
BP
818 if (ret != UCODE_OK)
819 return;
820
821 apply_microcode_early(&uci, true);
822}
823
824void reload_ucode_intel(void)
825{
826 struct ucode_cpu_info uci;
827 enum ucode_state ret;
828
4fe9349f 829 if (!mc_saved_data.num_saved)
fe055896
BP
830 return;
831
832 collect_cpu_info_early(&uci);
833
9198251a 834 ret = find_microcode_patch(mc_saved_data.mc_saved,
4fe9349f 835 mc_saved_data.num_saved, &uci);
fe055896
BP
836 if (ret != UCODE_OK)
837 return;
838
839 apply_microcode_early(&uci, false);
840}
841
d45de409 842static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
1da177e4 843{
92cb7612 844 struct cpuinfo_x86 *c = &cpu_data(cpu_num);
1da177e4
LT
845 unsigned int val[2];
846
d45de409 847 memset(csig, 0, sizeof(*csig));
1da177e4 848
d45de409 849 csig->sig = cpuid_eax(0x00000001);
9a3110bf
SL
850
851 if ((c->x86_model >= 5) || (c->x86 > 6)) {
852 /* get processor flags from MSR 0x17 */
853 rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
d45de409 854 csig->pf = 1 << ((val[1] >> 18) & 7);
1da177e4
LT
855 }
856
506ed6b5 857 csig->rev = c->microcode;
f58e1f53
JP
858 pr_info("CPU%d sig=0x%x, pf=0x%x, revision=0x%x\n",
859 cpu_num, csig->sig, csig->pf, csig->rev);
d45de409
DA
860
861 return 0;
1da177e4
LT
862}
863
9a3110bf
SL
864/*
865 * return 0 - no update found
866 * return 1 - found update
9a3110bf 867 */
de778275 868static int get_matching_mc(struct microcode_intel *mc, int cpu)
9a3110bf 869{
9cd4d78e
FY
870 struct cpu_signature cpu_sig;
871 unsigned int csig, cpf, crev;
9a3110bf 872
9cd4d78e 873 collect_cpu_info(cpu, &cpu_sig);
a0a29b62 874
9cd4d78e
FY
875 csig = cpu_sig.sig;
876 cpf = cpu_sig.pf;
877 crev = cpu_sig.rev;
9a3110bf 878
de778275 879 return has_newer_microcode(mc, csig, cpf, crev);
1da177e4
LT
880}
881
532ed374 882static int apply_microcode_intel(int cpu)
1da177e4 883{
de778275 884 struct microcode_intel *mc;
4bae1967 885 struct ucode_cpu_info *uci;
26cbaa4d 886 struct cpuinfo_x86 *c;
1da177e4 887 unsigned int val[2];
4bae1967 888
9a3110bf 889 /* We should bind the task to the CPU */
26cbaa4d 890 if (WARN_ON(raw_smp_processor_id() != cpu))
58b5f2cc 891 return -1;
9a3110bf 892
58b5f2cc
BP
893 uci = ucode_cpu_info + cpu;
894 mc = uci->mc;
de778275 895 if (!mc)
871b72dd 896 return 0;
1da177e4 897
9cd4d78e
FY
898 /*
899 * Microcode on this CPU could be updated earlier. Only apply the
de778275 900 * microcode patch in mc when it is newer than the one on this
9cd4d78e
FY
901 * CPU.
902 */
de778275 903 if (!get_matching_mc(mc, cpu))
9cd4d78e
FY
904 return 0;
905
1da177e4 906 /* write microcode via MSR 0x79 */
c416e611
BP
907 wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
908 wrmsrl(MSR_IA32_UCODE_REV, 0);
1da177e4 909
506ed6b5 910 /* As documented in the SDM: Do a CPUID 1 here */
487472bc 911 sync_core();
245067d1 912
1da177e4
LT
913 /* get the current revision from MSR 0x8B */
914 rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
915
de778275 916 if (val[1] != mc->hdr.rev) {
f58e1f53 917 pr_err("CPU%d update to revision 0x%x failed\n",
26cbaa4d 918 cpu, mc->hdr.rev);
871b72dd 919 return -1;
9a3110bf 920 }
26cbaa4d 921
3235dc3f 922 pr_info("CPU%d updated to revision 0x%x, date = %04x-%02x-%02x\n",
26cbaa4d 923 cpu, val[1],
de778275
BP
924 mc->hdr.date & 0xffff,
925 mc->hdr.date >> 24,
926 (mc->hdr.date >> 16) & 0xff);
4bae1967 927
26cbaa4d
BP
928 c = &cpu_data(cpu);
929
d45de409 930 uci->cpu_sig.rev = val[1];
506ed6b5 931 c->microcode = val[1];
871b72dd
DA
932
933 return 0;
1da177e4
LT
934}
935
871b72dd
DA
936static enum ucode_state generic_load_microcode(int cpu, void *data, size_t size,
937 int (*get_ucode_data)(void *, const void *, size_t))
9a3110bf 938{
a0a29b62 939 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
938179b4 940 u8 *ucode_ptr = data, *new_mc = NULL, *mc = NULL;
a0a29b62
DA
941 int new_rev = uci->cpu_sig.rev;
942 unsigned int leftover = size;
871b72dd 943 enum ucode_state state = UCODE_OK;
938179b4 944 unsigned int curr_mc_size = 0;
9cd4d78e 945 unsigned int csig, cpf;
9a3110bf 946
a0a29b62
DA
947 while (leftover) {
948 struct microcode_header_intel mc_header;
949 unsigned int mc_size;
9a3110bf 950
35a9ff4e
QC
951 if (leftover < sizeof(mc_header)) {
952 pr_err("error! Truncated header in microcode data file\n");
953 break;
954 }
955
a0a29b62
DA
956 if (get_ucode_data(&mc_header, ucode_ptr, sizeof(mc_header)))
957 break;
a30a6a2c 958
a0a29b62
DA
959 mc_size = get_totalsize(&mc_header);
960 if (!mc_size || mc_size > leftover) {
f58e1f53 961 pr_err("error! Bad data in microcode data file\n");
a0a29b62
DA
962 break;
963 }
a30a6a2c 964
938179b4
DS
965 /* For performance reasons, reuse mc area when possible */
966 if (!mc || mc_size > curr_mc_size) {
5cdd2de0 967 vfree(mc);
938179b4
DS
968 mc = vmalloc(mc_size);
969 if (!mc)
970 break;
971 curr_mc_size = mc_size;
972 }
a0a29b62
DA
973
974 if (get_ucode_data(mc, ucode_ptr, mc_size) ||
9cd4d78e 975 microcode_sanity_check(mc, 1) < 0) {
a0a29b62
DA
976 break;
977 }
978
9cd4d78e
FY
979 csig = uci->cpu_sig.sig;
980 cpf = uci->cpu_sig.pf;
8de3eafc 981 if (has_newer_microcode(mc, csig, cpf, new_rev)) {
5cdd2de0 982 vfree(new_mc);
a0a29b62
DA
983 new_rev = mc_header.rev;
984 new_mc = mc;
938179b4
DS
985 mc = NULL; /* trigger new vmalloc */
986 }
a0a29b62
DA
987
988 ucode_ptr += mc_size;
989 leftover -= mc_size;
a30a6a2c
SL
990 }
991
5cdd2de0 992 vfree(mc);
938179b4 993
871b72dd 994 if (leftover) {
5cdd2de0 995 vfree(new_mc);
871b72dd 996 state = UCODE_ERROR;
4bae1967 997 goto out;
871b72dd 998 }
4bae1967 999
871b72dd
DA
1000 if (!new_mc) {
1001 state = UCODE_NFOUND;
4bae1967 1002 goto out;
a30a6a2c 1003 }
a0a29b62 1004
5cdd2de0 1005 vfree(uci->mc);
4bae1967
IM
1006 uci->mc = (struct microcode_intel *)new_mc;
1007
9cd4d78e
FY
1008 /*
1009 * If early loading microcode is supported, save this mc into
1010 * permanent memory. So it will be loaded early when a CPU is hot added
1011 * or resumes.
1012 */
1013 save_mc_for_early(new_mc);
1014
f58e1f53
JP
1015 pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n",
1016 cpu, new_rev, uci->cpu_sig.rev);
871b72dd
DA
1017out:
1018 return state;
a30a6a2c
SL
1019}
1020
a0a29b62
DA
1021static int get_ucode_fw(void *to, const void *from, size_t n)
1022{
1023 memcpy(to, from, n);
1024 return 0;
1025}
a30a6a2c 1026
48e30685
BP
1027static enum ucode_state request_microcode_fw(int cpu, struct device *device,
1028 bool refresh_fw)
a30a6a2c
SL
1029{
1030 char name[30];
92cb7612 1031 struct cpuinfo_x86 *c = &cpu_data(cpu);
a30a6a2c 1032 const struct firmware *firmware;
871b72dd 1033 enum ucode_state ret;
a30a6a2c 1034
3e135d88 1035 sprintf(name, "intel-ucode/%02x-%02x-%02x",
a30a6a2c 1036 c->x86, c->x86_model, c->x86_mask);
871b72dd 1037
75da02b2 1038 if (request_firmware_direct(&firmware, name, device)) {
f58e1f53 1039 pr_debug("data file %s load failed\n", name);
871b72dd 1040 return UCODE_NFOUND;
a30a6a2c 1041 }
a0a29b62 1042
dd3feda7
JSR
1043 ret = generic_load_microcode(cpu, (void *)firmware->data,
1044 firmware->size, &get_ucode_fw);
a0a29b62 1045
a30a6a2c
SL
1046 release_firmware(firmware);
1047
a0a29b62
DA
1048 return ret;
1049}
1050
1051static int get_ucode_user(void *to, const void *from, size_t n)
1052{
1053 return copy_from_user(to, from, n);
1054}
1055
871b72dd
DA
1056static enum ucode_state
1057request_microcode_user(int cpu, const void __user *buf, size_t size)
a0a29b62 1058{
dd3feda7 1059 return generic_load_microcode(cpu, (void *)buf, size, &get_ucode_user);
a30a6a2c
SL
1060}
1061
8d86f390 1062static void microcode_fini_cpu(int cpu)
a30a6a2c
SL
1063{
1064 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
1065
18dbc916
DA
1066 vfree(uci->mc);
1067 uci->mc = NULL;
a30a6a2c 1068}
8d86f390 1069
4db646b1 1070static struct microcode_ops microcode_intel_ops = {
a0a29b62
DA
1071 .request_microcode_user = request_microcode_user,
1072 .request_microcode_fw = request_microcode_fw,
8d86f390 1073 .collect_cpu_info = collect_cpu_info,
532ed374 1074 .apply_microcode = apply_microcode_intel,
8d86f390
PO
1075 .microcode_fini_cpu = microcode_fini_cpu,
1076};
1077
18dbc916 1078struct microcode_ops * __init init_intel_microcode(void)
8d86f390 1079{
9a2bc335 1080 struct cpuinfo_x86 *c = &boot_cpu_data;
7164b3f5
SB
1081
1082 if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 ||
1083 cpu_has(c, X86_FEATURE_IA64)) {
1084 pr_err("Intel CPU family 0x%x not supported\n", c->x86);
1085 return NULL;
1086 }
1087
18dbc916 1088 return &microcode_intel_ops;
8d86f390
PO
1089}
1090