Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
6b44e72a | 2 | * Intel CPU Microcode Update Driver for Linux |
1da177e4 | 3 | * |
6b44e72a BP |
4 | * Copyright (C) 2000-2006 Tigran Aivazian <tigran@aivazian.fsnet.co.uk> |
5 | * 2006 Shaohua Li <shaohua.li@intel.com> | |
1da177e4 | 6 | * |
fe055896 BP |
7 | * Intel CPU microcode early update for Linux |
8 | * | |
9 | * Copyright (C) 2012 Fenghua Yu <fenghua.yu@intel.com> | |
10 | * H Peter Anvin" <hpa@zytor.com> | |
11 | * | |
6b44e72a BP |
12 | * This program is free software; you can redistribute it and/or |
13 | * modify it under the terms of the GNU General Public License | |
14 | * as published by the Free Software Foundation; either version | |
15 | * 2 of the License, or (at your option) any later version. | |
1da177e4 | 16 | */ |
f58e1f53 | 17 | |
fe055896 BP |
18 | /* |
19 | * This needs to be before all headers so that pr_debug in printk.h doesn't turn | |
20 | * printk calls into no_printk(). | |
21 | * | |
22 | *#define DEBUG | |
23 | */ | |
6b26e1bf | 24 | #define pr_fmt(fmt) "microcode: " fmt |
f58e1f53 | 25 | |
fe055896 | 26 | #include <linux/earlycpio.h> |
4bae1967 | 27 | #include <linux/firmware.h> |
4bae1967 | 28 | #include <linux/uaccess.h> |
fe055896 BP |
29 | #include <linux/vmalloc.h> |
30 | #include <linux/initrd.h> | |
4bae1967 | 31 | #include <linux/kernel.h> |
fe055896 BP |
32 | #include <linux/slab.h> |
33 | #include <linux/cpu.h> | |
34 | #include <linux/mm.h> | |
1da177e4 | 35 | |
9cd4d78e | 36 | #include <asm/microcode_intel.h> |
4bae1967 | 37 | #include <asm/processor.h> |
fe055896 BP |
38 | #include <asm/tlbflush.h> |
39 | #include <asm/setup.h> | |
4bae1967 | 40 | #include <asm/msr.h> |
1da177e4 | 41 | |
06b8534c | 42 | static const char ucode_path[] = "kernel/x86/microcode/GenuineIntel.bin"; |
fe055896 | 43 | |
06b8534c BP |
44 | /* Current microcode patch used in early patching */ |
45 | struct microcode_intel *intel_ucode_patch; | |
6c545647 | 46 | |
8027923a BP |
47 | static inline bool cpu_signatures_match(unsigned int s1, unsigned int p1, |
48 | unsigned int s2, unsigned int p2) | |
49 | { | |
50 | if (s1 != s2) | |
51 | return false; | |
52 | ||
53 | /* Processor flags are either both 0 ... */ | |
54 | if (!p1 && !p2) | |
55 | return true; | |
56 | ||
57 | /* ... or they intersect. */ | |
58 | return p1 & p2; | |
59 | } | |
60 | ||
61 | /* | |
62 | * Returns 1 if update has been found, 0 otherwise. | |
63 | */ | |
64 | static int find_matching_signature(void *mc, unsigned int csig, int cpf) | |
65 | { | |
66 | struct microcode_header_intel *mc_hdr = mc; | |
67 | struct extended_sigtable *ext_hdr; | |
68 | struct extended_signature *ext_sig; | |
69 | int i; | |
70 | ||
71 | if (cpu_signatures_match(csig, cpf, mc_hdr->sig, mc_hdr->pf)) | |
72 | return 1; | |
73 | ||
74 | /* Look for ext. headers: */ | |
75 | if (get_totalsize(mc_hdr) <= get_datasize(mc_hdr) + MC_HEADER_SIZE) | |
76 | return 0; | |
77 | ||
78 | ext_hdr = mc + get_datasize(mc_hdr) + MC_HEADER_SIZE; | |
79 | ext_sig = (void *)ext_hdr + EXT_HEADER_SIZE; | |
80 | ||
81 | for (i = 0; i < ext_hdr->count; i++) { | |
82 | if (cpu_signatures_match(csig, cpf, ext_sig->sig, ext_sig->pf)) | |
83 | return 1; | |
84 | ext_sig++; | |
85 | } | |
86 | return 0; | |
87 | } | |
88 | ||
89 | /* | |
90 | * Returns 1 if update has been found, 0 otherwise. | |
91 | */ | |
92 | static int has_newer_microcode(void *mc, unsigned int csig, int cpf, int new_rev) | |
93 | { | |
94 | struct microcode_header_intel *mc_hdr = mc; | |
95 | ||
96 | if (mc_hdr->rev <= new_rev) | |
97 | return 0; | |
98 | ||
99 | return find_matching_signature(mc, csig, cpf); | |
100 | } | |
101 | ||
fe055896 BP |
102 | /* |
103 | * Given CPU signature and a microcode patch, this function finds if the | |
104 | * microcode patch has matching family and model with the CPU. | |
06b8534c BP |
105 | * |
106 | * %true - if there's a match | |
107 | * %false - otherwise | |
fe055896 | 108 | */ |
06b8534c BP |
109 | static bool microcode_matches(struct microcode_header_intel *mc_header, |
110 | unsigned long sig) | |
fe055896 | 111 | { |
fe055896 BP |
112 | unsigned long total_size = get_totalsize(mc_header); |
113 | unsigned long data_size = get_datasize(mc_header); | |
06b8534c BP |
114 | struct extended_sigtable *ext_header; |
115 | unsigned int fam_ucode, model_ucode; | |
fe055896 | 116 | struct extended_signature *ext_sig; |
06b8534c BP |
117 | unsigned int fam, model; |
118 | int ext_sigcount, i; | |
fe055896 | 119 | |
99f925ce | 120 | fam = x86_family(sig); |
fe055896 BP |
121 | model = x86_model(sig); |
122 | ||
99f925ce | 123 | fam_ucode = x86_family(mc_header->sig); |
fe055896 BP |
124 | model_ucode = x86_model(mc_header->sig); |
125 | ||
126 | if (fam == fam_ucode && model == model_ucode) | |
06b8534c | 127 | return true; |
fe055896 BP |
128 | |
129 | /* Look for ext. headers: */ | |
130 | if (total_size <= data_size + MC_HEADER_SIZE) | |
06b8534c | 131 | return false; |
fe055896 BP |
132 | |
133 | ext_header = (void *) mc_header + data_size + MC_HEADER_SIZE; | |
134 | ext_sig = (void *)ext_header + EXT_HEADER_SIZE; | |
135 | ext_sigcount = ext_header->count; | |
136 | ||
137 | for (i = 0; i < ext_sigcount; i++) { | |
99f925ce | 138 | fam_ucode = x86_family(ext_sig->sig); |
fe055896 BP |
139 | model_ucode = x86_model(ext_sig->sig); |
140 | ||
141 | if (fam == fam_ucode && model == model_ucode) | |
06b8534c | 142 | return true; |
fe055896 BP |
143 | |
144 | ext_sig++; | |
145 | } | |
06b8534c | 146 | return false; |
fe055896 BP |
147 | } |
148 | ||
06b8534c | 149 | static struct ucode_patch *__alloc_microcode_buf(void *data, unsigned int size) |
fe055896 | 150 | { |
06b8534c | 151 | struct ucode_patch *p; |
fe055896 | 152 | |
06b8534c BP |
153 | p = kzalloc(size, GFP_KERNEL); |
154 | if (!p) | |
155 | return ERR_PTR(-ENOMEM); | |
fe055896 | 156 | |
06b8534c BP |
157 | p->data = kmemdup(data, size, GFP_KERNEL); |
158 | if (!p->data) { | |
159 | kfree(p); | |
160 | return ERR_PTR(-ENOMEM); | |
fe055896 BP |
161 | } |
162 | ||
06b8534c | 163 | return p; |
fe055896 BP |
164 | } |
165 | ||
06b8534c | 166 | static void save_microcode_patch(void *data, unsigned int size) |
fe055896 BP |
167 | { |
168 | struct microcode_header_intel *mc_hdr, *mc_saved_hdr; | |
06b8534c BP |
169 | struct ucode_patch *iter, *tmp, *p; |
170 | bool prev_found = false; | |
fe055896 | 171 | unsigned int sig, pf; |
fe055896 | 172 | |
06b8534c | 173 | mc_hdr = (struct microcode_header_intel *)data; |
fe055896 | 174 | |
06b8534c BP |
175 | list_for_each_entry_safe(iter, tmp, µcode_cache, plist) { |
176 | mc_saved_hdr = (struct microcode_header_intel *)iter->data; | |
fe055896 BP |
177 | sig = mc_saved_hdr->sig; |
178 | pf = mc_saved_hdr->pf; | |
179 | ||
06b8534c BP |
180 | if (find_matching_signature(data, sig, pf)) { |
181 | prev_found = true; | |
fe055896 | 182 | |
06b8534c BP |
183 | if (mc_hdr->rev <= mc_saved_hdr->rev) |
184 | continue; | |
fe055896 | 185 | |
06b8534c BP |
186 | p = __alloc_microcode_buf(data, size); |
187 | if (IS_ERR(p)) | |
188 | pr_err("Error allocating buffer %p\n", data); | |
189 | else | |
190 | list_replace(&iter->plist, &p->plist); | |
191 | } | |
fe055896 BP |
192 | } |
193 | ||
06b8534c BP |
194 | /* |
195 | * There weren't any previous patches found in the list cache; save the | |
196 | * newly found. | |
197 | */ | |
198 | if (!prev_found) { | |
199 | p = __alloc_microcode_buf(data, size); | |
200 | if (IS_ERR(p)) | |
201 | pr_err("Error allocating buffer for %p\n", data); | |
202 | else | |
203 | list_add_tail(&p->plist, µcode_cache); | |
204 | } | |
fe055896 BP |
205 | } |
206 | ||
8027923a BP |
207 | static int microcode_sanity_check(void *mc, int print_err) |
208 | { | |
209 | unsigned long total_size, data_size, ext_table_size; | |
210 | struct microcode_header_intel *mc_header = mc; | |
211 | struct extended_sigtable *ext_header = NULL; | |
212 | u32 sum, orig_sum, ext_sigcount = 0, i; | |
213 | struct extended_signature *ext_sig; | |
214 | ||
215 | total_size = get_totalsize(mc_header); | |
216 | data_size = get_datasize(mc_header); | |
217 | ||
218 | if (data_size + MC_HEADER_SIZE > total_size) { | |
219 | if (print_err) | |
220 | pr_err("Error: bad microcode data file size.\n"); | |
221 | return -EINVAL; | |
222 | } | |
223 | ||
224 | if (mc_header->ldrver != 1 || mc_header->hdrver != 1) { | |
225 | if (print_err) | |
226 | pr_err("Error: invalid/unknown microcode update format.\n"); | |
227 | return -EINVAL; | |
228 | } | |
229 | ||
230 | ext_table_size = total_size - (MC_HEADER_SIZE + data_size); | |
231 | if (ext_table_size) { | |
232 | u32 ext_table_sum = 0; | |
233 | u32 *ext_tablep; | |
234 | ||
235 | if ((ext_table_size < EXT_HEADER_SIZE) | |
236 | || ((ext_table_size - EXT_HEADER_SIZE) % EXT_SIGNATURE_SIZE)) { | |
237 | if (print_err) | |
238 | pr_err("Error: truncated extended signature table.\n"); | |
239 | return -EINVAL; | |
240 | } | |
241 | ||
242 | ext_header = mc + MC_HEADER_SIZE + data_size; | |
243 | if (ext_table_size != exttable_size(ext_header)) { | |
244 | if (print_err) | |
245 | pr_err("Error: extended signature table size mismatch.\n"); | |
246 | return -EFAULT; | |
247 | } | |
248 | ||
249 | ext_sigcount = ext_header->count; | |
250 | ||
251 | /* | |
252 | * Check extended table checksum: the sum of all dwords that | |
253 | * comprise a valid table must be 0. | |
254 | */ | |
255 | ext_tablep = (u32 *)ext_header; | |
256 | ||
257 | i = ext_table_size / sizeof(u32); | |
258 | while (i--) | |
259 | ext_table_sum += ext_tablep[i]; | |
260 | ||
261 | if (ext_table_sum) { | |
262 | if (print_err) | |
263 | pr_warn("Bad extended signature table checksum, aborting.\n"); | |
264 | return -EINVAL; | |
265 | } | |
266 | } | |
267 | ||
268 | /* | |
269 | * Calculate the checksum of update data and header. The checksum of | |
270 | * valid update data and header including the extended signature table | |
271 | * must be 0. | |
272 | */ | |
273 | orig_sum = 0; | |
274 | i = (MC_HEADER_SIZE + data_size) / sizeof(u32); | |
275 | while (i--) | |
276 | orig_sum += ((u32 *)mc)[i]; | |
277 | ||
278 | if (orig_sum) { | |
279 | if (print_err) | |
280 | pr_err("Bad microcode data checksum, aborting.\n"); | |
281 | return -EINVAL; | |
282 | } | |
283 | ||
284 | if (!ext_table_size) | |
285 | return 0; | |
286 | ||
287 | /* | |
288 | * Check extended signature checksum: 0 => valid. | |
289 | */ | |
290 | for (i = 0; i < ext_sigcount; i++) { | |
291 | ext_sig = (void *)ext_header + EXT_HEADER_SIZE + | |
292 | EXT_SIGNATURE_SIZE * i; | |
293 | ||
294 | sum = (mc_header->sig + mc_header->pf + mc_header->cksum) - | |
295 | (ext_sig->sig + ext_sig->pf + ext_sig->cksum); | |
296 | if (sum) { | |
297 | if (print_err) | |
298 | pr_err("Bad extended signature checksum, aborting.\n"); | |
299 | return -EINVAL; | |
300 | } | |
301 | } | |
302 | return 0; | |
303 | } | |
304 | ||
fe055896 BP |
305 | /* |
306 | * Get microcode matching with BSP's model. Only CPUs with the same model as | |
307 | * BSP can stay in the platform. | |
308 | */ | |
06b8534c BP |
309 | static struct microcode_intel * |
310 | scan_microcode(void *data, size_t size, struct ucode_cpu_info *uci, bool save) | |
fe055896 | 311 | { |
f96fde53 | 312 | struct microcode_header_intel *mc_header; |
06b8534c | 313 | struct microcode_intel *patch = NULL; |
f96fde53 | 314 | unsigned int mc_size; |
fe055896 | 315 | |
06b8534c BP |
316 | while (size) { |
317 | if (size < sizeof(struct microcode_header_intel)) | |
fe055896 BP |
318 | break; |
319 | ||
06b8534c | 320 | mc_header = (struct microcode_header_intel *)data; |
fe055896 BP |
321 | |
322 | mc_size = get_totalsize(mc_header); | |
06b8534c BP |
323 | if (!mc_size || |
324 | mc_size > size || | |
325 | microcode_sanity_check(data, 0) < 0) | |
fe055896 BP |
326 | break; |
327 | ||
06b8534c | 328 | size -= mc_size; |
fe055896 | 329 | |
06b8534c BP |
330 | if (!microcode_matches(mc_header, uci->cpu_sig.sig)) { |
331 | data += mc_size; | |
fe055896 BP |
332 | continue; |
333 | } | |
334 | ||
06b8534c BP |
335 | if (save) { |
336 | save_microcode_patch(data, mc_size); | |
337 | goto next; | |
338 | } | |
fe055896 | 339 | |
fe055896 | 340 | |
06b8534c BP |
341 | if (!patch) { |
342 | if (!has_newer_microcode(data, | |
343 | uci->cpu_sig.sig, | |
344 | uci->cpu_sig.pf, | |
345 | uci->cpu_sig.rev)) | |
346 | goto next; | |
fe055896 | 347 | |
06b8534c BP |
348 | } else { |
349 | struct microcode_header_intel *phdr = &patch->hdr; | |
350 | ||
351 | if (!has_newer_microcode(data, | |
352 | phdr->sig, | |
353 | phdr->pf, | |
354 | phdr->rev)) | |
355 | goto next; | |
356 | } | |
fe055896 | 357 | |
06b8534c BP |
358 | /* We have a newer patch, save it. */ |
359 | patch = data; | |
fe055896 | 360 | |
06b8534c BP |
361 | next: |
362 | data += mc_size; | |
363 | } | |
f96fde53 | 364 | |
06b8534c BP |
365 | if (size) |
366 | return NULL; | |
367 | ||
368 | return patch; | |
fe055896 BP |
369 | } |
370 | ||
371 | static int collect_cpu_info_early(struct ucode_cpu_info *uci) | |
372 | { | |
373 | unsigned int val[2]; | |
374 | unsigned int family, model; | |
06b8534c | 375 | struct cpu_signature csig = { 0 }; |
fe055896 BP |
376 | unsigned int eax, ebx, ecx, edx; |
377 | ||
fe055896 BP |
378 | memset(uci, 0, sizeof(*uci)); |
379 | ||
380 | eax = 0x00000001; | |
381 | ecx = 0; | |
382 | native_cpuid(&eax, &ebx, &ecx, &edx); | |
383 | csig.sig = eax; | |
384 | ||
06b8534c BP |
385 | family = x86_family(eax); |
386 | model = x86_model(eax); | |
fe055896 BP |
387 | |
388 | if ((model >= 5) || (family > 6)) { | |
389 | /* get processor flags from MSR 0x17 */ | |
390 | native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); | |
391 | csig.pf = 1 << ((val[1] >> 18) & 7); | |
392 | } | |
c416e611 | 393 | native_wrmsrl(MSR_IA32_UCODE_REV, 0); |
fe055896 BP |
394 | |
395 | /* As documented in the SDM: Do a CPUID 1 here */ | |
396 | sync_core(); | |
397 | ||
398 | /* get the current revision from MSR 0x8B */ | |
399 | native_rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]); | |
400 | ||
401 | csig.rev = val[1]; | |
402 | ||
403 | uci->cpu_sig = csig; | |
404 | uci->valid = 1; | |
405 | ||
406 | return 0; | |
407 | } | |
408 | ||
fe055896 BP |
409 | static void show_saved_mc(void) |
410 | { | |
c595ac2b | 411 | #ifdef DEBUG |
06b8534c | 412 | int i = 0, j; |
fe055896 BP |
413 | unsigned int sig, pf, rev, total_size, data_size, date; |
414 | struct ucode_cpu_info uci; | |
06b8534c | 415 | struct ucode_patch *p; |
fe055896 | 416 | |
06b8534c | 417 | if (list_empty(µcode_cache)) { |
fe055896 BP |
418 | pr_debug("no microcode data saved.\n"); |
419 | return; | |
420 | } | |
fe055896 BP |
421 | |
422 | collect_cpu_info_early(&uci); | |
423 | ||
06b8534c BP |
424 | sig = uci.cpu_sig.sig; |
425 | pf = uci.cpu_sig.pf; | |
426 | rev = uci.cpu_sig.rev; | |
fe055896 BP |
427 | pr_debug("CPU: sig=0x%x, pf=0x%x, rev=0x%x\n", sig, pf, rev); |
428 | ||
06b8534c | 429 | list_for_each_entry(p, µcode_cache, plist) { |
fe055896 BP |
430 | struct microcode_header_intel *mc_saved_header; |
431 | struct extended_sigtable *ext_header; | |
fe055896 | 432 | struct extended_signature *ext_sig; |
06b8534c BP |
433 | int ext_sigcount; |
434 | ||
435 | mc_saved_header = (struct microcode_header_intel *)p->data; | |
436 | ||
437 | sig = mc_saved_header->sig; | |
438 | pf = mc_saved_header->pf; | |
439 | rev = mc_saved_header->rev; | |
440 | date = mc_saved_header->date; | |
fe055896 | 441 | |
06b8534c BP |
442 | total_size = get_totalsize(mc_saved_header); |
443 | data_size = get_datasize(mc_saved_header); | |
fe055896 | 444 | |
c19ca6cb | 445 | pr_debug("mc_saved[%d]: sig=0x%x, pf=0x%x, rev=0x%x, total size=0x%x, date = %04x-%02x-%02x\n", |
06b8534c | 446 | i++, sig, pf, rev, total_size, |
fe055896 BP |
447 | date & 0xffff, |
448 | date >> 24, | |
449 | (date >> 16) & 0xff); | |
450 | ||
451 | /* Look for ext. headers: */ | |
452 | if (total_size <= data_size + MC_HEADER_SIZE) | |
453 | continue; | |
454 | ||
06b8534c | 455 | ext_header = (void *)mc_saved_header + data_size + MC_HEADER_SIZE; |
fe055896 BP |
456 | ext_sigcount = ext_header->count; |
457 | ext_sig = (void *)ext_header + EXT_HEADER_SIZE; | |
458 | ||
459 | for (j = 0; j < ext_sigcount; j++) { | |
460 | sig = ext_sig->sig; | |
461 | pf = ext_sig->pf; | |
462 | ||
463 | pr_debug("\tExtended[%d]: sig=0x%x, pf=0x%x\n", | |
464 | j, sig, pf); | |
465 | ||
466 | ext_sig++; | |
467 | } | |
fe055896 | 468 | } |
fe055896 | 469 | #endif |
c595ac2b | 470 | } |
fe055896 | 471 | |
fe055896 | 472 | /* |
06b8534c BP |
473 | * Save this microcode patch. It will be loaded early when a CPU is |
474 | * hot-added or resumes. | |
fe055896 | 475 | */ |
06b8534c | 476 | static void save_mc_for_early(u8 *mc, unsigned int size) |
fe055896 | 477 | { |
0c5fa827 | 478 | #ifdef CONFIG_HOTPLUG_CPU |
9f3cc2a0 | 479 | /* Synchronization during CPU hotplug. */ |
0c5fa827 BP |
480 | static DEFINE_MUTEX(x86_cpu_microcode_mutex); |
481 | ||
fe055896 BP |
482 | mutex_lock(&x86_cpu_microcode_mutex); |
483 | ||
06b8534c | 484 | save_microcode_patch(mc, size); |
fe055896 BP |
485 | show_saved_mc(); |
486 | ||
fe055896 | 487 | mutex_unlock(&x86_cpu_microcode_mutex); |
fe055896 | 488 | #endif |
0c5fa827 | 489 | } |
fe055896 | 490 | |
06b8534c | 491 | static bool load_builtin_intel_microcode(struct cpio_data *cp) |
fe055896 | 492 | { |
06b8534c | 493 | unsigned int eax = 1, ebx, ecx = 0, edx; |
fe055896 BP |
494 | char name[30]; |
495 | ||
06b8534c BP |
496 | if (IS_ENABLED(CONFIG_X86_32)) |
497 | return false; | |
498 | ||
fe055896 BP |
499 | native_cpuid(&eax, &ebx, &ecx, &edx); |
500 | ||
99f925ce BP |
501 | sprintf(name, "intel-ucode/%02x-%02x-%02x", |
502 | x86_family(eax), x86_model(eax), x86_stepping(eax)); | |
fe055896 BP |
503 | |
504 | return get_builtin_firmware(cp, name); | |
fe055896 BP |
505 | } |
506 | ||
fe055896 BP |
507 | /* |
508 | * Print ucode update info. | |
509 | */ | |
510 | static void | |
511 | print_ucode_info(struct ucode_cpu_info *uci, unsigned int date) | |
512 | { | |
b7f500ae BP |
513 | pr_info_once("microcode updated early to revision 0x%x, date = %04x-%02x-%02x\n", |
514 | uci->cpu_sig.rev, | |
515 | date & 0xffff, | |
516 | date >> 24, | |
517 | (date >> 16) & 0xff); | |
fe055896 BP |
518 | } |
519 | ||
520 | #ifdef CONFIG_X86_32 | |
521 | ||
522 | static int delay_ucode_info; | |
523 | static int current_mc_date; | |
524 | ||
525 | /* | |
526 | * Print early updated ucode info after printk works. This is delayed info dump. | |
527 | */ | |
528 | void show_ucode_info_early(void) | |
529 | { | |
530 | struct ucode_cpu_info uci; | |
531 | ||
532 | if (delay_ucode_info) { | |
533 | collect_cpu_info_early(&uci); | |
534 | print_ucode_info(&uci, current_mc_date); | |
535 | delay_ucode_info = 0; | |
536 | } | |
537 | } | |
538 | ||
539 | /* | |
06b8534c | 540 | * At this point, we can not call printk() yet. Delay printing microcode info in |
fe055896 BP |
541 | * show_ucode_info_early() until printk() works. |
542 | */ | |
543 | static void print_ucode(struct ucode_cpu_info *uci) | |
544 | { | |
de778275 | 545 | struct microcode_intel *mc; |
fe055896 BP |
546 | int *delay_ucode_info_p; |
547 | int *current_mc_date_p; | |
548 | ||
de778275 BP |
549 | mc = uci->mc; |
550 | if (!mc) | |
fe055896 BP |
551 | return; |
552 | ||
553 | delay_ucode_info_p = (int *)__pa_nodebug(&delay_ucode_info); | |
554 | current_mc_date_p = (int *)__pa_nodebug(¤t_mc_date); | |
555 | ||
556 | *delay_ucode_info_p = 1; | |
de778275 | 557 | *current_mc_date_p = mc->hdr.date; |
fe055896 BP |
558 | } |
559 | #else | |
560 | ||
561 | /* | |
562 | * Flush global tlb. We only do this in x86_64 where paging has been enabled | |
563 | * already and PGE should be enabled as well. | |
564 | */ | |
565 | static inline void flush_tlb_early(void) | |
566 | { | |
567 | __native_flush_tlb_global_irq_disabled(); | |
568 | } | |
569 | ||
570 | static inline void print_ucode(struct ucode_cpu_info *uci) | |
571 | { | |
de778275 | 572 | struct microcode_intel *mc; |
fe055896 | 573 | |
de778275 BP |
574 | mc = uci->mc; |
575 | if (!mc) | |
fe055896 BP |
576 | return; |
577 | ||
de778275 | 578 | print_ucode_info(uci, mc->hdr.date); |
fe055896 BP |
579 | } |
580 | #endif | |
581 | ||
582 | static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) | |
583 | { | |
de778275 | 584 | struct microcode_intel *mc; |
fe055896 BP |
585 | unsigned int val[2]; |
586 | ||
de778275 BP |
587 | mc = uci->mc; |
588 | if (!mc) | |
fe055896 BP |
589 | return 0; |
590 | ||
591 | /* write microcode via MSR 0x79 */ | |
c416e611 BP |
592 | native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); |
593 | native_wrmsrl(MSR_IA32_UCODE_REV, 0); | |
fe055896 BP |
594 | |
595 | /* As documented in the SDM: Do a CPUID 1 here */ | |
596 | sync_core(); | |
597 | ||
598 | /* get the current revision from MSR 0x8B */ | |
599 | native_rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]); | |
de778275 | 600 | if (val[1] != mc->hdr.rev) |
fe055896 BP |
601 | return -1; |
602 | ||
603 | #ifdef CONFIG_X86_64 | |
604 | /* Flush global tlb. This is precaution. */ | |
605 | flush_tlb_early(); | |
606 | #endif | |
607 | uci->cpu_sig.rev = val[1]; | |
608 | ||
609 | if (early) | |
610 | print_ucode(uci); | |
611 | else | |
de778275 | 612 | print_ucode_info(uci, mc->hdr.date); |
fe055896 BP |
613 | |
614 | return 0; | |
615 | } | |
616 | ||
fe055896 BP |
617 | int __init save_microcode_in_initrd_intel(void) |
618 | { | |
06b8534c BP |
619 | struct ucode_cpu_info uci; |
620 | struct cpio_data cp; | |
fe055896 | 621 | |
6c545647 | 622 | /* |
06b8534c | 623 | * AP loading didn't find any microcode patch, no need to save anything. |
6c545647 | 624 | */ |
06b8534c BP |
625 | if (!intel_ucode_patch || IS_ERR(intel_ucode_patch)) |
626 | return 0; | |
4fe9349f | 627 | |
06b8534c BP |
628 | if (!load_builtin_intel_microcode(&cp)) |
629 | cp = find_microcode_in_initrd(ucode_path, false); | |
fe055896 | 630 | |
06b8534c BP |
631 | if (!(cp.data && cp.size)) |
632 | return 0; | |
fe055896 | 633 | |
06b8534c | 634 | collect_cpu_info_early(&uci); |
6c545647 | 635 | |
06b8534c | 636 | scan_microcode(cp.data, cp.size, &uci, true); |
6c545647 | 637 | |
06b8534c | 638 | show_saved_mc(); |
6c545647 | 639 | |
06b8534c BP |
640 | return 0; |
641 | } | |
6c545647 | 642 | |
6c545647 | 643 | |
06b8534c BP |
644 | /* |
645 | * @res_patch, output: a pointer to the patch we found. | |
646 | */ | |
647 | static struct microcode_intel *__load_ucode_intel(struct ucode_cpu_info *uci) | |
648 | { | |
649 | static const char *path; | |
650 | struct cpio_data cp; | |
651 | bool use_pa; | |
6c545647 | 652 | |
06b8534c BP |
653 | if (IS_ENABLED(CONFIG_X86_32)) { |
654 | path = (const char *)__pa_nodebug(ucode_path); | |
655 | use_pa = true; | |
656 | } else { | |
657 | path = ucode_path; | |
658 | use_pa = false; | |
6c545647 | 659 | } |
6c545647 | 660 | |
06b8534c BP |
661 | /* try built-in microcode first */ |
662 | if (!load_builtin_intel_microcode(&cp)) | |
663 | cp = find_microcode_in_initrd(path, use_pa); | |
6c545647 | 664 | |
06b8534c BP |
665 | if (!(cp.data && cp.size)) |
666 | return NULL; | |
6c545647 | 667 | |
06b8534c | 668 | collect_cpu_info_early(uci); |
6c545647 | 669 | |
06b8534c | 670 | return scan_microcode(cp.data, cp.size, uci, false); |
6c545647 BP |
671 | } |
672 | ||
06b8534c | 673 | void __init load_ucode_intel_bsp(void) |
fe055896 | 674 | { |
06b8534c | 675 | struct microcode_intel *patch; |
fe055896 | 676 | struct ucode_cpu_info uci; |
fe055896 | 677 | |
06b8534c BP |
678 | patch = __load_ucode_intel(&uci); |
679 | if (!patch) | |
fe055896 BP |
680 | return; |
681 | ||
06b8534c | 682 | uci.mc = patch; |
fe055896 BP |
683 | |
684 | apply_microcode_early(&uci, true); | |
685 | } | |
686 | ||
06b8534c | 687 | void load_ucode_intel_ap(void) |
fe055896 | 688 | { |
06b8534c BP |
689 | struct microcode_intel *patch, **iup; |
690 | struct ucode_cpu_info uci; | |
264285ac | 691 | |
06b8534c BP |
692 | if (IS_ENABLED(CONFIG_X86_32)) |
693 | iup = (struct microcode_intel **) __pa_nodebug(&intel_ucode_patch); | |
694 | else | |
695 | iup = &intel_ucode_patch; | |
696 | ||
697 | reget: | |
698 | if (!*iup) { | |
699 | patch = __load_ucode_intel(&uci); | |
700 | if (!patch) | |
701 | return; | |
6c545647 | 702 | |
06b8534c BP |
703 | *iup = patch; |
704 | } | |
705 | ||
706 | uci.mc = *iup; | |
707 | ||
708 | if (apply_microcode_early(&uci, true)) { | |
709 | /* Mixed-silicon system? Try to refetch the proper patch: */ | |
710 | *iup = NULL; | |
711 | ||
712 | goto reget; | |
713 | } | |
fe055896 BP |
714 | } |
715 | ||
06b8534c | 716 | static struct microcode_intel *find_patch(struct ucode_cpu_info *uci) |
fe055896 | 717 | { |
06b8534c BP |
718 | struct microcode_header_intel *phdr; |
719 | struct ucode_patch *iter, *tmp; | |
fe055896 | 720 | |
06b8534c | 721 | list_for_each_entry_safe(iter, tmp, µcode_cache, plist) { |
fe055896 | 722 | |
06b8534c | 723 | phdr = (struct microcode_header_intel *)iter->data; |
efaad554 | 724 | |
06b8534c BP |
725 | if (phdr->rev <= uci->cpu_sig.rev) |
726 | continue; | |
efaad554 | 727 | |
06b8534c BP |
728 | if (!find_matching_signature(phdr, |
729 | uci->cpu_sig.sig, | |
730 | uci->cpu_sig.pf)) | |
731 | continue; | |
fe055896 | 732 | |
06b8534c BP |
733 | return iter->data; |
734 | } | |
735 | return NULL; | |
fe055896 BP |
736 | } |
737 | ||
738 | void reload_ucode_intel(void) | |
739 | { | |
06b8534c | 740 | struct microcode_intel *p; |
fe055896 | 741 | struct ucode_cpu_info uci; |
fe055896 BP |
742 | |
743 | collect_cpu_info_early(&uci); | |
744 | ||
06b8534c BP |
745 | p = find_patch(&uci); |
746 | if (!p) | |
fe055896 BP |
747 | return; |
748 | ||
06b8534c BP |
749 | uci.mc = p; |
750 | ||
fe055896 BP |
751 | apply_microcode_early(&uci, false); |
752 | } | |
753 | ||
d45de409 | 754 | static int collect_cpu_info(int cpu_num, struct cpu_signature *csig) |
1da177e4 | 755 | { |
354542d0 | 756 | static struct cpu_signature prev; |
92cb7612 | 757 | struct cpuinfo_x86 *c = &cpu_data(cpu_num); |
1da177e4 LT |
758 | unsigned int val[2]; |
759 | ||
d45de409 | 760 | memset(csig, 0, sizeof(*csig)); |
1da177e4 | 761 | |
d45de409 | 762 | csig->sig = cpuid_eax(0x00000001); |
9a3110bf SL |
763 | |
764 | if ((c->x86_model >= 5) || (c->x86 > 6)) { | |
765 | /* get processor flags from MSR 0x17 */ | |
766 | rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); | |
d45de409 | 767 | csig->pf = 1 << ((val[1] >> 18) & 7); |
1da177e4 LT |
768 | } |
769 | ||
506ed6b5 | 770 | csig->rev = c->microcode; |
354542d0 AK |
771 | |
772 | /* No extra locking on prev, races are harmless. */ | |
773 | if (csig->sig != prev.sig || csig->pf != prev.pf || csig->rev != prev.rev) { | |
774 | pr_info("sig=0x%x, pf=0x%x, revision=0x%x\n", | |
775 | csig->sig, csig->pf, csig->rev); | |
776 | prev = *csig; | |
777 | } | |
d45de409 DA |
778 | |
779 | return 0; | |
1da177e4 LT |
780 | } |
781 | ||
532ed374 | 782 | static int apply_microcode_intel(int cpu) |
1da177e4 | 783 | { |
de778275 | 784 | struct microcode_intel *mc; |
4bae1967 | 785 | struct ucode_cpu_info *uci; |
26cbaa4d | 786 | struct cpuinfo_x86 *c; |
1da177e4 | 787 | unsigned int val[2]; |
354542d0 | 788 | static int prev_rev; |
4bae1967 | 789 | |
9a3110bf | 790 | /* We should bind the task to the CPU */ |
26cbaa4d | 791 | if (WARN_ON(raw_smp_processor_id() != cpu)) |
58b5f2cc | 792 | return -1; |
9a3110bf | 793 | |
58b5f2cc BP |
794 | uci = ucode_cpu_info + cpu; |
795 | mc = uci->mc; | |
06b8534c BP |
796 | if (!mc) { |
797 | /* Look for a newer patch in our cache: */ | |
798 | mc = find_patch(uci); | |
799 | if (!mc) | |
800 | return 0; | |
801 | } | |
9cd4d78e | 802 | |
1da177e4 | 803 | /* write microcode via MSR 0x79 */ |
c416e611 BP |
804 | wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); |
805 | wrmsrl(MSR_IA32_UCODE_REV, 0); | |
1da177e4 | 806 | |
506ed6b5 | 807 | /* As documented in the SDM: Do a CPUID 1 here */ |
487472bc | 808 | sync_core(); |
245067d1 | 809 | |
1da177e4 LT |
810 | /* get the current revision from MSR 0x8B */ |
811 | rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]); | |
812 | ||
de778275 | 813 | if (val[1] != mc->hdr.rev) { |
f58e1f53 | 814 | pr_err("CPU%d update to revision 0x%x failed\n", |
26cbaa4d | 815 | cpu, mc->hdr.rev); |
871b72dd | 816 | return -1; |
9a3110bf | 817 | } |
26cbaa4d | 818 | |
354542d0 AK |
819 | if (val[1] != prev_rev) { |
820 | pr_info("updated to revision 0x%x, date = %04x-%02x-%02x\n", | |
821 | val[1], | |
822 | mc->hdr.date & 0xffff, | |
823 | mc->hdr.date >> 24, | |
824 | (mc->hdr.date >> 16) & 0xff); | |
825 | prev_rev = val[1]; | |
826 | } | |
4bae1967 | 827 | |
26cbaa4d BP |
828 | c = &cpu_data(cpu); |
829 | ||
d45de409 | 830 | uci->cpu_sig.rev = val[1]; |
506ed6b5 | 831 | c->microcode = val[1]; |
871b72dd DA |
832 | |
833 | return 0; | |
1da177e4 LT |
834 | } |
835 | ||
871b72dd DA |
836 | static enum ucode_state generic_load_microcode(int cpu, void *data, size_t size, |
837 | int (*get_ucode_data)(void *, const void *, size_t)) | |
9a3110bf | 838 | { |
a0a29b62 | 839 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; |
938179b4 | 840 | u8 *ucode_ptr = data, *new_mc = NULL, *mc = NULL; |
a0a29b62 DA |
841 | int new_rev = uci->cpu_sig.rev; |
842 | unsigned int leftover = size; | |
938179b4 | 843 | unsigned int curr_mc_size = 0; |
9cd4d78e | 844 | unsigned int csig, cpf; |
9a3110bf | 845 | |
a0a29b62 DA |
846 | while (leftover) { |
847 | struct microcode_header_intel mc_header; | |
848 | unsigned int mc_size; | |
9a3110bf | 849 | |
35a9ff4e QC |
850 | if (leftover < sizeof(mc_header)) { |
851 | pr_err("error! Truncated header in microcode data file\n"); | |
852 | break; | |
853 | } | |
854 | ||
a0a29b62 DA |
855 | if (get_ucode_data(&mc_header, ucode_ptr, sizeof(mc_header))) |
856 | break; | |
a30a6a2c | 857 | |
a0a29b62 DA |
858 | mc_size = get_totalsize(&mc_header); |
859 | if (!mc_size || mc_size > leftover) { | |
f58e1f53 | 860 | pr_err("error! Bad data in microcode data file\n"); |
a0a29b62 DA |
861 | break; |
862 | } | |
a30a6a2c | 863 | |
938179b4 DS |
864 | /* For performance reasons, reuse mc area when possible */ |
865 | if (!mc || mc_size > curr_mc_size) { | |
5cdd2de0 | 866 | vfree(mc); |
938179b4 DS |
867 | mc = vmalloc(mc_size); |
868 | if (!mc) | |
869 | break; | |
870 | curr_mc_size = mc_size; | |
871 | } | |
a0a29b62 DA |
872 | |
873 | if (get_ucode_data(mc, ucode_ptr, mc_size) || | |
9cd4d78e | 874 | microcode_sanity_check(mc, 1) < 0) { |
a0a29b62 DA |
875 | break; |
876 | } | |
877 | ||
9cd4d78e FY |
878 | csig = uci->cpu_sig.sig; |
879 | cpf = uci->cpu_sig.pf; | |
8de3eafc | 880 | if (has_newer_microcode(mc, csig, cpf, new_rev)) { |
5cdd2de0 | 881 | vfree(new_mc); |
a0a29b62 DA |
882 | new_rev = mc_header.rev; |
883 | new_mc = mc; | |
938179b4 DS |
884 | mc = NULL; /* trigger new vmalloc */ |
885 | } | |
a0a29b62 DA |
886 | |
887 | ucode_ptr += mc_size; | |
888 | leftover -= mc_size; | |
a30a6a2c SL |
889 | } |
890 | ||
5cdd2de0 | 891 | vfree(mc); |
938179b4 | 892 | |
871b72dd | 893 | if (leftover) { |
5cdd2de0 | 894 | vfree(new_mc); |
f61337d9 | 895 | return UCODE_ERROR; |
871b72dd | 896 | } |
4bae1967 | 897 | |
f61337d9 BP |
898 | if (!new_mc) |
899 | return UCODE_NFOUND; | |
a0a29b62 | 900 | |
5cdd2de0 | 901 | vfree(uci->mc); |
4bae1967 IM |
902 | uci->mc = (struct microcode_intel *)new_mc; |
903 | ||
9cd4d78e FY |
904 | /* |
905 | * If early loading microcode is supported, save this mc into | |
906 | * permanent memory. So it will be loaded early when a CPU is hot added | |
907 | * or resumes. | |
908 | */ | |
06b8534c | 909 | save_mc_for_early(new_mc, curr_mc_size); |
9cd4d78e | 910 | |
f58e1f53 JP |
911 | pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n", |
912 | cpu, new_rev, uci->cpu_sig.rev); | |
f61337d9 BP |
913 | |
914 | return UCODE_OK; | |
a30a6a2c SL |
915 | } |
916 | ||
a0a29b62 DA |
917 | static int get_ucode_fw(void *to, const void *from, size_t n) |
918 | { | |
919 | memcpy(to, from, n); | |
920 | return 0; | |
921 | } | |
a30a6a2c | 922 | |
48e30685 BP |
923 | static enum ucode_state request_microcode_fw(int cpu, struct device *device, |
924 | bool refresh_fw) | |
a30a6a2c SL |
925 | { |
926 | char name[30]; | |
92cb7612 | 927 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
a30a6a2c | 928 | const struct firmware *firmware; |
871b72dd | 929 | enum ucode_state ret; |
a30a6a2c | 930 | |
3e135d88 | 931 | sprintf(name, "intel-ucode/%02x-%02x-%02x", |
a30a6a2c | 932 | c->x86, c->x86_model, c->x86_mask); |
871b72dd | 933 | |
75da02b2 | 934 | if (request_firmware_direct(&firmware, name, device)) { |
f58e1f53 | 935 | pr_debug("data file %s load failed\n", name); |
871b72dd | 936 | return UCODE_NFOUND; |
a30a6a2c | 937 | } |
a0a29b62 | 938 | |
dd3feda7 JSR |
939 | ret = generic_load_microcode(cpu, (void *)firmware->data, |
940 | firmware->size, &get_ucode_fw); | |
a0a29b62 | 941 | |
a30a6a2c SL |
942 | release_firmware(firmware); |
943 | ||
a0a29b62 DA |
944 | return ret; |
945 | } | |
946 | ||
947 | static int get_ucode_user(void *to, const void *from, size_t n) | |
948 | { | |
949 | return copy_from_user(to, from, n); | |
950 | } | |
951 | ||
871b72dd DA |
952 | static enum ucode_state |
953 | request_microcode_user(int cpu, const void __user *buf, size_t size) | |
a0a29b62 | 954 | { |
dd3feda7 | 955 | return generic_load_microcode(cpu, (void *)buf, size, &get_ucode_user); |
a30a6a2c SL |
956 | } |
957 | ||
4db646b1 | 958 | static struct microcode_ops microcode_intel_ops = { |
a0a29b62 DA |
959 | .request_microcode_user = request_microcode_user, |
960 | .request_microcode_fw = request_microcode_fw, | |
8d86f390 | 961 | .collect_cpu_info = collect_cpu_info, |
532ed374 | 962 | .apply_microcode = apply_microcode_intel, |
8d86f390 PO |
963 | }; |
964 | ||
18dbc916 | 965 | struct microcode_ops * __init init_intel_microcode(void) |
8d86f390 | 966 | { |
9a2bc335 | 967 | struct cpuinfo_x86 *c = &boot_cpu_data; |
7164b3f5 SB |
968 | |
969 | if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 || | |
970 | cpu_has(c, X86_FEATURE_IA64)) { | |
971 | pr_err("Intel CPU family 0x%x not supported\n", c->x86); | |
972 | return NULL; | |
973 | } | |
974 | ||
18dbc916 | 975 | return µcode_intel_ops; |
8d86f390 | 976 | } |