Commit | Line | Data |
---|---|---|
80cc9f10 PO |
1 | /* |
2 | * AMD CPU Microcode Update Driver for Linux | |
fe055896 BP |
3 | * |
4 | * This driver allows to upgrade microcode on F10h AMD | |
5 | * CPUs and later. | |
6 | * | |
597e11a3 | 7 | * Copyright (C) 2008-2011 Advanced Micro Devices Inc. |
14cfbe55 | 8 | * 2013-2016 Borislav Petkov <bp@alien8.de> |
80cc9f10 PO |
9 | * |
10 | * Author: Peter Oruba <peter.oruba@amd.com> | |
11 | * | |
12 | * Based on work by: | |
cea58224 | 13 | * Tigran Aivazian <aivazian.tigran@gmail.com> |
80cc9f10 | 14 | * |
fe055896 BP |
15 | * early loader: |
16 | * Copyright (C) 2013 Advanced Micro Devices, Inc. | |
17 | * | |
18 | * Author: Jacob Shin <jacob.shin@amd.com> | |
19 | * Fixes: Borislav Petkov <bp@suse.de> | |
80cc9f10 | 20 | * |
2a3282a7 | 21 | * Licensed under the terms of the GNU General Public |
80cc9f10 | 22 | * License version 2. See file COPYING for details. |
4bae1967 | 23 | */ |
6b26e1bf | 24 | #define pr_fmt(fmt) "microcode: " fmt |
f58e1f53 | 25 | |
fe055896 | 26 | #include <linux/earlycpio.h> |
4bae1967 | 27 | #include <linux/firmware.h> |
4bae1967 IM |
28 | #include <linux/uaccess.h> |
29 | #include <linux/vmalloc.h> | |
fe055896 | 30 | #include <linux/initrd.h> |
4bae1967 | 31 | #include <linux/kernel.h> |
80cc9f10 | 32 | #include <linux/pci.h> |
80cc9f10 | 33 | |
fe055896 | 34 | #include <asm/microcode_amd.h> |
80cc9f10 | 35 | #include <asm/microcode.h> |
4bae1967 | 36 | #include <asm/processor.h> |
fe055896 BP |
37 | #include <asm/setup.h> |
38 | #include <asm/cpu.h> | |
4bae1967 | 39 | #include <asm/msr.h> |
80cc9f10 | 40 | |
a0a29b62 | 41 | static struct equiv_cpu_entry *equiv_cpu_table; |
80cc9f10 | 42 | |
fe055896 BP |
43 | /* |
44 | * This points to the current valid container of microcode patches which we will | |
f454177f BP |
45 | * save from the initrd/builtin before jettisoning its contents. @mc is the |
46 | * microcode patch we found to match. | |
fe055896 | 47 | */ |
69f5f983 | 48 | struct cont_desc { |
f454177f | 49 | struct microcode_amd *mc; |
309aac77 | 50 | u32 cpuid_1_eax; |
f454177f | 51 | u32 psize; |
f454177f BP |
52 | u8 *data; |
53 | size_t size; | |
69f5f983 | 54 | }; |
fe055896 BP |
55 | |
56 | static u32 ucode_new_rev; | |
a13004a2 | 57 | static u8 amd_ucode_patch[PATCH_MAX_SIZE]; |
fe055896 | 58 | |
06b8534c BP |
59 | /* |
60 | * Microcode patch container file is prepended to the initrd in cpio | |
1897a969 | 61 | * format. See Documentation/x86/microcode.txt |
06b8534c BP |
62 | */ |
63 | static const char | |
64 | ucode_path[] __maybe_unused = "kernel/x86/microcode/AuthenticAMD.bin"; | |
fe055896 | 65 | |
1f02ac06 | 66 | static u16 find_equiv_id(struct equiv_cpu_entry *equiv_table, u32 sig) |
76bd11c2 | 67 | { |
1f02ac06 BP |
68 | for (; equiv_table && equiv_table->installed_cpu; equiv_table++) { |
69 | if (sig == equiv_table->installed_cpu) | |
70 | return equiv_table->equiv_cpu; | |
76bd11c2 | 71 | } |
1f02ac06 | 72 | |
76bd11c2 BP |
73 | return 0; |
74 | } | |
75 | ||
fe055896 | 76 | /* |
06b8534c | 77 | * This scans the ucode blob for the proper container as we can have multiple |
8feaa64a BP |
78 | * containers glued together. Returns the equivalence ID from the equivalence |
79 | * table or 0 if none found. | |
8801b3fc BP |
80 | * Returns the amount of bytes consumed while scanning. @desc contains all the |
81 | * data we're going to use in later stages of the application. | |
fe055896 | 82 | */ |
8801b3fc | 83 | static ssize_t parse_container(u8 *ucode, ssize_t size, struct cont_desc *desc) |
fe055896 BP |
84 | { |
85 | struct equiv_cpu_entry *eq; | |
8801b3fc BP |
86 | ssize_t orig_size = size; |
87 | u32 *hdr = (u32 *)ucode; | |
8801b3fc BP |
88 | u16 eq_id; |
89 | u8 *buf; | |
90 | ||
91 | /* Am I looking at an equivalence table header? */ | |
92 | if (hdr[0] != UCODE_MAGIC || | |
93 | hdr[1] != UCODE_EQUIV_CPU_TABLE_TYPE || | |
da0aa3dd | 94 | hdr[2] == 0) |
8801b3fc | 95 | return CONTAINER_HDR_SZ; |
fe055896 | 96 | |
8801b3fc | 97 | buf = ucode; |
06b8534c | 98 | |
8801b3fc | 99 | eq = (struct equiv_cpu_entry *)(buf + CONTAINER_HDR_SZ); |
fe055896 | 100 | |
8801b3fc | 101 | /* Find the equivalence ID of our CPU in this table: */ |
309aac77 | 102 | eq_id = find_equiv_id(eq, desc->cpuid_1_eax); |
fe055896 | 103 | |
8801b3fc BP |
104 | buf += hdr[2] + CONTAINER_HDR_SZ; |
105 | size -= hdr[2] + CONTAINER_HDR_SZ; | |
fe055896 | 106 | |
8801b3fc BP |
107 | /* |
108 | * Scan through the rest of the container to find where it ends. We do | |
109 | * some basic sanity-checking too. | |
110 | */ | |
111 | while (size > 0) { | |
112 | struct microcode_amd *mc; | |
113 | u32 patch_size; | |
fe055896 | 114 | |
8801b3fc | 115 | hdr = (u32 *)buf; |
8feaa64a | 116 | |
8801b3fc BP |
117 | if (hdr[0] != UCODE_UCODE_TYPE) |
118 | break; | |
fe055896 | 119 | |
8801b3fc BP |
120 | /* Sanity-check patch size. */ |
121 | patch_size = hdr[1]; | |
122 | if (patch_size > PATCH_MAX_SIZE) | |
123 | break; | |
06b8534c | 124 | |
8801b3fc BP |
125 | /* Skip patch section header: */ |
126 | buf += SECTION_HDR_SIZE; | |
127 | size -= SECTION_HDR_SIZE; | |
fe055896 | 128 | |
8801b3fc BP |
129 | mc = (struct microcode_amd *)buf; |
130 | if (eq_id == mc->hdr.processor_rev_id) { | |
131 | desc->psize = patch_size; | |
132 | desc->mc = mc; | |
fe055896 BP |
133 | } |
134 | ||
8801b3fc BP |
135 | buf += patch_size; |
136 | size -= patch_size; | |
fe055896 BP |
137 | } |
138 | ||
8801b3fc BP |
139 | /* |
140 | * If we have found a patch (desc->mc), it means we're looking at the | |
141 | * container which has a patch for this CPU so return 0 to mean, @ucode | |
142 | * already points to the proper container. Otherwise, we return the size | |
143 | * we scanned so that we can advance to the next container in the | |
144 | * buffer. | |
145 | */ | |
146 | if (desc->mc) { | |
da0aa3dd BP |
147 | desc->data = ucode; |
148 | desc->size = orig_size - size; | |
8801b3fc BP |
149 | |
150 | return 0; | |
151 | } | |
152 | ||
153 | return orig_size - size; | |
154 | } | |
155 | ||
156 | /* | |
157 | * Scan the ucode blob for the proper container as we can have multiple | |
158 | * containers glued together. | |
159 | */ | |
160 | static void scan_containers(u8 *ucode, size_t size, struct cont_desc *desc) | |
161 | { | |
162 | ssize_t rem = size; | |
163 | ||
164 | while (rem >= 0) { | |
165 | ssize_t s = parse_container(ucode, rem, desc); | |
166 | if (!s) | |
167 | return; | |
168 | ||
169 | ucode += s; | |
170 | rem -= s; | |
171 | } | |
06b8534c BP |
172 | } |
173 | ||
ef901dc3 | 174 | static int __apply_microcode_amd(struct microcode_amd *mc) |
06b8534c BP |
175 | { |
176 | u32 rev, dummy; | |
177 | ||
ef901dc3 | 178 | native_wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc->hdr.data_code); |
06b8534c BP |
179 | |
180 | /* verify patch application was successful */ | |
181 | native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); | |
ef901dc3 | 182 | if (rev != mc->hdr.patch_id) |
06b8534c BP |
183 | return -1; |
184 | ||
185 | return 0; | |
186 | } | |
187 | ||
188 | /* | |
189 | * Early load occurs before we can vmalloc(). So we look for the microcode | |
190 | * patch container file in initrd, traverse equivalent cpu table, look for a | |
191 | * matching microcode patch, and update, all in initrd memory in place. | |
192 | * When vmalloc() is available for use later -- on 64-bit during first AP load, | |
193 | * and on 32-bit during save_microcode_in_initrd_amd() -- we can call | |
194 | * load_microcode_amd() to save equivalent cpu table and microcode patches in | |
195 | * kernel heap memory. | |
200d3553 | 196 | * |
8801b3fc | 197 | * Returns true if container found (sets @desc), false otherwise. |
06b8534c | 198 | */ |
309aac77 | 199 | static bool |
69f5f983 | 200 | apply_microcode_early_amd(u32 cpuid_1_eax, void *ucode, size_t size, bool save_patch) |
06b8534c | 201 | { |
8801b3fc | 202 | struct cont_desc desc = { 0 }; |
06b8534c | 203 | u8 (*patch)[PATCH_MAX_SIZE]; |
8801b3fc | 204 | struct microcode_amd *mc; |
f3ad136d | 205 | u32 rev, dummy, *new_rev; |
8801b3fc | 206 | bool ret = false; |
06b8534c BP |
207 | |
208 | #ifdef CONFIG_X86_32 | |
209 | new_rev = (u32 *)__pa_nodebug(&ucode_new_rev); | |
210 | patch = (u8 (*)[PATCH_MAX_SIZE])__pa_nodebug(&amd_ucode_patch); | |
211 | #else | |
212 | new_rev = &ucode_new_rev; | |
213 | patch = &amd_ucode_patch; | |
214 | #endif | |
fe055896 | 215 | |
309aac77 BP |
216 | desc.cpuid_1_eax = cpuid_1_eax; |
217 | ||
8801b3fc | 218 | scan_containers(ucode, size, &desc); |
06b8534c | 219 | |
8801b3fc BP |
220 | mc = desc.mc; |
221 | if (!mc) | |
222 | return ret; | |
fe055896 | 223 | |
f3ad136d | 224 | native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); |
8801b3fc BP |
225 | if (rev >= mc->hdr.patch_id) |
226 | return ret; | |
fe055896 | 227 | |
8801b3fc BP |
228 | if (!__apply_microcode_amd(mc)) { |
229 | *new_rev = mc->hdr.patch_id; | |
230 | ret = true; | |
fe055896 | 231 | |
8801b3fc BP |
232 | if (save_patch) |
233 | memcpy(patch, mc, min_t(u32, desc.psize, PATCH_MAX_SIZE)); | |
fe055896 | 234 | } |
200d3553 | 235 | |
8801b3fc | 236 | return ret; |
fe055896 BP |
237 | } |
238 | ||
06b8534c | 239 | static bool get_builtin_microcode(struct cpio_data *cp, unsigned int family) |
fe055896 BP |
240 | { |
241 | #ifdef CONFIG_X86_64 | |
242 | char fw_name[36] = "amd-ucode/microcode_amd.bin"; | |
243 | ||
244 | if (family >= 0x15) | |
245 | snprintf(fw_name, sizeof(fw_name), | |
246 | "amd-ucode/microcode_amd_fam%.2xh.bin", family); | |
247 | ||
248 | return get_builtin_firmware(cp, fw_name); | |
249 | #else | |
250 | return false; | |
251 | #endif | |
252 | } | |
253 | ||
d7f7dc7b | 254 | static void __load_ucode_amd(unsigned int cpuid_1_eax, struct cpio_data *ret) |
fe055896 | 255 | { |
06b8534c | 256 | struct ucode_cpu_info *uci; |
fe055896 | 257 | struct cpio_data cp; |
06b8534c BP |
258 | const char *path; |
259 | bool use_pa; | |
fe055896 | 260 | |
06b8534c BP |
261 | if (IS_ENABLED(CONFIG_X86_32)) { |
262 | uci = (struct ucode_cpu_info *)__pa_nodebug(ucode_cpu_info); | |
263 | path = (const char *)__pa_nodebug(ucode_path); | |
264 | use_pa = true; | |
265 | } else { | |
266 | uci = ucode_cpu_info; | |
267 | path = ucode_path; | |
268 | use_pa = false; | |
269 | } | |
fe055896 | 270 | |
309aac77 | 271 | if (!get_builtin_microcode(&cp, x86_family(cpuid_1_eax))) |
06b8534c | 272 | cp = find_microcode_in_initrd(path, use_pa); |
6c545647 | 273 | |
309aac77 BP |
274 | /* Needed in load_microcode_amd() */ |
275 | uci->cpu_sig.sig = cpuid_1_eax; | |
fe055896 | 276 | |
e71bb4ec | 277 | *ret = cp; |
fe055896 BP |
278 | } |
279 | ||
e71bb4ec | 280 | void __init load_ucode_amd_bsp(unsigned int cpuid_1_eax) |
fe055896 | 281 | { |
e71bb4ec | 282 | struct cpio_data cp = { }; |
fe055896 | 283 | |
e71bb4ec | 284 | __load_ucode_amd(cpuid_1_eax, &cp); |
06b8534c | 285 | if (!(cp.data && cp.size)) |
fe055896 BP |
286 | return; |
287 | ||
69f5f983 | 288 | apply_microcode_early_amd(cpuid_1_eax, cp.data, cp.size, true); |
fe055896 | 289 | } |
e71bb4ec | 290 | |
309aac77 | 291 | void load_ucode_amd_ap(unsigned int cpuid_1_eax) |
fe055896 | 292 | { |
fe055896 | 293 | struct microcode_amd *mc; |
69f5f983 BP |
294 | struct cpio_data cp; |
295 | u32 *new_rev, rev, dummy; | |
fe055896 | 296 | |
e71bb4ec | 297 | if (IS_ENABLED(CONFIG_X86_32)) { |
69f5f983 BP |
298 | mc = (struct microcode_amd *)__pa_nodebug(amd_ucode_patch); |
299 | new_rev = (u32 *)__pa_nodebug(&ucode_new_rev); | |
e71bb4ec | 300 | } else { |
69f5f983 BP |
301 | mc = (struct microcode_amd *)amd_ucode_patch; |
302 | new_rev = &ucode_new_rev; | |
e71bb4ec BP |
303 | } |
304 | ||
69f5f983 | 305 | native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); |
06b8534c | 306 | |
69f5f983 BP |
307 | /* Check whether we have saved a new patch already: */ |
308 | if (*new_rev && rev < mc->hdr.patch_id) { | |
309 | if (!__apply_microcode_amd(mc)) { | |
310 | *new_rev = mc->hdr.patch_id; | |
06b8534c BP |
311 | return; |
312 | } | |
313 | } | |
88b2f634 | 314 | |
69f5f983 BP |
315 | __load_ucode_amd(cpuid_1_eax, &cp); |
316 | if (!(cp.data && cp.size)) | |
fe055896 BP |
317 | return; |
318 | ||
69f5f983 | 319 | apply_microcode_early_amd(cpuid_1_eax, cp.data, cp.size, false); |
fe055896 | 320 | } |
fe055896 | 321 | |
76bd11c2 | 322 | static enum ucode_state |
dac6ca24 | 323 | load_microcode_amd(bool save, u8 family, const u8 *data, size_t size); |
76bd11c2 | 324 | |
309aac77 | 325 | int __init save_microcode_in_initrd_amd(unsigned int cpuid_1_eax) |
fe055896 | 326 | { |
72edfe95 | 327 | struct cont_desc desc = { 0 }; |
fe055896 | 328 | enum ucode_state ret; |
72edfe95 | 329 | struct cpio_data cp; |
fe055896 | 330 | |
72edfe95 BP |
331 | cp = find_microcode_in_initrd(ucode_path, false); |
332 | if (!(cp.data && cp.size)) | |
333 | return -EINVAL; | |
309aac77 | 334 | |
72edfe95 | 335 | desc.cpuid_1_eax = cpuid_1_eax; |
88b2f634 | 336 | |
72edfe95 | 337 | scan_containers(cp.data, cp.size, &desc); |
da0aa3dd | 338 | if (!desc.mc) |
72edfe95 | 339 | return -EINVAL; |
fe055896 | 340 | |
dac6ca24 | 341 | ret = load_microcode_amd(true, x86_family(cpuid_1_eax), desc.data, desc.size); |
2613f36e | 342 | if (ret > UCODE_UPDATED) |
72edfe95 | 343 | return -EINVAL; |
fe055896 | 344 | |
72edfe95 | 345 | return 0; |
fe055896 BP |
346 | } |
347 | ||
348 | void reload_ucode_amd(void) | |
349 | { | |
350 | struct microcode_amd *mc; | |
f3ad136d | 351 | u32 rev, dummy; |
fe055896 BP |
352 | |
353 | mc = (struct microcode_amd *)amd_ucode_patch; | |
354 | ||
f3ad136d BP |
355 | rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); |
356 | ||
06b8534c | 357 | if (rev < mc->hdr.patch_id) { |
fe055896 BP |
358 | if (!__apply_microcode_amd(mc)) { |
359 | ucode_new_rev = mc->hdr.patch_id; | |
a58017c6 | 360 | pr_info("reload patch_level=0x%08x\n", ucode_new_rev); |
fe055896 BP |
361 | } |
362 | } | |
363 | } | |
a76096a6 | 364 | static u16 __find_equiv_id(unsigned int cpu) |
c96d2c09 BP |
365 | { |
366 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; | |
a76096a6 | 367 | return find_equiv_id(equiv_cpu_table, uci->cpu_sig.sig); |
c96d2c09 BP |
368 | } |
369 | ||
370 | static u32 find_cpu_family_by_equiv_cpu(u16 equiv_cpu) | |
371 | { | |
372 | int i = 0; | |
373 | ||
374 | BUG_ON(!equiv_cpu_table); | |
375 | ||
376 | while (equiv_cpu_table[i].equiv_cpu != 0) { | |
377 | if (equiv_cpu == equiv_cpu_table[i].equiv_cpu) | |
378 | return equiv_cpu_table[i].installed_cpu; | |
379 | i++; | |
380 | } | |
381 | return 0; | |
382 | } | |
383 | ||
a3eb3b4d BP |
384 | /* |
385 | * a small, trivial cache of per-family ucode patches | |
386 | */ | |
387 | static struct ucode_patch *cache_find_patch(u16 equiv_cpu) | |
388 | { | |
389 | struct ucode_patch *p; | |
390 | ||
058dc498 | 391 | list_for_each_entry(p, µcode_cache, plist) |
a3eb3b4d BP |
392 | if (p->equiv_cpu == equiv_cpu) |
393 | return p; | |
394 | return NULL; | |
395 | } | |
396 | ||
397 | static void update_cache(struct ucode_patch *new_patch) | |
398 | { | |
399 | struct ucode_patch *p; | |
400 | ||
058dc498 | 401 | list_for_each_entry(p, µcode_cache, plist) { |
a3eb3b4d | 402 | if (p->equiv_cpu == new_patch->equiv_cpu) { |
a99f0342 | 403 | if (p->patch_id >= new_patch->patch_id) { |
a3eb3b4d | 404 | /* we already have the latest patch */ |
a99f0342 SW |
405 | kfree(new_patch->data); |
406 | kfree(new_patch); | |
a3eb3b4d | 407 | return; |
a99f0342 | 408 | } |
a3eb3b4d BP |
409 | |
410 | list_replace(&p->plist, &new_patch->plist); | |
411 | kfree(p->data); | |
412 | kfree(p); | |
413 | return; | |
414 | } | |
415 | } | |
416 | /* no patch found, add it */ | |
058dc498 | 417 | list_add_tail(&new_patch->plist, µcode_cache); |
a3eb3b4d BP |
418 | } |
419 | ||
420 | static void free_cache(void) | |
421 | { | |
2d297480 | 422 | struct ucode_patch *p, *tmp; |
a3eb3b4d | 423 | |
058dc498 | 424 | list_for_each_entry_safe(p, tmp, µcode_cache, plist) { |
a3eb3b4d BP |
425 | __list_del(p->plist.prev, p->plist.next); |
426 | kfree(p->data); | |
427 | kfree(p); | |
428 | } | |
429 | } | |
430 | ||
431 | static struct ucode_patch *find_patch(unsigned int cpu) | |
432 | { | |
433 | u16 equiv_id; | |
434 | ||
a76096a6 | 435 | equiv_id = __find_equiv_id(cpu); |
a3eb3b4d BP |
436 | if (!equiv_id) |
437 | return NULL; | |
438 | ||
439 | return cache_find_patch(equiv_id); | |
440 | } | |
441 | ||
d45de409 | 442 | static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig) |
80cc9f10 | 443 | { |
3b2e3d85 | 444 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
757885e9 JS |
445 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; |
446 | struct ucode_patch *p; | |
80cc9f10 | 447 | |
5f5b7472 | 448 | csig->sig = cpuid_eax(0x00000001); |
bcb80e53 | 449 | csig->rev = c->microcode; |
757885e9 JS |
450 | |
451 | /* | |
452 | * a patch could have been loaded early, set uci->mc so that | |
453 | * mc_bp_resume() can call apply_microcode() | |
454 | */ | |
455 | p = find_patch(cpu); | |
456 | if (p && (p->patch_id == csig->rev)) | |
457 | uci->mc = p->data; | |
458 | ||
258721ef BP |
459 | pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev); |
460 | ||
d45de409 | 461 | return 0; |
80cc9f10 PO |
462 | } |
463 | ||
84516098 | 464 | static unsigned int verify_patch_size(u8 family, u32 patch_size, |
be62adb4 | 465 | unsigned int size) |
80cc9f10 | 466 | { |
be62adb4 BP |
467 | u32 max_size; |
468 | ||
469 | #define F1XH_MPB_MAX_SIZE 2048 | |
470 | #define F14H_MPB_MAX_SIZE 1824 | |
471 | #define F15H_MPB_MAX_SIZE 4096 | |
36c46ca4 | 472 | #define F16H_MPB_MAX_SIZE 3458 |
f4e9b7af | 473 | #define F17H_MPB_MAX_SIZE 3200 |
be62adb4 | 474 | |
84516098 | 475 | switch (family) { |
be62adb4 BP |
476 | case 0x14: |
477 | max_size = F14H_MPB_MAX_SIZE; | |
478 | break; | |
479 | case 0x15: | |
480 | max_size = F15H_MPB_MAX_SIZE; | |
481 | break; | |
36c46ca4 BO |
482 | case 0x16: |
483 | max_size = F16H_MPB_MAX_SIZE; | |
484 | break; | |
f4e9b7af TL |
485 | case 0x17: |
486 | max_size = F17H_MPB_MAX_SIZE; | |
487 | break; | |
be62adb4 BP |
488 | default: |
489 | max_size = F1XH_MPB_MAX_SIZE; | |
490 | break; | |
491 | } | |
492 | ||
493 | if (patch_size > min_t(u32, size, max_size)) { | |
494 | pr_err("patch size mismatch\n"); | |
495 | return 0; | |
496 | } | |
497 | ||
498 | return patch_size; | |
499 | } | |
500 | ||
3f1f576a | 501 | static enum ucode_state apply_microcode_amd(int cpu) |
80cc9f10 | 502 | { |
bcb80e53 | 503 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
2efb05e8 BP |
504 | struct microcode_amd *mc_amd; |
505 | struct ucode_cpu_info *uci; | |
506 | struct ucode_patch *p; | |
8da38eba | 507 | enum ucode_state ret; |
f3ad136d | 508 | u32 rev, dummy; |
2efb05e8 BP |
509 | |
510 | BUG_ON(raw_smp_processor_id() != cpu); | |
80cc9f10 | 511 | |
2efb05e8 | 512 | uci = ucode_cpu_info + cpu; |
80cc9f10 | 513 | |
2efb05e8 BP |
514 | p = find_patch(cpu); |
515 | if (!p) | |
3f1f576a | 516 | return UCODE_NFOUND; |
80cc9f10 | 517 | |
2efb05e8 BP |
518 | mc_amd = p->data; |
519 | uci->mc = p->data; | |
520 | ||
f3ad136d | 521 | rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); |
80cc9f10 | 522 | |
685ca6d7 BP |
523 | /* need to apply patch? */ |
524 | if (rev >= mc_amd->hdr.patch_id) { | |
8da38eba FS |
525 | ret = UCODE_OK; |
526 | goto out; | |
685ca6d7 BP |
527 | } |
528 | ||
d982057f | 529 | if (__apply_microcode_amd(mc_amd)) { |
258721ef | 530 | pr_err("CPU%d: update failed for patch_level=0x%08x\n", |
a76096a6 | 531 | cpu, mc_amd->hdr.patch_id); |
3f1f576a | 532 | return UCODE_ERROR; |
d982057f | 533 | } |
80cc9f10 | 534 | |
8da38eba FS |
535 | rev = mc_amd->hdr.patch_id; |
536 | ret = UCODE_UPDATED; | |
537 | ||
538 | pr_info("CPU%d: new patch_level=0x%08x\n", cpu, rev); | |
539 | ||
540 | out: | |
541 | uci->cpu_sig.rev = rev; | |
542 | c->microcode = rev; | |
871b72dd | 543 | |
370a132b PB |
544 | /* Update boot_cpu_data's revision too, if we're on the BSP: */ |
545 | if (c->cpu_index == boot_cpu_data.cpu_index) | |
8da38eba | 546 | boot_cpu_data.microcode = rev; |
370a132b | 547 | |
8da38eba | 548 | return ret; |
80cc9f10 PO |
549 | } |
550 | ||
0657d9eb | 551 | static int install_equiv_cpu_table(const u8 *buf) |
80cc9f10 | 552 | { |
10de52d6 BP |
553 | unsigned int *ibuf = (unsigned int *)buf; |
554 | unsigned int type = ibuf[1]; | |
555 | unsigned int size = ibuf[2]; | |
80cc9f10 | 556 | |
10de52d6 | 557 | if (type != UCODE_EQUIV_CPU_TABLE_TYPE || !size) { |
258721ef BP |
558 | pr_err("empty section/" |
559 | "invalid type field in container file section header\n"); | |
10de52d6 | 560 | return -EINVAL; |
80cc9f10 PO |
561 | } |
562 | ||
8e5e9521 | 563 | equiv_cpu_table = vmalloc(size); |
80cc9f10 | 564 | if (!equiv_cpu_table) { |
f58e1f53 | 565 | pr_err("failed to allocate equivalent CPU table\n"); |
10de52d6 | 566 | return -ENOMEM; |
80cc9f10 PO |
567 | } |
568 | ||
e7e632f5 | 569 | memcpy(equiv_cpu_table, buf + CONTAINER_HDR_SZ, size); |
80cc9f10 | 570 | |
40b7f3df BP |
571 | /* add header length */ |
572 | return size + CONTAINER_HDR_SZ; | |
80cc9f10 PO |
573 | } |
574 | ||
a0a29b62 | 575 | static void free_equiv_cpu_table(void) |
80cc9f10 | 576 | { |
aeef50bc F |
577 | vfree(equiv_cpu_table); |
578 | equiv_cpu_table = NULL; | |
a0a29b62 | 579 | } |
80cc9f10 | 580 | |
2efb05e8 | 581 | static void cleanup(void) |
a0a29b62 | 582 | { |
2efb05e8 BP |
583 | free_equiv_cpu_table(); |
584 | free_cache(); | |
585 | } | |
586 | ||
587 | /* | |
588 | * We return the current size even if some of the checks failed so that | |
589 | * we can skip over the next patch. If we return a negative value, we | |
590 | * signal a grave error like a memory allocation has failed and the | |
591 | * driver cannot continue functioning normally. In such cases, we tear | |
592 | * down everything we've used up so far and exit. | |
593 | */ | |
84516098 | 594 | static int verify_and_add_patch(u8 family, u8 *fw, unsigned int leftover) |
2efb05e8 | 595 | { |
2efb05e8 BP |
596 | struct microcode_header_amd *mc_hdr; |
597 | struct ucode_patch *patch; | |
598 | unsigned int patch_size, crnt_size, ret; | |
599 | u32 proc_fam; | |
600 | u16 proc_id; | |
601 | ||
602 | patch_size = *(u32 *)(fw + 4); | |
603 | crnt_size = patch_size + SECTION_HDR_SIZE; | |
604 | mc_hdr = (struct microcode_header_amd *)(fw + SECTION_HDR_SIZE); | |
605 | proc_id = mc_hdr->processor_rev_id; | |
606 | ||
607 | proc_fam = find_cpu_family_by_equiv_cpu(proc_id); | |
608 | if (!proc_fam) { | |
609 | pr_err("No patch family for equiv ID: 0x%04x\n", proc_id); | |
610 | return crnt_size; | |
611 | } | |
612 | ||
613 | /* check if patch is for the current family */ | |
614 | proc_fam = ((proc_fam >> 8) & 0xf) + ((proc_fam >> 20) & 0xff); | |
84516098 | 615 | if (proc_fam != family) |
2efb05e8 BP |
616 | return crnt_size; |
617 | ||
618 | if (mc_hdr->nb_dev_id || mc_hdr->sb_dev_id) { | |
619 | pr_err("Patch-ID 0x%08x: chipset-specific code unsupported.\n", | |
620 | mc_hdr->patch_id); | |
621 | return crnt_size; | |
622 | } | |
623 | ||
84516098 | 624 | ret = verify_patch_size(family, patch_size, leftover); |
2efb05e8 BP |
625 | if (!ret) { |
626 | pr_err("Patch-ID 0x%08x: size mismatch.\n", mc_hdr->patch_id); | |
627 | return crnt_size; | |
628 | } | |
629 | ||
630 | patch = kzalloc(sizeof(*patch), GFP_KERNEL); | |
631 | if (!patch) { | |
632 | pr_err("Patch allocation failure.\n"); | |
633 | return -EINVAL; | |
634 | } | |
635 | ||
9cc6f743 | 636 | patch->data = kmemdup(fw + SECTION_HDR_SIZE, patch_size, GFP_KERNEL); |
2efb05e8 BP |
637 | if (!patch->data) { |
638 | pr_err("Patch data allocation failure.\n"); | |
639 | kfree(patch); | |
640 | return -EINVAL; | |
641 | } | |
642 | ||
2efb05e8 BP |
643 | INIT_LIST_HEAD(&patch->plist); |
644 | patch->patch_id = mc_hdr->patch_id; | |
645 | patch->equiv_cpu = proc_id; | |
646 | ||
5335ba5c BP |
647 | pr_debug("%s: Added patch_id: 0x%08x, proc_id: 0x%04x\n", |
648 | __func__, patch->patch_id, proc_id); | |
649 | ||
2efb05e8 BP |
650 | /* ... and add to cache. */ |
651 | update_cache(patch); | |
652 | ||
653 | return crnt_size; | |
654 | } | |
655 | ||
84516098 TK |
656 | static enum ucode_state __load_microcode_amd(u8 family, const u8 *data, |
657 | size_t size) | |
2efb05e8 BP |
658 | { |
659 | enum ucode_state ret = UCODE_ERROR; | |
660 | unsigned int leftover; | |
661 | u8 *fw = (u8 *)data; | |
662 | int crnt_size = 0; | |
1396fa9c | 663 | int offset; |
80cc9f10 | 664 | |
2efb05e8 | 665 | offset = install_equiv_cpu_table(data); |
10de52d6 | 666 | if (offset < 0) { |
f58e1f53 | 667 | pr_err("failed to create equivalent cpu table\n"); |
2efb05e8 | 668 | return ret; |
80cc9f10 | 669 | } |
2efb05e8 | 670 | fw += offset; |
a0a29b62 DA |
671 | leftover = size - offset; |
672 | ||
2efb05e8 | 673 | if (*(u32 *)fw != UCODE_UCODE_TYPE) { |
be62adb4 | 674 | pr_err("invalid type field in container file section header\n"); |
2efb05e8 BP |
675 | free_equiv_cpu_table(); |
676 | return ret; | |
be62adb4 | 677 | } |
a0a29b62 | 678 | |
be62adb4 | 679 | while (leftover) { |
84516098 | 680 | crnt_size = verify_and_add_patch(family, fw, leftover); |
2efb05e8 BP |
681 | if (crnt_size < 0) |
682 | return ret; | |
d733689a | 683 | |
2efb05e8 BP |
684 | fw += crnt_size; |
685 | leftover -= crnt_size; | |
80cc9f10 | 686 | } |
a0a29b62 | 687 | |
2efb05e8 | 688 | return UCODE_OK; |
a0a29b62 DA |
689 | } |
690 | ||
76bd11c2 | 691 | static enum ucode_state |
dac6ca24 | 692 | load_microcode_amd(bool save, u8 family, const u8 *data, size_t size) |
a76096a6 | 693 | { |
2613f36e | 694 | struct ucode_patch *p; |
a76096a6 JS |
695 | enum ucode_state ret; |
696 | ||
697 | /* free old equiv table */ | |
698 | free_equiv_cpu_table(); | |
699 | ||
84516098 | 700 | ret = __load_microcode_amd(family, data, size); |
2613f36e | 701 | if (ret != UCODE_OK) { |
a76096a6 | 702 | cleanup(); |
2613f36e BP |
703 | return ret; |
704 | } | |
a76096a6 | 705 | |
2613f36e BP |
706 | p = find_patch(0); |
707 | if (!p) { | |
708 | return ret; | |
709 | } else { | |
710 | if (boot_cpu_data.microcode == p->patch_id) | |
711 | return ret; | |
712 | ||
713 | ret = UCODE_NEW; | |
757885e9 | 714 | } |
2613f36e BP |
715 | |
716 | /* save BSP's matching patch for early load */ | |
717 | if (!save) | |
718 | return ret; | |
719 | ||
720 | memset(amd_ucode_patch, 0, PATCH_MAX_SIZE); | |
721 | memcpy(amd_ucode_patch, p->data, min_t(u32, ksize(p->data), PATCH_MAX_SIZE)); | |
722 | ||
a76096a6 JS |
723 | return ret; |
724 | } | |
725 | ||
5b68edc9 AH |
726 | /* |
727 | * AMD microcode firmware naming convention, up to family 15h they are in | |
728 | * the legacy file: | |
729 | * | |
730 | * amd-ucode/microcode_amd.bin | |
731 | * | |
732 | * This legacy file is always smaller than 2K in size. | |
733 | * | |
2efb05e8 | 734 | * Beginning with family 15h, they are in family-specific firmware files: |
5b68edc9 AH |
735 | * |
736 | * amd-ucode/microcode_amd_fam15h.bin | |
737 | * amd-ucode/microcode_amd_fam16h.bin | |
738 | * ... | |
739 | * | |
740 | * These might be larger than 2K. | |
741 | */ | |
48e30685 BP |
742 | static enum ucode_state request_microcode_amd(int cpu, struct device *device, |
743 | bool refresh_fw) | |
a0a29b62 | 744 | { |
5b68edc9 | 745 | char fw_name[36] = "amd-ucode/microcode_amd.bin"; |
5b68edc9 | 746 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
dac6ca24 | 747 | bool bsp = c->cpu_index == boot_cpu_data.cpu_index; |
2efb05e8 BP |
748 | enum ucode_state ret = UCODE_NFOUND; |
749 | const struct firmware *fw; | |
750 | ||
751 | /* reload ucode container only on the boot cpu */ | |
dac6ca24 | 752 | if (!refresh_fw || !bsp) |
2efb05e8 | 753 | return UCODE_OK; |
5b68edc9 AH |
754 | |
755 | if (c->x86 >= 0x15) | |
756 | snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86); | |
a0a29b62 | 757 | |
75da02b2 | 758 | if (request_firmware_direct(&fw, (const char *)fw_name, device)) { |
11f918d3 | 759 | pr_debug("failed to load file %s\n", fw_name); |
ffc7e8ac | 760 | goto out; |
3b2e3d85 | 761 | } |
a0a29b62 | 762 | |
ffc7e8ac BP |
763 | ret = UCODE_ERROR; |
764 | if (*(u32 *)fw->data != UCODE_MAGIC) { | |
258721ef | 765 | pr_err("invalid magic value (0x%08x)\n", *(u32 *)fw->data); |
ffc7e8ac | 766 | goto fw_release; |
506f90ee BP |
767 | } |
768 | ||
dac6ca24 | 769 | ret = load_microcode_amd(bsp, c->x86, fw->data, fw->size); |
a0a29b62 | 770 | |
2efb05e8 | 771 | fw_release: |
ffc7e8ac | 772 | release_firmware(fw); |
3b2e3d85 | 773 | |
2efb05e8 | 774 | out: |
a0a29b62 DA |
775 | return ret; |
776 | } | |
777 | ||
871b72dd DA |
778 | static enum ucode_state |
779 | request_microcode_user(int cpu, const void __user *buf, size_t size) | |
a0a29b62 | 780 | { |
871b72dd | 781 | return UCODE_ERROR; |
80cc9f10 PO |
782 | } |
783 | ||
80cc9f10 PO |
784 | static void microcode_fini_cpu_amd(int cpu) |
785 | { | |
786 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; | |
787 | ||
18dbc916 | 788 | uci->mc = NULL; |
80cc9f10 PO |
789 | } |
790 | ||
791 | static struct microcode_ops microcode_amd_ops = { | |
a0a29b62 | 792 | .request_microcode_user = request_microcode_user, |
ffc7e8ac | 793 | .request_microcode_fw = request_microcode_amd, |
80cc9f10 PO |
794 | .collect_cpu_info = collect_cpu_info_amd, |
795 | .apply_microcode = apply_microcode_amd, | |
796 | .microcode_fini_cpu = microcode_fini_cpu_amd, | |
797 | }; | |
798 | ||
18dbc916 | 799 | struct microcode_ops * __init init_amd_microcode(void) |
80cc9f10 | 800 | { |
9a2bc335 | 801 | struct cpuinfo_x86 *c = &boot_cpu_data; |
283c1f25 AH |
802 | |
803 | if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) { | |
1b74dde7 | 804 | pr_warn("AMD CPU family 0x%x not supported\n", c->x86); |
283c1f25 AH |
805 | return NULL; |
806 | } | |
807 | ||
f7eb59dd BP |
808 | if (ucode_new_rev) |
809 | pr_info_once("microcode updated early to new patch_level=0x%08x\n", | |
810 | ucode_new_rev); | |
811 | ||
18dbc916 | 812 | return µcode_amd_ops; |
80cc9f10 | 813 | } |
f72c1a57 BP |
814 | |
815 | void __exit exit_amd_microcode(void) | |
816 | { | |
2efb05e8 | 817 | cleanup(); |
f72c1a57 | 818 | } |