[linux-2.6-block.git] / arch / x86 / kernel / cpu / mcheck / therm_throt.c

/*
 * Thermal throttle event support code (such as syslog messaging and rate
 * limiting) that was factored out from x86_64 (mce_intel.c) and i386 (p4.c).
 *
 * This allows consistent reporting of CPU thermal throttle events.
 *
 * Maintains a counter in /sys that keeps track of the number of thermal
 * events, such that the user knows how bad the thermal problem might be
 * (since the logging to syslog and mcelog is rate limited).
 *
 * Author: Dmitriy Zavin (dmitriyz@google.com)
 *
 * Credits: Adapted from Zwane Mwaikambo's original code in mce_intel.c.
 *          Inspired by Ross Biro's and Al Borchers' counter code.
 */
#include <linux/interrupt.h>
#include <linux/notifier.h>
#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/percpu.h>
#include <linux/export.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/smp.h>
#include <linux/cpu.h>

#include <asm/processor.h>
#include <asm/apic.h>
#include <asm/idle.h>
#include <asm/mce.h>
#include <asm/msr.h>
#include <asm/trace/irq_vectors.h>

/* How long to wait between reporting thermal events */
#define CHECK_INTERVAL		(300 * HZ)

#define THERMAL_THROTTLING_EVENT	0
#define POWER_LIMIT_EVENT		1

/*
 * Current thermal event state:
 */
struct _thermal_state {
	bool			new_event;
	int			event;
	u64			next_check;
	unsigned long		count;
	unsigned long		last_count;
};

struct thermal_state {
	struct _thermal_state core_throttle;
	struct _thermal_state core_power_limit;
	struct _thermal_state package_throttle;
	struct _thermal_state package_power_limit;
	struct _thermal_state core_thresh0;
	struct _thermal_state core_thresh1;
	struct _thermal_state pkg_thresh0;
	struct _thermal_state pkg_thresh1;
};

/* Callback to handle core threshold interrupts */
int (*platform_thermal_notify)(__u64 msr_val);
EXPORT_SYMBOL(platform_thermal_notify);

/* Callback to handle core package threshold_interrupts */
int (*platform_thermal_package_notify)(__u64 msr_val);
EXPORT_SYMBOL_GPL(platform_thermal_package_notify);

/* Callback support of rate control, return true, if
 * callback has rate control */
bool (*platform_thermal_package_rate_control)(void);
EXPORT_SYMBOL_GPL(platform_thermal_package_rate_control);


static DEFINE_PER_CPU(struct thermal_state, thermal_state);

static atomic_t therm_throt_en	= ATOMIC_INIT(0);

static u32 lvtthmr_init __read_mostly;

#ifdef CONFIG_SYSFS
#define define_therm_throt_device_one_ro(_name)				\
	static DEVICE_ATTR(_name, 0444,					\
			   therm_throt_device_show_##_name,		\
				   NULL)				\

#define define_therm_throt_device_show_func(event, name)		\
									\
static ssize_t therm_throt_device_show_##event##_##name(		\
			struct device *dev,				\
			struct device_attribute *attr,			\
			char *buf)					\
{									\
	unsigned int cpu = dev->id;					\
	ssize_t ret;							\
									\
	preempt_disable();	/* CPU hotplug */			\
	if (cpu_online(cpu)) {						\
		ret = sprintf(buf, "%lu\n",				\
			      per_cpu(thermal_state, cpu).event.name);	\
	} else								\
		ret = 0;						\
	preempt_enable();						\
									\
	return ret;							\
}

define_therm_throt_device_show_func(core_throttle, count);
define_therm_throt_device_one_ro(core_throttle_count);

define_therm_throt_device_show_func(core_power_limit, count);
define_therm_throt_device_one_ro(core_power_limit_count);

define_therm_throt_device_show_func(package_throttle, count);
define_therm_throt_device_one_ro(package_throttle_count);

define_therm_throt_device_show_func(package_power_limit, count);
define_therm_throt_device_one_ro(package_power_limit_count);

static struct attribute *thermal_throttle_attrs[] = {
	&dev_attr_core_throttle_count.attr,
	NULL
};

static struct attribute_group thermal_attr_group = {
	.attrs	= thermal_throttle_attrs,
	.name	= "thermal_throttle"
};
#endif /* CONFIG_SYSFS */

#define CORE_LEVEL	0
#define PACKAGE_LEVEL	1

/***
 * therm_throt_process - Process thermal throttling event from interrupt
 * @curr: Whether the condition is current or not (boolean), since the
 *        thermal interrupt normally gets called both when the thermal
 *        event begins and once the event has ended.
 *
 * This function is called by the thermal interrupt after the
 * IRQ has been acknowledged.
 *
 * It will take care of rate limiting and printing messages to the syslog.
 *
 * Returns: 0 : Event should NOT be further logged, i.e. still in
 *              "timeout" from previous log message.
 *          1 : Event should be logged further, and a message has been
 *              printed to the syslog.
 */
static int therm_throt_process(bool new_event, int event, int level)
{
	struct _thermal_state *state;
	unsigned int this_cpu = smp_processor_id();
	bool old_event;
	u64 now;
	struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu);

	now = get_jiffies_64();
	if (level == CORE_LEVEL) {
		if (event == THERMAL_THROTTLING_EVENT)
			state = &pstate->core_throttle;
		else if (event == POWER_LIMIT_EVENT)
			state = &pstate->core_power_limit;
		else
			 return 0;
	} else if (level == PACKAGE_LEVEL) {
		if (event == THERMAL_THROTTLING_EVENT)
			state = &pstate->package_throttle;
		else if (event == POWER_LIMIT_EVENT)
			state = &pstate->package_power_limit;
		else
			return 0;
	} else
		return 0;

	old_event = state->new_event;
	state->new_event = new_event;

	if (new_event)
		state->count++;

	if (time_before64(now, state->next_check) &&
			state->count != state->last_count)
		return 0;

	state->next_check = now + CHECK_INTERVAL;
	state->last_count = state->count;

	/* if we just entered the thermal event */
	if (new_event) {
		if (event == THERMAL_THROTTLING_EVENT)
			pr_crit("CPU%d: %s temperature above threshold, cpu clock throttled (total events = %lu)\n",
				this_cpu,
				level == CORE_LEVEL ? "Core" : "Package",
				state->count);
		return 1;
	}
	if (old_event) {
		if (event == THERMAL_THROTTLING_EVENT)
			pr_info("CPU%d: %s temperature/speed normal\n", this_cpu,
				level == CORE_LEVEL ? "Core" : "Package");
		return 1;
	}

	return 0;
}

static int thresh_event_valid(int level, int event)
{
	struct _thermal_state *state;
	unsigned int this_cpu = smp_processor_id();
	struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu);
	u64 now = get_jiffies_64();

	if (level == PACKAGE_LEVEL)
		state = (event == 0) ? &pstate->pkg_thresh0 :
						&pstate->pkg_thresh1;
	else
		state = (event == 0) ? &pstate->core_thresh0 :
						&pstate->core_thresh1;

	if (time_before64(now, state->next_check))
		return 0;

	state->next_check = now + CHECK_INTERVAL;

	return 1;
}

static bool int_pln_enable;
static int __init int_pln_enable_setup(char *s)
{
	int_pln_enable = true;

	return 1;
}
__setup("int_pln_enable", int_pln_enable_setup);

#ifdef CONFIG_SYSFS
/* Add/Remove thermal_throttle interface for CPU device: */
static int thermal_throttle_add_dev(struct device *dev, unsigned int cpu)
{
	int err;
	struct cpuinfo_x86 *c = &cpu_data(cpu);

	err = sysfs_create_group(&dev->kobj, &thermal_attr_group);
	if (err)
		return err;

	if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
		err = sysfs_add_file_to_group(&dev->kobj,
					      &dev_attr_core_power_limit_count.attr,
					      thermal_attr_group.name);
	if (cpu_has(c, X86_FEATURE_PTS)) {
		err = sysfs_add_file_to_group(&dev->kobj,
					      &dev_attr_package_throttle_count.attr,
					      thermal_attr_group.name);
		if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
			err = sysfs_add_file_to_group(&dev->kobj,
					&dev_attr_package_power_limit_count.attr,
					thermal_attr_group.name);
	}

	return err;
}

static void thermal_throttle_remove_dev(struct device *dev)
{
	sysfs_remove_group(&dev->kobj, &thermal_attr_group);
}

/* Get notified when a cpu comes on/off. Be hotplug friendly. */
static int
thermal_throttle_cpu_callback(struct notifier_block *nfb,
			      unsigned long action,
			      void *hcpu)
{
	unsigned int cpu = (unsigned long)hcpu;
	struct device *dev;
	int err = 0;

	dev = get_cpu_device(cpu);

	switch (action) {
	case CPU_UP_PREPARE:
	case CPU_UP_PREPARE_FROZEN:
		err = thermal_throttle_add_dev(dev, cpu);
		WARN_ON(err);
		break;
	case CPU_UP_CANCELED:
	case CPU_UP_CANCELED_FROZEN:
	case CPU_DEAD:
	case CPU_DEAD_FROZEN:
		thermal_throttle_remove_dev(dev);
		break;
	}
	return notifier_from_errno(err);
}

static struct notifier_block thermal_throttle_cpu_notifier =
{
	.notifier_call = thermal_throttle_cpu_callback,
};

static __init int thermal_throttle_init_device(void)
{
	unsigned int cpu = 0;
	int err;

	if (!atomic_read(&therm_throt_en))
		return 0;

	cpu_notifier_register_begin();

	/* connect live CPUs to sysfs */
	for_each_online_cpu(cpu) {
		err = thermal_throttle_add_dev(get_cpu_device(cpu), cpu);
		WARN_ON(err);
	}

	__register_hotcpu_notifier(&thermal_throttle_cpu_notifier);
	cpu_notifier_register_done();

	return 0;
}
device_initcall(thermal_throttle_init_device);

#endif /* CONFIG_SYSFS */

static void notify_package_thresholds(__u64 msr_val)
{
	bool notify_thres_0 = false;
	bool notify_thres_1 = false;

	if (!platform_thermal_package_notify)
		return;

	/* lower threshold check */
	if (msr_val & THERM_LOG_THRESHOLD0)
		notify_thres_0 = true;
	/* higher threshold check */
	if (msr_val & THERM_LOG_THRESHOLD1)
		notify_thres_1 = true;

	if (!notify_thres_0 && !notify_thres_1)
		return;

	if (platform_thermal_package_rate_control &&
		platform_thermal_package_rate_control()) {
		/* Rate control is implemented in callback */
		platform_thermal_package_notify(msr_val);
		return;
	}

	/* lower threshold reached */
	if (notify_thres_0 && thresh_event_valid(PACKAGE_LEVEL, 0))
		platform_thermal_package_notify(msr_val);
	/* higher threshold reached */
	if (notify_thres_1 && thresh_event_valid(PACKAGE_LEVEL, 1))
		platform_thermal_package_notify(msr_val);
}

static void notify_thresholds(__u64 msr_val)
{
	/* check whether the interrupt handler is defined;
	 * otherwise simply return
	 */
	if (!platform_thermal_notify)
		return;

	/* lower threshold reached */
	if ((msr_val & THERM_LOG_THRESHOLD0) &&
			thresh_event_valid(CORE_LEVEL, 0))
		platform_thermal_notify(msr_val);
	/* higher threshold reached */
	if ((msr_val & THERM_LOG_THRESHOLD1) &&
			thresh_event_valid(CORE_LEVEL, 1))
		platform_thermal_notify(msr_val);
}

/* Thermal transition interrupt handler */
static void intel_thermal_interrupt(void)
{
	__u64 msr_val;

	if (static_cpu_has(X86_FEATURE_HWP))
		wrmsrl_safe(MSR_HWP_STATUS, 0);

	rdmsrl(MSR_IA32_THERM_STATUS, msr_val);

	/* Check for violation of core thermal thresholds*/
	notify_thresholds(msr_val);

	if (therm_throt_process(msr_val & THERM_STATUS_PROCHOT,
				THERMAL_THROTTLING_EVENT,
				CORE_LEVEL) != 0)
		mce_log_therm_throt_event(msr_val);

	if (this_cpu_has(X86_FEATURE_PLN) && int_pln_enable)
		therm_throt_process(msr_val & THERM_STATUS_POWER_LIMIT,
					POWER_LIMIT_EVENT,
					CORE_LEVEL);

	if (this_cpu_has(X86_FEATURE_PTS)) {
		rdmsrl(MSR_IA32_PACKAGE_THERM_STATUS, msr_val);
		/* check violations of package thermal thresholds */
		notify_package_thresholds(msr_val);
		therm_throt_process(msr_val & PACKAGE_THERM_STATUS_PROCHOT,
					THERMAL_THROTTLING_EVENT,
					PACKAGE_LEVEL);
		if (this_cpu_has(X86_FEATURE_PLN) && int_pln_enable)
			therm_throt_process(msr_val &
					PACKAGE_THERM_STATUS_POWER_LIMIT,
					POWER_LIMIT_EVENT,
					PACKAGE_LEVEL);
	}
}

static void unexpected_thermal_interrupt(void)
{
	pr_err("CPU%d: Unexpected LVT thermal interrupt!\n",
		smp_processor_id());
}

static void (*smp_thermal_vector)(void) = unexpected_thermal_interrupt;

static inline void __smp_thermal_interrupt(void)
{
	inc_irq_stat(irq_thermal_count);
	smp_thermal_vector();
}

asmlinkage __visible void smp_thermal_interrupt(struct pt_regs *regs)
{
	entering_irq();
	__smp_thermal_interrupt();
	exiting_ack_irq();
}

asmlinkage __visible void smp_trace_thermal_interrupt(struct pt_regs *regs)
{
	entering_irq();
	trace_thermal_apic_entry(THERMAL_APIC_VECTOR);
	__smp_thermal_interrupt();
	trace_thermal_apic_exit(THERMAL_APIC_VECTOR);
	exiting_ack_irq();
}

/* Thermal monitoring depends on APIC, ACPI and clock modulation */
static int intel_thermal_supported(struct cpuinfo_x86 *c)
{
	if (!boot_cpu_has(X86_FEATURE_APIC))
		return 0;
	if (!cpu_has(c, X86_FEATURE_ACPI) || !cpu_has(c, X86_FEATURE_ACC))
		return 0;
	return 1;
}

void __init mcheck_intel_therm_init(void)
{
	/*
	 * This function is only called on boot CPU. Save the init thermal
	 * LVT value on BSP and use that value to restore APs' thermal LVT
	 * entry BIOS programmed later
	 */
	if (intel_thermal_supported(&boot_cpu_data))
		lvtthmr_init = apic_read(APIC_LVTTHMR);
}

void intel_init_thermal(struct cpuinfo_x86 *c)
{
	unsigned int cpu = smp_processor_id();
	int tm2 = 0;
	u32 l, h;

	if (!intel_thermal_supported(c))
		return;

	/*
	 * First check if its enabled already, in which case there might
	 * be some SMM goo which handles it, so we can't even put a handler
	 * since it might be delivered via SMI already:
	 */
	rdmsr(MSR_IA32_MISC_ENABLE, l, h);

	h = lvtthmr_init;
	/*
	 * The initial value of thermal LVT entries on all APs always reads
	 * 0x10000 because APs are woken up by BSP issuing INIT-SIPI-SIPI
	 * sequence to them and LVT registers are reset to 0s except for
	 * the mask bits which are set to 1s when APs receive INIT IPI.
	 * If BIOS takes over the thermal interrupt and sets its interrupt
	 * delivery mode to SMI (not fixed), it restores the value that the
	 * BIOS has programmed on AP based on BSP's info we saved since BIOS
	 * is always setting the same value for all threads/cores.
	 */
	if ((h & APIC_DM_FIXED_MASK) != APIC_DM_FIXED)
		apic_write(APIC_LVTTHMR, lvtthmr_init);


	if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) {
		if (system_state == SYSTEM_BOOTING)
			pr_debug("CPU%d: Thermal monitoring handled by SMI\n", cpu);
		return;
	}

	/* early Pentium M models use different method for enabling TM2 */
	if (cpu_has(c, X86_FEATURE_TM2)) {
		if (c->x86 == 6 && (c->x86_model == 9 || c->x86_model == 13)) {
			rdmsr(MSR_THERM2_CTL, l, h);
			if (l & MSR_THERM2_CTL_TM_SELECT)
				tm2 = 1;
		} else if (l & MSR_IA32_MISC_ENABLE_TM2)
			tm2 = 1;
	}

	/* We'll mask the thermal vector in the lapic till we're ready: */
	h = THERMAL_APIC_VECTOR | APIC_DM_FIXED | APIC_LVT_MASKED;
	apic_write(APIC_LVTTHMR, h);

	rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
	if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable)
		wrmsr(MSR_IA32_THERM_INTERRUPT,
			(l | (THERM_INT_LOW_ENABLE
			| THERM_INT_HIGH_ENABLE)) & ~THERM_INT_PLN_ENABLE, h);
	else if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
		wrmsr(MSR_IA32_THERM_INTERRUPT,
			l | (THERM_INT_LOW_ENABLE
			| THERM_INT_HIGH_ENABLE | THERM_INT_PLN_ENABLE), h);
	else
		wrmsr(MSR_IA32_THERM_INTERRUPT,
		      l | (THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE), h);

	if (cpu_has(c, X86_FEATURE_PTS)) {
		rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
		if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable)
			wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
				(l | (PACKAGE_THERM_INT_LOW_ENABLE
				| PACKAGE_THERM_INT_HIGH_ENABLE))
				& ~PACKAGE_THERM_INT_PLN_ENABLE, h);
		else if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
			wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
				l | (PACKAGE_THERM_INT_LOW_ENABLE
				| PACKAGE_THERM_INT_HIGH_ENABLE
				| PACKAGE_THERM_INT_PLN_ENABLE), h);
		else
			wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
			      l | (PACKAGE_THERM_INT_LOW_ENABLE
				| PACKAGE_THERM_INT_HIGH_ENABLE), h);
	}

	smp_thermal_vector = intel_thermal_interrupt;

	rdmsr(MSR_IA32_MISC_ENABLE, l, h);
	wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h);

	/* Unmask the thermal vector: */
	l = apic_read(APIC_LVTTHMR);
	apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);

	pr_info_once("CPU0: Thermal monitoring enabled (%s)\n",
		      tm2 ? "TM2" : "TM1");

	/* enable thermal throttle processing */
	atomic_set(&therm_throt_en, 1);
}
Commit	Line	Data
15d5f839	1	/*
3222b36f DZ	2	* Thermal throttle event support code (such as syslog messaging and rate
3222b36f DZ	3	* limiting) that was factored out from x86_64 (mce_intel.c) and i386 (p4.c).
cb6f3c15	4	*
3222b36f DZ	5	* This allows consistent reporting of CPU thermal throttle events.
	6	*
	7	* Maintains a counter in /sys that keeps track of the number of thermal
	8	* events, such that the user knows how bad the thermal problem might be
	9	* (since the logging to syslog and mcelog is rate limited).
15d5f839 DZ	10	*
	11	* Author: Dmitriy Zavin (dmitriyz@google.com)
	12	*
	13	* Credits: Adapted from Zwane Mwaikambo's original code in mce_intel.c.
3222b36f	14	* Inspired by Ross Biro's and Al Borchers' counter code.
15d5f839	15	*/
a65c88dd	16	#include <linux/interrupt.h>
cb6f3c15 IM	17	#include <linux/notifier.h>
cb6f3c15 IM	18	#include <linux/jiffies.h>
895287c0	19	#include <linux/kernel.h>
15d5f839	20	#include <linux/percpu.h>
69c60c88	21	#include <linux/export.h>
895287c0 HS	22	#include <linux/types.h>
	23	#include <linux/init.h>
	24	#include <linux/smp.h>
15d5f839	25	#include <linux/cpu.h>
cb6f3c15	26
895287c0	27	#include <asm/processor.h>
895287c0	28	#include <asm/apic.h>
a65c88dd HS	29	#include <asm/idle.h>
a65c88dd HS	30	#include <asm/mce.h>
895287c0	31	#include <asm/msr.h>
cf910e83	32	#include <asm/trace/irq_vectors.h>
15d5f839 DZ	33
15d5f839 DZ	34	/* How long to wait between reporting thermal events */
cb6f3c15	35	#define CHECK_INTERVAL (300 * HZ)
15d5f839	36
0199114c FY	37	#define THERMAL_THROTTLING_EVENT 0
	38	#define POWER_LIMIT_EVENT 1
	39
39676840	40	/*
0199114c	41	* Current thermal event state:
39676840	42	*/
55d435a2	43	struct _thermal_state {
0199114c FY	44	bool new_event;
0199114c FY	45	int event;
39676840	46	u64 next_check;
0199114c FY	47	unsigned long count;
0199114c FY	48	unsigned long last_count;
39676840	49	};
cb6f3c15	50
55d435a2	51	struct thermal_state {
0199114c FY	52	struct _thermal_state core_throttle;
	53	struct _thermal_state core_power_limit;
	54	struct _thermal_state package_throttle;
	55	struct _thermal_state package_power_limit;
9e76a97e D	56	struct _thermal_state core_thresh0;
9e76a97e D	57	struct _thermal_state core_thresh1;
25cdce17 SP	58	struct _thermal_state pkg_thresh0;
25cdce17 SP	59	struct _thermal_state pkg_thresh1;
55d435a2 FY	60	};
55d435a2 FY	61
9e76a97e D	62	/* Callback to handle core threshold interrupts */
9e76a97e D	63	int (*platform_thermal_notify)(__u64 msr_val);
f21bbec9	64	EXPORT_SYMBOL(platform_thermal_notify);
9e76a97e	65
25cdce17 SP	66	/* Callback to handle core package threshold_interrupts */
	67	int (*platform_thermal_package_notify)(__u64 msr_val);
	68	EXPORT_SYMBOL_GPL(platform_thermal_package_notify);
	69
	70	/* Callback support of rate control, return true, if
	71	* callback has rate control */
	72	bool (*platform_thermal_package_rate_control)(void);
	73	EXPORT_SYMBOL_GPL(platform_thermal_package_rate_control);
	74
	75
39676840 IM	76	static DEFINE_PER_CPU(struct thermal_state, thermal_state);
	77
	78	static atomic_t therm_throt_en = ATOMIC_INIT(0);
3222b36f	79
a2202aa2 YW	80	static u32 lvtthmr_init __read_mostly;
a2202aa2 YW	81
3222b36f	82	#ifdef CONFIG_SYSFS
8a25a2fd KS	83	#define define_therm_throt_device_one_ro(_name) \
	84	static DEVICE_ATTR(_name, 0444, \
	85	therm_throt_device_show_##_name, \
55d435a2	86	NULL) \
cb6f3c15	87
8a25a2fd	88	#define define_therm_throt_device_show_func(event, name) \
39676840	89	\
8a25a2fd KS	90	static ssize_t therm_throt_device_show_##event##_##name( \
	91	struct device *dev, \
	92	struct device_attribute *attr, \
39676840	93	char *buf) \
cb6f3c15 IM	94	{ \
	95	unsigned int cpu = dev->id; \
	96	ssize_t ret; \
	97	\
	98	preempt_disable(); /* CPU hotplug */ \
55d435a2	99	if (cpu_online(cpu)) { \
cb6f3c15	100	ret = sprintf(buf, "%lu\n", \
0199114c	101	per_cpu(thermal_state, cpu).event.name); \
55d435a2	102	} else \
cb6f3c15 IM	103	ret = 0; \
	104	preempt_enable(); \
	105	\
	106	return ret; \
3222b36f DZ	107	}
3222b36f DZ	108
8a25a2fd KS	109	define_therm_throt_device_show_func(core_throttle, count);
8a25a2fd KS	110	define_therm_throt_device_one_ro(core_throttle_count);
55d435a2	111
8a25a2fd KS	112	define_therm_throt_device_show_func(core_power_limit, count);
8a25a2fd KS	113	define_therm_throt_device_one_ro(core_power_limit_count);
0199114c	114
8a25a2fd KS	115	define_therm_throt_device_show_func(package_throttle, count);
8a25a2fd KS	116	define_therm_throt_device_one_ro(package_throttle_count);
3222b36f	117
8a25a2fd KS	118	define_therm_throt_device_show_func(package_power_limit, count);
8a25a2fd KS	119	define_therm_throt_device_one_ro(package_power_limit_count);
0199114c	120
3222b36f	121	static struct attribute *thermal_throttle_attrs[] = {
8a25a2fd	122	&dev_attr_core_throttle_count.attr,
3222b36f DZ	123	NULL
	124	};
	125
0199114c	126	static struct attribute_group thermal_attr_group = {
cb6f3c15 IM	127	.attrs = thermal_throttle_attrs,
cb6f3c15 IM	128	.name = "thermal_throttle"
3222b36f DZ	129	};
3222b36f DZ	130	#endif /* CONFIG_SYSFS */
15d5f839	131
0199114c FY	132	#define CORE_LEVEL 0
	133	#define PACKAGE_LEVEL 1
	134
15d5f839	135	/***
3222b36f	136	* therm_throt_process - Process thermal throttling event from interrupt
15d5f839 DZ	137	* @curr: Whether the condition is current or not (boolean), since the
	138	* thermal interrupt normally gets called both when the thermal
	139	* event begins and once the event has ended.
	140	*
3222b36f	141	* This function is called by the thermal interrupt after the
15d5f839 DZ	142	* IRQ has been acknowledged.
	143	*
	144	* It will take care of rate limiting and printing messages to the syslog.
	145	*
	146	* Returns: 0 : Event should NOT be further logged, i.e. still in
	147	* "timeout" from previous log message.
	148	* 1 : Event should be logged further, and a message has been
	149	* printed to the syslog.
	150	*/
0199114c	151	static int therm_throt_process(bool new_event, int event, int level)
15d5f839	152	{
55d435a2	153	struct _thermal_state *state;
0199114c FY	154	unsigned int this_cpu = smp_processor_id();
0199114c FY	155	bool old_event;
39676840	156	u64 now;
0199114c	157	struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu);
39676840	158
39676840	159	now = get_jiffies_64();
0199114c FY	160	if (level == CORE_LEVEL) {
	161	if (event == THERMAL_THROTTLING_EVENT)
	162	state = &pstate->core_throttle;
	163	else if (event == POWER_LIMIT_EVENT)
	164	state = &pstate->core_power_limit;
	165	else
	166	return 0;
	167	} else if (level == PACKAGE_LEVEL) {
	168	if (event == THERMAL_THROTTLING_EVENT)
	169	state = &pstate->package_throttle;
	170	else if (event == POWER_LIMIT_EVENT)
	171	state = &pstate->package_power_limit;
	172	else
	173	return 0;
	174	} else
	175	return 0;
39676840	176
0199114c FY	177	old_event = state->new_event;
0199114c FY	178	state->new_event = new_event;
15d5f839	179
0199114c FY	180	if (new_event)
0199114c FY	181	state->count++;
3222b36f	182
b417c9fd	183	if (time_before64(now, state->next_check) &&
0199114c	184	state->count != state->last_count)
15d5f839 DZ	185	return 0;
15d5f839 DZ	186
39676840	187	state->next_check = now + CHECK_INTERVAL;
0199114c	188	state->last_count = state->count;
15d5f839 DZ	189
15d5f839 DZ	190	/* if we just entered the thermal event */
0199114c FY	191	if (new_event) {
0199114c FY	192	if (event == THERMAL_THROTTLING_EVENT)
1b74dde7	193	pr_crit("CPU%d: %s temperature above threshold, cpu clock throttled (total events = %lu)\n",
0199114c FY	194	this_cpu,
	195	level == CORE_LEVEL ? "Core" : "Package",
	196	state->count);
4e5c25d4 HD	197	return 1;
4e5c25d4 HD	198	}
0199114c FY	199	if (old_event) {
0199114c FY	200	if (event == THERMAL_THROTTLING_EVENT)
1b74dde7	201	pr_info("CPU%d: %s temperature/speed normal\n", this_cpu,
0199114c	202	level == CORE_LEVEL ? "Core" : "Package");
4e5c25d4	203	return 1;
15d5f839 DZ	204	}
15d5f839 DZ	205
4e5c25d4	206	return 0;
15d5f839	207	}
3222b36f	208
25cdce17	209	static int thresh_event_valid(int level, int event)
9e76a97e D	210	{
	211	struct _thermal_state *state;
	212	unsigned int this_cpu = smp_processor_id();
	213	struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu);
	214	u64 now = get_jiffies_64();
	215
25cdce17 SP	216	if (level == PACKAGE_LEVEL)
	217	state = (event == 0) ? &pstate->pkg_thresh0 :
	218	&pstate->pkg_thresh1;
	219	else
	220	state = (event == 0) ? &pstate->core_thresh0 :
	221	&pstate->core_thresh1;
9e76a97e D	222
	223	if (time_before64(now, state->next_check))
	224	return 0;
	225
	226	state->next_check = now + CHECK_INTERVAL;
25cdce17	227
9e76a97e D	228	return 1;
	229	}
	230
6bb2ff84 FY	231	static bool int_pln_enable;
	232	static int __init int_pln_enable_setup(char *s)
	233	{
	234	int_pln_enable = true;
	235
	236	return 1;
	237	}
	238	__setup("int_pln_enable", int_pln_enable_setup);
	239
3222b36f	240	#ifdef CONFIG_SYSFS
cb6f3c15	241	/* Add/Remove thermal_throttle interface for CPU device: */
148f9bb8	242	static int thermal_throttle_add_dev(struct device *dev, unsigned int cpu)
3222b36f	243	{
55d435a2	244	int err;
51e3c1b5	245	struct cpuinfo_x86 *c = &cpu_data(cpu);
55d435a2	246
8a25a2fd	247	err = sysfs_create_group(&dev->kobj, &thermal_attr_group);
55d435a2 FY	248	if (err)
	249	return err;
	250
6bb2ff84	251	if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
8a25a2fd KS	252	err = sysfs_add_file_to_group(&dev->kobj,
8a25a2fd KS	253	&dev_attr_core_power_limit_count.attr,
0199114c	254	thermal_attr_group.name);
b62be8ea	255	if (cpu_has(c, X86_FEATURE_PTS)) {
8a25a2fd KS	256	err = sysfs_add_file_to_group(&dev->kobj,
8a25a2fd KS	257	&dev_attr_package_throttle_count.attr,
0199114c	258	thermal_attr_group.name);
6bb2ff84	259	if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
8a25a2fd KS	260	err = sysfs_add_file_to_group(&dev->kobj,
8a25a2fd KS	261	&dev_attr_package_power_limit_count.attr,
0199114c	262	thermal_attr_group.name);
b62be8ea	263	}
55d435a2 FY	264
55d435a2 FY	265	return err;
3222b36f DZ	266	}
3222b36f DZ	267
148f9bb8	268	static void thermal_throttle_remove_dev(struct device *dev)
3222b36f	269	{
8a25a2fd	270	sysfs_remove_group(&dev->kobj, &thermal_attr_group);
3222b36f DZ	271	}
3222b36f DZ	272
3222b36f	273	/* Get notified when a cpu comes on/off. Be hotplug friendly. */
148f9bb8	274	static int
cb6f3c15 IM	275	thermal_throttle_cpu_callback(struct notifier_block *nfb,
	276	unsigned long action,
	277	void *hcpu)
3222b36f DZ	278	{
3222b36f DZ	279	unsigned int cpu = (unsigned long)hcpu;
8a25a2fd	280	struct device *dev;
c7e38a9c	281	int err = 0;
3222b36f	282
8a25a2fd	283	dev = get_cpu_device(cpu);
cb6f3c15	284
3222b36f	285	switch (action) {
c7e38a9c AM	286	case CPU_UP_PREPARE:
c7e38a9c AM	287	case CPU_UP_PREPARE_FROZEN:
8a25a2fd	288	err = thermal_throttle_add_dev(dev, cpu);
6569345a	289	WARN_ON(err);
3222b36f	290	break;
c7e38a9c AM	291	case CPU_UP_CANCELED:
c7e38a9c AM	292	case CPU_UP_CANCELED_FROZEN:
3222b36f	293	case CPU_DEAD:
8bb78442	294	case CPU_DEAD_FROZEN:
8a25a2fd	295	thermal_throttle_remove_dev(dev);
3222b36f DZ	296	break;
3222b36f DZ	297	}
a94247e7	298	return notifier_from_errno(err);
3222b36f DZ	299	}
3222b36f DZ	300
148f9bb8	301	static struct notifier_block thermal_throttle_cpu_notifier =
3222b36f DZ	302	{
	303	.notifier_call = thermal_throttle_cpu_callback,
	304	};
3222b36f DZ	305
	306	static __init int thermal_throttle_init_device(void)
	307	{
	308	unsigned int cpu = 0;
6569345a	309	int err;
3222b36f DZ	310
	311	if (!atomic_read(&therm_throt_en))
	312	return 0;
	313
4e6192bb	314	cpu_notifier_register_begin();
3222b36f	315
3222b36f	316	/* connect live CPUs to sysfs */
6569345a	317	for_each_online_cpu(cpu) {
8a25a2fd	318	err = thermal_throttle_add_dev(get_cpu_device(cpu), cpu);
6569345a SH	319	WARN_ON(err);
6569345a SH	320	}
3222b36f	321
4e6192bb SB	322	__register_hotcpu_notifier(&thermal_throttle_cpu_notifier);
	323	cpu_notifier_register_done();
	324
3222b36f DZ	325	return 0;
3222b36f DZ	326	}
3222b36f	327	device_initcall(thermal_throttle_init_device);
a65c88dd	328
3222b36f	329	#endif /* CONFIG_SYSFS */
a65c88dd	330
25cdce17 SP	331	static void notify_package_thresholds(__u64 msr_val)
	332	{
	333	bool notify_thres_0 = false;
	334	bool notify_thres_1 = false;
	335
	336	if (!platform_thermal_package_notify)
	337	return;
	338
	339	/* lower threshold check */
	340	if (msr_val & THERM_LOG_THRESHOLD0)
	341	notify_thres_0 = true;
	342	/* higher threshold check */
	343	if (msr_val & THERM_LOG_THRESHOLD1)
	344	notify_thres_1 = true;
	345
	346	if (!notify_thres_0 && !notify_thres_1)
	347	return;
	348
	349	if (platform_thermal_package_rate_control &&
	350	platform_thermal_package_rate_control()) {
	351	/* Rate control is implemented in callback */
	352	platform_thermal_package_notify(msr_val);
	353	return;
	354	}
	355
	356	/* lower threshold reached */
	357	if (notify_thres_0 && thresh_event_valid(PACKAGE_LEVEL, 0))
	358	platform_thermal_package_notify(msr_val);
	359	/* higher threshold reached */
	360	if (notify_thres_1 && thresh_event_valid(PACKAGE_LEVEL, 1))
	361	platform_thermal_package_notify(msr_val);
	362	}
	363
9e76a97e D	364	static void notify_thresholds(__u64 msr_val)
	365	{
	366	/* check whether the interrupt handler is defined;
	367	* otherwise simply return
	368	*/
	369	if (!platform_thermal_notify)
	370	return;
	371
	372	/* lower threshold reached */
25cdce17 SP	373	if ((msr_val & THERM_LOG_THRESHOLD0) &&
25cdce17 SP	374	thresh_event_valid(CORE_LEVEL, 0))
9e76a97e D	375	platform_thermal_notify(msr_val);
9e76a97e D	376	/* higher threshold reached */
25cdce17 SP	377	if ((msr_val & THERM_LOG_THRESHOLD1) &&
25cdce17 SP	378	thresh_event_valid(CORE_LEVEL, 1))
9e76a97e D	379	platform_thermal_notify(msr_val);
	380	}
	381
a65c88dd	382	/* Thermal transition interrupt handler */
8363fc82	383	static void intel_thermal_interrupt(void)
a65c88dd HS	384	{
	385	__u64 msr_val;
	386
a2121167 SP	387	if (static_cpu_has(X86_FEATURE_HWP))
	388	wrmsrl_safe(MSR_HWP_STATUS, 0);
	389
a65c88dd	390	rdmsrl(MSR_IA32_THERM_STATUS, msr_val);
0199114c	391
9e76a97e D	392	/* Check for violation of core thermal thresholds*/
	393	notify_thresholds(msr_val);
	394
55d435a2	395	if (therm_throt_process(msr_val & THERM_STATUS_PROCHOT,
0199114c	396	THERMAL_THROTTLING_EVENT,
55d435a2	397	CORE_LEVEL) != 0)
29e9bf18	398	mce_log_therm_throt_event(msr_val);
0199114c	399
6bb2ff84	400	if (this_cpu_has(X86_FEATURE_PLN) && int_pln_enable)
29e9bf18	401	therm_throt_process(msr_val & THERM_STATUS_POWER_LIMIT,
0199114c	402	POWER_LIMIT_EVENT,
29e9bf18	403	CORE_LEVEL);
55d435a2	404
fe504213	405	if (this_cpu_has(X86_FEATURE_PTS)) {
55d435a2	406	rdmsrl(MSR_IA32_PACKAGE_THERM_STATUS, msr_val);
25cdce17 SP	407	/* check violations of package thermal thresholds */
25cdce17 SP	408	notify_package_thresholds(msr_val);
29e9bf18	409	therm_throt_process(msr_val & PACKAGE_THERM_STATUS_PROCHOT,
0199114c	410	THERMAL_THROTTLING_EVENT,
29e9bf18	411	PACKAGE_LEVEL);
6bb2ff84	412	if (this_cpu_has(X86_FEATURE_PLN) && int_pln_enable)
29e9bf18	413	therm_throt_process(msr_val &
0199114c FY	414	PACKAGE_THERM_STATUS_POWER_LIMIT,
0199114c FY	415	POWER_LIMIT_EVENT,
29e9bf18	416	PACKAGE_LEVEL);
55d435a2	417	}
a65c88dd HS	418	}
	419
	420	static void unexpected_thermal_interrupt(void)
	421	{
1b74dde7 CY	422	pr_err("CPU%d: Unexpected LVT thermal interrupt!\n",
1b74dde7 CY	423	smp_processor_id());
a65c88dd HS	424	}
	425
	426	static void (*smp_thermal_vector)(void) = unexpected_thermal_interrupt;
	427
eddc0e92	428	static inline void __smp_thermal_interrupt(void)
a65c88dd	429	{
a65c88dd HS	430	inc_irq_stat(irq_thermal_count);
a65c88dd HS	431	smp_thermal_vector();
eddc0e92 SA	432	}
eddc0e92 SA	433
2605fc21	434	asmlinkage __visible void smp_thermal_interrupt(struct pt_regs *regs)
eddc0e92 SA	435	{
	436	entering_irq();
	437	__smp_thermal_interrupt();
	438	exiting_ack_irq();
a65c88dd HS	439	}
a65c88dd HS	440
2605fc21	441	asmlinkage __visible void smp_trace_thermal_interrupt(struct pt_regs *regs)
cf910e83 SA	442	{
	443	entering_irq();
	444	trace_thermal_apic_entry(THERMAL_APIC_VECTOR);
	445	__smp_thermal_interrupt();
	446	trace_thermal_apic_exit(THERMAL_APIC_VECTOR);
	447	exiting_ack_irq();
	448	}
	449
70fe4407 HS	450	/* Thermal monitoring depends on APIC, ACPI and clock modulation */
	451	static int intel_thermal_supported(struct cpuinfo_x86 *c)
	452	{
93984fbd	453	if (!boot_cpu_has(X86_FEATURE_APIC))
70fe4407 HS	454	return 0;
	455	if (!cpu_has(c, X86_FEATURE_ACPI) \|\| !cpu_has(c, X86_FEATURE_ACC))
	456	return 0;
	457	return 1;
	458	}
	459
ce6b5d76	460	void __init mcheck_intel_therm_init(void)
a2202aa2 YW	461	{
	462	/*
	463	* This function is only called on boot CPU. Save the init thermal
	464	* LVT value on BSP and use that value to restore APs' thermal LVT
	465	* entry BIOS programmed later
	466	*/
70fe4407	467	if (intel_thermal_supported(&boot_cpu_data))
a2202aa2 YW	468	lvtthmr_init = apic_read(APIC_LVTTHMR);
	469	}
	470
cffd377e	471	void intel_init_thermal(struct cpuinfo_x86 *c)
895287c0 HS	472	{
	473	unsigned int cpu = smp_processor_id();
	474	int tm2 = 0;
	475	u32 l, h;
	476
70fe4407	477	if (!intel_thermal_supported(c))
895287c0 HS	478	return;
	479
	480	/*
	481	* First check if its enabled already, in which case there might
	482	* be some SMM goo which handles it, so we can't even put a handler
	483	* since it might be delivered via SMI already:
	484	*/
	485	rdmsr(MSR_IA32_MISC_ENABLE, l, h);
a2202aa2	486
e503f9e4	487	h = lvtthmr_init;
a2202aa2 YW	488	/*
	489	* The initial value of thermal LVT entries on all APs always reads
	490	* 0x10000 because APs are woken up by BSP issuing INIT-SIPI-SIPI
	491	* sequence to them and LVT registers are reset to 0s except for
	492	* the mask bits which are set to 1s when APs receive INIT IPI.
e503f9e4 YS	493	* If BIOS takes over the thermal interrupt and sets its interrupt
	494	* delivery mode to SMI (not fixed), it restores the value that the
	495	* BIOS has programmed on AP based on BSP's info we saved since BIOS
	496	* is always setting the same value for all threads/cores.
a2202aa2	497	*/
e503f9e4 YS	498	if ((h & APIC_DM_FIXED_MASK) != APIC_DM_FIXED)
e503f9e4 YS	499	apic_write(APIC_LVTTHMR, lvtthmr_init);
a2202aa2	500
a2202aa2	501
895287c0	502	if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) {
d286c3af	503	if (system_state == SYSTEM_BOOTING)
1b74dde7	504	pr_debug("CPU%d: Thermal monitoring handled by SMI\n", cpu);
895287c0 HS	505	return;
	506	}
	507
f3a0867b BZ	508	/* early Pentium M models use different method for enabling TM2 */
	509	if (cpu_has(c, X86_FEATURE_TM2)) {
	510	if (c->x86 == 6 && (c->x86_model == 9 \|\| c->x86_model == 13)) {
	511	rdmsr(MSR_THERM2_CTL, l, h);
	512	if (l & MSR_THERM2_CTL_TM_SELECT)
	513	tm2 = 1;
	514	} else if (l & MSR_IA32_MISC_ENABLE_TM2)
	515	tm2 = 1;
	516	}
	517
895287c0 HS	518	/* We'll mask the thermal vector in the lapic till we're ready: */
	519	h = THERMAL_APIC_VECTOR \| APIC_DM_FIXED \| APIC_LVT_MASKED;
	520	apic_write(APIC_LVTTHMR, h);
	521
	522	rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
6bb2ff84	523	if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable)
0199114c	524	wrmsr(MSR_IA32_THERM_INTERRUPT,
6bb2ff84 FY	525	(l \| (THERM_INT_LOW_ENABLE
	526	\| THERM_INT_HIGH_ENABLE)) & ~THERM_INT_PLN_ENABLE, h);
	527	else if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
0199114c	528	wrmsr(MSR_IA32_THERM_INTERRUPT,
6bb2ff84	529	l \| (THERM_INT_LOW_ENABLE
0199114c FY	530	\| THERM_INT_HIGH_ENABLE \| THERM_INT_PLN_ENABLE), h);
	531	else
	532	wrmsr(MSR_IA32_THERM_INTERRUPT,
	533	l \| (THERM_INT_LOW_ENABLE \| THERM_INT_HIGH_ENABLE), h);
895287c0	534
55d435a2 FY	535	if (cpu_has(c, X86_FEATURE_PTS)) {
55d435a2 FY	536	rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
6bb2ff84	537	if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable)
0199114c	538	wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
6bb2ff84 FY	539	(l \| (PACKAGE_THERM_INT_LOW_ENABLE
	540	\| PACKAGE_THERM_INT_HIGH_ENABLE))
	541	& ~PACKAGE_THERM_INT_PLN_ENABLE, h);
	542	else if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
	543	wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
	544	l \| (PACKAGE_THERM_INT_LOW_ENABLE
0199114c FY	545	\| PACKAGE_THERM_INT_HIGH_ENABLE
	546	\| PACKAGE_THERM_INT_PLN_ENABLE), h);
	547	else
	548	wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
	549	l \| (PACKAGE_THERM_INT_LOW_ENABLE
	550	\| PACKAGE_THERM_INT_HIGH_ENABLE), h);
55d435a2 FY	551	}
55d435a2 FY	552
8363fc82	553	smp_thermal_vector = intel_thermal_interrupt;
895287c0 HS	554
	555	rdmsr(MSR_IA32_MISC_ENABLE, l, h);
	556	wrmsr(MSR_IA32_MISC_ENABLE, l \| MSR_IA32_MISC_ENABLE_TM1, h);
	557
	558	/* Unmask the thermal vector: */
	559	l = apic_read(APIC_LVTTHMR);
	560	apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
	561
1b74dde7 CY	562	pr_info_once("CPU0: Thermal monitoring enabled (%s)\n",
1b74dde7 CY	563	tm2 ? "TM2" : "TM1");
895287c0 HS	564
	565	/* enable thermal throttle processing */
	566	atomic_set(&therm_throt_en, 1);
	567	}