Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * P5 specific Machine Check Exception Reporting | |
87c6fe26 | 3 | * (C) Copyright 2002 Alan Cox <alan@lxorguk.ukuu.org.uk> |
1da177e4 | 4 | */ |
1da177e4 | 5 | #include <linux/interrupt.h> |
ed8bc7ed IM |
6 | #include <linux/kernel.h> |
7 | #include <linux/types.h> | |
8 | #include <linux/init.h> | |
1da177e4 LT |
9 | #include <linux/smp.h> |
10 | ||
15777205 | 11 | #include <asm/processor.h> |
1da177e4 LT |
12 | #include <asm/system.h> |
13 | #include <asm/msr.h> | |
14 | ||
15 | #include "mce.h" | |
16 | ||
ed8bc7ed | 17 | /* Machine check handler for Pentium class Intel CPUs: */ |
15777205 | 18 | static void pentium_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 LT |
19 | { |
20 | u32 loaddr, hi, lotype; | |
ed8bc7ed | 21 | |
1da177e4 LT |
22 | rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi); |
23 | rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi); | |
ed8bc7ed IM |
24 | |
25 | printk(KERN_EMERG | |
26 | "CPU#%d: Machine Check Exception: 0x%8X (type 0x%8X).\n", | |
27 | smp_processor_id(), loaddr, lotype); | |
28 | ||
29 | if (lotype & (1<<5)) { | |
30 | printk(KERN_EMERG | |
31 | "CPU#%d: Possible thermal failure (CPU on fire ?).\n", | |
32 | smp_processor_id()); | |
33 | } | |
34 | ||
1da177e4 LT |
35 | add_taint(TAINT_MACHINE_CHECK); |
36 | } | |
37 | ||
ed8bc7ed | 38 | /* Set up machine check reporting for processors with Intel style MCE: */ |
31ab269a | 39 | void intel_p5_mcheck_init(struct cpuinfo_x86 *c) |
1da177e4 LT |
40 | { |
41 | u32 l, h; | |
15777205 | 42 | |
ed8bc7ed | 43 | /* Check for MCE support: */ |
15777205 PC |
44 | if (!cpu_has(c, X86_FEATURE_MCE)) |
45 | return; | |
1da177e4 | 46 | |
ed8bc7ed | 47 | /* Default P5 to off as its often misconnected: */ |
15777205 | 48 | if (mce_disabled != -1) |
1da177e4 | 49 | return; |
ed8bc7ed | 50 | |
1da177e4 | 51 | machine_check_vector = pentium_machine_check; |
ed8bc7ed | 52 | /* Make sure the vector pointer is visible before we enable MCEs: */ |
1da177e4 LT |
53 | wmb(); |
54 | ||
ed8bc7ed | 55 | /* Read registers before enabling: */ |
1da177e4 LT |
56 | rdmsr(MSR_IA32_P5_MC_ADDR, l, h); |
57 | rdmsr(MSR_IA32_P5_MC_TYPE, l, h); | |
ed8bc7ed IM |
58 | printk(KERN_INFO |
59 | "Intel old style machine check architecture supported.\n"); | |
1da177e4 | 60 | |
ed8bc7ed | 61 | /* Enable MCE: */ |
1da177e4 | 62 | set_in_cr4(X86_CR4_MCE); |
ed8bc7ed IM |
63 | printk(KERN_INFO |
64 | "Intel old style machine check reporting enabled on CPU#%d.\n", | |
65 | smp_processor_id()); | |
1da177e4 | 66 | } |